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radv: calculate and emit GFX9 GS registers to pipeline state.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
59
60 #include <llvm-c/TargetMachine.h>
61
62 /* Pre-declarations needed for WSI entrypoints */
63 struct wl_surface;
64 struct wl_display;
65 typedef struct xcb_connection_t xcb_connection_t;
66 typedef uint32_t xcb_visualid_t;
67 typedef uint32_t xcb_window_t;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "radv_entrypoints.h"
74
75 #include "wsi_common.h"
76
77 #define ATI_VENDOR_ID 0x1002
78
79 #define MAX_VBS 32
80 #define MAX_VERTEX_ATTRIBS 32
81 #define MAX_RTS 8
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
90 #define MAX_VIEWS 8
91
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
93
94 enum radv_mem_heap {
95 RADV_MEM_HEAP_VRAM,
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
97 RADV_MEM_HEAP_GTT,
98 RADV_MEM_HEAP_COUNT
99 };
100
101 enum radv_mem_type {
102 RADV_MEM_TYPE_VRAM,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
105 RADV_MEM_TYPE_GTT_CACHED,
106 RADV_MEM_TYPE_COUNT
107 };
108
109 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
110
111 static inline uint32_t
112 align_u32(uint32_t v, uint32_t a)
113 {
114 assert(a != 0 && a == (a & -a));
115 return (v + a - 1) & ~(a - 1);
116 }
117
118 static inline uint32_t
119 align_u32_npot(uint32_t v, uint32_t a)
120 {
121 return (v + a - 1) / a * a;
122 }
123
124 static inline uint64_t
125 align_u64(uint64_t v, uint64_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 static inline int32_t
132 align_i32(int32_t v, int32_t a)
133 {
134 assert(a != 0 && a == (a & -a));
135 return (v + a - 1) & ~(a - 1);
136 }
137
138 /** Alignment must be a power of 2. */
139 static inline bool
140 radv_is_aligned(uintmax_t n, uintmax_t a)
141 {
142 assert(a == (a & -a));
143 return (n & (a - 1)) == 0;
144 }
145
146 static inline uint32_t
147 round_up_u32(uint32_t v, uint32_t a)
148 {
149 return (v + a - 1) / a;
150 }
151
152 static inline uint64_t
153 round_up_u64(uint64_t v, uint64_t a)
154 {
155 return (v + a - 1) / a;
156 }
157
158 static inline uint32_t
159 radv_minify(uint32_t n, uint32_t levels)
160 {
161 if (unlikely(n == 0))
162 return 0;
163 else
164 return MAX2(n >> levels, 1);
165 }
166 static inline float
167 radv_clamp_f(float f, float min, float max)
168 {
169 assert(min < max);
170
171 if (f > max)
172 return max;
173 else if (f < min)
174 return min;
175 else
176 return f;
177 }
178
179 static inline bool
180 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
181 {
182 if (*inout_mask & clear_mask) {
183 *inout_mask &= ~clear_mask;
184 return true;
185 } else {
186 return false;
187 }
188 }
189
190 #define for_each_bit(b, dword) \
191 for (uint32_t __dword = (dword); \
192 (b) = __builtin_ffs(__dword) - 1, __dword; \
193 __dword &= ~(1 << (b)))
194
195 #define typed_memcpy(dest, src, count) ({ \
196 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
197 memcpy((dest), (src), (count) * sizeof(*(src))); \
198 })
199
200 /* Whenever we generate an error, pass it through this function. Useful for
201 * debugging, where we can break on it. Only call at error site, not when
202 * propagating errors. Might be useful to plug in a stack trace here.
203 */
204
205 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
206
207 #ifdef DEBUG
208 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
209 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
210 #else
211 #define vk_error(error) error
212 #define vk_errorf(error, format, ...) error
213 #endif
214
215 void __radv_finishme(const char *file, int line, const char *format, ...)
216 radv_printflike(3, 4);
217 void radv_loge(const char *format, ...) radv_printflike(1, 2);
218 void radv_loge_v(const char *format, va_list va);
219
220 /**
221 * Print a FINISHME message, including its source location.
222 */
223 #define radv_finishme(format, ...) \
224 do { \
225 static bool reported = false; \
226 if (!reported) { \
227 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
228 reported = true; \
229 } \
230 } while (0)
231
232 /* A non-fatal assert. Useful for debugging. */
233 #ifdef DEBUG
234 #define radv_assert(x) ({ \
235 if (unlikely(!(x))) \
236 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
237 })
238 #else
239 #define radv_assert(x)
240 #endif
241
242 #define stub_return(v) \
243 do { \
244 radv_finishme("stub %s", __func__); \
245 return (v); \
246 } while (0)
247
248 #define stub() \
249 do { \
250 radv_finishme("stub %s", __func__); \
251 return; \
252 } while (0)
253
254 void *radv_lookup_entrypoint(const char *name);
255
256 struct radv_physical_device {
257 VK_LOADER_DATA _loader_data;
258
259 struct radv_instance * instance;
260
261 struct radeon_winsys *ws;
262 struct radeon_info rad_info;
263 char path[20];
264 const char * name;
265 uint8_t driver_uuid[VK_UUID_SIZE];
266 uint8_t device_uuid[VK_UUID_SIZE];
267 uint8_t cache_uuid[VK_UUID_SIZE];
268
269 int local_fd;
270 struct wsi_device wsi_device;
271
272 bool has_rbplus; /* if RB+ register exist */
273 bool rbplus_allowed; /* if RB+ is allowed */
274 bool has_clear_state;
275
276 /* This is the drivers on-disk cache used as a fallback as opposed to
277 * the pipeline cache defined by apps.
278 */
279 struct disk_cache * disk_cache;
280 };
281
282 struct radv_instance {
283 VK_LOADER_DATA _loader_data;
284
285 VkAllocationCallbacks alloc;
286
287 uint32_t apiVersion;
288 int physicalDeviceCount;
289 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
290
291 uint64_t debug_flags;
292 uint64_t perftest_flags;
293 };
294
295 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
296 void radv_finish_wsi(struct radv_physical_device *physical_device);
297
298 bool radv_instance_extension_supported(const char *name);
299 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
300 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
301 const char *name);
302
303 struct cache_entry;
304
305 struct radv_pipeline_cache {
306 struct radv_device * device;
307 pthread_mutex_t mutex;
308
309 uint32_t total_size;
310 uint32_t table_size;
311 uint32_t kernel_count;
312 struct cache_entry ** hash_table;
313 bool modified;
314
315 VkAllocationCallbacks alloc;
316 };
317
318 void
319 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
320 struct radv_device *device);
321 void
322 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
323 void
324 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
325 const void *data, size_t size);
326
327 struct radv_shader_variant;
328
329 bool
330 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
331 struct radv_pipeline_cache *cache,
332 const unsigned char *sha1,
333 struct radv_shader_variant **variants);
334
335 void
336 radv_pipeline_cache_insert_shaders(struct radv_device *device,
337 struct radv_pipeline_cache *cache,
338 const unsigned char *sha1,
339 struct radv_shader_variant **variants,
340 const void *const *codes,
341 const unsigned *code_sizes);
342
343 struct radv_meta_state {
344 VkAllocationCallbacks alloc;
345
346 struct radv_pipeline_cache cache;
347
348 /**
349 * Use array element `i` for images with `2^i` samples.
350 */
351 struct {
352 VkRenderPass render_pass[NUM_META_FS_KEYS];
353 VkPipeline color_pipelines[NUM_META_FS_KEYS];
354
355 VkRenderPass depthstencil_rp;
356 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
357 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
358 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
359 } clear[1 + MAX_SAMPLES_LOG2];
360
361 VkPipelineLayout clear_color_p_layout;
362 VkPipelineLayout clear_depth_p_layout;
363 struct {
364 VkRenderPass render_pass[NUM_META_FS_KEYS];
365
366 /** Pipeline that blits from a 1D image. */
367 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
368
369 /** Pipeline that blits from a 2D image. */
370 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
371
372 /** Pipeline that blits from a 3D image. */
373 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
374
375 VkRenderPass depth_only_rp;
376 VkPipeline depth_only_1d_pipeline;
377 VkPipeline depth_only_2d_pipeline;
378 VkPipeline depth_only_3d_pipeline;
379
380 VkRenderPass stencil_only_rp;
381 VkPipeline stencil_only_1d_pipeline;
382 VkPipeline stencil_only_2d_pipeline;
383 VkPipeline stencil_only_3d_pipeline;
384 VkPipelineLayout pipeline_layout;
385 VkDescriptorSetLayout ds_layout;
386 } blit;
387
388 struct {
389 VkRenderPass render_passes[NUM_META_FS_KEYS];
390
391 VkPipelineLayout p_layouts[2];
392 VkDescriptorSetLayout ds_layouts[2];
393 VkPipeline pipelines[2][NUM_META_FS_KEYS];
394
395 VkRenderPass depth_only_rp;
396 VkPipeline depth_only_pipeline[2];
397
398 VkRenderPass stencil_only_rp;
399 VkPipeline stencil_only_pipeline[2];
400 } blit2d;
401
402 struct {
403 VkPipelineLayout img_p_layout;
404 VkDescriptorSetLayout img_ds_layout;
405 VkPipeline pipeline;
406 } itob;
407 struct {
408 VkPipelineLayout img_p_layout;
409 VkDescriptorSetLayout img_ds_layout;
410 VkPipeline pipeline;
411 } btoi;
412 struct {
413 VkPipelineLayout img_p_layout;
414 VkDescriptorSetLayout img_ds_layout;
415 VkPipeline pipeline;
416 } itoi;
417 struct {
418 VkPipelineLayout img_p_layout;
419 VkDescriptorSetLayout img_ds_layout;
420 VkPipeline pipeline;
421 } cleari;
422
423 struct {
424 VkPipeline pipeline;
425 VkRenderPass pass;
426 } resolve;
427
428 struct {
429 VkDescriptorSetLayout ds_layout;
430 VkPipelineLayout p_layout;
431 struct {
432 VkPipeline pipeline;
433 VkPipeline i_pipeline;
434 VkPipeline srgb_pipeline;
435 } rc[MAX_SAMPLES_LOG2];
436 } resolve_compute;
437
438 struct {
439 VkDescriptorSetLayout ds_layout;
440 VkPipelineLayout p_layout;
441
442 struct {
443 VkRenderPass render_pass[NUM_META_FS_KEYS];
444 VkPipeline pipeline[NUM_META_FS_KEYS];
445 } rc[MAX_SAMPLES_LOG2];
446 } resolve_fragment;
447
448 struct {
449 VkPipeline decompress_pipeline;
450 VkPipeline resummarize_pipeline;
451 VkRenderPass pass;
452 } depth_decomp[1 + MAX_SAMPLES_LOG2];
453
454 struct {
455 VkPipeline cmask_eliminate_pipeline;
456 VkPipeline fmask_decompress_pipeline;
457 VkRenderPass pass;
458 } fast_clear_flush;
459
460 struct {
461 VkPipelineLayout fill_p_layout;
462 VkPipelineLayout copy_p_layout;
463 VkDescriptorSetLayout fill_ds_layout;
464 VkDescriptorSetLayout copy_ds_layout;
465 VkPipeline fill_pipeline;
466 VkPipeline copy_pipeline;
467 } buffer;
468
469 struct {
470 VkDescriptorSetLayout ds_layout;
471 VkPipelineLayout p_layout;
472 VkPipeline occlusion_query_pipeline;
473 VkPipeline pipeline_statistics_query_pipeline;
474 } query;
475 };
476
477 /* queue types */
478 #define RADV_QUEUE_GENERAL 0
479 #define RADV_QUEUE_COMPUTE 1
480 #define RADV_QUEUE_TRANSFER 2
481
482 #define RADV_MAX_QUEUE_FAMILIES 3
483
484 enum ring_type radv_queue_family_to_ring(int f);
485
486 struct radv_queue {
487 VK_LOADER_DATA _loader_data;
488 struct radv_device * device;
489 struct radeon_winsys_ctx *hw_ctx;
490 int queue_family_index;
491 int queue_idx;
492
493 uint32_t scratch_size;
494 uint32_t compute_scratch_size;
495 uint32_t esgs_ring_size;
496 uint32_t gsvs_ring_size;
497 bool has_tess_rings;
498 bool has_sample_positions;
499
500 struct radeon_winsys_bo *scratch_bo;
501 struct radeon_winsys_bo *descriptor_bo;
502 struct radeon_winsys_bo *compute_scratch_bo;
503 struct radeon_winsys_bo *esgs_ring_bo;
504 struct radeon_winsys_bo *gsvs_ring_bo;
505 struct radeon_winsys_bo *tess_factor_ring_bo;
506 struct radeon_winsys_bo *tess_offchip_ring_bo;
507 struct radeon_winsys_cs *initial_preamble_cs;
508 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
509 struct radeon_winsys_cs *continue_preamble_cs;
510 };
511
512 struct radv_device {
513 VK_LOADER_DATA _loader_data;
514
515 VkAllocationCallbacks alloc;
516
517 struct radv_instance * instance;
518 struct radeon_winsys *ws;
519
520 struct radv_meta_state meta_state;
521
522 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
523 int queue_count[RADV_MAX_QUEUE_FAMILIES];
524 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
525
526 bool llvm_supports_spill;
527 bool has_distributed_tess;
528 uint32_t tess_offchip_block_dw_size;
529 uint32_t scratch_waves;
530
531 uint32_t gs_table_depth;
532
533 /* MSAA sample locations.
534 * The first index is the sample index.
535 * The second index is the coordinate: X, Y. */
536 float sample_locations_1x[1][2];
537 float sample_locations_2x[2][2];
538 float sample_locations_4x[4][2];
539 float sample_locations_8x[8][2];
540 float sample_locations_16x[16][2];
541
542 /* CIK and later */
543 uint32_t gfx_init_size_dw;
544 struct radeon_winsys_bo *gfx_init;
545
546 struct radeon_winsys_bo *trace_bo;
547 uint32_t *trace_id_ptr;
548
549 struct radv_physical_device *physical_device;
550
551 /* Backup in-memory cache to be used if the app doesn't provide one */
552 struct radv_pipeline_cache * mem_cache;
553
554 /*
555 * use different counters so MSAA MRTs get consecutive surface indices,
556 * even if MASK is allocated in between.
557 */
558 uint32_t image_mrt_offset_counter;
559 uint32_t fmask_mrt_offset_counter;
560 struct list_head shader_slabs;
561 mtx_t shader_slab_mutex;
562
563 /* For detecting VM faults reported by dmesg. */
564 uint64_t dmesg_timestamp;
565 };
566
567 struct radv_device_memory {
568 struct radeon_winsys_bo *bo;
569 /* for dedicated allocations */
570 struct radv_image *image;
571 struct radv_buffer *buffer;
572 uint32_t type_index;
573 VkDeviceSize map_size;
574 void * map;
575 };
576
577
578 struct radv_descriptor_range {
579 uint64_t va;
580 uint32_t size;
581 };
582
583 struct radv_descriptor_set {
584 const struct radv_descriptor_set_layout *layout;
585 uint32_t size;
586
587 struct radeon_winsys_bo *bo;
588 uint64_t va;
589 uint32_t *mapped_ptr;
590 struct radv_descriptor_range *dynamic_descriptors;
591
592 struct list_head vram_list;
593
594 struct radeon_winsys_bo *descriptors[0];
595 };
596
597 struct radv_push_descriptor_set
598 {
599 struct radv_descriptor_set set;
600 uint32_t capacity;
601 };
602
603 struct radv_descriptor_pool {
604 struct radeon_winsys_bo *bo;
605 uint8_t *mapped_ptr;
606 uint64_t current_offset;
607 uint64_t size;
608
609 struct list_head vram_list;
610
611 uint8_t *host_memory_base;
612 uint8_t *host_memory_ptr;
613 uint8_t *host_memory_end;
614 };
615
616 struct radv_descriptor_update_template_entry {
617 VkDescriptorType descriptor_type;
618
619 /* The number of descriptors to update */
620 uint32_t descriptor_count;
621
622 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
623 uint32_t dst_offset;
624
625 /* In dwords. Not valid/used for dynamic descriptors */
626 uint32_t dst_stride;
627
628 uint32_t buffer_offset;
629
630 /* Only valid for combined image samplers and samplers */
631 uint16_t has_sampler;
632
633 /* In bytes */
634 size_t src_offset;
635 size_t src_stride;
636
637 /* For push descriptors */
638 const uint32_t *immutable_samplers;
639 };
640
641 struct radv_descriptor_update_template {
642 uint32_t entry_count;
643 struct radv_descriptor_update_template_entry entry[0];
644 };
645
646 struct radv_buffer {
647 struct radv_device * device;
648 VkDeviceSize size;
649
650 VkBufferUsageFlags usage;
651 VkBufferCreateFlags flags;
652
653 /* Set when bound */
654 struct radeon_winsys_bo * bo;
655 VkDeviceSize offset;
656 };
657
658
659 enum radv_cmd_dirty_bits {
660 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
661 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
662 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
663 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
664 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
665 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
666 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
667 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
668 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
669 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
670 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
671 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
672 RADV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
673 };
674 typedef uint32_t radv_cmd_dirty_mask_t;
675
676 enum radv_cmd_flush_bits {
677 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
678 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
679 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
680 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
681 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
682 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
683 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
684 /* Same as above, but only writes back and doesn't invalidate */
685 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
686 /* Framebuffer caches */
687 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
688 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
689 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
690 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
691 /* Engine synchronization. */
692 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
693 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
694 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
695 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
696
697 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
698 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
699 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
700 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
701 };
702
703 struct radv_vertex_binding {
704 struct radv_buffer * buffer;
705 VkDeviceSize offset;
706 };
707
708 struct radv_viewport_state {
709 uint32_t count;
710 VkViewport viewports[MAX_VIEWPORTS];
711 };
712
713 struct radv_scissor_state {
714 uint32_t count;
715 VkRect2D scissors[MAX_SCISSORS];
716 };
717
718 struct radv_dynamic_state {
719 struct radv_viewport_state viewport;
720
721 struct radv_scissor_state scissor;
722
723 float line_width;
724
725 struct {
726 float bias;
727 float clamp;
728 float slope;
729 } depth_bias;
730
731 float blend_constants[4];
732
733 struct {
734 float min;
735 float max;
736 } depth_bounds;
737
738 struct {
739 uint32_t front;
740 uint32_t back;
741 } stencil_compare_mask;
742
743 struct {
744 uint32_t front;
745 uint32_t back;
746 } stencil_write_mask;
747
748 struct {
749 uint32_t front;
750 uint32_t back;
751 } stencil_reference;
752 };
753
754 extern const struct radv_dynamic_state default_dynamic_state;
755
756 const char *
757 radv_get_debug_option_name(int id);
758
759 const char *
760 radv_get_perftest_option_name(int id);
761
762 /**
763 * Attachment state when recording a renderpass instance.
764 *
765 * The clear value is valid only if there exists a pending clear.
766 */
767 struct radv_attachment_state {
768 VkImageAspectFlags pending_clear_aspects;
769 uint32_t cleared_views;
770 VkClearValue clear_value;
771 VkImageLayout current_layout;
772 };
773
774 struct radv_cmd_state {
775 bool vb_dirty;
776 radv_cmd_dirty_mask_t dirty;
777 bool push_descriptors_dirty;
778 bool predicating;
779
780 struct radv_pipeline * pipeline;
781 struct radv_pipeline * emitted_pipeline;
782 struct radv_pipeline * compute_pipeline;
783 struct radv_pipeline * emitted_compute_pipeline;
784 struct radv_framebuffer * framebuffer;
785 struct radv_render_pass * pass;
786 const struct radv_subpass * subpass;
787 struct radv_dynamic_state dynamic;
788 struct radv_vertex_binding vertex_bindings[MAX_VBS];
789 struct radv_descriptor_set * descriptors[MAX_SETS];
790 struct radv_attachment_state * attachments;
791 VkRect2D render_area;
792 uint32_t index_type;
793 uint32_t max_index_count;
794 uint64_t index_va;
795 int32_t last_primitive_reset_en;
796 uint32_t last_primitive_reset_index;
797 enum radv_cmd_flush_bits flush_bits;
798 unsigned active_occlusion_queries;
799 float offset_scale;
800 uint32_t descriptors_dirty;
801 uint32_t trace_id;
802 uint32_t last_ia_multi_vgt_param;
803 };
804
805 struct radv_cmd_pool {
806 VkAllocationCallbacks alloc;
807 struct list_head cmd_buffers;
808 struct list_head free_cmd_buffers;
809 uint32_t queue_family_index;
810 };
811
812 struct radv_cmd_buffer_upload {
813 uint8_t *map;
814 unsigned offset;
815 uint64_t size;
816 struct radeon_winsys_bo *upload_bo;
817 struct list_head list;
818 };
819
820 struct radv_cmd_buffer {
821 VK_LOADER_DATA _loader_data;
822
823 struct radv_device * device;
824
825 struct radv_cmd_pool * pool;
826 struct list_head pool_link;
827
828 VkCommandBufferUsageFlags usage_flags;
829 VkCommandBufferLevel level;
830 struct radeon_winsys_cs *cs;
831 struct radv_cmd_state state;
832 uint32_t queue_family_index;
833
834 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
835 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
836 VkShaderStageFlags push_constant_stages;
837 struct radv_push_descriptor_set push_descriptors;
838 struct radv_descriptor_set meta_push_descriptors;
839
840 struct radv_cmd_buffer_upload upload;
841
842 uint32_t scratch_size_needed;
843 uint32_t compute_scratch_size_needed;
844 uint32_t esgs_ring_size_needed;
845 uint32_t gsvs_ring_size_needed;
846 bool tess_rings_needed;
847 bool sample_positions_needed;
848
849 VkResult record_result;
850
851 int ring_offsets_idx; /* just used for verification */
852 uint32_t gfx9_fence_offset;
853 struct radeon_winsys_bo *gfx9_fence_bo;
854 uint32_t gfx9_fence_idx;
855 };
856
857 struct radv_image;
858
859 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
860
861 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
862 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
863
864 void cik_create_gfx_config(struct radv_device *device);
865
866 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
867 int count, const VkViewport *viewports);
868 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
869 int count, const VkRect2D *scissors,
870 const VkViewport *viewports, bool can_use_guardband);
871 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
872 bool instanced_draw, bool indirect_draw,
873 uint32_t draw_vertex_count);
874 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
875 bool predicated,
876 enum chip_class chip_class,
877 bool is_mec,
878 unsigned event, unsigned event_flags,
879 unsigned data_sel,
880 uint64_t va,
881 uint32_t old_fence,
882 uint32_t new_fence);
883
884 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
885 bool predicated,
886 uint64_t va, uint32_t ref,
887 uint32_t mask);
888 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
889 bool predicated,
890 enum chip_class chip_class,
891 uint32_t *fence_ptr, uint64_t va,
892 bool is_mec,
893 enum radv_cmd_flush_bits flush_bits);
894 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
895 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
896 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
897 uint64_t src_va, uint64_t dest_va,
898 uint64_t size);
899 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
900 unsigned size);
901 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
902 uint64_t size, unsigned value);
903 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
904 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
905 struct radv_descriptor_set *set,
906 unsigned idx);
907 bool
908 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
909 unsigned size,
910 unsigned alignment,
911 unsigned *out_offset,
912 void **ptr);
913 void
914 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
915 const struct radv_subpass *subpass,
916 bool transitions);
917 bool
918 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
919 unsigned size, unsigned alignmnet,
920 const void *data, unsigned *out_offset);
921 void
922 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
923 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
924 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
925 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
926 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
927 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
928 unsigned radv_cayman_get_maxdist(int log_samples);
929 void radv_device_init_msaa(struct radv_device *device);
930 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
931 struct radv_image *image,
932 VkClearDepthStencilValue ds_clear_value,
933 VkImageAspectFlags aspects);
934 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
935 struct radv_image *image,
936 int idx,
937 uint32_t color_values[2]);
938 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
939 struct radv_image *image,
940 bool value);
941 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
942 struct radeon_winsys_bo *bo,
943 uint64_t offset, uint64_t size, uint32_t value);
944 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
945 bool radv_get_memory_fd(struct radv_device *device,
946 struct radv_device_memory *memory,
947 int *pFD);
948 /*
949 * Takes x,y,z as exact numbers of invocations, instead of blocks.
950 *
951 * Limitations: Can't call normal dispatch functions without binding or rebinding
952 * the compute pipeline.
953 */
954 void radv_unaligned_dispatch(
955 struct radv_cmd_buffer *cmd_buffer,
956 uint32_t x,
957 uint32_t y,
958 uint32_t z);
959
960 struct radv_event {
961 struct radeon_winsys_bo *bo;
962 uint64_t *map;
963 };
964
965 struct radv_shader_module;
966 struct ac_shader_variant_key;
967
968 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
969 #define RADV_HASH_SHADER_SISCHED (1 << 1)
970 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
971 void
972 radv_hash_shaders(unsigned char *hash,
973 const VkPipelineShaderStageCreateInfo **stages,
974 const struct radv_pipeline_layout *layout,
975 const struct ac_shader_variant_key *keys,
976 uint32_t flags);
977
978 static inline gl_shader_stage
979 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
980 {
981 assert(__builtin_popcount(vk_stage) == 1);
982 return ffs(vk_stage) - 1;
983 }
984
985 static inline VkShaderStageFlagBits
986 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
987 {
988 return (1 << mesa_stage);
989 }
990
991 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
992
993 #define radv_foreach_stage(stage, stage_bits) \
994 for (gl_shader_stage stage, \
995 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
996 stage = __builtin_ffs(__tmp) - 1, __tmp; \
997 __tmp &= ~(1 << (stage)))
998
999 struct radv_depth_stencil_state {
1000 uint32_t db_depth_control;
1001 uint32_t db_stencil_control;
1002 uint32_t db_render_control;
1003 uint32_t db_render_override2;
1004 };
1005
1006 struct radv_blend_state {
1007 uint32_t cb_color_control;
1008 uint32_t cb_target_mask;
1009 uint32_t sx_mrt_blend_opt[8];
1010 uint32_t cb_blend_control[8];
1011
1012 uint32_t spi_shader_col_format;
1013 uint32_t cb_shader_mask;
1014 uint32_t db_alpha_to_mask;
1015 };
1016
1017 unsigned radv_format_meta_fs_key(VkFormat format);
1018
1019 struct radv_raster_state {
1020 uint32_t pa_cl_clip_cntl;
1021 uint32_t spi_interp_control;
1022 uint32_t pa_su_vtx_cntl;
1023 uint32_t pa_su_sc_mode_cntl;
1024 };
1025
1026 struct radv_multisample_state {
1027 uint32_t db_eqaa;
1028 uint32_t pa_sc_line_cntl;
1029 uint32_t pa_sc_mode_cntl_0;
1030 uint32_t pa_sc_mode_cntl_1;
1031 uint32_t pa_sc_aa_config;
1032 uint32_t pa_sc_aa_mask[2];
1033 unsigned num_samples;
1034 };
1035
1036 struct radv_prim_vertex_count {
1037 uint8_t min;
1038 uint8_t incr;
1039 };
1040
1041 struct radv_tessellation_state {
1042 uint32_t ls_hs_config;
1043 uint32_t tcs_in_layout;
1044 uint32_t tcs_out_layout;
1045 uint32_t tcs_out_offsets;
1046 uint32_t offchip_layout;
1047 unsigned num_patches;
1048 unsigned lds_size;
1049 unsigned num_tcs_input_cp;
1050 uint32_t tf_param;
1051 };
1052
1053 struct radv_gs_state {
1054 uint32_t vgt_gs_onchip_cntl;
1055 uint32_t vgt_gs_max_prims_per_subgroup;
1056 uint32_t vgt_esgs_ring_itemsize;
1057 uint32_t lds_size;
1058 };
1059
1060 struct radv_vertex_elements_info {
1061 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1062 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1063 uint32_t binding[MAX_VERTEX_ATTRIBS];
1064 uint32_t offset[MAX_VERTEX_ATTRIBS];
1065 uint32_t count;
1066 };
1067
1068 #define SI_GS_PER_ES 128
1069
1070 struct radv_pipeline {
1071 struct radv_device * device;
1072 uint32_t dynamic_state_mask;
1073 struct radv_dynamic_state dynamic_state;
1074
1075 struct radv_pipeline_layout * layout;
1076
1077 bool needs_data_cache;
1078 bool need_indirect_descriptor_sets;
1079 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1080 struct radv_shader_variant *gs_copy_shader;
1081 VkShaderStageFlags active_stages;
1082
1083 struct radv_vertex_elements_info vertex_elements;
1084
1085 uint32_t binding_stride[MAX_VBS];
1086
1087 union {
1088 struct {
1089 struct radv_blend_state blend;
1090 struct radv_depth_stencil_state ds;
1091 struct radv_raster_state raster;
1092 struct radv_multisample_state ms;
1093 struct radv_tessellation_state tess;
1094 struct radv_gs_state gs;
1095 uint32_t db_shader_control;
1096 uint32_t shader_z_format;
1097 unsigned prim;
1098 unsigned gs_out;
1099 uint32_t vgt_gs_mode;
1100 bool vgt_primitiveid_en;
1101 bool prim_restart_enable;
1102 bool partial_es_wave;
1103 uint8_t primgroup_size;
1104 unsigned esgs_ring_size;
1105 unsigned gsvs_ring_size;
1106 uint32_t ps_input_cntl[32];
1107 uint32_t ps_input_cntl_num;
1108 uint32_t pa_cl_vs_out_cntl;
1109 uint32_t vgt_shader_stages_en;
1110 uint32_t vtx_base_sgpr;
1111 uint32_t base_ia_multi_vgt_param;
1112 bool wd_switch_on_eop;
1113 bool ia_switch_on_eoi;
1114 bool partial_vs_wave;
1115 uint8_t vtx_emit_num;
1116 uint32_t vtx_reuse_depth;
1117 struct radv_prim_vertex_count prim_vertex_count;
1118 bool can_use_guardband;
1119 } graphics;
1120 };
1121
1122 unsigned max_waves;
1123 unsigned scratch_bytes_per_wave;
1124 };
1125
1126 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1127 {
1128 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1129 }
1130
1131 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1132 {
1133 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1134 }
1135
1136 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1137 gl_shader_stage stage,
1138 int idx);
1139
1140 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1141
1142 struct radv_graphics_pipeline_create_info {
1143 bool use_rectlist;
1144 bool db_depth_clear;
1145 bool db_stencil_clear;
1146 bool db_depth_disable_expclear;
1147 bool db_stencil_disable_expclear;
1148 bool db_flush_depth_inplace;
1149 bool db_flush_stencil_inplace;
1150 bool db_resummarize;
1151 uint32_t custom_blend_mode;
1152 };
1153
1154 VkResult
1155 radv_graphics_pipeline_create(VkDevice device,
1156 VkPipelineCache cache,
1157 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1158 const struct radv_graphics_pipeline_create_info *extra,
1159 const VkAllocationCallbacks *alloc,
1160 VkPipeline *pPipeline);
1161
1162 struct vk_format_description;
1163 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1164 int first_non_void);
1165 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1166 int first_non_void);
1167 uint32_t radv_translate_colorformat(VkFormat format);
1168 uint32_t radv_translate_color_numformat(VkFormat format,
1169 const struct vk_format_description *desc,
1170 int first_non_void);
1171 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1172 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1173 uint32_t radv_translate_dbformat(VkFormat format);
1174 uint32_t radv_translate_tex_dataformat(VkFormat format,
1175 const struct vk_format_description *desc,
1176 int first_non_void);
1177 uint32_t radv_translate_tex_numformat(VkFormat format,
1178 const struct vk_format_description *desc,
1179 int first_non_void);
1180 bool radv_format_pack_clear_color(VkFormat format,
1181 uint32_t clear_vals[2],
1182 VkClearColorValue *value);
1183 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1184 bool radv_dcc_formats_compatible(VkFormat format1,
1185 VkFormat format2);
1186
1187 struct radv_fmask_info {
1188 uint64_t offset;
1189 uint64_t size;
1190 unsigned alignment;
1191 unsigned pitch_in_pixels;
1192 unsigned bank_height;
1193 unsigned slice_tile_max;
1194 unsigned tile_mode_index;
1195 unsigned tile_swizzle;
1196 };
1197
1198 struct radv_cmask_info {
1199 uint64_t offset;
1200 uint64_t size;
1201 unsigned alignment;
1202 unsigned slice_tile_max;
1203 unsigned base_address_reg;
1204 };
1205
1206 struct radv_image {
1207 VkImageType type;
1208 /* The original VkFormat provided by the client. This may not match any
1209 * of the actual surface formats.
1210 */
1211 VkFormat vk_format;
1212 VkImageAspectFlags aspects;
1213 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1214 struct ac_surf_info info;
1215 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1216 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1217
1218 VkDeviceSize size;
1219 uint32_t alignment;
1220
1221 unsigned queue_family_mask;
1222 bool exclusive;
1223 bool shareable;
1224
1225 /* Set when bound */
1226 struct radeon_winsys_bo *bo;
1227 VkDeviceSize offset;
1228 uint64_t dcc_offset;
1229 uint64_t htile_offset;
1230 bool tc_compatible_htile;
1231 struct radeon_surf surface;
1232
1233 struct radv_fmask_info fmask;
1234 struct radv_cmask_info cmask;
1235 uint64_t clear_value_offset;
1236 uint64_t dcc_pred_offset;
1237 };
1238
1239 /* Whether the image has a htile that is known consistent with the contents of
1240 * the image. */
1241 bool radv_layout_has_htile(const struct radv_image *image,
1242 VkImageLayout layout,
1243 unsigned queue_mask);
1244
1245 /* Whether the image has a htile that is known consistent with the contents of
1246 * the image and is allowed to be in compressed form.
1247 *
1248 * If this is false reads that don't use the htile should be able to return
1249 * correct results.
1250 */
1251 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1252 VkImageLayout layout,
1253 unsigned queue_mask);
1254
1255 bool radv_layout_can_fast_clear(const struct radv_image *image,
1256 VkImageLayout layout,
1257 unsigned queue_mask);
1258
1259 static inline bool
1260 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1261 {
1262 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1263 }
1264
1265 static inline bool
1266 radv_htile_enabled(const struct radv_image *image, unsigned level)
1267 {
1268 return image->surface.htile_size && level == 0;
1269 }
1270
1271 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1272
1273 static inline uint32_t
1274 radv_get_layerCount(const struct radv_image *image,
1275 const VkImageSubresourceRange *range)
1276 {
1277 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1278 image->info.array_size - range->baseArrayLayer : range->layerCount;
1279 }
1280
1281 static inline uint32_t
1282 radv_get_levelCount(const struct radv_image *image,
1283 const VkImageSubresourceRange *range)
1284 {
1285 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1286 image->info.levels - range->baseMipLevel : range->levelCount;
1287 }
1288
1289 struct radeon_bo_metadata;
1290 void
1291 radv_init_metadata(struct radv_device *device,
1292 struct radv_image *image,
1293 struct radeon_bo_metadata *metadata);
1294
1295 struct radv_image_view {
1296 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1297 struct radeon_winsys_bo *bo;
1298
1299 VkImageViewType type;
1300 VkImageAspectFlags aspect_mask;
1301 VkFormat vk_format;
1302 uint32_t base_layer;
1303 uint32_t layer_count;
1304 uint32_t base_mip;
1305 uint32_t level_count;
1306 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1307
1308 uint32_t descriptor[8];
1309 uint32_t fmask_descriptor[8];
1310
1311 /* Descriptor for use as a storage image as opposed to a sampled image.
1312 * This has a few differences for cube maps (e.g. type).
1313 */
1314 uint32_t storage_descriptor[8];
1315 uint32_t storage_fmask_descriptor[8];
1316 };
1317
1318 struct radv_image_create_info {
1319 const VkImageCreateInfo *vk_info;
1320 bool scanout;
1321 };
1322
1323 VkResult radv_image_create(VkDevice _device,
1324 const struct radv_image_create_info *info,
1325 const VkAllocationCallbacks* alloc,
1326 VkImage *pImage);
1327
1328 void radv_image_view_init(struct radv_image_view *view,
1329 struct radv_device *device,
1330 const VkImageViewCreateInfo* pCreateInfo);
1331
1332 struct radv_buffer_view {
1333 struct radeon_winsys_bo *bo;
1334 VkFormat vk_format;
1335 uint64_t range; /**< VkBufferViewCreateInfo::range */
1336 uint32_t state[4];
1337 };
1338 void radv_buffer_view_init(struct radv_buffer_view *view,
1339 struct radv_device *device,
1340 const VkBufferViewCreateInfo* pCreateInfo);
1341
1342 static inline struct VkExtent3D
1343 radv_sanitize_image_extent(const VkImageType imageType,
1344 const struct VkExtent3D imageExtent)
1345 {
1346 switch (imageType) {
1347 case VK_IMAGE_TYPE_1D:
1348 return (VkExtent3D) { imageExtent.width, 1, 1 };
1349 case VK_IMAGE_TYPE_2D:
1350 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1351 case VK_IMAGE_TYPE_3D:
1352 return imageExtent;
1353 default:
1354 unreachable("invalid image type");
1355 }
1356 }
1357
1358 static inline struct VkOffset3D
1359 radv_sanitize_image_offset(const VkImageType imageType,
1360 const struct VkOffset3D imageOffset)
1361 {
1362 switch (imageType) {
1363 case VK_IMAGE_TYPE_1D:
1364 return (VkOffset3D) { imageOffset.x, 0, 0 };
1365 case VK_IMAGE_TYPE_2D:
1366 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1367 case VK_IMAGE_TYPE_3D:
1368 return imageOffset;
1369 default:
1370 unreachable("invalid image type");
1371 }
1372 }
1373
1374 static inline bool
1375 radv_image_extent_compare(const struct radv_image *image,
1376 const VkExtent3D *extent)
1377 {
1378 if (extent->width != image->info.width ||
1379 extent->height != image->info.height ||
1380 extent->depth != image->info.depth)
1381 return false;
1382 return true;
1383 }
1384
1385 struct radv_sampler {
1386 uint32_t state[4];
1387 };
1388
1389 struct radv_color_buffer_info {
1390 uint64_t cb_color_base;
1391 uint64_t cb_color_cmask;
1392 uint64_t cb_color_fmask;
1393 uint64_t cb_dcc_base;
1394 uint32_t cb_color_pitch;
1395 uint32_t cb_color_slice;
1396 uint32_t cb_color_view;
1397 uint32_t cb_color_info;
1398 uint32_t cb_color_attrib;
1399 uint32_t cb_color_attrib2;
1400 uint32_t cb_dcc_control;
1401 uint32_t cb_color_cmask_slice;
1402 uint32_t cb_color_fmask_slice;
1403 uint32_t cb_clear_value0;
1404 uint32_t cb_clear_value1;
1405 uint32_t micro_tile_mode;
1406 uint32_t gfx9_epitch;
1407 };
1408
1409 struct radv_ds_buffer_info {
1410 uint64_t db_z_read_base;
1411 uint64_t db_stencil_read_base;
1412 uint64_t db_z_write_base;
1413 uint64_t db_stencil_write_base;
1414 uint64_t db_htile_data_base;
1415 uint32_t db_depth_info;
1416 uint32_t db_z_info;
1417 uint32_t db_stencil_info;
1418 uint32_t db_depth_view;
1419 uint32_t db_depth_size;
1420 uint32_t db_depth_slice;
1421 uint32_t db_htile_surface;
1422 uint32_t pa_su_poly_offset_db_fmt_cntl;
1423 uint32_t db_z_info2;
1424 uint32_t db_stencil_info2;
1425 float offset_scale;
1426 };
1427
1428 struct radv_attachment_info {
1429 union {
1430 struct radv_color_buffer_info cb;
1431 struct radv_ds_buffer_info ds;
1432 };
1433 struct radv_image_view *attachment;
1434 };
1435
1436 struct radv_framebuffer {
1437 uint32_t width;
1438 uint32_t height;
1439 uint32_t layers;
1440
1441 uint32_t attachment_count;
1442 struct radv_attachment_info attachments[0];
1443 };
1444
1445 struct radv_subpass_barrier {
1446 VkPipelineStageFlags src_stage_mask;
1447 VkAccessFlags src_access_mask;
1448 VkAccessFlags dst_access_mask;
1449 };
1450
1451 struct radv_subpass {
1452 uint32_t input_count;
1453 uint32_t color_count;
1454 VkAttachmentReference * input_attachments;
1455 VkAttachmentReference * color_attachments;
1456 VkAttachmentReference * resolve_attachments;
1457 VkAttachmentReference depth_stencil_attachment;
1458
1459 /** Subpass has at least one resolve attachment */
1460 bool has_resolve;
1461
1462 struct radv_subpass_barrier start_barrier;
1463
1464 uint32_t view_mask;
1465 };
1466
1467 struct radv_render_pass_attachment {
1468 VkFormat format;
1469 uint32_t samples;
1470 VkAttachmentLoadOp load_op;
1471 VkAttachmentLoadOp stencil_load_op;
1472 VkImageLayout initial_layout;
1473 VkImageLayout final_layout;
1474 uint32_t view_mask;
1475 };
1476
1477 struct radv_render_pass {
1478 uint32_t attachment_count;
1479 uint32_t subpass_count;
1480 VkAttachmentReference * subpass_attachments;
1481 struct radv_render_pass_attachment * attachments;
1482 struct radv_subpass_barrier end_barrier;
1483 struct radv_subpass subpasses[0];
1484 };
1485
1486 VkResult radv_device_init_meta(struct radv_device *device);
1487 void radv_device_finish_meta(struct radv_device *device);
1488
1489 struct radv_query_pool {
1490 struct radeon_winsys_bo *bo;
1491 uint32_t stride;
1492 uint32_t availability_offset;
1493 char *ptr;
1494 VkQueryType type;
1495 uint32_t pipeline_stats_mask;
1496 };
1497
1498 struct radv_semaphore {
1499 /* use a winsys sem for non-exportable */
1500 struct radeon_winsys_sem *sem;
1501 uint32_t syncobj;
1502 uint32_t temp_syncobj;
1503 };
1504
1505 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1506 int num_wait_sems,
1507 const VkSemaphore *wait_sems,
1508 int num_signal_sems,
1509 const VkSemaphore *signal_sems);
1510 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1511
1512 void
1513 radv_update_descriptor_sets(struct radv_device *device,
1514 struct radv_cmd_buffer *cmd_buffer,
1515 VkDescriptorSet overrideSet,
1516 uint32_t descriptorWriteCount,
1517 const VkWriteDescriptorSet *pDescriptorWrites,
1518 uint32_t descriptorCopyCount,
1519 const VkCopyDescriptorSet *pDescriptorCopies);
1520
1521 void
1522 radv_update_descriptor_set_with_template(struct radv_device *device,
1523 struct radv_cmd_buffer *cmd_buffer,
1524 struct radv_descriptor_set *set,
1525 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1526 const void *pData);
1527
1528 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1529 VkPipelineBindPoint pipelineBindPoint,
1530 VkPipelineLayout _layout,
1531 uint32_t set,
1532 uint32_t descriptorWriteCount,
1533 const VkWriteDescriptorSet *pDescriptorWrites);
1534
1535 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1536 struct radv_image *image, uint32_t value);
1537 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1538 struct radv_image *image, uint32_t value);
1539
1540 struct radv_fence {
1541 struct radeon_winsys_fence *fence;
1542 bool submitted;
1543 bool signalled;
1544 };
1545
1546 struct radeon_winsys_sem;
1547
1548 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1549 \
1550 static inline struct __radv_type * \
1551 __radv_type ## _from_handle(__VkType _handle) \
1552 { \
1553 return (struct __radv_type *) _handle; \
1554 } \
1555 \
1556 static inline __VkType \
1557 __radv_type ## _to_handle(struct __radv_type *_obj) \
1558 { \
1559 return (__VkType) _obj; \
1560 }
1561
1562 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1563 \
1564 static inline struct __radv_type * \
1565 __radv_type ## _from_handle(__VkType _handle) \
1566 { \
1567 return (struct __radv_type *)(uintptr_t) _handle; \
1568 } \
1569 \
1570 static inline __VkType \
1571 __radv_type ## _to_handle(struct __radv_type *_obj) \
1572 { \
1573 return (__VkType)(uintptr_t) _obj; \
1574 }
1575
1576 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1577 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1578
1579 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1580 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1581 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1582 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1583 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1584
1585 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1586 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1587 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1588 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1589 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1590 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1591 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1592 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1593 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1594 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1595 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1596 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1597 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1598 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1599 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1600 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1601 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1602 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1603 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1604 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1605 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1606
1607 #endif /* RADV_PRIVATE_H */