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radv: implement image to image operations for R32G32B32
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "ac_llvm_util.h"
62 #include "radv_descriptor_set.h"
63 #include "radv_extensions.h"
64 #include "radv_cs.h"
65
66 #include <llvm-c/TargetMachine.h>
67
68 /* Pre-declarations needed for WSI entrypoints */
69 struct wl_surface;
70 struct wl_display;
71 typedef struct xcb_connection_t xcb_connection_t;
72 typedef uint32_t xcb_visualid_t;
73 typedef uint32_t xcb_window_t;
74
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vk_icd.h>
78 #include <vulkan/vk_android_native_buffer.h>
79
80 #include "radv_entrypoints.h"
81
82 #include "wsi_common.h"
83 #include "wsi_common_display.h"
84
85 #define ATI_VENDOR_ID 0x1002
86
87 #define MAX_VBS 32
88 #define MAX_VERTEX_ATTRIBS 32
89 #define MAX_RTS 8
90 #define MAX_VIEWPORTS 16
91 #define MAX_SCISSORS 16
92 #define MAX_DISCARD_RECTANGLES 4
93 #define MAX_PUSH_CONSTANTS_SIZE 128
94 #define MAX_PUSH_DESCRIPTORS 32
95 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
96 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
97 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
98 #define MAX_SAMPLES_LOG2 4
99 #define NUM_META_FS_KEYS 12
100 #define RADV_MAX_DRM_DEVICES 8
101 #define MAX_VIEWS 8
102
103 #define NUM_DEPTH_CLEAR_PIPELINES 3
104
105 /*
106 * This is the point we switch from using CP to compute shader
107 * for certain buffer operations.
108 */
109 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
110
111 #define RADV_BUFFER_UPDATE_THRESHOLD 1024
112
113 enum radv_mem_heap {
114 RADV_MEM_HEAP_VRAM,
115 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
116 RADV_MEM_HEAP_GTT,
117 RADV_MEM_HEAP_COUNT
118 };
119
120 enum radv_mem_type {
121 RADV_MEM_TYPE_VRAM,
122 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
123 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
124 RADV_MEM_TYPE_GTT_CACHED,
125 RADV_MEM_TYPE_COUNT
126 };
127
128 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
129
130 static inline uint32_t
131 align_u32(uint32_t v, uint32_t a)
132 {
133 assert(a != 0 && a == (a & -a));
134 return (v + a - 1) & ~(a - 1);
135 }
136
137 static inline uint32_t
138 align_u32_npot(uint32_t v, uint32_t a)
139 {
140 return (v + a - 1) / a * a;
141 }
142
143 static inline uint64_t
144 align_u64(uint64_t v, uint64_t a)
145 {
146 assert(a != 0 && a == (a & -a));
147 return (v + a - 1) & ~(a - 1);
148 }
149
150 static inline int32_t
151 align_i32(int32_t v, int32_t a)
152 {
153 assert(a != 0 && a == (a & -a));
154 return (v + a - 1) & ~(a - 1);
155 }
156
157 /** Alignment must be a power of 2. */
158 static inline bool
159 radv_is_aligned(uintmax_t n, uintmax_t a)
160 {
161 assert(a == (a & -a));
162 return (n & (a - 1)) == 0;
163 }
164
165 static inline uint32_t
166 round_up_u32(uint32_t v, uint32_t a)
167 {
168 return (v + a - 1) / a;
169 }
170
171 static inline uint64_t
172 round_up_u64(uint64_t v, uint64_t a)
173 {
174 return (v + a - 1) / a;
175 }
176
177 static inline uint32_t
178 radv_minify(uint32_t n, uint32_t levels)
179 {
180 if (unlikely(n == 0))
181 return 0;
182 else
183 return MAX2(n >> levels, 1);
184 }
185 static inline float
186 radv_clamp_f(float f, float min, float max)
187 {
188 assert(min < max);
189
190 if (f > max)
191 return max;
192 else if (f < min)
193 return min;
194 else
195 return f;
196 }
197
198 static inline bool
199 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
200 {
201 if (*inout_mask & clear_mask) {
202 *inout_mask &= ~clear_mask;
203 return true;
204 } else {
205 return false;
206 }
207 }
208
209 #define for_each_bit(b, dword) \
210 for (uint32_t __dword = (dword); \
211 (b) = __builtin_ffs(__dword) - 1, __dword; \
212 __dword &= ~(1 << (b)))
213
214 #define typed_memcpy(dest, src, count) ({ \
215 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
216 memcpy((dest), (src), (count) * sizeof(*(src))); \
217 })
218
219 /* Whenever we generate an error, pass it through this function. Useful for
220 * debugging, where we can break on it. Only call at error site, not when
221 * propagating errors. Might be useful to plug in a stack trace here.
222 */
223
224 struct radv_instance;
225
226 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
227
228 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
229 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
230
231 void __radv_finishme(const char *file, int line, const char *format, ...)
232 radv_printflike(3, 4);
233 void radv_loge(const char *format, ...) radv_printflike(1, 2);
234 void radv_loge_v(const char *format, va_list va);
235 void radv_logi(const char *format, ...) radv_printflike(1, 2);
236 void radv_logi_v(const char *format, va_list va);
237
238 /**
239 * Print a FINISHME message, including its source location.
240 */
241 #define radv_finishme(format, ...) \
242 do { \
243 static bool reported = false; \
244 if (!reported) { \
245 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
246 reported = true; \
247 } \
248 } while (0)
249
250 /* A non-fatal assert. Useful for debugging. */
251 #ifdef DEBUG
252 #define radv_assert(x) ({ \
253 if (unlikely(!(x))) \
254 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
255 })
256 #else
257 #define radv_assert(x)
258 #endif
259
260 #define stub_return(v) \
261 do { \
262 radv_finishme("stub %s", __func__); \
263 return (v); \
264 } while (0)
265
266 #define stub() \
267 do { \
268 radv_finishme("stub %s", __func__); \
269 return; \
270 } while (0)
271
272 void *radv_lookup_entrypoint_unchecked(const char *name);
273 void *radv_lookup_entrypoint_checked(const char *name,
274 uint32_t core_version,
275 const struct radv_instance_extension_table *instance,
276 const struct radv_device_extension_table *device);
277
278 struct radv_physical_device {
279 VK_LOADER_DATA _loader_data;
280
281 struct radv_instance * instance;
282
283 struct radeon_winsys *ws;
284 struct radeon_info rad_info;
285 char path[20];
286 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
287 uint8_t driver_uuid[VK_UUID_SIZE];
288 uint8_t device_uuid[VK_UUID_SIZE];
289 uint8_t cache_uuid[VK_UUID_SIZE];
290
291 int local_fd;
292 int master_fd;
293 struct wsi_device wsi_device;
294
295 bool has_rbplus; /* if RB+ register exist */
296 bool rbplus_allowed; /* if RB+ is allowed */
297 bool has_clear_state;
298 bool cpdma_prefetch_writes_memory;
299 bool has_scissor_bug;
300
301 bool has_out_of_order_rast;
302 bool out_of_order_rast_allowed;
303
304 /* Whether DCC should be enabled for MSAA textures. */
305 bool dcc_msaa_allowed;
306
307 /* This is the drivers on-disk cache used as a fallback as opposed to
308 * the pipeline cache defined by apps.
309 */
310 struct disk_cache * disk_cache;
311
312 VkPhysicalDeviceMemoryProperties memory_properties;
313 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
314
315 drmPciBusInfo bus_info;
316
317 struct radv_device_extension_table supported_extensions;
318 };
319
320 struct radv_instance {
321 VK_LOADER_DATA _loader_data;
322
323 VkAllocationCallbacks alloc;
324
325 uint32_t apiVersion;
326 int physicalDeviceCount;
327 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
328
329 uint64_t debug_flags;
330 uint64_t perftest_flags;
331
332 struct vk_debug_report_instance debug_report_callbacks;
333
334 struct radv_instance_extension_table enabled_extensions;
335 };
336
337 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
338 void radv_finish_wsi(struct radv_physical_device *physical_device);
339
340 bool radv_instance_extension_supported(const char *name);
341 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
342 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
343 const char *name);
344
345 struct cache_entry;
346
347 struct radv_pipeline_cache {
348 struct radv_device * device;
349 pthread_mutex_t mutex;
350
351 uint32_t total_size;
352 uint32_t table_size;
353 uint32_t kernel_count;
354 struct cache_entry ** hash_table;
355 bool modified;
356
357 VkAllocationCallbacks alloc;
358 };
359
360 struct radv_pipeline_key {
361 uint32_t instance_rate_inputs;
362 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
363 uint64_t vertex_alpha_adjust;
364 unsigned tess_input_vertices;
365 uint32_t col_format;
366 uint32_t is_int8;
367 uint32_t is_int10;
368 uint8_t log2_ps_iter_samples;
369 uint8_t num_samples;
370 uint32_t has_multiview_view_index : 1;
371 uint32_t optimisations_disabled : 1;
372 };
373
374 void
375 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
376 struct radv_device *device);
377 void
378 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
379 bool
380 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
381 const void *data, size_t size);
382
383 struct radv_shader_variant;
384
385 bool
386 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
387 struct radv_pipeline_cache *cache,
388 const unsigned char *sha1,
389 struct radv_shader_variant **variants);
390
391 void
392 radv_pipeline_cache_insert_shaders(struct radv_device *device,
393 struct radv_pipeline_cache *cache,
394 const unsigned char *sha1,
395 struct radv_shader_variant **variants,
396 const void *const *codes,
397 const unsigned *code_sizes);
398
399 enum radv_blit_ds_layout {
400 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
401 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
402 RADV_BLIT_DS_LAYOUT_COUNT,
403 };
404
405 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
406 {
407 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
408 }
409
410 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
411 {
412 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
413 }
414
415 enum radv_meta_dst_layout {
416 RADV_META_DST_LAYOUT_GENERAL,
417 RADV_META_DST_LAYOUT_OPTIMAL,
418 RADV_META_DST_LAYOUT_COUNT,
419 };
420
421 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
422 {
423 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
424 }
425
426 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
427 {
428 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
429 }
430
431 struct radv_meta_state {
432 VkAllocationCallbacks alloc;
433
434 struct radv_pipeline_cache cache;
435
436 /*
437 * For on-demand pipeline creation, makes sure that
438 * only one thread tries to build a pipeline at the same time.
439 */
440 mtx_t mtx;
441
442 /**
443 * Use array element `i` for images with `2^i` samples.
444 */
445 struct {
446 VkRenderPass render_pass[NUM_META_FS_KEYS];
447 VkPipeline color_pipelines[NUM_META_FS_KEYS];
448
449 VkRenderPass depthstencil_rp;
450 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
451 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
452 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
453 } clear[1 + MAX_SAMPLES_LOG2];
454
455 VkPipelineLayout clear_color_p_layout;
456 VkPipelineLayout clear_depth_p_layout;
457 struct {
458 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
459
460 /** Pipeline that blits from a 1D image. */
461 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
462
463 /** Pipeline that blits from a 2D image. */
464 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
465
466 /** Pipeline that blits from a 3D image. */
467 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
468
469 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
470 VkPipeline depth_only_1d_pipeline;
471 VkPipeline depth_only_2d_pipeline;
472 VkPipeline depth_only_3d_pipeline;
473
474 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
475 VkPipeline stencil_only_1d_pipeline;
476 VkPipeline stencil_only_2d_pipeline;
477 VkPipeline stencil_only_3d_pipeline;
478 VkPipelineLayout pipeline_layout;
479 VkDescriptorSetLayout ds_layout;
480 } blit;
481
482 struct {
483 VkPipelineLayout p_layouts[5];
484 VkDescriptorSetLayout ds_layouts[5];
485 VkPipeline pipelines[5][NUM_META_FS_KEYS];
486
487 VkPipeline depth_only_pipeline[5];
488
489 VkPipeline stencil_only_pipeline[5];
490 } blit2d[1 + MAX_SAMPLES_LOG2];
491
492 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
493 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
494 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
495
496 struct {
497 VkPipelineLayout img_p_layout;
498 VkDescriptorSetLayout img_ds_layout;
499 VkPipeline pipeline;
500 VkPipeline pipeline_3d;
501 } itob;
502 struct {
503 VkPipelineLayout img_p_layout;
504 VkDescriptorSetLayout img_ds_layout;
505 VkPipeline pipeline;
506 VkPipeline pipeline_3d;
507 } btoi;
508 struct {
509 VkPipelineLayout img_p_layout;
510 VkDescriptorSetLayout img_ds_layout;
511 VkPipeline pipeline;
512 } btoi_r32g32b32;
513 struct {
514 VkPipelineLayout img_p_layout;
515 VkDescriptorSetLayout img_ds_layout;
516 VkPipeline pipeline;
517 VkPipeline pipeline_3d;
518 } itoi;
519 struct {
520 VkPipelineLayout img_p_layout;
521 VkDescriptorSetLayout img_ds_layout;
522 VkPipeline pipeline;
523 } itoi_r32g32b32;
524 struct {
525 VkPipelineLayout img_p_layout;
526 VkDescriptorSetLayout img_ds_layout;
527 VkPipeline pipeline;
528 VkPipeline pipeline_3d;
529 } cleari;
530 struct {
531 VkPipelineLayout img_p_layout;
532 VkDescriptorSetLayout img_ds_layout;
533 VkPipeline pipeline;
534 } cleari_r32g32b32;
535
536 struct {
537 VkPipelineLayout p_layout;
538 VkPipeline pipeline[NUM_META_FS_KEYS];
539 VkRenderPass pass[NUM_META_FS_KEYS];
540 } resolve;
541
542 struct {
543 VkDescriptorSetLayout ds_layout;
544 VkPipelineLayout p_layout;
545 struct {
546 VkPipeline pipeline;
547 VkPipeline i_pipeline;
548 VkPipeline srgb_pipeline;
549 } rc[MAX_SAMPLES_LOG2];
550 } resolve_compute;
551
552 struct {
553 VkDescriptorSetLayout ds_layout;
554 VkPipelineLayout p_layout;
555
556 struct {
557 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
558 VkPipeline pipeline[NUM_META_FS_KEYS];
559 } rc[MAX_SAMPLES_LOG2];
560 } resolve_fragment;
561
562 struct {
563 VkPipelineLayout p_layout;
564 VkPipeline decompress_pipeline;
565 VkPipeline resummarize_pipeline;
566 VkRenderPass pass;
567 } depth_decomp[1 + MAX_SAMPLES_LOG2];
568
569 struct {
570 VkPipelineLayout p_layout;
571 VkPipeline cmask_eliminate_pipeline;
572 VkPipeline fmask_decompress_pipeline;
573 VkPipeline dcc_decompress_pipeline;
574 VkRenderPass pass;
575
576 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
577 VkPipelineLayout dcc_decompress_compute_p_layout;
578 VkPipeline dcc_decompress_compute_pipeline;
579 } fast_clear_flush;
580
581 struct {
582 VkPipelineLayout fill_p_layout;
583 VkPipelineLayout copy_p_layout;
584 VkDescriptorSetLayout fill_ds_layout;
585 VkDescriptorSetLayout copy_ds_layout;
586 VkPipeline fill_pipeline;
587 VkPipeline copy_pipeline;
588 } buffer;
589
590 struct {
591 VkDescriptorSetLayout ds_layout;
592 VkPipelineLayout p_layout;
593 VkPipeline occlusion_query_pipeline;
594 VkPipeline pipeline_statistics_query_pipeline;
595 } query;
596 };
597
598 /* queue types */
599 #define RADV_QUEUE_GENERAL 0
600 #define RADV_QUEUE_COMPUTE 1
601 #define RADV_QUEUE_TRANSFER 2
602
603 #define RADV_MAX_QUEUE_FAMILIES 3
604
605 enum ring_type radv_queue_family_to_ring(int f);
606
607 struct radv_queue {
608 VK_LOADER_DATA _loader_data;
609 struct radv_device * device;
610 struct radeon_winsys_ctx *hw_ctx;
611 enum radeon_ctx_priority priority;
612 uint32_t queue_family_index;
613 int queue_idx;
614 VkDeviceQueueCreateFlags flags;
615
616 uint32_t scratch_size;
617 uint32_t compute_scratch_size;
618 uint32_t esgs_ring_size;
619 uint32_t gsvs_ring_size;
620 bool has_tess_rings;
621 bool has_sample_positions;
622
623 struct radeon_winsys_bo *scratch_bo;
624 struct radeon_winsys_bo *descriptor_bo;
625 struct radeon_winsys_bo *compute_scratch_bo;
626 struct radeon_winsys_bo *esgs_ring_bo;
627 struct radeon_winsys_bo *gsvs_ring_bo;
628 struct radeon_winsys_bo *tess_rings_bo;
629 struct radeon_cmdbuf *initial_preamble_cs;
630 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
631 struct radeon_cmdbuf *continue_preamble_cs;
632 };
633
634 struct radv_bo_list {
635 struct radv_winsys_bo_list list;
636 unsigned capacity;
637 pthread_mutex_t mutex;
638 };
639
640 struct radv_device {
641 VK_LOADER_DATA _loader_data;
642
643 VkAllocationCallbacks alloc;
644
645 struct radv_instance * instance;
646 struct radeon_winsys *ws;
647
648 struct radv_meta_state meta_state;
649
650 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
651 int queue_count[RADV_MAX_QUEUE_FAMILIES];
652 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
653
654 bool always_use_syncobj;
655 bool has_distributed_tess;
656 bool pbb_allowed;
657 bool dfsm_allowed;
658 uint32_t tess_offchip_block_dw_size;
659 uint32_t scratch_waves;
660 uint32_t dispatch_initiator;
661
662 uint32_t gs_table_depth;
663
664 /* MSAA sample locations.
665 * The first index is the sample index.
666 * The second index is the coordinate: X, Y. */
667 float sample_locations_1x[1][2];
668 float sample_locations_2x[2][2];
669 float sample_locations_4x[4][2];
670 float sample_locations_8x[8][2];
671 float sample_locations_16x[16][2];
672
673 /* CIK and later */
674 uint32_t gfx_init_size_dw;
675 struct radeon_winsys_bo *gfx_init;
676
677 struct radeon_winsys_bo *trace_bo;
678 uint32_t *trace_id_ptr;
679
680 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
681 bool keep_shader_info;
682
683 struct radv_physical_device *physical_device;
684
685 /* Backup in-memory cache to be used if the app doesn't provide one */
686 struct radv_pipeline_cache * mem_cache;
687
688 /*
689 * use different counters so MSAA MRTs get consecutive surface indices,
690 * even if MASK is allocated in between.
691 */
692 uint32_t image_mrt_offset_counter;
693 uint32_t fmask_mrt_offset_counter;
694 struct list_head shader_slabs;
695 mtx_t shader_slab_mutex;
696
697 /* For detecting VM faults reported by dmesg. */
698 uint64_t dmesg_timestamp;
699
700 struct radv_device_extension_table enabled_extensions;
701
702 /* Whether the driver uses a global BO list. */
703 bool use_global_bo_list;
704
705 struct radv_bo_list bo_list;
706
707 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
708 int force_aniso;
709 };
710
711 struct radv_device_memory {
712 struct radeon_winsys_bo *bo;
713 /* for dedicated allocations */
714 struct radv_image *image;
715 struct radv_buffer *buffer;
716 uint32_t type_index;
717 VkDeviceSize map_size;
718 void * map;
719 void * user_ptr;
720 };
721
722
723 struct radv_descriptor_range {
724 uint64_t va;
725 uint32_t size;
726 };
727
728 struct radv_descriptor_set {
729 const struct radv_descriptor_set_layout *layout;
730 uint32_t size;
731
732 struct radeon_winsys_bo *bo;
733 uint64_t va;
734 uint32_t *mapped_ptr;
735 struct radv_descriptor_range *dynamic_descriptors;
736
737 struct radeon_winsys_bo *descriptors[0];
738 };
739
740 struct radv_push_descriptor_set
741 {
742 struct radv_descriptor_set set;
743 uint32_t capacity;
744 };
745
746 struct radv_descriptor_pool_entry {
747 uint32_t offset;
748 uint32_t size;
749 struct radv_descriptor_set *set;
750 };
751
752 struct radv_descriptor_pool {
753 struct radeon_winsys_bo *bo;
754 uint8_t *mapped_ptr;
755 uint64_t current_offset;
756 uint64_t size;
757
758 uint8_t *host_memory_base;
759 uint8_t *host_memory_ptr;
760 uint8_t *host_memory_end;
761
762 uint32_t entry_count;
763 uint32_t max_entry_count;
764 struct radv_descriptor_pool_entry entries[0];
765 };
766
767 struct radv_descriptor_update_template_entry {
768 VkDescriptorType descriptor_type;
769
770 /* The number of descriptors to update */
771 uint32_t descriptor_count;
772
773 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
774 uint32_t dst_offset;
775
776 /* In dwords. Not valid/used for dynamic descriptors */
777 uint32_t dst_stride;
778
779 uint32_t buffer_offset;
780
781 /* Only valid for combined image samplers and samplers */
782 uint16_t has_sampler;
783
784 /* In bytes */
785 size_t src_offset;
786 size_t src_stride;
787
788 /* For push descriptors */
789 const uint32_t *immutable_samplers;
790 };
791
792 struct radv_descriptor_update_template {
793 uint32_t entry_count;
794 VkPipelineBindPoint bind_point;
795 struct radv_descriptor_update_template_entry entry[0];
796 };
797
798 struct radv_buffer {
799 VkDeviceSize size;
800
801 VkBufferUsageFlags usage;
802 VkBufferCreateFlags flags;
803
804 /* Set when bound */
805 struct radeon_winsys_bo * bo;
806 VkDeviceSize offset;
807
808 bool shareable;
809 };
810
811 enum radv_dynamic_state_bits {
812 RADV_DYNAMIC_VIEWPORT = 1 << 0,
813 RADV_DYNAMIC_SCISSOR = 1 << 1,
814 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
815 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
816 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
817 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
818 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
819 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
820 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
821 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
822 RADV_DYNAMIC_ALL = (1 << 10) - 1,
823 };
824
825 enum radv_cmd_dirty_bits {
826 /* Keep the dynamic state dirty bits in sync with
827 * enum radv_dynamic_state_bits */
828 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
829 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
830 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
831 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
832 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
833 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
834 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
835 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
836 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
837 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
838 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
839 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
840 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
841 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
842 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
843 };
844
845 enum radv_cmd_flush_bits {
846 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
847 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
848 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
849 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
850 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
851 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
852 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
853 /* Same as above, but only writes back and doesn't invalidate */
854 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
855 /* Framebuffer caches */
856 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
857 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
858 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
859 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
860 /* Engine synchronization. */
861 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
862 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
863 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
864 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
865 /* Pipeline query controls. */
866 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
867 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
868
869 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
870 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
871 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
872 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
873 };
874
875 struct radv_vertex_binding {
876 struct radv_buffer * buffer;
877 VkDeviceSize offset;
878 };
879
880 struct radv_viewport_state {
881 uint32_t count;
882 VkViewport viewports[MAX_VIEWPORTS];
883 };
884
885 struct radv_scissor_state {
886 uint32_t count;
887 VkRect2D scissors[MAX_SCISSORS];
888 };
889
890 struct radv_discard_rectangle_state {
891 uint32_t count;
892 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
893 };
894
895 struct radv_dynamic_state {
896 /**
897 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
898 * Defines the set of saved dynamic state.
899 */
900 uint32_t mask;
901
902 struct radv_viewport_state viewport;
903
904 struct radv_scissor_state scissor;
905
906 float line_width;
907
908 struct {
909 float bias;
910 float clamp;
911 float slope;
912 } depth_bias;
913
914 float blend_constants[4];
915
916 struct {
917 float min;
918 float max;
919 } depth_bounds;
920
921 struct {
922 uint32_t front;
923 uint32_t back;
924 } stencil_compare_mask;
925
926 struct {
927 uint32_t front;
928 uint32_t back;
929 } stencil_write_mask;
930
931 struct {
932 uint32_t front;
933 uint32_t back;
934 } stencil_reference;
935
936 struct radv_discard_rectangle_state discard_rectangle;
937 };
938
939 extern const struct radv_dynamic_state default_dynamic_state;
940
941 const char *
942 radv_get_debug_option_name(int id);
943
944 const char *
945 radv_get_perftest_option_name(int id);
946
947 /**
948 * Attachment state when recording a renderpass instance.
949 *
950 * The clear value is valid only if there exists a pending clear.
951 */
952 struct radv_attachment_state {
953 VkImageAspectFlags pending_clear_aspects;
954 uint32_t cleared_views;
955 VkClearValue clear_value;
956 VkImageLayout current_layout;
957 };
958
959 struct radv_descriptor_state {
960 struct radv_descriptor_set *sets[MAX_SETS];
961 uint32_t dirty;
962 uint32_t valid;
963 struct radv_push_descriptor_set push_set;
964 bool push_dirty;
965 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
966 };
967
968 struct radv_cmd_state {
969 /* Vertex descriptors */
970 uint64_t vb_va;
971 unsigned vb_size;
972
973 bool predicating;
974 uint32_t dirty;
975
976 uint32_t prefetch_L2_mask;
977
978 struct radv_pipeline * pipeline;
979 struct radv_pipeline * emitted_pipeline;
980 struct radv_pipeline * compute_pipeline;
981 struct radv_pipeline * emitted_compute_pipeline;
982 struct radv_framebuffer * framebuffer;
983 struct radv_render_pass * pass;
984 const struct radv_subpass * subpass;
985 struct radv_dynamic_state dynamic;
986 struct radv_attachment_state * attachments;
987 VkRect2D render_area;
988
989 /* Index buffer */
990 struct radv_buffer *index_buffer;
991 uint64_t index_offset;
992 uint32_t index_type;
993 uint32_t max_index_count;
994 uint64_t index_va;
995 int32_t last_index_type;
996
997 int32_t last_primitive_reset_en;
998 uint32_t last_primitive_reset_index;
999 enum radv_cmd_flush_bits flush_bits;
1000 unsigned active_occlusion_queries;
1001 bool perfect_occlusion_queries_enabled;
1002 unsigned active_pipeline_queries;
1003 float offset_scale;
1004 uint32_t trace_id;
1005 uint32_t last_ia_multi_vgt_param;
1006
1007 uint32_t last_num_instances;
1008 uint32_t last_first_instance;
1009 uint32_t last_vertex_offset;
1010
1011 /* Whether CP DMA is busy/idle. */
1012 bool dma_is_busy;
1013
1014 /* Conditional rendering info. */
1015 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1016 uint64_t predication_va;
1017 };
1018
1019 struct radv_cmd_pool {
1020 VkAllocationCallbacks alloc;
1021 struct list_head cmd_buffers;
1022 struct list_head free_cmd_buffers;
1023 uint32_t queue_family_index;
1024 };
1025
1026 struct radv_cmd_buffer_upload {
1027 uint8_t *map;
1028 unsigned offset;
1029 uint64_t size;
1030 struct radeon_winsys_bo *upload_bo;
1031 struct list_head list;
1032 };
1033
1034 enum radv_cmd_buffer_status {
1035 RADV_CMD_BUFFER_STATUS_INVALID,
1036 RADV_CMD_BUFFER_STATUS_INITIAL,
1037 RADV_CMD_BUFFER_STATUS_RECORDING,
1038 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1039 RADV_CMD_BUFFER_STATUS_PENDING,
1040 };
1041
1042 struct radv_cmd_buffer {
1043 VK_LOADER_DATA _loader_data;
1044
1045 struct radv_device * device;
1046
1047 struct radv_cmd_pool * pool;
1048 struct list_head pool_link;
1049
1050 VkCommandBufferUsageFlags usage_flags;
1051 VkCommandBufferLevel level;
1052 enum radv_cmd_buffer_status status;
1053 struct radeon_cmdbuf *cs;
1054 struct radv_cmd_state state;
1055 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1056 uint32_t queue_family_index;
1057
1058 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1059 VkShaderStageFlags push_constant_stages;
1060 struct radv_descriptor_set meta_push_descriptors;
1061
1062 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1063
1064 struct radv_cmd_buffer_upload upload;
1065
1066 uint32_t scratch_size_needed;
1067 uint32_t compute_scratch_size_needed;
1068 uint32_t esgs_ring_size_needed;
1069 uint32_t gsvs_ring_size_needed;
1070 bool tess_rings_needed;
1071 bool sample_positions_needed;
1072
1073 VkResult record_result;
1074
1075 uint32_t gfx9_fence_offset;
1076 struct radeon_winsys_bo *gfx9_fence_bo;
1077 uint32_t gfx9_fence_idx;
1078 uint64_t gfx9_eop_bug_va;
1079
1080 /**
1081 * Whether a query pool has been resetted and we have to flush caches.
1082 */
1083 bool pending_reset_query;
1084 };
1085
1086 struct radv_image;
1087
1088 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1089
1090 void si_emit_graphics(struct radv_physical_device *physical_device,
1091 struct radeon_cmdbuf *cs);
1092 void si_emit_compute(struct radv_physical_device *physical_device,
1093 struct radeon_cmdbuf *cs);
1094
1095 void cik_create_gfx_config(struct radv_device *device);
1096
1097 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1098 int count, const VkViewport *viewports);
1099 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1100 int count, const VkRect2D *scissors,
1101 const VkViewport *viewports, bool can_use_guardband);
1102 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1103 bool instanced_draw, bool indirect_draw,
1104 uint32_t draw_vertex_count);
1105 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1106 enum chip_class chip_class,
1107 bool is_mec,
1108 unsigned event, unsigned event_flags,
1109 unsigned data_sel,
1110 uint64_t va,
1111 uint32_t old_fence,
1112 uint32_t new_fence,
1113 uint64_t gfx9_eop_bug_va);
1114
1115 void si_emit_wait_fence(struct radeon_cmdbuf *cs,
1116 uint64_t va, uint32_t ref,
1117 uint32_t mask);
1118 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1119 enum chip_class chip_class,
1120 uint32_t *fence_ptr, uint64_t va,
1121 bool is_mec,
1122 enum radv_cmd_flush_bits flush_bits,
1123 uint64_t gfx9_eop_bug_va);
1124 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1125 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1126 bool inverted, uint64_t va);
1127 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1128 uint64_t src_va, uint64_t dest_va,
1129 uint64_t size);
1130 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1131 unsigned size);
1132 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1133 uint64_t size, unsigned value);
1134 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1135
1136 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1137 bool
1138 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1139 unsigned size,
1140 unsigned alignment,
1141 unsigned *out_offset,
1142 void **ptr);
1143 void
1144 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1145 const struct radv_subpass *subpass,
1146 bool transitions);
1147 bool
1148 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1149 unsigned size, unsigned alignmnet,
1150 const void *data, unsigned *out_offset);
1151
1152 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1153 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1154 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1155 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1156 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
1157 unsigned radv_cayman_get_maxdist(int log_samples);
1158 void radv_device_init_msaa(struct radv_device *device);
1159
1160 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1161 struct radv_image *image,
1162 VkClearDepthStencilValue ds_clear_value,
1163 VkImageAspectFlags aspects);
1164
1165 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1166 struct radv_image *image,
1167 int cb_idx,
1168 uint32_t color_values[2]);
1169
1170 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1171 struct radv_image *image,
1172 bool value);
1173 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1174 struct radeon_winsys_bo *bo,
1175 uint64_t offset, uint64_t size, uint32_t value);
1176 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1177 bool radv_get_memory_fd(struct radv_device *device,
1178 struct radv_device_memory *memory,
1179 int *pFD);
1180
1181 static inline void
1182 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1183 unsigned sh_offset, unsigned pointer_count,
1184 bool use_32bit_pointers)
1185 {
1186 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1187 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1188 }
1189
1190 static inline void
1191 radv_emit_shader_pointer_body(struct radv_device *device,
1192 struct radeon_cmdbuf *cs,
1193 uint64_t va, bool use_32bit_pointers)
1194 {
1195 radeon_emit(cs, va);
1196
1197 if (use_32bit_pointers) {
1198 assert(va == 0 ||
1199 (va >> 32) == device->physical_device->rad_info.address32_hi);
1200 } else {
1201 radeon_emit(cs, va >> 32);
1202 }
1203 }
1204
1205 static inline void
1206 radv_emit_shader_pointer(struct radv_device *device,
1207 struct radeon_cmdbuf *cs,
1208 uint32_t sh_offset, uint64_t va, bool global)
1209 {
1210 bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
1211
1212 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1213 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1214 }
1215
1216 static inline struct radv_descriptor_state *
1217 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1218 VkPipelineBindPoint bind_point)
1219 {
1220 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1221 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1222 return &cmd_buffer->descriptors[bind_point];
1223 }
1224
1225 /*
1226 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1227 *
1228 * Limitations: Can't call normal dispatch functions without binding or rebinding
1229 * the compute pipeline.
1230 */
1231 void radv_unaligned_dispatch(
1232 struct radv_cmd_buffer *cmd_buffer,
1233 uint32_t x,
1234 uint32_t y,
1235 uint32_t z);
1236
1237 struct radv_event {
1238 struct radeon_winsys_bo *bo;
1239 uint64_t *map;
1240 };
1241
1242 struct radv_shader_module;
1243
1244 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1245 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1246 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1247 void
1248 radv_hash_shaders(unsigned char *hash,
1249 const VkPipelineShaderStageCreateInfo **stages,
1250 const struct radv_pipeline_layout *layout,
1251 const struct radv_pipeline_key *key,
1252 uint32_t flags);
1253
1254 static inline gl_shader_stage
1255 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1256 {
1257 assert(__builtin_popcount(vk_stage) == 1);
1258 return ffs(vk_stage) - 1;
1259 }
1260
1261 static inline VkShaderStageFlagBits
1262 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1263 {
1264 return (1 << mesa_stage);
1265 }
1266
1267 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1268
1269 #define radv_foreach_stage(stage, stage_bits) \
1270 for (gl_shader_stage stage, \
1271 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1272 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1273 __tmp &= ~(1 << (stage)))
1274
1275 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1276 unsigned radv_format_meta_fs_key(VkFormat format);
1277
1278 struct radv_multisample_state {
1279 uint32_t db_eqaa;
1280 uint32_t pa_sc_line_cntl;
1281 uint32_t pa_sc_mode_cntl_0;
1282 uint32_t pa_sc_mode_cntl_1;
1283 uint32_t pa_sc_aa_config;
1284 uint32_t pa_sc_aa_mask[2];
1285 unsigned num_samples;
1286 };
1287
1288 struct radv_prim_vertex_count {
1289 uint8_t min;
1290 uint8_t incr;
1291 };
1292
1293 struct radv_vertex_elements_info {
1294 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1295 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1296 uint32_t binding[MAX_VERTEX_ATTRIBS];
1297 uint32_t offset[MAX_VERTEX_ATTRIBS];
1298 uint32_t count;
1299 };
1300
1301 struct radv_ia_multi_vgt_param_helpers {
1302 uint32_t base;
1303 bool partial_es_wave;
1304 uint8_t primgroup_size;
1305 bool wd_switch_on_eop;
1306 bool ia_switch_on_eoi;
1307 bool partial_vs_wave;
1308 };
1309
1310 #define SI_GS_PER_ES 128
1311
1312 struct radv_pipeline {
1313 struct radv_device * device;
1314 struct radv_dynamic_state dynamic_state;
1315
1316 struct radv_pipeline_layout * layout;
1317
1318 bool need_indirect_descriptor_sets;
1319 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1320 struct radv_shader_variant *gs_copy_shader;
1321 VkShaderStageFlags active_stages;
1322
1323 struct radeon_cmdbuf cs;
1324
1325 struct radv_vertex_elements_info vertex_elements;
1326
1327 uint32_t binding_stride[MAX_VBS];
1328
1329 uint32_t user_data_0[MESA_SHADER_STAGES];
1330 union {
1331 struct {
1332 struct radv_multisample_state ms;
1333 uint32_t spi_baryc_cntl;
1334 bool prim_restart_enable;
1335 unsigned esgs_ring_size;
1336 unsigned gsvs_ring_size;
1337 uint32_t vtx_base_sgpr;
1338 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1339 uint8_t vtx_emit_num;
1340 struct radv_prim_vertex_count prim_vertex_count;
1341 bool can_use_guardband;
1342 uint32_t needed_dynamic_state;
1343 bool disable_out_of_order_rast_for_occlusion;
1344
1345 /* Used for rbplus */
1346 uint32_t col_format;
1347 uint32_t cb_target_mask;
1348 } graphics;
1349 };
1350
1351 unsigned max_waves;
1352 unsigned scratch_bytes_per_wave;
1353 };
1354
1355 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1356 {
1357 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1358 }
1359
1360 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1361 {
1362 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1363 }
1364
1365 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1366 gl_shader_stage stage,
1367 int idx);
1368
1369 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1370 gl_shader_stage stage);
1371
1372 struct radv_graphics_pipeline_create_info {
1373 bool use_rectlist;
1374 bool db_depth_clear;
1375 bool db_stencil_clear;
1376 bool db_depth_disable_expclear;
1377 bool db_stencil_disable_expclear;
1378 bool db_flush_depth_inplace;
1379 bool db_flush_stencil_inplace;
1380 bool db_resummarize;
1381 uint32_t custom_blend_mode;
1382 };
1383
1384 VkResult
1385 radv_graphics_pipeline_create(VkDevice device,
1386 VkPipelineCache cache,
1387 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1388 const struct radv_graphics_pipeline_create_info *extra,
1389 const VkAllocationCallbacks *alloc,
1390 VkPipeline *pPipeline);
1391
1392 struct vk_format_description;
1393 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1394 int first_non_void);
1395 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1396 int first_non_void);
1397 uint32_t radv_translate_colorformat(VkFormat format);
1398 uint32_t radv_translate_color_numformat(VkFormat format,
1399 const struct vk_format_description *desc,
1400 int first_non_void);
1401 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1402 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1403 uint32_t radv_translate_dbformat(VkFormat format);
1404 uint32_t radv_translate_tex_dataformat(VkFormat format,
1405 const struct vk_format_description *desc,
1406 int first_non_void);
1407 uint32_t radv_translate_tex_numformat(VkFormat format,
1408 const struct vk_format_description *desc,
1409 int first_non_void);
1410 bool radv_format_pack_clear_color(VkFormat format,
1411 uint32_t clear_vals[2],
1412 VkClearColorValue *value);
1413 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1414 bool radv_dcc_formats_compatible(VkFormat format1,
1415 VkFormat format2);
1416
1417 struct radv_fmask_info {
1418 uint64_t offset;
1419 uint64_t size;
1420 unsigned alignment;
1421 unsigned pitch_in_pixels;
1422 unsigned bank_height;
1423 unsigned slice_tile_max;
1424 unsigned tile_mode_index;
1425 unsigned tile_swizzle;
1426 };
1427
1428 struct radv_cmask_info {
1429 uint64_t offset;
1430 uint64_t size;
1431 unsigned alignment;
1432 unsigned slice_tile_max;
1433 };
1434
1435 struct radv_image {
1436 VkImageType type;
1437 /* The original VkFormat provided by the client. This may not match any
1438 * of the actual surface formats.
1439 */
1440 VkFormat vk_format;
1441 VkImageAspectFlags aspects;
1442 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1443 struct ac_surf_info info;
1444 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1445 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1446
1447 VkDeviceSize size;
1448 uint32_t alignment;
1449
1450 unsigned queue_family_mask;
1451 bool exclusive;
1452 bool shareable;
1453
1454 /* Set when bound */
1455 struct radeon_winsys_bo *bo;
1456 VkDeviceSize offset;
1457 uint64_t dcc_offset;
1458 uint64_t htile_offset;
1459 bool tc_compatible_htile;
1460 struct radeon_surf surface;
1461
1462 struct radv_fmask_info fmask;
1463 struct radv_cmask_info cmask;
1464 uint64_t clear_value_offset;
1465 uint64_t dcc_pred_offset;
1466
1467 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1468 VkDeviceMemory owned_memory;
1469 };
1470
1471 /* Whether the image has a htile that is known consistent with the contents of
1472 * the image. */
1473 bool radv_layout_has_htile(const struct radv_image *image,
1474 VkImageLayout layout,
1475 unsigned queue_mask);
1476
1477 /* Whether the image has a htile that is known consistent with the contents of
1478 * the image and is allowed to be in compressed form.
1479 *
1480 * If this is false reads that don't use the htile should be able to return
1481 * correct results.
1482 */
1483 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1484 VkImageLayout layout,
1485 unsigned queue_mask);
1486
1487 bool radv_layout_can_fast_clear(const struct radv_image *image,
1488 VkImageLayout layout,
1489 unsigned queue_mask);
1490
1491 bool radv_layout_dcc_compressed(const struct radv_image *image,
1492 VkImageLayout layout,
1493 unsigned queue_mask);
1494
1495 /**
1496 * Return whether the image has CMASK metadata for color surfaces.
1497 */
1498 static inline bool
1499 radv_image_has_cmask(const struct radv_image *image)
1500 {
1501 return image->cmask.size;
1502 }
1503
1504 /**
1505 * Return whether the image has FMASK metadata for color surfaces.
1506 */
1507 static inline bool
1508 radv_image_has_fmask(const struct radv_image *image)
1509 {
1510 return image->fmask.size;
1511 }
1512
1513 /**
1514 * Return whether the image has DCC metadata for color surfaces.
1515 */
1516 static inline bool
1517 radv_image_has_dcc(const struct radv_image *image)
1518 {
1519 return image->surface.dcc_size;
1520 }
1521
1522 /**
1523 * Return whether DCC metadata is enabled for a level.
1524 */
1525 static inline bool
1526 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1527 {
1528 return radv_image_has_dcc(image) &&
1529 level < image->surface.num_dcc_levels;
1530 }
1531
1532 /**
1533 * Return whether the image has CB metadata.
1534 */
1535 static inline bool
1536 radv_image_has_CB_metadata(const struct radv_image *image)
1537 {
1538 return radv_image_has_cmask(image) ||
1539 radv_image_has_fmask(image) ||
1540 radv_image_has_dcc(image);
1541 }
1542
1543 /**
1544 * Return whether the image has HTILE metadata for depth surfaces.
1545 */
1546 static inline bool
1547 radv_image_has_htile(const struct radv_image *image)
1548 {
1549 return image->surface.htile_size;
1550 }
1551
1552 /**
1553 * Return whether HTILE metadata is enabled for a level.
1554 */
1555 static inline bool
1556 radv_htile_enabled(const struct radv_image *image, unsigned level)
1557 {
1558 return radv_image_has_htile(image) && level == 0;
1559 }
1560
1561 /**
1562 * Return whether the image is TC-compatible HTILE.
1563 */
1564 static inline bool
1565 radv_image_is_tc_compat_htile(const struct radv_image *image)
1566 {
1567 return radv_image_has_htile(image) && image->tc_compatible_htile;
1568 }
1569
1570 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1571
1572 static inline uint32_t
1573 radv_get_layerCount(const struct radv_image *image,
1574 const VkImageSubresourceRange *range)
1575 {
1576 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1577 image->info.array_size - range->baseArrayLayer : range->layerCount;
1578 }
1579
1580 static inline uint32_t
1581 radv_get_levelCount(const struct radv_image *image,
1582 const VkImageSubresourceRange *range)
1583 {
1584 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1585 image->info.levels - range->baseMipLevel : range->levelCount;
1586 }
1587
1588 struct radeon_bo_metadata;
1589 void
1590 radv_init_metadata(struct radv_device *device,
1591 struct radv_image *image,
1592 struct radeon_bo_metadata *metadata);
1593
1594 struct radv_image_view {
1595 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1596 struct radeon_winsys_bo *bo;
1597
1598 VkImageViewType type;
1599 VkImageAspectFlags aspect_mask;
1600 VkFormat vk_format;
1601 uint32_t base_layer;
1602 uint32_t layer_count;
1603 uint32_t base_mip;
1604 uint32_t level_count;
1605 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1606
1607 uint32_t descriptor[16];
1608
1609 /* Descriptor for use as a storage image as opposed to a sampled image.
1610 * This has a few differences for cube maps (e.g. type).
1611 */
1612 uint32_t storage_descriptor[16];
1613 };
1614
1615 struct radv_image_create_info {
1616 const VkImageCreateInfo *vk_info;
1617 bool scanout;
1618 bool no_metadata_planes;
1619 };
1620
1621 VkResult radv_image_create(VkDevice _device,
1622 const struct radv_image_create_info *info,
1623 const VkAllocationCallbacks* alloc,
1624 VkImage *pImage);
1625
1626 VkResult
1627 radv_image_from_gralloc(VkDevice device_h,
1628 const VkImageCreateInfo *base_info,
1629 const VkNativeBufferANDROID *gralloc_info,
1630 const VkAllocationCallbacks *alloc,
1631 VkImage *out_image_h);
1632
1633 void radv_image_view_init(struct radv_image_view *view,
1634 struct radv_device *device,
1635 const VkImageViewCreateInfo* pCreateInfo);
1636
1637 struct radv_buffer_view {
1638 struct radeon_winsys_bo *bo;
1639 VkFormat vk_format;
1640 uint64_t range; /**< VkBufferViewCreateInfo::range */
1641 uint32_t state[4];
1642 };
1643 void radv_buffer_view_init(struct radv_buffer_view *view,
1644 struct radv_device *device,
1645 const VkBufferViewCreateInfo* pCreateInfo);
1646
1647 static inline struct VkExtent3D
1648 radv_sanitize_image_extent(const VkImageType imageType,
1649 const struct VkExtent3D imageExtent)
1650 {
1651 switch (imageType) {
1652 case VK_IMAGE_TYPE_1D:
1653 return (VkExtent3D) { imageExtent.width, 1, 1 };
1654 case VK_IMAGE_TYPE_2D:
1655 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1656 case VK_IMAGE_TYPE_3D:
1657 return imageExtent;
1658 default:
1659 unreachable("invalid image type");
1660 }
1661 }
1662
1663 static inline struct VkOffset3D
1664 radv_sanitize_image_offset(const VkImageType imageType,
1665 const struct VkOffset3D imageOffset)
1666 {
1667 switch (imageType) {
1668 case VK_IMAGE_TYPE_1D:
1669 return (VkOffset3D) { imageOffset.x, 0, 0 };
1670 case VK_IMAGE_TYPE_2D:
1671 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1672 case VK_IMAGE_TYPE_3D:
1673 return imageOffset;
1674 default:
1675 unreachable("invalid image type");
1676 }
1677 }
1678
1679 static inline bool
1680 radv_image_extent_compare(const struct radv_image *image,
1681 const VkExtent3D *extent)
1682 {
1683 if (extent->width != image->info.width ||
1684 extent->height != image->info.height ||
1685 extent->depth != image->info.depth)
1686 return false;
1687 return true;
1688 }
1689
1690 struct radv_sampler {
1691 uint32_t state[4];
1692 };
1693
1694 struct radv_color_buffer_info {
1695 uint64_t cb_color_base;
1696 uint64_t cb_color_cmask;
1697 uint64_t cb_color_fmask;
1698 uint64_t cb_dcc_base;
1699 uint32_t cb_color_pitch;
1700 uint32_t cb_color_slice;
1701 uint32_t cb_color_view;
1702 uint32_t cb_color_info;
1703 uint32_t cb_color_attrib;
1704 uint32_t cb_color_attrib2;
1705 uint32_t cb_dcc_control;
1706 uint32_t cb_color_cmask_slice;
1707 uint32_t cb_color_fmask_slice;
1708 };
1709
1710 struct radv_ds_buffer_info {
1711 uint64_t db_z_read_base;
1712 uint64_t db_stencil_read_base;
1713 uint64_t db_z_write_base;
1714 uint64_t db_stencil_write_base;
1715 uint64_t db_htile_data_base;
1716 uint32_t db_depth_info;
1717 uint32_t db_z_info;
1718 uint32_t db_stencil_info;
1719 uint32_t db_depth_view;
1720 uint32_t db_depth_size;
1721 uint32_t db_depth_slice;
1722 uint32_t db_htile_surface;
1723 uint32_t pa_su_poly_offset_db_fmt_cntl;
1724 uint32_t db_z_info2;
1725 uint32_t db_stencil_info2;
1726 float offset_scale;
1727 };
1728
1729 struct radv_attachment_info {
1730 union {
1731 struct radv_color_buffer_info cb;
1732 struct radv_ds_buffer_info ds;
1733 };
1734 struct radv_image_view *attachment;
1735 };
1736
1737 struct radv_framebuffer {
1738 uint32_t width;
1739 uint32_t height;
1740 uint32_t layers;
1741
1742 uint32_t attachment_count;
1743 struct radv_attachment_info attachments[0];
1744 };
1745
1746 struct radv_subpass_barrier {
1747 VkPipelineStageFlags src_stage_mask;
1748 VkAccessFlags src_access_mask;
1749 VkAccessFlags dst_access_mask;
1750 };
1751
1752 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1753 const struct radv_subpass_barrier *barrier);
1754
1755 struct radv_subpass_attachment {
1756 uint32_t attachment;
1757 VkImageLayout layout;
1758 };
1759
1760 struct radv_subpass {
1761 uint32_t input_count;
1762 uint32_t color_count;
1763 struct radv_subpass_attachment * input_attachments;
1764 struct radv_subpass_attachment * color_attachments;
1765 struct radv_subpass_attachment * resolve_attachments;
1766 struct radv_subpass_attachment depth_stencil_attachment;
1767
1768 /** Subpass has at least one resolve attachment */
1769 bool has_resolve;
1770
1771 struct radv_subpass_barrier start_barrier;
1772
1773 uint32_t view_mask;
1774 VkSampleCountFlagBits max_sample_count;
1775 };
1776
1777 struct radv_render_pass_attachment {
1778 VkFormat format;
1779 uint32_t samples;
1780 VkAttachmentLoadOp load_op;
1781 VkAttachmentLoadOp stencil_load_op;
1782 VkImageLayout initial_layout;
1783 VkImageLayout final_layout;
1784 uint32_t view_mask;
1785 };
1786
1787 struct radv_render_pass {
1788 uint32_t attachment_count;
1789 uint32_t subpass_count;
1790 struct radv_subpass_attachment * subpass_attachments;
1791 struct radv_render_pass_attachment * attachments;
1792 struct radv_subpass_barrier end_barrier;
1793 struct radv_subpass subpasses[0];
1794 };
1795
1796 VkResult radv_device_init_meta(struct radv_device *device);
1797 void radv_device_finish_meta(struct radv_device *device);
1798
1799 struct radv_query_pool {
1800 struct radeon_winsys_bo *bo;
1801 uint32_t stride;
1802 uint32_t availability_offset;
1803 uint64_t size;
1804 char *ptr;
1805 VkQueryType type;
1806 uint32_t pipeline_stats_mask;
1807 };
1808
1809 struct radv_semaphore {
1810 /* use a winsys sem for non-exportable */
1811 struct radeon_winsys_sem *sem;
1812 uint32_t syncobj;
1813 uint32_t temp_syncobj;
1814 };
1815
1816 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1817 VkPipelineBindPoint bind_point,
1818 struct radv_descriptor_set *set,
1819 unsigned idx);
1820
1821 void
1822 radv_update_descriptor_sets(struct radv_device *device,
1823 struct radv_cmd_buffer *cmd_buffer,
1824 VkDescriptorSet overrideSet,
1825 uint32_t descriptorWriteCount,
1826 const VkWriteDescriptorSet *pDescriptorWrites,
1827 uint32_t descriptorCopyCount,
1828 const VkCopyDescriptorSet *pDescriptorCopies);
1829
1830 void
1831 radv_update_descriptor_set_with_template(struct radv_device *device,
1832 struct radv_cmd_buffer *cmd_buffer,
1833 struct radv_descriptor_set *set,
1834 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1835 const void *pData);
1836
1837 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1838 VkPipelineBindPoint pipelineBindPoint,
1839 VkPipelineLayout _layout,
1840 uint32_t set,
1841 uint32_t descriptorWriteCount,
1842 const VkWriteDescriptorSet *pDescriptorWrites);
1843
1844 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1845 struct radv_image *image, uint32_t value);
1846
1847 struct radv_fence {
1848 struct radeon_winsys_fence *fence;
1849 struct wsi_fence *fence_wsi;
1850 bool submitted;
1851 bool signalled;
1852
1853 uint32_t syncobj;
1854 uint32_t temp_syncobj;
1855 };
1856
1857 /* radv_nir_to_llvm.c */
1858 struct radv_shader_variant_info;
1859 struct radv_nir_compiler_options;
1860
1861 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
1862 struct nir_shader *geom_shader,
1863 struct ac_shader_binary *binary,
1864 struct ac_shader_config *config,
1865 struct radv_shader_variant_info *shader_info,
1866 const struct radv_nir_compiler_options *option);
1867
1868 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
1869 struct ac_shader_binary *binary,
1870 struct ac_shader_config *config,
1871 struct radv_shader_variant_info *shader_info,
1872 struct nir_shader *const *nir,
1873 int nir_count,
1874 const struct radv_nir_compiler_options *options);
1875
1876 /* radv_shader_info.h */
1877 struct radv_shader_info;
1878
1879 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1880 const struct radv_nir_compiler_options *options,
1881 struct radv_shader_info *info);
1882
1883 struct radeon_winsys_sem;
1884
1885 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1886 \
1887 static inline struct __radv_type * \
1888 __radv_type ## _from_handle(__VkType _handle) \
1889 { \
1890 return (struct __radv_type *) _handle; \
1891 } \
1892 \
1893 static inline __VkType \
1894 __radv_type ## _to_handle(struct __radv_type *_obj) \
1895 { \
1896 return (__VkType) _obj; \
1897 }
1898
1899 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1900 \
1901 static inline struct __radv_type * \
1902 __radv_type ## _from_handle(__VkType _handle) \
1903 { \
1904 return (struct __radv_type *)(uintptr_t) _handle; \
1905 } \
1906 \
1907 static inline __VkType \
1908 __radv_type ## _to_handle(struct __radv_type *_obj) \
1909 { \
1910 return (__VkType)(uintptr_t) _obj; \
1911 }
1912
1913 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1914 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1915
1916 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1917 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1918 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1919 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1920 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1921
1922 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1923 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1924 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1925 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1926 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1927 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1928 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1929 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1930 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1931 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1932 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1933 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1934 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1935 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1936 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1937 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1938 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1939 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1940 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1941 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1942 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1943
1944 #endif /* RADV_PRIVATE_H */