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Revert "radv: Don't store buffer references in the descriptor set."
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "radv_descriptor_set.h"
61 #include "radv_extensions.h"
62
63 #include <llvm-c/TargetMachine.h>
64
65 /* Pre-declarations needed for WSI entrypoints */
66 struct wl_surface;
67 struct wl_display;
68 typedef struct xcb_connection_t xcb_connection_t;
69 typedef uint32_t xcb_visualid_t;
70 typedef uint32_t xcb_window_t;
71
72 #include <vulkan/vulkan.h>
73 #include <vulkan/vulkan_intel.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vk_android_native_buffer.h>
76
77 #include "radv_entrypoints.h"
78
79 #include "wsi_common.h"
80
81 #define ATI_VENDOR_ID 0x1002
82
83 #define MAX_VBS 32
84 #define MAX_VERTEX_ATTRIBS 32
85 #define MAX_RTS 8
86 #define MAX_VIEWPORTS 16
87 #define MAX_SCISSORS 16
88 #define MAX_DISCARD_RECTANGLES 4
89 #define MAX_PUSH_CONSTANTS_SIZE 128
90 #define MAX_PUSH_DESCRIPTORS 32
91 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
92 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
93 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
94 #define MAX_SAMPLES_LOG2 4
95 #define NUM_META_FS_KEYS 13
96 #define RADV_MAX_DRM_DEVICES 8
97 #define MAX_VIEWS 8
98
99 #define NUM_DEPTH_CLEAR_PIPELINES 3
100
101 /*
102 * This is the point we switch from using CP to compute shader
103 * for certain buffer operations.
104 */
105 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
106
107 enum radv_mem_heap {
108 RADV_MEM_HEAP_VRAM,
109 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
110 RADV_MEM_HEAP_GTT,
111 RADV_MEM_HEAP_COUNT
112 };
113
114 enum radv_mem_type {
115 RADV_MEM_TYPE_VRAM,
116 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
117 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
118 RADV_MEM_TYPE_GTT_CACHED,
119 RADV_MEM_TYPE_COUNT
120 };
121
122 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
123
124 static inline uint32_t
125 align_u32(uint32_t v, uint32_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 static inline uint32_t
132 align_u32_npot(uint32_t v, uint32_t a)
133 {
134 return (v + a - 1) / a * a;
135 }
136
137 static inline uint64_t
138 align_u64(uint64_t v, uint64_t a)
139 {
140 assert(a != 0 && a == (a & -a));
141 return (v + a - 1) & ~(a - 1);
142 }
143
144 static inline int32_t
145 align_i32(int32_t v, int32_t a)
146 {
147 assert(a != 0 && a == (a & -a));
148 return (v + a - 1) & ~(a - 1);
149 }
150
151 /** Alignment must be a power of 2. */
152 static inline bool
153 radv_is_aligned(uintmax_t n, uintmax_t a)
154 {
155 assert(a == (a & -a));
156 return (n & (a - 1)) == 0;
157 }
158
159 static inline uint32_t
160 round_up_u32(uint32_t v, uint32_t a)
161 {
162 return (v + a - 1) / a;
163 }
164
165 static inline uint64_t
166 round_up_u64(uint64_t v, uint64_t a)
167 {
168 return (v + a - 1) / a;
169 }
170
171 static inline uint32_t
172 radv_minify(uint32_t n, uint32_t levels)
173 {
174 if (unlikely(n == 0))
175 return 0;
176 else
177 return MAX2(n >> levels, 1);
178 }
179 static inline float
180 radv_clamp_f(float f, float min, float max)
181 {
182 assert(min < max);
183
184 if (f > max)
185 return max;
186 else if (f < min)
187 return min;
188 else
189 return f;
190 }
191
192 static inline bool
193 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
194 {
195 if (*inout_mask & clear_mask) {
196 *inout_mask &= ~clear_mask;
197 return true;
198 } else {
199 return false;
200 }
201 }
202
203 #define for_each_bit(b, dword) \
204 for (uint32_t __dword = (dword); \
205 (b) = __builtin_ffs(__dword) - 1, __dword; \
206 __dword &= ~(1 << (b)))
207
208 #define typed_memcpy(dest, src, count) ({ \
209 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
210 memcpy((dest), (src), (count) * sizeof(*(src))); \
211 })
212
213 /* Whenever we generate an error, pass it through this function. Useful for
214 * debugging, where we can break on it. Only call at error site, not when
215 * propagating errors. Might be useful to plug in a stack trace here.
216 */
217
218 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
219
220 #ifdef DEBUG
221 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
222 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
223 #else
224 #define vk_error(error) error
225 #define vk_errorf(error, format, ...) error
226 #endif
227
228 void __radv_finishme(const char *file, int line, const char *format, ...)
229 radv_printflike(3, 4);
230 void radv_loge(const char *format, ...) radv_printflike(1, 2);
231 void radv_loge_v(const char *format, va_list va);
232
233 /**
234 * Print a FINISHME message, including its source location.
235 */
236 #define radv_finishme(format, ...) \
237 do { \
238 static bool reported = false; \
239 if (!reported) { \
240 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
241 reported = true; \
242 } \
243 } while (0)
244
245 /* A non-fatal assert. Useful for debugging. */
246 #ifdef DEBUG
247 #define radv_assert(x) ({ \
248 if (unlikely(!(x))) \
249 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
250 })
251 #else
252 #define radv_assert(x)
253 #endif
254
255 #define stub_return(v) \
256 do { \
257 radv_finishme("stub %s", __func__); \
258 return (v); \
259 } while (0)
260
261 #define stub() \
262 do { \
263 radv_finishme("stub %s", __func__); \
264 return; \
265 } while (0)
266
267 void *radv_lookup_entrypoint_unchecked(const char *name);
268 void *radv_lookup_entrypoint_checked(const char *name,
269 uint32_t core_version,
270 const struct radv_instance_extension_table *instance,
271 const struct radv_device_extension_table *device);
272
273 struct radv_physical_device {
274 VK_LOADER_DATA _loader_data;
275
276 struct radv_instance * instance;
277
278 struct radeon_winsys *ws;
279 struct radeon_info rad_info;
280 char path[20];
281 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
282 uint8_t driver_uuid[VK_UUID_SIZE];
283 uint8_t device_uuid[VK_UUID_SIZE];
284 uint8_t cache_uuid[VK_UUID_SIZE];
285
286 int local_fd;
287 struct wsi_device wsi_device;
288
289 bool has_rbplus; /* if RB+ register exist */
290 bool rbplus_allowed; /* if RB+ is allowed */
291 bool has_clear_state;
292 bool cpdma_prefetch_writes_memory;
293 bool has_scissor_bug;
294
295 bool has_out_of_order_rast;
296 bool out_of_order_rast_allowed;
297
298 /* Whether DCC should be enabled for MSAA textures. */
299 bool dcc_msaa_allowed;
300
301 /* This is the drivers on-disk cache used as a fallback as opposed to
302 * the pipeline cache defined by apps.
303 */
304 struct disk_cache * disk_cache;
305
306 VkPhysicalDeviceMemoryProperties memory_properties;
307 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
308
309 struct radv_device_extension_table supported_extensions;
310 };
311
312 struct radv_instance {
313 VK_LOADER_DATA _loader_data;
314
315 VkAllocationCallbacks alloc;
316
317 uint32_t apiVersion;
318 int physicalDeviceCount;
319 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
320
321 uint64_t debug_flags;
322 uint64_t perftest_flags;
323
324 struct vk_debug_report_instance debug_report_callbacks;
325
326 struct radv_instance_extension_table enabled_extensions;
327 };
328
329 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
330 void radv_finish_wsi(struct radv_physical_device *physical_device);
331
332 bool radv_instance_extension_supported(const char *name);
333 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
334 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
335 const char *name);
336
337 struct cache_entry;
338
339 struct radv_pipeline_cache {
340 struct radv_device * device;
341 pthread_mutex_t mutex;
342
343 uint32_t total_size;
344 uint32_t table_size;
345 uint32_t kernel_count;
346 struct cache_entry ** hash_table;
347 bool modified;
348
349 VkAllocationCallbacks alloc;
350 };
351
352 struct radv_pipeline_key {
353 uint32_t instance_rate_inputs;
354 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
355 unsigned tess_input_vertices;
356 uint32_t col_format;
357 uint32_t is_int8;
358 uint32_t is_int10;
359 uint8_t log2_ps_iter_samples;
360 uint8_t log2_num_samples;
361 uint32_t multisample : 1;
362 uint32_t has_multiview_view_index : 1;
363 };
364
365 void
366 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
367 struct radv_device *device);
368 void
369 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
370 void
371 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
372 const void *data, size_t size);
373
374 struct radv_shader_variant;
375
376 bool
377 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
378 struct radv_pipeline_cache *cache,
379 const unsigned char *sha1,
380 struct radv_shader_variant **variants);
381
382 void
383 radv_pipeline_cache_insert_shaders(struct radv_device *device,
384 struct radv_pipeline_cache *cache,
385 const unsigned char *sha1,
386 struct radv_shader_variant **variants,
387 const void *const *codes,
388 const unsigned *code_sizes);
389
390 enum radv_blit_ds_layout {
391 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
392 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
393 RADV_BLIT_DS_LAYOUT_COUNT,
394 };
395
396 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
397 {
398 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
399 }
400
401 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
402 {
403 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
404 }
405
406 enum radv_meta_dst_layout {
407 RADV_META_DST_LAYOUT_GENERAL,
408 RADV_META_DST_LAYOUT_OPTIMAL,
409 RADV_META_DST_LAYOUT_COUNT,
410 };
411
412 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
413 {
414 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
415 }
416
417 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
418 {
419 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
420 }
421
422 struct radv_meta_state {
423 VkAllocationCallbacks alloc;
424
425 struct radv_pipeline_cache cache;
426
427 /**
428 * Use array element `i` for images with `2^i` samples.
429 */
430 struct {
431 VkRenderPass render_pass[NUM_META_FS_KEYS];
432 VkPipeline color_pipelines[NUM_META_FS_KEYS];
433
434 VkRenderPass depthstencil_rp;
435 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
436 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
437 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
438 } clear[1 + MAX_SAMPLES_LOG2];
439
440 VkPipelineLayout clear_color_p_layout;
441 VkPipelineLayout clear_depth_p_layout;
442 struct {
443 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
444
445 /** Pipeline that blits from a 1D image. */
446 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
447
448 /** Pipeline that blits from a 2D image. */
449 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
450
451 /** Pipeline that blits from a 3D image. */
452 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
453
454 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
455 VkPipeline depth_only_1d_pipeline;
456 VkPipeline depth_only_2d_pipeline;
457 VkPipeline depth_only_3d_pipeline;
458
459 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
460 VkPipeline stencil_only_1d_pipeline;
461 VkPipeline stencil_only_2d_pipeline;
462 VkPipeline stencil_only_3d_pipeline;
463 VkPipelineLayout pipeline_layout;
464 VkDescriptorSetLayout ds_layout;
465 } blit;
466
467 struct {
468 VkRenderPass render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
469
470 VkPipelineLayout p_layouts[3];
471 VkDescriptorSetLayout ds_layouts[3];
472 VkPipeline pipelines[3][NUM_META_FS_KEYS];
473
474 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
475 VkPipeline depth_only_pipeline[3];
476
477 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
478 VkPipeline stencil_only_pipeline[3];
479 } blit2d;
480
481 struct {
482 VkPipelineLayout img_p_layout;
483 VkDescriptorSetLayout img_ds_layout;
484 VkPipeline pipeline;
485 VkPipeline pipeline_3d;
486 } itob;
487 struct {
488 VkPipelineLayout img_p_layout;
489 VkDescriptorSetLayout img_ds_layout;
490 VkPipeline pipeline;
491 VkPipeline pipeline_3d;
492 } btoi;
493 struct {
494 VkPipelineLayout img_p_layout;
495 VkDescriptorSetLayout img_ds_layout;
496 VkPipeline pipeline;
497 VkPipeline pipeline_3d;
498 } itoi;
499 struct {
500 VkPipelineLayout img_p_layout;
501 VkDescriptorSetLayout img_ds_layout;
502 VkPipeline pipeline;
503 VkPipeline pipeline_3d;
504 } cleari;
505
506 struct {
507 VkPipelineLayout p_layout;
508 VkPipeline pipeline[NUM_META_FS_KEYS];
509 VkRenderPass pass[NUM_META_FS_KEYS];
510 } resolve;
511
512 struct {
513 VkDescriptorSetLayout ds_layout;
514 VkPipelineLayout p_layout;
515 struct {
516 VkPipeline pipeline;
517 VkPipeline i_pipeline;
518 VkPipeline srgb_pipeline;
519 } rc[MAX_SAMPLES_LOG2];
520 } resolve_compute;
521
522 struct {
523 VkDescriptorSetLayout ds_layout;
524 VkPipelineLayout p_layout;
525
526 struct {
527 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
528 VkPipeline pipeline[NUM_META_FS_KEYS];
529 } rc[MAX_SAMPLES_LOG2];
530 } resolve_fragment;
531
532 struct {
533 VkPipelineLayout p_layout;
534 VkPipeline decompress_pipeline;
535 VkPipeline resummarize_pipeline;
536 VkRenderPass pass;
537 } depth_decomp[1 + MAX_SAMPLES_LOG2];
538
539 struct {
540 VkPipelineLayout p_layout;
541 VkPipeline cmask_eliminate_pipeline;
542 VkPipeline fmask_decompress_pipeline;
543 VkPipeline dcc_decompress_pipeline;
544 VkRenderPass pass;
545
546 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
547 VkPipelineLayout dcc_decompress_compute_p_layout;
548 VkPipeline dcc_decompress_compute_pipeline;
549 } fast_clear_flush;
550
551 struct {
552 VkPipelineLayout fill_p_layout;
553 VkPipelineLayout copy_p_layout;
554 VkDescriptorSetLayout fill_ds_layout;
555 VkDescriptorSetLayout copy_ds_layout;
556 VkPipeline fill_pipeline;
557 VkPipeline copy_pipeline;
558 } buffer;
559
560 struct {
561 VkDescriptorSetLayout ds_layout;
562 VkPipelineLayout p_layout;
563 VkPipeline occlusion_query_pipeline;
564 VkPipeline pipeline_statistics_query_pipeline;
565 } query;
566 };
567
568 /* queue types */
569 #define RADV_QUEUE_GENERAL 0
570 #define RADV_QUEUE_COMPUTE 1
571 #define RADV_QUEUE_TRANSFER 2
572
573 #define RADV_MAX_QUEUE_FAMILIES 3
574
575 enum ring_type radv_queue_family_to_ring(int f);
576
577 struct radv_queue {
578 VK_LOADER_DATA _loader_data;
579 struct radv_device * device;
580 struct radeon_winsys_ctx *hw_ctx;
581 enum radeon_ctx_priority priority;
582 uint32_t queue_family_index;
583 int queue_idx;
584 VkDeviceQueueCreateFlags flags;
585
586 uint32_t scratch_size;
587 uint32_t compute_scratch_size;
588 uint32_t esgs_ring_size;
589 uint32_t gsvs_ring_size;
590 bool has_tess_rings;
591 bool has_sample_positions;
592
593 struct radeon_winsys_bo *scratch_bo;
594 struct radeon_winsys_bo *descriptor_bo;
595 struct radeon_winsys_bo *compute_scratch_bo;
596 struct radeon_winsys_bo *esgs_ring_bo;
597 struct radeon_winsys_bo *gsvs_ring_bo;
598 struct radeon_winsys_bo *tess_rings_bo;
599 struct radeon_winsys_cs *initial_preamble_cs;
600 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
601 struct radeon_winsys_cs *continue_preamble_cs;
602 };
603
604 struct radv_bo_list {
605 struct radv_winsys_bo_list list;
606 unsigned capacity;
607 pthread_mutex_t mutex;
608 };
609
610 struct radv_device {
611 VK_LOADER_DATA _loader_data;
612
613 VkAllocationCallbacks alloc;
614
615 struct radv_instance * instance;
616 struct radeon_winsys *ws;
617
618 struct radv_meta_state meta_state;
619
620 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
621 int queue_count[RADV_MAX_QUEUE_FAMILIES];
622 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
623
624 bool always_use_syncobj;
625 bool llvm_supports_spill;
626 bool has_distributed_tess;
627 bool pbb_allowed;
628 bool dfsm_allowed;
629 uint32_t tess_offchip_block_dw_size;
630 uint32_t scratch_waves;
631 uint32_t dispatch_initiator;
632
633 uint32_t gs_table_depth;
634
635 /* MSAA sample locations.
636 * The first index is the sample index.
637 * The second index is the coordinate: X, Y. */
638 float sample_locations_1x[1][2];
639 float sample_locations_2x[2][2];
640 float sample_locations_4x[4][2];
641 float sample_locations_8x[8][2];
642 float sample_locations_16x[16][2];
643
644 /* CIK and later */
645 uint32_t gfx_init_size_dw;
646 struct radeon_winsys_bo *gfx_init;
647
648 struct radeon_winsys_bo *trace_bo;
649 uint32_t *trace_id_ptr;
650
651 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
652 bool keep_shader_info;
653
654 struct radv_physical_device *physical_device;
655
656 /* Backup in-memory cache to be used if the app doesn't provide one */
657 struct radv_pipeline_cache * mem_cache;
658
659 /*
660 * use different counters so MSAA MRTs get consecutive surface indices,
661 * even if MASK is allocated in between.
662 */
663 uint32_t image_mrt_offset_counter;
664 uint32_t fmask_mrt_offset_counter;
665 struct list_head shader_slabs;
666 mtx_t shader_slab_mutex;
667
668 /* For detecting VM faults reported by dmesg. */
669 uint64_t dmesg_timestamp;
670
671 struct radv_device_extension_table enabled_extensions;
672
673 struct radv_bo_list bo_list;
674 };
675
676 struct radv_device_memory {
677 struct radeon_winsys_bo *bo;
678 /* for dedicated allocations */
679 struct radv_image *image;
680 struct radv_buffer *buffer;
681 uint32_t type_index;
682 VkDeviceSize map_size;
683 void * map;
684 void * user_ptr;
685 };
686
687
688 struct radv_descriptor_range {
689 uint64_t va;
690 uint32_t size;
691 };
692
693 struct radv_descriptor_set {
694 const struct radv_descriptor_set_layout *layout;
695 uint32_t size;
696
697 struct radeon_winsys_bo *bo;
698 uint64_t va;
699 uint32_t *mapped_ptr;
700 struct radv_descriptor_range *dynamic_descriptors;
701
702 struct radeon_winsys_bo *descriptors[0];
703 };
704
705 struct radv_push_descriptor_set
706 {
707 struct radv_descriptor_set set;
708 uint32_t capacity;
709 };
710
711 struct radv_descriptor_pool_entry {
712 uint32_t offset;
713 uint32_t size;
714 struct radv_descriptor_set *set;
715 };
716
717 struct radv_descriptor_pool {
718 struct radeon_winsys_bo *bo;
719 uint8_t *mapped_ptr;
720 uint64_t current_offset;
721 uint64_t size;
722
723 uint8_t *host_memory_base;
724 uint8_t *host_memory_ptr;
725 uint8_t *host_memory_end;
726
727 uint32_t entry_count;
728 uint32_t max_entry_count;
729 struct radv_descriptor_pool_entry entries[0];
730 };
731
732 struct radv_descriptor_update_template_entry {
733 VkDescriptorType descriptor_type;
734
735 /* The number of descriptors to update */
736 uint32_t descriptor_count;
737
738 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
739 uint32_t dst_offset;
740
741 /* In dwords. Not valid/used for dynamic descriptors */
742 uint32_t dst_stride;
743
744 uint32_t buffer_offset;
745
746 /* Only valid for combined image samplers and samplers */
747 uint16_t has_sampler;
748
749 /* In bytes */
750 size_t src_offset;
751 size_t src_stride;
752
753 /* For push descriptors */
754 const uint32_t *immutable_samplers;
755 };
756
757 struct radv_descriptor_update_template {
758 uint32_t entry_count;
759 VkPipelineBindPoint bind_point;
760 struct radv_descriptor_update_template_entry entry[0];
761 };
762
763 struct radv_buffer {
764 VkDeviceSize size;
765
766 VkBufferUsageFlags usage;
767 VkBufferCreateFlags flags;
768
769 /* Set when bound */
770 struct radeon_winsys_bo * bo;
771 VkDeviceSize offset;
772
773 bool shareable;
774 };
775
776 enum radv_dynamic_state_bits {
777 RADV_DYNAMIC_VIEWPORT = 1 << 0,
778 RADV_DYNAMIC_SCISSOR = 1 << 1,
779 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
780 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
781 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
782 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
783 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
784 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
785 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
786 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
787 RADV_DYNAMIC_ALL = (1 << 10) - 1,
788 };
789
790 enum radv_cmd_dirty_bits {
791 /* Keep the dynamic state dirty bits in sync with
792 * enum radv_dynamic_state_bits */
793 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
794 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
795 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
796 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
797 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
798 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
799 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
800 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
801 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
802 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
803 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
804 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
805 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
806 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
807 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
808 };
809
810 enum radv_cmd_flush_bits {
811 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
812 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
813 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
814 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
815 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
816 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
817 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
818 /* Same as above, but only writes back and doesn't invalidate */
819 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
820 /* Framebuffer caches */
821 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
822 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
823 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
824 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
825 /* Engine synchronization. */
826 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
827 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
828 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
829 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
830
831 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
832 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
833 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
834 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
835 };
836
837 struct radv_vertex_binding {
838 struct radv_buffer * buffer;
839 VkDeviceSize offset;
840 };
841
842 struct radv_viewport_state {
843 uint32_t count;
844 VkViewport viewports[MAX_VIEWPORTS];
845 };
846
847 struct radv_scissor_state {
848 uint32_t count;
849 VkRect2D scissors[MAX_SCISSORS];
850 };
851
852 struct radv_discard_rectangle_state {
853 uint32_t count;
854 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
855 };
856
857 struct radv_dynamic_state {
858 /**
859 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
860 * Defines the set of saved dynamic state.
861 */
862 uint32_t mask;
863
864 struct radv_viewport_state viewport;
865
866 struct radv_scissor_state scissor;
867
868 float line_width;
869
870 struct {
871 float bias;
872 float clamp;
873 float slope;
874 } depth_bias;
875
876 float blend_constants[4];
877
878 struct {
879 float min;
880 float max;
881 } depth_bounds;
882
883 struct {
884 uint32_t front;
885 uint32_t back;
886 } stencil_compare_mask;
887
888 struct {
889 uint32_t front;
890 uint32_t back;
891 } stencil_write_mask;
892
893 struct {
894 uint32_t front;
895 uint32_t back;
896 } stencil_reference;
897
898 struct radv_discard_rectangle_state discard_rectangle;
899 };
900
901 extern const struct radv_dynamic_state default_dynamic_state;
902
903 const char *
904 radv_get_debug_option_name(int id);
905
906 const char *
907 radv_get_perftest_option_name(int id);
908
909 /**
910 * Attachment state when recording a renderpass instance.
911 *
912 * The clear value is valid only if there exists a pending clear.
913 */
914 struct radv_attachment_state {
915 VkImageAspectFlags pending_clear_aspects;
916 uint32_t cleared_views;
917 VkClearValue clear_value;
918 VkImageLayout current_layout;
919 };
920
921 struct radv_descriptor_state {
922 struct radv_descriptor_set *sets[MAX_SETS];
923 uint32_t dirty;
924 uint32_t valid;
925 struct radv_push_descriptor_set push_set;
926 bool push_dirty;
927 };
928
929 struct radv_cmd_state {
930 /* Vertex descriptors */
931 uint64_t vb_va;
932 unsigned vb_size;
933
934 bool predicating;
935 uint32_t dirty;
936
937 uint32_t prefetch_L2_mask;
938
939 struct radv_pipeline * pipeline;
940 struct radv_pipeline * emitted_pipeline;
941 struct radv_pipeline * compute_pipeline;
942 struct radv_pipeline * emitted_compute_pipeline;
943 struct radv_framebuffer * framebuffer;
944 struct radv_render_pass * pass;
945 const struct radv_subpass * subpass;
946 struct radv_dynamic_state dynamic;
947 struct radv_attachment_state * attachments;
948 VkRect2D render_area;
949
950 /* Index buffer */
951 struct radv_buffer *index_buffer;
952 uint64_t index_offset;
953 uint32_t index_type;
954 uint32_t max_index_count;
955 uint64_t index_va;
956 int32_t last_index_type;
957
958 int32_t last_primitive_reset_en;
959 uint32_t last_primitive_reset_index;
960 enum radv_cmd_flush_bits flush_bits;
961 unsigned active_occlusion_queries;
962 bool perfect_occlusion_queries_enabled;
963 float offset_scale;
964 uint32_t trace_id;
965 uint32_t last_ia_multi_vgt_param;
966
967 uint32_t last_num_instances;
968 uint32_t last_first_instance;
969 uint32_t last_vertex_offset;
970 };
971
972 struct radv_cmd_pool {
973 VkAllocationCallbacks alloc;
974 struct list_head cmd_buffers;
975 struct list_head free_cmd_buffers;
976 uint32_t queue_family_index;
977 };
978
979 struct radv_cmd_buffer_upload {
980 uint8_t *map;
981 unsigned offset;
982 uint64_t size;
983 struct radeon_winsys_bo *upload_bo;
984 struct list_head list;
985 };
986
987 enum radv_cmd_buffer_status {
988 RADV_CMD_BUFFER_STATUS_INVALID,
989 RADV_CMD_BUFFER_STATUS_INITIAL,
990 RADV_CMD_BUFFER_STATUS_RECORDING,
991 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
992 RADV_CMD_BUFFER_STATUS_PENDING,
993 };
994
995 struct radv_cmd_buffer {
996 VK_LOADER_DATA _loader_data;
997
998 struct radv_device * device;
999
1000 struct radv_cmd_pool * pool;
1001 struct list_head pool_link;
1002
1003 VkCommandBufferUsageFlags usage_flags;
1004 VkCommandBufferLevel level;
1005 enum radv_cmd_buffer_status status;
1006 struct radeon_winsys_cs *cs;
1007 struct radv_cmd_state state;
1008 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1009 uint32_t queue_family_index;
1010
1011 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1012 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1013 VkShaderStageFlags push_constant_stages;
1014 struct radv_descriptor_set meta_push_descriptors;
1015
1016 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1017
1018 struct radv_cmd_buffer_upload upload;
1019
1020 uint32_t scratch_size_needed;
1021 uint32_t compute_scratch_size_needed;
1022 uint32_t esgs_ring_size_needed;
1023 uint32_t gsvs_ring_size_needed;
1024 bool tess_rings_needed;
1025 bool sample_positions_needed;
1026
1027 VkResult record_result;
1028
1029 int ring_offsets_idx; /* just used for verification */
1030 uint32_t gfx9_fence_offset;
1031 struct radeon_winsys_bo *gfx9_fence_bo;
1032 uint32_t gfx9_fence_idx;
1033
1034 /**
1035 * Whether a query pool has been resetted and we have to flush caches.
1036 */
1037 bool pending_reset_query;
1038 };
1039
1040 struct radv_image;
1041
1042 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1043
1044 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
1045 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
1046
1047 void cik_create_gfx_config(struct radv_device *device);
1048
1049 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
1050 int count, const VkViewport *viewports);
1051 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
1052 int count, const VkRect2D *scissors,
1053 const VkViewport *viewports, bool can_use_guardband);
1054 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1055 bool instanced_draw, bool indirect_draw,
1056 uint32_t draw_vertex_count);
1057 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
1058 bool predicated,
1059 enum chip_class chip_class,
1060 bool is_mec,
1061 unsigned event, unsigned event_flags,
1062 unsigned data_sel,
1063 uint64_t va,
1064 uint32_t old_fence,
1065 uint32_t new_fence);
1066
1067 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
1068 bool predicated,
1069 uint64_t va, uint32_t ref,
1070 uint32_t mask);
1071 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
1072 enum chip_class chip_class,
1073 uint32_t *fence_ptr, uint64_t va,
1074 bool is_mec,
1075 enum radv_cmd_flush_bits flush_bits);
1076 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1077 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1078 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1079 uint64_t src_va, uint64_t dest_va,
1080 uint64_t size);
1081 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1082 unsigned size);
1083 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1084 uint64_t size, unsigned value);
1085 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1086 bool
1087 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1088 unsigned size,
1089 unsigned alignment,
1090 unsigned *out_offset,
1091 void **ptr);
1092 void
1093 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1094 const struct radv_subpass *subpass,
1095 bool transitions);
1096 bool
1097 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1098 unsigned size, unsigned alignmnet,
1099 const void *data, unsigned *out_offset);
1100
1101 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1102 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1103 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1104 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1105 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1106 unsigned radv_cayman_get_maxdist(int log_samples);
1107 void radv_device_init_msaa(struct radv_device *device);
1108 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1109 struct radv_image *image,
1110 VkClearDepthStencilValue ds_clear_value,
1111 VkImageAspectFlags aspects);
1112 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1113 struct radv_image *image,
1114 int idx,
1115 uint32_t color_values[2]);
1116 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1117 struct radv_image *image,
1118 bool value);
1119 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1120 struct radeon_winsys_bo *bo,
1121 uint64_t offset, uint64_t size, uint32_t value);
1122 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1123 bool radv_get_memory_fd(struct radv_device *device,
1124 struct radv_device_memory *memory,
1125 int *pFD);
1126
1127 static inline struct radv_descriptor_state *
1128 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1129 VkPipelineBindPoint bind_point)
1130 {
1131 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1132 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1133 return &cmd_buffer->descriptors[bind_point];
1134 }
1135
1136 /*
1137 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1138 *
1139 * Limitations: Can't call normal dispatch functions without binding or rebinding
1140 * the compute pipeline.
1141 */
1142 void radv_unaligned_dispatch(
1143 struct radv_cmd_buffer *cmd_buffer,
1144 uint32_t x,
1145 uint32_t y,
1146 uint32_t z);
1147
1148 struct radv_event {
1149 struct radeon_winsys_bo *bo;
1150 uint64_t *map;
1151 };
1152
1153 struct radv_shader_module;
1154
1155 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1156 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1157 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1158 void
1159 radv_hash_shaders(unsigned char *hash,
1160 const VkPipelineShaderStageCreateInfo **stages,
1161 const struct radv_pipeline_layout *layout,
1162 const struct radv_pipeline_key *key,
1163 uint32_t flags);
1164
1165 static inline gl_shader_stage
1166 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1167 {
1168 assert(__builtin_popcount(vk_stage) == 1);
1169 return ffs(vk_stage) - 1;
1170 }
1171
1172 static inline VkShaderStageFlagBits
1173 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1174 {
1175 return (1 << mesa_stage);
1176 }
1177
1178 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1179
1180 #define radv_foreach_stage(stage, stage_bits) \
1181 for (gl_shader_stage stage, \
1182 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1183 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1184 __tmp &= ~(1 << (stage)))
1185
1186 unsigned radv_format_meta_fs_key(VkFormat format);
1187
1188 struct radv_multisample_state {
1189 uint32_t db_eqaa;
1190 uint32_t pa_sc_line_cntl;
1191 uint32_t pa_sc_mode_cntl_0;
1192 uint32_t pa_sc_mode_cntl_1;
1193 uint32_t pa_sc_aa_config;
1194 uint32_t pa_sc_aa_mask[2];
1195 unsigned num_samples;
1196 };
1197
1198 struct radv_prim_vertex_count {
1199 uint8_t min;
1200 uint8_t incr;
1201 };
1202
1203 struct radv_vertex_elements_info {
1204 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1205 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1206 uint32_t binding[MAX_VERTEX_ATTRIBS];
1207 uint32_t offset[MAX_VERTEX_ATTRIBS];
1208 uint32_t count;
1209 };
1210
1211 struct radv_ia_multi_vgt_param_helpers {
1212 uint32_t base;
1213 bool partial_es_wave;
1214 uint8_t primgroup_size;
1215 bool wd_switch_on_eop;
1216 bool ia_switch_on_eoi;
1217 bool partial_vs_wave;
1218 };
1219
1220 #define SI_GS_PER_ES 128
1221
1222 struct radv_pipeline {
1223 struct radv_device * device;
1224 struct radv_dynamic_state dynamic_state;
1225
1226 struct radv_pipeline_layout * layout;
1227
1228 bool need_indirect_descriptor_sets;
1229 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1230 struct radv_shader_variant *gs_copy_shader;
1231 VkShaderStageFlags active_stages;
1232
1233 struct radeon_winsys_cs cs;
1234
1235 struct radv_vertex_elements_info vertex_elements;
1236
1237 uint32_t binding_stride[MAX_VBS];
1238
1239 uint32_t user_data_0[MESA_SHADER_STAGES];
1240 union {
1241 struct {
1242 struct radv_multisample_state ms;
1243 uint32_t spi_baryc_cntl;
1244 bool prim_restart_enable;
1245 unsigned esgs_ring_size;
1246 unsigned gsvs_ring_size;
1247 uint32_t vtx_base_sgpr;
1248 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1249 uint8_t vtx_emit_num;
1250 struct radv_prim_vertex_count prim_vertex_count;
1251 bool can_use_guardband;
1252 uint32_t needed_dynamic_state;
1253 bool disable_out_of_order_rast_for_occlusion;
1254
1255 /* Used for rbplus */
1256 uint32_t col_format;
1257 uint32_t cb_target_mask;
1258 } graphics;
1259 };
1260
1261 unsigned max_waves;
1262 unsigned scratch_bytes_per_wave;
1263 };
1264
1265 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1266 {
1267 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1268 }
1269
1270 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1271 {
1272 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1273 }
1274
1275 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1276 gl_shader_stage stage,
1277 int idx);
1278
1279 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1280
1281 struct radv_graphics_pipeline_create_info {
1282 bool use_rectlist;
1283 bool db_depth_clear;
1284 bool db_stencil_clear;
1285 bool db_depth_disable_expclear;
1286 bool db_stencil_disable_expclear;
1287 bool db_flush_depth_inplace;
1288 bool db_flush_stencil_inplace;
1289 bool db_resummarize;
1290 uint32_t custom_blend_mode;
1291 };
1292
1293 VkResult
1294 radv_graphics_pipeline_create(VkDevice device,
1295 VkPipelineCache cache,
1296 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1297 const struct radv_graphics_pipeline_create_info *extra,
1298 const VkAllocationCallbacks *alloc,
1299 VkPipeline *pPipeline);
1300
1301 struct vk_format_description;
1302 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1303 int first_non_void);
1304 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1305 int first_non_void);
1306 uint32_t radv_translate_colorformat(VkFormat format);
1307 uint32_t radv_translate_color_numformat(VkFormat format,
1308 const struct vk_format_description *desc,
1309 int first_non_void);
1310 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1311 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1312 uint32_t radv_translate_dbformat(VkFormat format);
1313 uint32_t radv_translate_tex_dataformat(VkFormat format,
1314 const struct vk_format_description *desc,
1315 int first_non_void);
1316 uint32_t radv_translate_tex_numformat(VkFormat format,
1317 const struct vk_format_description *desc,
1318 int first_non_void);
1319 bool radv_format_pack_clear_color(VkFormat format,
1320 uint32_t clear_vals[2],
1321 VkClearColorValue *value);
1322 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1323 bool radv_dcc_formats_compatible(VkFormat format1,
1324 VkFormat format2);
1325
1326 struct radv_fmask_info {
1327 uint64_t offset;
1328 uint64_t size;
1329 unsigned alignment;
1330 unsigned pitch_in_pixels;
1331 unsigned bank_height;
1332 unsigned slice_tile_max;
1333 unsigned tile_mode_index;
1334 unsigned tile_swizzle;
1335 };
1336
1337 struct radv_cmask_info {
1338 uint64_t offset;
1339 uint64_t size;
1340 unsigned alignment;
1341 unsigned slice_tile_max;
1342 };
1343
1344 struct radv_image {
1345 VkImageType type;
1346 /* The original VkFormat provided by the client. This may not match any
1347 * of the actual surface formats.
1348 */
1349 VkFormat vk_format;
1350 VkImageAspectFlags aspects;
1351 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1352 struct ac_surf_info info;
1353 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1354 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1355
1356 VkDeviceSize size;
1357 uint32_t alignment;
1358
1359 unsigned queue_family_mask;
1360 bool exclusive;
1361 bool shareable;
1362
1363 /* Set when bound */
1364 struct radeon_winsys_bo *bo;
1365 VkDeviceSize offset;
1366 uint64_t dcc_offset;
1367 uint64_t htile_offset;
1368 bool tc_compatible_htile;
1369 struct radeon_surf surface;
1370
1371 struct radv_fmask_info fmask;
1372 struct radv_cmask_info cmask;
1373 uint64_t clear_value_offset;
1374 uint64_t dcc_pred_offset;
1375
1376 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1377 VkDeviceMemory owned_memory;
1378 };
1379
1380 /* Whether the image has a htile that is known consistent with the contents of
1381 * the image. */
1382 bool radv_layout_has_htile(const struct radv_image *image,
1383 VkImageLayout layout,
1384 unsigned queue_mask);
1385
1386 /* Whether the image has a htile that is known consistent with the contents of
1387 * the image and is allowed to be in compressed form.
1388 *
1389 * If this is false reads that don't use the htile should be able to return
1390 * correct results.
1391 */
1392 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1393 VkImageLayout layout,
1394 unsigned queue_mask);
1395
1396 bool radv_layout_can_fast_clear(const struct radv_image *image,
1397 VkImageLayout layout,
1398 unsigned queue_mask);
1399
1400 bool radv_layout_dcc_compressed(const struct radv_image *image,
1401 VkImageLayout layout,
1402 unsigned queue_mask);
1403
1404 /**
1405 * Return whether the image has CMASK metadata for color surfaces.
1406 */
1407 static inline bool
1408 radv_image_has_cmask(const struct radv_image *image)
1409 {
1410 return image->cmask.size;
1411 }
1412
1413 /**
1414 * Return whether the image has FMASK metadata for color surfaces.
1415 */
1416 static inline bool
1417 radv_image_has_fmask(const struct radv_image *image)
1418 {
1419 return image->fmask.size;
1420 }
1421
1422 /**
1423 * Return whether the image has DCC metadata for color surfaces.
1424 */
1425 static inline bool
1426 radv_image_has_dcc(const struct radv_image *image)
1427 {
1428 return image->surface.dcc_size;
1429 }
1430
1431 /**
1432 * Return whether DCC metadata is enabled for a level.
1433 */
1434 static inline bool
1435 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1436 {
1437 return radv_image_has_dcc(image) &&
1438 level < image->surface.num_dcc_levels;
1439 }
1440
1441 /**
1442 * Return whether the image has HTILE metadata for depth surfaces.
1443 */
1444 static inline bool
1445 radv_image_has_htile(const struct radv_image *image)
1446 {
1447 return image->surface.htile_size;
1448 }
1449
1450 /**
1451 * Return whether HTILE metadata is enabled for a level.
1452 */
1453 static inline bool
1454 radv_htile_enabled(const struct radv_image *image, unsigned level)
1455 {
1456 return radv_image_has_htile(image) && level == 0;
1457 }
1458
1459 /**
1460 * Return whether the image is TC-compatible HTILE.
1461 */
1462 static inline bool
1463 radv_image_is_tc_compat_htile(const struct radv_image *image)
1464 {
1465 return radv_image_has_htile(image) && image->tc_compatible_htile;
1466 }
1467
1468 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1469
1470 static inline uint32_t
1471 radv_get_layerCount(const struct radv_image *image,
1472 const VkImageSubresourceRange *range)
1473 {
1474 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1475 image->info.array_size - range->baseArrayLayer : range->layerCount;
1476 }
1477
1478 static inline uint32_t
1479 radv_get_levelCount(const struct radv_image *image,
1480 const VkImageSubresourceRange *range)
1481 {
1482 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1483 image->info.levels - range->baseMipLevel : range->levelCount;
1484 }
1485
1486 struct radeon_bo_metadata;
1487 void
1488 radv_init_metadata(struct radv_device *device,
1489 struct radv_image *image,
1490 struct radeon_bo_metadata *metadata);
1491
1492 struct radv_image_view {
1493 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1494 struct radeon_winsys_bo *bo;
1495
1496 VkImageViewType type;
1497 VkImageAspectFlags aspect_mask;
1498 VkFormat vk_format;
1499 uint32_t base_layer;
1500 uint32_t layer_count;
1501 uint32_t base_mip;
1502 uint32_t level_count;
1503 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1504
1505 uint32_t descriptor[16];
1506
1507 /* Descriptor for use as a storage image as opposed to a sampled image.
1508 * This has a few differences for cube maps (e.g. type).
1509 */
1510 uint32_t storage_descriptor[16];
1511 };
1512
1513 struct radv_image_create_info {
1514 const VkImageCreateInfo *vk_info;
1515 bool scanout;
1516 bool no_metadata_planes;
1517 };
1518
1519 VkResult radv_image_create(VkDevice _device,
1520 const struct radv_image_create_info *info,
1521 const VkAllocationCallbacks* alloc,
1522 VkImage *pImage);
1523
1524 VkResult
1525 radv_image_from_gralloc(VkDevice device_h,
1526 const VkImageCreateInfo *base_info,
1527 const VkNativeBufferANDROID *gralloc_info,
1528 const VkAllocationCallbacks *alloc,
1529 VkImage *out_image_h);
1530
1531 void radv_image_view_init(struct radv_image_view *view,
1532 struct radv_device *device,
1533 const VkImageViewCreateInfo* pCreateInfo);
1534
1535 struct radv_buffer_view {
1536 struct radeon_winsys_bo *bo;
1537 VkFormat vk_format;
1538 uint64_t range; /**< VkBufferViewCreateInfo::range */
1539 uint32_t state[4];
1540 };
1541 void radv_buffer_view_init(struct radv_buffer_view *view,
1542 struct radv_device *device,
1543 const VkBufferViewCreateInfo* pCreateInfo);
1544
1545 static inline struct VkExtent3D
1546 radv_sanitize_image_extent(const VkImageType imageType,
1547 const struct VkExtent3D imageExtent)
1548 {
1549 switch (imageType) {
1550 case VK_IMAGE_TYPE_1D:
1551 return (VkExtent3D) { imageExtent.width, 1, 1 };
1552 case VK_IMAGE_TYPE_2D:
1553 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1554 case VK_IMAGE_TYPE_3D:
1555 return imageExtent;
1556 default:
1557 unreachable("invalid image type");
1558 }
1559 }
1560
1561 static inline struct VkOffset3D
1562 radv_sanitize_image_offset(const VkImageType imageType,
1563 const struct VkOffset3D imageOffset)
1564 {
1565 switch (imageType) {
1566 case VK_IMAGE_TYPE_1D:
1567 return (VkOffset3D) { imageOffset.x, 0, 0 };
1568 case VK_IMAGE_TYPE_2D:
1569 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1570 case VK_IMAGE_TYPE_3D:
1571 return imageOffset;
1572 default:
1573 unreachable("invalid image type");
1574 }
1575 }
1576
1577 static inline bool
1578 radv_image_extent_compare(const struct radv_image *image,
1579 const VkExtent3D *extent)
1580 {
1581 if (extent->width != image->info.width ||
1582 extent->height != image->info.height ||
1583 extent->depth != image->info.depth)
1584 return false;
1585 return true;
1586 }
1587
1588 struct radv_sampler {
1589 uint32_t state[4];
1590 };
1591
1592 struct radv_color_buffer_info {
1593 uint64_t cb_color_base;
1594 uint64_t cb_color_cmask;
1595 uint64_t cb_color_fmask;
1596 uint64_t cb_dcc_base;
1597 uint32_t cb_color_pitch;
1598 uint32_t cb_color_slice;
1599 uint32_t cb_color_view;
1600 uint32_t cb_color_info;
1601 uint32_t cb_color_attrib;
1602 uint32_t cb_color_attrib2;
1603 uint32_t cb_dcc_control;
1604 uint32_t cb_color_cmask_slice;
1605 uint32_t cb_color_fmask_slice;
1606 };
1607
1608 struct radv_ds_buffer_info {
1609 uint64_t db_z_read_base;
1610 uint64_t db_stencil_read_base;
1611 uint64_t db_z_write_base;
1612 uint64_t db_stencil_write_base;
1613 uint64_t db_htile_data_base;
1614 uint32_t db_depth_info;
1615 uint32_t db_z_info;
1616 uint32_t db_stencil_info;
1617 uint32_t db_depth_view;
1618 uint32_t db_depth_size;
1619 uint32_t db_depth_slice;
1620 uint32_t db_htile_surface;
1621 uint32_t pa_su_poly_offset_db_fmt_cntl;
1622 uint32_t db_z_info2;
1623 uint32_t db_stencil_info2;
1624 float offset_scale;
1625 };
1626
1627 struct radv_attachment_info {
1628 union {
1629 struct radv_color_buffer_info cb;
1630 struct radv_ds_buffer_info ds;
1631 };
1632 struct radv_image_view *attachment;
1633 };
1634
1635 struct radv_framebuffer {
1636 uint32_t width;
1637 uint32_t height;
1638 uint32_t layers;
1639
1640 uint32_t attachment_count;
1641 struct radv_attachment_info attachments[0];
1642 };
1643
1644 struct radv_subpass_barrier {
1645 VkPipelineStageFlags src_stage_mask;
1646 VkAccessFlags src_access_mask;
1647 VkAccessFlags dst_access_mask;
1648 };
1649
1650 struct radv_subpass {
1651 uint32_t input_count;
1652 uint32_t color_count;
1653 VkAttachmentReference * input_attachments;
1654 VkAttachmentReference * color_attachments;
1655 VkAttachmentReference * resolve_attachments;
1656 VkAttachmentReference depth_stencil_attachment;
1657
1658 /** Subpass has at least one resolve attachment */
1659 bool has_resolve;
1660
1661 struct radv_subpass_barrier start_barrier;
1662
1663 uint32_t view_mask;
1664 VkSampleCountFlagBits max_sample_count;
1665 };
1666
1667 struct radv_render_pass_attachment {
1668 VkFormat format;
1669 uint32_t samples;
1670 VkAttachmentLoadOp load_op;
1671 VkAttachmentLoadOp stencil_load_op;
1672 VkImageLayout initial_layout;
1673 VkImageLayout final_layout;
1674 uint32_t view_mask;
1675 };
1676
1677 struct radv_render_pass {
1678 uint32_t attachment_count;
1679 uint32_t subpass_count;
1680 VkAttachmentReference * subpass_attachments;
1681 struct radv_render_pass_attachment * attachments;
1682 struct radv_subpass_barrier end_barrier;
1683 struct radv_subpass subpasses[0];
1684 };
1685
1686 VkResult radv_device_init_meta(struct radv_device *device);
1687 void radv_device_finish_meta(struct radv_device *device);
1688
1689 struct radv_query_pool {
1690 struct radeon_winsys_bo *bo;
1691 uint32_t stride;
1692 uint32_t availability_offset;
1693 uint64_t size;
1694 char *ptr;
1695 VkQueryType type;
1696 uint32_t pipeline_stats_mask;
1697 };
1698
1699 struct radv_semaphore {
1700 /* use a winsys sem for non-exportable */
1701 struct radeon_winsys_sem *sem;
1702 uint32_t syncobj;
1703 uint32_t temp_syncobj;
1704 };
1705
1706 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1707 int num_wait_sems,
1708 const VkSemaphore *wait_sems,
1709 int num_signal_sems,
1710 const VkSemaphore *signal_sems,
1711 VkFence fence);
1712 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1713
1714 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1715 VkPipelineBindPoint bind_point,
1716 struct radv_descriptor_set *set,
1717 unsigned idx);
1718
1719 void
1720 radv_update_descriptor_sets(struct radv_device *device,
1721 struct radv_cmd_buffer *cmd_buffer,
1722 VkDescriptorSet overrideSet,
1723 uint32_t descriptorWriteCount,
1724 const VkWriteDescriptorSet *pDescriptorWrites,
1725 uint32_t descriptorCopyCount,
1726 const VkCopyDescriptorSet *pDescriptorCopies);
1727
1728 void
1729 radv_update_descriptor_set_with_template(struct radv_device *device,
1730 struct radv_cmd_buffer *cmd_buffer,
1731 struct radv_descriptor_set *set,
1732 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1733 const void *pData);
1734
1735 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1736 VkPipelineBindPoint pipelineBindPoint,
1737 VkPipelineLayout _layout,
1738 uint32_t set,
1739 uint32_t descriptorWriteCount,
1740 const VkWriteDescriptorSet *pDescriptorWrites);
1741
1742 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1743 struct radv_image *image, uint32_t value);
1744
1745 struct radv_fence {
1746 struct radeon_winsys_fence *fence;
1747 bool submitted;
1748 bool signalled;
1749
1750 uint32_t syncobj;
1751 uint32_t temp_syncobj;
1752 };
1753
1754 /* radv_nir_to_llvm.c */
1755 struct radv_shader_variant_info;
1756 struct radv_nir_compiler_options;
1757
1758 void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
1759 struct nir_shader *geom_shader,
1760 struct ac_shader_binary *binary,
1761 struct ac_shader_config *config,
1762 struct radv_shader_variant_info *shader_info,
1763 const struct radv_nir_compiler_options *option);
1764
1765 void radv_compile_nir_shader(LLVMTargetMachineRef tm,
1766 struct ac_shader_binary *binary,
1767 struct ac_shader_config *config,
1768 struct radv_shader_variant_info *shader_info,
1769 struct nir_shader *const *nir,
1770 int nir_count,
1771 const struct radv_nir_compiler_options *options);
1772
1773 /* radv_shader_info.h */
1774 struct radv_shader_info;
1775
1776 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1777 const struct radv_nir_compiler_options *options,
1778 struct radv_shader_info *info);
1779
1780 struct radeon_winsys_sem;
1781
1782 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1783 \
1784 static inline struct __radv_type * \
1785 __radv_type ## _from_handle(__VkType _handle) \
1786 { \
1787 return (struct __radv_type *) _handle; \
1788 } \
1789 \
1790 static inline __VkType \
1791 __radv_type ## _to_handle(struct __radv_type *_obj) \
1792 { \
1793 return (__VkType) _obj; \
1794 }
1795
1796 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1797 \
1798 static inline struct __radv_type * \
1799 __radv_type ## _from_handle(__VkType _handle) \
1800 { \
1801 return (struct __radv_type *)(uintptr_t) _handle; \
1802 } \
1803 \
1804 static inline __VkType \
1805 __radv_type ## _to_handle(struct __radv_type *_obj) \
1806 { \
1807 return (__VkType)(uintptr_t) _obj; \
1808 }
1809
1810 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1811 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1812
1813 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1814 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1815 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1816 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1817 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1818
1819 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1820 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1821 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1822 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1823 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1824 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1825 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1826 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1827 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1828 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1829 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1830 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1831 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1832 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1833 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1834 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1835 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1836 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1837 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1838 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1839 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1840
1841 #endif /* RADV_PRIVATE_H */