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radv: Implement pipeline statistics queries.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/vk_alloc.h"
51 #include "main/macros.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "radv_debug.h"
57 #include "radv_descriptor_set.h"
58
59 #include <llvm-c/TargetMachine.h>
60
61 /* Pre-declarations needed for WSI entrypoints */
62 struct wl_surface;
63 struct wl_display;
64 typedef struct xcb_connection_t xcb_connection_t;
65 typedef uint32_t xcb_visualid_t;
66 typedef uint32_t xcb_window_t;
67
68 #include <vulkan/vulkan.h>
69 #include <vulkan/vulkan_intel.h>
70 #include <vulkan/vk_icd.h>
71
72 #include "radv_entrypoints.h"
73
74 #include "wsi_common.h"
75
76 #define MAX_VBS 32
77 #define MAX_VERTEX_ATTRIBS 32
78 #define MAX_RTS 8
79 #define MAX_VIEWPORTS 16
80 #define MAX_SCISSORS 16
81 #define MAX_PUSH_CONSTANTS_SIZE 128
82 #define MAX_PUSH_DESCRIPTORS 32
83 #define MAX_DYNAMIC_BUFFERS 16
84 #define MAX_SAMPLES_LOG2 4
85 #define NUM_META_FS_KEYS 11
86 #define RADV_MAX_DRM_DEVICES 8
87
88 #define NUM_DEPTH_CLEAR_PIPELINES 3
89
90 enum radv_mem_heap {
91 RADV_MEM_HEAP_VRAM,
92 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
93 RADV_MEM_HEAP_GTT,
94 RADV_MEM_HEAP_COUNT
95 };
96
97 enum radv_mem_type {
98 RADV_MEM_TYPE_VRAM,
99 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
100 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
101 RADV_MEM_TYPE_GTT_CACHED,
102 RADV_MEM_TYPE_COUNT
103 };
104
105 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
106
107 static inline uint32_t
108 align_u32(uint32_t v, uint32_t a)
109 {
110 assert(a != 0 && a == (a & -a));
111 return (v + a - 1) & ~(a - 1);
112 }
113
114 static inline uint32_t
115 align_u32_npot(uint32_t v, uint32_t a)
116 {
117 return (v + a - 1) / a * a;
118 }
119
120 static inline uint64_t
121 align_u64(uint64_t v, uint64_t a)
122 {
123 assert(a != 0 && a == (a & -a));
124 return (v + a - 1) & ~(a - 1);
125 }
126
127 static inline int32_t
128 align_i32(int32_t v, int32_t a)
129 {
130 assert(a != 0 && a == (a & -a));
131 return (v + a - 1) & ~(a - 1);
132 }
133
134 /** Alignment must be a power of 2. */
135 static inline bool
136 radv_is_aligned(uintmax_t n, uintmax_t a)
137 {
138 assert(a == (a & -a));
139 return (n & (a - 1)) == 0;
140 }
141
142 static inline uint32_t
143 round_up_u32(uint32_t v, uint32_t a)
144 {
145 return (v + a - 1) / a;
146 }
147
148 static inline uint64_t
149 round_up_u64(uint64_t v, uint64_t a)
150 {
151 return (v + a - 1) / a;
152 }
153
154 static inline uint32_t
155 radv_minify(uint32_t n, uint32_t levels)
156 {
157 if (unlikely(n == 0))
158 return 0;
159 else
160 return MAX2(n >> levels, 1);
161 }
162 static inline float
163 radv_clamp_f(float f, float min, float max)
164 {
165 assert(min < max);
166
167 if (f > max)
168 return max;
169 else if (f < min)
170 return min;
171 else
172 return f;
173 }
174
175 static inline bool
176 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
177 {
178 if (*inout_mask & clear_mask) {
179 *inout_mask &= ~clear_mask;
180 return true;
181 } else {
182 return false;
183 }
184 }
185
186 #define for_each_bit(b, dword) \
187 for (uint32_t __dword = (dword); \
188 (b) = __builtin_ffs(__dword) - 1, __dword; \
189 __dword &= ~(1 << (b)))
190
191 #define typed_memcpy(dest, src, count) ({ \
192 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
193 memcpy((dest), (src), (count) * sizeof(*(src))); \
194 })
195
196 #define zero(x) (memset(&(x), 0, sizeof(x)))
197
198 /* Whenever we generate an error, pass it through this function. Useful for
199 * debugging, where we can break on it. Only call at error site, not when
200 * propagating errors. Might be useful to plug in a stack trace here.
201 */
202
203 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
204
205 #ifdef DEBUG
206 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
207 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
208 #else
209 #define vk_error(error) error
210 #define vk_errorf(error, format, ...) error
211 #endif
212
213 void __radv_finishme(const char *file, int line, const char *format, ...)
214 radv_printflike(3, 4);
215 void radv_loge(const char *format, ...) radv_printflike(1, 2);
216 void radv_loge_v(const char *format, va_list va);
217
218 /**
219 * Print a FINISHME message, including its source location.
220 */
221 #define radv_finishme(format, ...) \
222 do { \
223 static bool reported = false; \
224 if (!reported) { \
225 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
226 reported = true; \
227 } \
228 } while (0)
229
230 /* A non-fatal assert. Useful for debugging. */
231 #ifdef DEBUG
232 #define radv_assert(x) ({ \
233 if (unlikely(!(x))) \
234 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
235 })
236 #else
237 #define radv_assert(x)
238 #endif
239
240 #define stub_return(v) \
241 do { \
242 radv_finishme("stub %s", __func__); \
243 return (v); \
244 } while (0)
245
246 #define stub() \
247 do { \
248 radv_finishme("stub %s", __func__); \
249 return; \
250 } while (0)
251
252 void *radv_lookup_entrypoint(const char *name);
253
254 struct radv_extensions {
255 VkExtensionProperties *ext_array;
256 uint32_t num_ext;
257 };
258
259 struct radv_physical_device {
260 VK_LOADER_DATA _loader_data;
261
262 struct radv_instance * instance;
263
264 struct radeon_winsys *ws;
265 struct radeon_info rad_info;
266 char path[20];
267 const char * name;
268 uint8_t uuid[VK_UUID_SIZE];
269
270 int local_fd;
271 struct wsi_device wsi_device;
272 struct radv_extensions extensions;
273 };
274
275 struct radv_instance {
276 VK_LOADER_DATA _loader_data;
277
278 VkAllocationCallbacks alloc;
279
280 uint32_t apiVersion;
281 int physicalDeviceCount;
282 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
283
284 uint64_t debug_flags;
285 };
286
287 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
288 void radv_finish_wsi(struct radv_physical_device *physical_device);
289
290 struct cache_entry;
291
292 struct radv_pipeline_cache {
293 struct radv_device * device;
294 pthread_mutex_t mutex;
295
296 uint32_t total_size;
297 uint32_t table_size;
298 uint32_t kernel_count;
299 struct cache_entry ** hash_table;
300 bool modified;
301
302 VkAllocationCallbacks alloc;
303 };
304
305 void
306 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
307 struct radv_device *device);
308 void
309 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
310 void
311 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
312 const void *data, size_t size);
313
314 struct radv_shader_variant *
315 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
316 struct radv_pipeline_cache *cache,
317 const unsigned char *sha1);
318
319 struct radv_shader_variant *
320 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
321 const unsigned char *sha1,
322 struct radv_shader_variant *variant,
323 const void *code, unsigned code_size);
324
325 void radv_shader_variant_destroy(struct radv_device *device,
326 struct radv_shader_variant *variant);
327
328 struct radv_meta_state {
329 VkAllocationCallbacks alloc;
330
331 struct radv_pipeline_cache cache;
332
333 /**
334 * Use array element `i` for images with `2^i` samples.
335 */
336 struct {
337 VkRenderPass render_pass[NUM_META_FS_KEYS];
338 struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
339
340 VkRenderPass depthstencil_rp;
341 struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
342 struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
343 struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
344 } clear[1 + MAX_SAMPLES_LOG2];
345
346 struct {
347 VkRenderPass render_pass[NUM_META_FS_KEYS];
348
349 /** Pipeline that blits from a 1D image. */
350 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
351
352 /** Pipeline that blits from a 2D image. */
353 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
354
355 /** Pipeline that blits from a 3D image. */
356 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
357
358 VkRenderPass depth_only_rp;
359 VkPipeline depth_only_1d_pipeline;
360 VkPipeline depth_only_2d_pipeline;
361 VkPipeline depth_only_3d_pipeline;
362
363 VkRenderPass stencil_only_rp;
364 VkPipeline stencil_only_1d_pipeline;
365 VkPipeline stencil_only_2d_pipeline;
366 VkPipeline stencil_only_3d_pipeline;
367 VkPipelineLayout pipeline_layout;
368 VkDescriptorSetLayout ds_layout;
369 } blit;
370
371 struct {
372 VkRenderPass render_passes[NUM_META_FS_KEYS];
373
374 VkPipelineLayout p_layouts[2];
375 VkDescriptorSetLayout ds_layouts[2];
376 VkPipeline pipelines[2][NUM_META_FS_KEYS];
377
378 VkRenderPass depth_only_rp;
379 VkPipeline depth_only_pipeline[2];
380
381 VkRenderPass stencil_only_rp;
382 VkPipeline stencil_only_pipeline[2];
383 } blit2d;
384
385 struct {
386 VkPipelineLayout img_p_layout;
387 VkDescriptorSetLayout img_ds_layout;
388 VkPipeline pipeline;
389 } itob;
390 struct {
391 VkRenderPass render_pass;
392 VkPipelineLayout img_p_layout;
393 VkDescriptorSetLayout img_ds_layout;
394 VkPipeline pipeline;
395 } btoi;
396 struct {
397 VkPipelineLayout img_p_layout;
398 VkDescriptorSetLayout img_ds_layout;
399 VkPipeline pipeline;
400 } itoi;
401 struct {
402 VkPipelineLayout img_p_layout;
403 VkDescriptorSetLayout img_ds_layout;
404 VkPipeline pipeline;
405 } cleari;
406
407 struct {
408 VkPipeline pipeline;
409 VkRenderPass pass;
410 } resolve;
411
412 struct {
413 VkDescriptorSetLayout ds_layout;
414 VkPipelineLayout p_layout;
415 struct {
416 VkPipeline pipeline;
417 VkPipeline i_pipeline;
418 } rc[MAX_SAMPLES_LOG2];
419 } resolve_compute;
420
421 struct {
422 VkPipeline decompress_pipeline;
423 VkPipeline resummarize_pipeline;
424 VkRenderPass pass;
425 } depth_decomp;
426
427 struct {
428 VkPipeline cmask_eliminate_pipeline;
429 VkPipeline fmask_decompress_pipeline;
430 VkRenderPass pass;
431 } fast_clear_flush;
432
433 struct {
434 VkPipelineLayout fill_p_layout;
435 VkPipelineLayout copy_p_layout;
436 VkDescriptorSetLayout fill_ds_layout;
437 VkDescriptorSetLayout copy_ds_layout;
438 VkPipeline fill_pipeline;
439 VkPipeline copy_pipeline;
440 } buffer;
441
442 struct {
443 VkDescriptorSetLayout ds_layout;
444 VkPipelineLayout p_layout;
445 VkPipeline occlusion_query_pipeline;
446 VkPipeline pipeline_statistics_query_pipeline;
447 } query;
448 };
449
450 /* queue types */
451 #define RADV_QUEUE_GENERAL 0
452 #define RADV_QUEUE_COMPUTE 1
453 #define RADV_QUEUE_TRANSFER 2
454
455 #define RADV_MAX_QUEUE_FAMILIES 3
456
457 enum ring_type radv_queue_family_to_ring(int f);
458
459 struct radv_queue {
460 VK_LOADER_DATA _loader_data;
461 struct radv_device * device;
462 struct radeon_winsys_ctx *hw_ctx;
463 int queue_family_index;
464 int queue_idx;
465
466 uint32_t scratch_size;
467 uint32_t compute_scratch_size;
468 uint32_t esgs_ring_size;
469 uint32_t gsvs_ring_size;
470 bool has_tess_rings;
471 bool has_sample_positions;
472
473 struct radeon_winsys_bo *scratch_bo;
474 struct radeon_winsys_bo *descriptor_bo;
475 struct radeon_winsys_bo *compute_scratch_bo;
476 struct radeon_winsys_bo *esgs_ring_bo;
477 struct radeon_winsys_bo *gsvs_ring_bo;
478 struct radeon_winsys_bo *tess_factor_ring_bo;
479 struct radeon_winsys_bo *tess_offchip_ring_bo;
480 struct radeon_winsys_cs *initial_preamble_cs;
481 struct radeon_winsys_cs *continue_preamble_cs;
482 };
483
484 struct radv_device {
485 VK_LOADER_DATA _loader_data;
486
487 VkAllocationCallbacks alloc;
488
489 struct radv_instance * instance;
490 struct radeon_winsys *ws;
491
492 struct radv_meta_state meta_state;
493
494 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
495 int queue_count[RADV_MAX_QUEUE_FAMILIES];
496 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
497 struct radeon_winsys_cs *flush_cs[RADV_MAX_QUEUE_FAMILIES];
498
499 uint64_t debug_flags;
500
501 bool llvm_supports_spill;
502 bool has_distributed_tess;
503 uint32_t tess_offchip_block_dw_size;
504 uint32_t scratch_waves;
505
506 uint32_t gs_table_depth;
507
508 /* MSAA sample locations.
509 * The first index is the sample index.
510 * The second index is the coordinate: X, Y. */
511 float sample_locations_1x[1][2];
512 float sample_locations_2x[2][2];
513 float sample_locations_4x[4][2];
514 float sample_locations_8x[8][2];
515 float sample_locations_16x[16][2];
516
517 /* CIK and later */
518 uint32_t gfx_init_size_dw;
519 struct radeon_winsys_bo *gfx_init;
520
521 struct radeon_winsys_bo *trace_bo;
522 uint32_t *trace_id_ptr;
523
524 struct radv_physical_device *physical_device;
525
526 /* Backup in-memory cache to be used if the app doesn't provide one */
527 struct radv_pipeline_cache * mem_cache;
528 };
529
530 struct radv_device_memory {
531 struct radeon_winsys_bo *bo;
532 /* for dedicated allocations */
533 struct radv_image *image;
534 struct radv_buffer *buffer;
535 uint32_t type_index;
536 VkDeviceSize map_size;
537 void * map;
538 };
539
540
541 struct radv_descriptor_range {
542 uint64_t va;
543 uint32_t size;
544 };
545
546 struct radv_descriptor_set {
547 const struct radv_descriptor_set_layout *layout;
548 uint32_t size;
549
550 struct radeon_winsys_bo *bo;
551 uint64_t va;
552 uint32_t *mapped_ptr;
553 struct radv_descriptor_range *dynamic_descriptors;
554
555 struct list_head vram_list;
556
557 struct radeon_winsys_bo *descriptors[0];
558 };
559
560 struct radv_push_descriptor_set
561 {
562 struct radv_descriptor_set set;
563 uint32_t capacity;
564 };
565
566 struct radv_descriptor_pool {
567 struct radeon_winsys_bo *bo;
568 uint8_t *mapped_ptr;
569 uint64_t current_offset;
570 uint64_t size;
571
572 struct list_head vram_list;
573 };
574
575 struct radv_descriptor_update_template_entry {
576 VkDescriptorType descriptor_type;
577
578 /* The number of descriptors to update */
579 uint16_t descriptor_count;
580
581 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
582 uint16_t dst_offset;
583
584 /* In dwords. Not valid/used for dynamic descriptors */
585 uint16_t dst_stride;
586
587 uint16_t buffer_offset;
588 uint16_t buffer_count;
589
590 /* Only valid for combined image samplers and samplers */
591 uint16_t has_sampler;
592
593 /* In bytes */
594 size_t src_offset;
595 size_t src_stride;
596
597 /* For push descriptors */
598 uint32_t *immutable_samplers;
599 };
600
601 struct radv_descriptor_update_template {
602 uint32_t entry_count;
603 struct radv_descriptor_update_template_entry entry[0];
604 };
605
606 struct radv_buffer {
607 struct radv_device * device;
608 VkDeviceSize size;
609
610 VkBufferUsageFlags usage;
611 VkBufferCreateFlags flags;
612
613 /* Set when bound */
614 struct radeon_winsys_bo * bo;
615 VkDeviceSize offset;
616 };
617
618
619 enum radv_cmd_dirty_bits {
620 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
621 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
622 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
623 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
624 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
625 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
626 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
627 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
628 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
629 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
630 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
631 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
632 RADV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
633 };
634 typedef uint32_t radv_cmd_dirty_mask_t;
635
636 enum radv_cmd_flush_bits {
637 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
638 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
639 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
640 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
641 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
642 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
643 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
644 /* Same as above, but only writes back and doesn't invalidate */
645 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
646 /* Framebuffer caches */
647 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
648 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
649 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
650 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
651 /* Engine synchronization. */
652 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
653 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
654 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
655 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
656
657 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
658 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
659 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
660 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
661 };
662
663 struct radv_vertex_binding {
664 struct radv_buffer * buffer;
665 VkDeviceSize offset;
666 };
667
668 struct radv_dynamic_state {
669 struct {
670 uint32_t count;
671 VkViewport viewports[MAX_VIEWPORTS];
672 } viewport;
673
674 struct {
675 uint32_t count;
676 VkRect2D scissors[MAX_SCISSORS];
677 } scissor;
678
679 float line_width;
680
681 struct {
682 float bias;
683 float clamp;
684 float slope;
685 } depth_bias;
686
687 float blend_constants[4];
688
689 struct {
690 float min;
691 float max;
692 } depth_bounds;
693
694 struct {
695 uint32_t front;
696 uint32_t back;
697 } stencil_compare_mask;
698
699 struct {
700 uint32_t front;
701 uint32_t back;
702 } stencil_write_mask;
703
704 struct {
705 uint32_t front;
706 uint32_t back;
707 } stencil_reference;
708 };
709
710 extern const struct radv_dynamic_state default_dynamic_state;
711
712 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
713 const struct radv_dynamic_state *src,
714 uint32_t copy_mask);
715 /**
716 * Attachment state when recording a renderpass instance.
717 *
718 * The clear value is valid only if there exists a pending clear.
719 */
720 struct radv_attachment_state {
721 VkImageAspectFlags pending_clear_aspects;
722 VkClearValue clear_value;
723 VkImageLayout current_layout;
724 };
725
726 struct radv_cmd_state {
727 uint32_t vb_dirty;
728 radv_cmd_dirty_mask_t dirty;
729 bool vertex_descriptors_dirty;
730 bool push_descriptors_dirty;
731
732 struct radv_pipeline * pipeline;
733 struct radv_pipeline * emitted_pipeline;
734 struct radv_pipeline * compute_pipeline;
735 struct radv_pipeline * emitted_compute_pipeline;
736 struct radv_framebuffer * framebuffer;
737 struct radv_render_pass * pass;
738 const struct radv_subpass * subpass;
739 struct radv_dynamic_state dynamic;
740 struct radv_vertex_binding vertex_bindings[MAX_VBS];
741 struct radv_descriptor_set * descriptors[MAX_SETS];
742 struct radv_attachment_state * attachments;
743 VkRect2D render_area;
744 struct radv_buffer * index_buffer;
745 uint32_t index_type;
746 uint32_t index_offset;
747 uint32_t last_primitive_reset_index;
748 enum radv_cmd_flush_bits flush_bits;
749 unsigned active_occlusion_queries;
750 float offset_scale;
751 uint32_t descriptors_dirty;
752 uint32_t trace_id;
753 uint32_t last_ia_multi_vgt_param;
754 };
755
756 struct radv_cmd_pool {
757 VkAllocationCallbacks alloc;
758 struct list_head cmd_buffers;
759 struct list_head free_cmd_buffers;
760 uint32_t queue_family_index;
761 };
762
763 struct radv_cmd_buffer_upload {
764 uint8_t *map;
765 unsigned offset;
766 uint64_t size;
767 struct radeon_winsys_bo *upload_bo;
768 struct list_head list;
769 };
770
771 struct radv_cmd_buffer {
772 VK_LOADER_DATA _loader_data;
773
774 struct radv_device * device;
775
776 struct radv_cmd_pool * pool;
777 struct list_head pool_link;
778
779 VkCommandBufferUsageFlags usage_flags;
780 VkCommandBufferLevel level;
781 struct radeon_winsys_cs *cs;
782 struct radv_cmd_state state;
783 uint32_t queue_family_index;
784
785 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
786 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
787 VkShaderStageFlags push_constant_stages;
788 struct radv_push_descriptor_set push_descriptors;
789
790 struct radv_cmd_buffer_upload upload;
791
792 bool record_fail;
793
794 uint32_t scratch_size_needed;
795 uint32_t compute_scratch_size_needed;
796 uint32_t esgs_ring_size_needed;
797 uint32_t gsvs_ring_size_needed;
798 bool tess_rings_needed;
799 bool sample_positions_needed;
800
801 int ring_offsets_idx; /* just used for verification */
802 };
803
804 struct radv_image;
805
806 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
807
808 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
809 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
810
811 void cik_create_gfx_config(struct radv_device *device);
812
813 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
814 int count, const VkViewport *viewports);
815 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
816 int count, const VkRect2D *scissors,
817 const VkViewport *viewports, bool can_use_guardband);
818 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
819 bool instanced_draw, bool indirect_draw,
820 uint32_t draw_vertex_count);
821 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
822 enum chip_class chip_class,
823 bool is_mec,
824 enum radv_cmd_flush_bits flush_bits);
825 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
826 enum chip_class chip_class,
827 bool is_mec,
828 enum radv_cmd_flush_bits flush_bits);
829 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
830 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
831 uint64_t src_va, uint64_t dest_va,
832 uint64_t size);
833 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
834 uint64_t size, unsigned value);
835 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
836 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
837 struct radv_descriptor_set *set,
838 unsigned idx);
839 bool
840 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
841 unsigned size,
842 unsigned alignment,
843 unsigned *out_offset,
844 void **ptr);
845 void
846 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
847 const struct radv_subpass *subpass,
848 bool transitions);
849 bool
850 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
851 unsigned size, unsigned alignmnet,
852 const void *data, unsigned *out_offset);
853 void
854 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
855 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
856 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
857 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
858 unsigned radv_cayman_get_maxdist(int log_samples);
859 void radv_device_init_msaa(struct radv_device *device);
860 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
861 struct radv_image *image,
862 VkClearDepthStencilValue ds_clear_value,
863 VkImageAspectFlags aspects);
864 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
865 struct radv_image *image,
866 int idx,
867 uint32_t color_values[2]);
868 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
869 struct radeon_winsys_bo *bo,
870 uint64_t offset, uint64_t size, uint32_t value);
871 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
872 bool radv_get_memory_fd(struct radv_device *device,
873 struct radv_device_memory *memory,
874 int *pFD);
875 /*
876 * Takes x,y,z as exact numbers of invocations, instead of blocks.
877 *
878 * Limitations: Can't call normal dispatch functions without binding or rebinding
879 * the compute pipeline.
880 */
881 void radv_unaligned_dispatch(
882 struct radv_cmd_buffer *cmd_buffer,
883 uint32_t x,
884 uint32_t y,
885 uint32_t z);
886
887 struct radv_event {
888 struct radeon_winsys_bo *bo;
889 uint64_t *map;
890 };
891
892 struct nir_shader;
893
894 struct radv_shader_module {
895 struct nir_shader * nir;
896 unsigned char sha1[20];
897 uint32_t size;
898 char data[0];
899 };
900
901 union ac_shader_variant_key;
902
903 void
904 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
905 const char *entrypoint,
906 const VkSpecializationInfo *spec_info,
907 const struct radv_pipeline_layout *layout,
908 const union ac_shader_variant_key *key,
909 uint32_t is_geom_copy_shader);
910
911 static inline gl_shader_stage
912 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
913 {
914 assert(__builtin_popcount(vk_stage) == 1);
915 return ffs(vk_stage) - 1;
916 }
917
918 static inline VkShaderStageFlagBits
919 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
920 {
921 return (1 << mesa_stage);
922 }
923
924 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
925
926 #define radv_foreach_stage(stage, stage_bits) \
927 for (gl_shader_stage stage, \
928 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
929 stage = __builtin_ffs(__tmp) - 1, __tmp; \
930 __tmp &= ~(1 << (stage)))
931
932 struct radv_shader_variant {
933 uint32_t ref_count;
934
935 struct radeon_winsys_bo *bo;
936 struct ac_shader_config config;
937 struct ac_shader_variant_info info;
938 unsigned rsrc1;
939 unsigned rsrc2;
940 uint32_t code_size;
941 };
942
943 struct radv_depth_stencil_state {
944 uint32_t db_depth_control;
945 uint32_t db_stencil_control;
946 uint32_t db_render_control;
947 uint32_t db_render_override2;
948 };
949
950 struct radv_blend_state {
951 uint32_t cb_color_control;
952 uint32_t cb_target_mask;
953 uint32_t sx_mrt0_blend_opt[8];
954 uint32_t cb_blend_control[8];
955
956 uint32_t spi_shader_col_format;
957 uint32_t cb_shader_mask;
958 uint32_t db_alpha_to_mask;
959 };
960
961 unsigned radv_format_meta_fs_key(VkFormat format);
962
963 struct radv_raster_state {
964 uint32_t pa_cl_clip_cntl;
965 uint32_t spi_interp_control;
966 uint32_t pa_su_point_size;
967 uint32_t pa_su_point_minmax;
968 uint32_t pa_su_line_cntl;
969 uint32_t pa_su_vtx_cntl;
970 uint32_t pa_su_sc_mode_cntl;
971 };
972
973 struct radv_multisample_state {
974 uint32_t db_eqaa;
975 uint32_t pa_sc_line_cntl;
976 uint32_t pa_sc_mode_cntl_0;
977 uint32_t pa_sc_mode_cntl_1;
978 uint32_t pa_sc_aa_config;
979 uint32_t pa_sc_aa_mask[2];
980 unsigned num_samples;
981 };
982
983 struct radv_prim_vertex_count {
984 uint8_t min;
985 uint8_t incr;
986 };
987
988 struct radv_tessellation_state {
989 uint32_t ls_hs_config;
990 uint32_t tcs_in_layout;
991 uint32_t tcs_out_layout;
992 uint32_t tcs_out_offsets;
993 uint32_t offchip_layout;
994 unsigned num_patches;
995 unsigned lds_size;
996 unsigned num_tcs_input_cp;
997 uint32_t tf_param;
998 };
999
1000 struct radv_pipeline {
1001 struct radv_device * device;
1002 uint32_t dynamic_state_mask;
1003 struct radv_dynamic_state dynamic_state;
1004
1005 struct radv_pipeline_layout * layout;
1006
1007 bool needs_data_cache;
1008
1009 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1010 struct radv_shader_variant *gs_copy_shader;
1011 VkShaderStageFlags active_stages;
1012
1013 uint32_t va_rsrc_word3[MAX_VERTEX_ATTRIBS];
1014 uint32_t va_format_size[MAX_VERTEX_ATTRIBS];
1015 uint32_t va_binding[MAX_VERTEX_ATTRIBS];
1016 uint32_t va_offset[MAX_VERTEX_ATTRIBS];
1017 uint32_t num_vertex_attribs;
1018 uint32_t binding_stride[MAX_VBS];
1019
1020 union {
1021 struct {
1022 struct radv_blend_state blend;
1023 struct radv_depth_stencil_state ds;
1024 struct radv_raster_state raster;
1025 struct radv_multisample_state ms;
1026 struct radv_tessellation_state tess;
1027 uint32_t db_shader_control;
1028 uint32_t shader_z_format;
1029 unsigned prim;
1030 unsigned gs_out;
1031 uint32_t vgt_gs_mode;
1032 bool prim_restart_enable;
1033 unsigned esgs_ring_size;
1034 unsigned gsvs_ring_size;
1035 uint32_t ps_input_cntl[32];
1036 uint32_t ps_input_cntl_num;
1037 uint32_t pa_cl_vs_out_cntl;
1038 uint32_t vgt_shader_stages_en;
1039 struct radv_prim_vertex_count prim_vertex_count;
1040 bool can_use_guardband;
1041 } graphics;
1042 };
1043
1044 unsigned max_waves;
1045 unsigned scratch_bytes_per_wave;
1046 };
1047
1048 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1049 {
1050 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1051 }
1052
1053 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1054 {
1055 return pipeline->shaders[MESA_SHADER_TESS_EVAL] ? true : false;
1056 }
1057
1058 struct radv_graphics_pipeline_create_info {
1059 bool use_rectlist;
1060 bool db_depth_clear;
1061 bool db_stencil_clear;
1062 bool db_depth_disable_expclear;
1063 bool db_stencil_disable_expclear;
1064 bool db_flush_depth_inplace;
1065 bool db_flush_stencil_inplace;
1066 bool db_resummarize;
1067 uint32_t custom_blend_mode;
1068 };
1069
1070 VkResult
1071 radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
1072 struct radv_pipeline_cache *cache,
1073 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1074 const struct radv_graphics_pipeline_create_info *extra,
1075 const VkAllocationCallbacks *alloc);
1076
1077 VkResult
1078 radv_graphics_pipeline_create(VkDevice device,
1079 VkPipelineCache cache,
1080 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1081 const struct radv_graphics_pipeline_create_info *extra,
1082 const VkAllocationCallbacks *alloc,
1083 VkPipeline *pPipeline);
1084
1085 struct vk_format_description;
1086 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1087 int first_non_void);
1088 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1089 int first_non_void);
1090 uint32_t radv_translate_colorformat(VkFormat format);
1091 uint32_t radv_translate_color_numformat(VkFormat format,
1092 const struct vk_format_description *desc,
1093 int first_non_void);
1094 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1095 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1096 uint32_t radv_translate_dbformat(VkFormat format);
1097 uint32_t radv_translate_tex_dataformat(VkFormat format,
1098 const struct vk_format_description *desc,
1099 int first_non_void);
1100 uint32_t radv_translate_tex_numformat(VkFormat format,
1101 const struct vk_format_description *desc,
1102 int first_non_void);
1103 bool radv_format_pack_clear_color(VkFormat format,
1104 uint32_t clear_vals[2],
1105 VkClearColorValue *value);
1106 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1107
1108 struct radv_fmask_info {
1109 uint64_t offset;
1110 uint64_t size;
1111 unsigned alignment;
1112 unsigned pitch_in_pixels;
1113 unsigned bank_height;
1114 unsigned slice_tile_max;
1115 unsigned tile_mode_index;
1116 };
1117
1118 struct radv_cmask_info {
1119 uint64_t offset;
1120 uint64_t size;
1121 unsigned alignment;
1122 unsigned slice_tile_max;
1123 unsigned base_address_reg;
1124 };
1125
1126 struct r600_htile_info {
1127 uint64_t offset;
1128 uint64_t size;
1129 unsigned pitch;
1130 unsigned height;
1131 unsigned xalign;
1132 unsigned yalign;
1133 };
1134
1135 struct radv_image {
1136 VkImageType type;
1137 /* The original VkFormat provided by the client. This may not match any
1138 * of the actual surface formats.
1139 */
1140 VkFormat vk_format;
1141 VkImageAspectFlags aspects;
1142 VkExtent3D extent;
1143 uint32_t levels;
1144 uint32_t array_size;
1145 uint32_t samples; /**< VkImageCreateInfo::samples */
1146 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1147 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1148 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1149
1150 VkDeviceSize size;
1151 uint32_t alignment;
1152
1153 bool exclusive;
1154 unsigned queue_family_mask;
1155
1156 /* Set when bound */
1157 struct radeon_winsys_bo *bo;
1158 VkDeviceSize offset;
1159 uint32_t dcc_offset;
1160 uint32_t htile_offset;
1161 struct radeon_surf surface;
1162
1163 struct radv_fmask_info fmask;
1164 struct radv_cmask_info cmask;
1165 uint32_t clear_value_offset;
1166 };
1167
1168 bool radv_layout_has_htile(const struct radv_image *image,
1169 VkImageLayout layout);
1170 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1171 VkImageLayout layout);
1172 bool radv_layout_can_expclear(const struct radv_image *image,
1173 VkImageLayout layout);
1174 bool radv_layout_can_fast_clear(const struct radv_image *image,
1175 VkImageLayout layout,
1176 unsigned queue_mask);
1177
1178
1179 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1180
1181 static inline uint32_t
1182 radv_get_layerCount(const struct radv_image *image,
1183 const VkImageSubresourceRange *range)
1184 {
1185 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1186 image->array_size - range->baseArrayLayer : range->layerCount;
1187 }
1188
1189 static inline uint32_t
1190 radv_get_levelCount(const struct radv_image *image,
1191 const VkImageSubresourceRange *range)
1192 {
1193 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1194 image->levels - range->baseMipLevel : range->levelCount;
1195 }
1196
1197 struct radeon_bo_metadata;
1198 void
1199 radv_init_metadata(struct radv_device *device,
1200 struct radv_image *image,
1201 struct radeon_bo_metadata *metadata);
1202
1203 struct radv_image_view {
1204 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1205 struct radeon_winsys_bo *bo;
1206
1207 VkImageViewType type;
1208 VkImageAspectFlags aspect_mask;
1209 VkFormat vk_format;
1210 uint32_t base_layer;
1211 uint32_t layer_count;
1212 uint32_t base_mip;
1213 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1214
1215 uint32_t descriptor[8];
1216 uint32_t fmask_descriptor[8];
1217 };
1218
1219 struct radv_image_create_info {
1220 const VkImageCreateInfo *vk_info;
1221 uint32_t stride;
1222 bool scanout;
1223 };
1224
1225 VkResult radv_image_create(VkDevice _device,
1226 const struct radv_image_create_info *info,
1227 const VkAllocationCallbacks* alloc,
1228 VkImage *pImage);
1229
1230 void radv_image_view_init(struct radv_image_view *view,
1231 struct radv_device *device,
1232 const VkImageViewCreateInfo* pCreateInfo,
1233 struct radv_cmd_buffer *cmd_buffer,
1234 VkImageUsageFlags usage_mask);
1235 void radv_image_set_optimal_micro_tile_mode(struct radv_device *device,
1236 struct radv_image *image, uint32_t micro_tile_mode);
1237 struct radv_buffer_view {
1238 struct radeon_winsys_bo *bo;
1239 VkFormat vk_format;
1240 uint64_t range; /**< VkBufferViewCreateInfo::range */
1241 uint32_t state[4];
1242 };
1243 void radv_buffer_view_init(struct radv_buffer_view *view,
1244 struct radv_device *device,
1245 const VkBufferViewCreateInfo* pCreateInfo,
1246 struct radv_cmd_buffer *cmd_buffer);
1247
1248 static inline struct VkExtent3D
1249 radv_sanitize_image_extent(const VkImageType imageType,
1250 const struct VkExtent3D imageExtent)
1251 {
1252 switch (imageType) {
1253 case VK_IMAGE_TYPE_1D:
1254 return (VkExtent3D) { imageExtent.width, 1, 1 };
1255 case VK_IMAGE_TYPE_2D:
1256 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1257 case VK_IMAGE_TYPE_3D:
1258 return imageExtent;
1259 default:
1260 unreachable("invalid image type");
1261 }
1262 }
1263
1264 static inline struct VkOffset3D
1265 radv_sanitize_image_offset(const VkImageType imageType,
1266 const struct VkOffset3D imageOffset)
1267 {
1268 switch (imageType) {
1269 case VK_IMAGE_TYPE_1D:
1270 return (VkOffset3D) { imageOffset.x, 0, 0 };
1271 case VK_IMAGE_TYPE_2D:
1272 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1273 case VK_IMAGE_TYPE_3D:
1274 return imageOffset;
1275 default:
1276 unreachable("invalid image type");
1277 }
1278 }
1279
1280 struct radv_sampler {
1281 uint32_t state[4];
1282 };
1283
1284 struct radv_color_buffer_info {
1285 uint32_t cb_color_base;
1286 uint32_t cb_color_pitch;
1287 uint32_t cb_color_slice;
1288 uint32_t cb_color_view;
1289 uint32_t cb_color_info;
1290 uint32_t cb_color_attrib;
1291 uint32_t cb_dcc_control;
1292 uint32_t cb_color_cmask;
1293 uint32_t cb_color_cmask_slice;
1294 uint32_t cb_color_fmask;
1295 uint32_t cb_color_fmask_slice;
1296 uint32_t cb_clear_value0;
1297 uint32_t cb_clear_value1;
1298 uint32_t cb_dcc_base;
1299 uint32_t micro_tile_mode;
1300 };
1301
1302 struct radv_ds_buffer_info {
1303 uint32_t db_depth_info;
1304 uint32_t db_z_info;
1305 uint32_t db_stencil_info;
1306 uint32_t db_z_read_base;
1307 uint32_t db_stencil_read_base;
1308 uint32_t db_z_write_base;
1309 uint32_t db_stencil_write_base;
1310 uint32_t db_depth_view;
1311 uint32_t db_depth_size;
1312 uint32_t db_depth_slice;
1313 uint32_t db_htile_surface;
1314 uint32_t db_htile_data_base;
1315 uint32_t pa_su_poly_offset_db_fmt_cntl;
1316 float offset_scale;
1317 };
1318
1319 struct radv_attachment_info {
1320 union {
1321 struct radv_color_buffer_info cb;
1322 struct radv_ds_buffer_info ds;
1323 };
1324 struct radv_image_view *attachment;
1325 };
1326
1327 struct radv_framebuffer {
1328 uint32_t width;
1329 uint32_t height;
1330 uint32_t layers;
1331
1332 uint32_t attachment_count;
1333 struct radv_attachment_info attachments[0];
1334 };
1335
1336 struct radv_subpass_barrier {
1337 VkPipelineStageFlags src_stage_mask;
1338 VkAccessFlags src_access_mask;
1339 VkAccessFlags dst_access_mask;
1340 };
1341
1342 struct radv_subpass {
1343 uint32_t input_count;
1344 VkAttachmentReference * input_attachments;
1345 uint32_t color_count;
1346 VkAttachmentReference * color_attachments;
1347 VkAttachmentReference * resolve_attachments;
1348 VkAttachmentReference depth_stencil_attachment;
1349
1350 /** Subpass has at least one resolve attachment */
1351 bool has_resolve;
1352
1353 struct radv_subpass_barrier start_barrier;
1354 };
1355
1356 struct radv_render_pass_attachment {
1357 VkFormat format;
1358 uint32_t samples;
1359 VkAttachmentLoadOp load_op;
1360 VkAttachmentLoadOp stencil_load_op;
1361 VkImageLayout initial_layout;
1362 VkImageLayout final_layout;
1363 };
1364
1365 struct radv_render_pass {
1366 uint32_t attachment_count;
1367 uint32_t subpass_count;
1368 VkAttachmentReference * subpass_attachments;
1369 struct radv_render_pass_attachment * attachments;
1370 struct radv_subpass_barrier end_barrier;
1371 struct radv_subpass subpasses[0];
1372 };
1373
1374 VkResult radv_device_init_meta(struct radv_device *device);
1375 void radv_device_finish_meta(struct radv_device *device);
1376
1377 struct radv_query_pool {
1378 struct radeon_winsys_bo *bo;
1379 uint32_t stride;
1380 uint32_t availability_offset;
1381 char *ptr;
1382 VkQueryType type;
1383 uint32_t pipeline_stats_mask;
1384 };
1385
1386 VkResult
1387 radv_temp_descriptor_set_create(struct radv_device *device,
1388 struct radv_cmd_buffer *cmd_buffer,
1389 VkDescriptorSetLayout _layout,
1390 VkDescriptorSet *_set);
1391
1392 void
1393 radv_temp_descriptor_set_destroy(struct radv_device *device,
1394 VkDescriptorSet _set);
1395
1396 void
1397 radv_update_descriptor_sets(struct radv_device *device,
1398 struct radv_cmd_buffer *cmd_buffer,
1399 VkDescriptorSet overrideSet,
1400 uint32_t descriptorWriteCount,
1401 const VkWriteDescriptorSet *pDescriptorWrites,
1402 uint32_t descriptorCopyCount,
1403 const VkCopyDescriptorSet *pDescriptorCopies);
1404
1405 void
1406 radv_update_descriptor_set_with_template(struct radv_device *device,
1407 struct radv_cmd_buffer *cmd_buffer,
1408 struct radv_descriptor_set *set,
1409 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1410 const void *pData);
1411
1412 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1413 struct radv_image *image, uint32_t value);
1414 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1415 struct radv_image *image, uint32_t value);
1416
1417 struct radv_fence {
1418 struct radeon_winsys_fence *fence;
1419 bool submitted;
1420 bool signalled;
1421 };
1422
1423 struct radeon_winsys_sem;
1424
1425 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1426 \
1427 static inline struct __radv_type * \
1428 __radv_type ## _from_handle(__VkType _handle) \
1429 { \
1430 return (struct __radv_type *) _handle; \
1431 } \
1432 \
1433 static inline __VkType \
1434 __radv_type ## _to_handle(struct __radv_type *_obj) \
1435 { \
1436 return (__VkType) _obj; \
1437 }
1438
1439 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1440 \
1441 static inline struct __radv_type * \
1442 __radv_type ## _from_handle(__VkType _handle) \
1443 { \
1444 return (struct __radv_type *)(uintptr_t) _handle; \
1445 } \
1446 \
1447 static inline __VkType \
1448 __radv_type ## _to_handle(struct __radv_type *_obj) \
1449 { \
1450 return (__VkType)(uintptr_t) _obj; \
1451 }
1452
1453 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1454 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1455
1456 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1457 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1458 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1459 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1460 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1461
1462 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1463 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1464 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1465 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1466 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1467 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1468 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1469 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1470 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1471 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1472 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1473 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1474 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1475 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1476 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1477 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1478 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1479 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1480 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1481 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1482 RADV_DEFINE_NONDISP_HANDLE_CASTS(radeon_winsys_sem, VkSemaphore)
1483
1484 #endif /* RADV_PRIVATE_H */