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radv: implement out-of-order rasterization when it's safe on VI+
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52 #include "vk_debug_report.h"
53
54 #include "radv_radeon_winsys.h"
55 #include "ac_binary.h"
56 #include "ac_nir_to_llvm.h"
57 #include "ac_gpu_info.h"
58 #include "ac_surface.h"
59 #include "radv_descriptor_set.h"
60 #include "radv_extensions.h"
61
62 #include <llvm-c/TargetMachine.h>
63
64 /* Pre-declarations needed for WSI entrypoints */
65 struct wl_surface;
66 struct wl_display;
67 typedef struct xcb_connection_t xcb_connection_t;
68 typedef uint32_t xcb_visualid_t;
69 typedef uint32_t xcb_window_t;
70
71 #include <vulkan/vulkan.h>
72 #include <vulkan/vulkan_intel.h>
73 #include <vulkan/vk_icd.h>
74 #include <vulkan/vk_android_native_buffer.h>
75
76 #include "radv_entrypoints.h"
77
78 #include "wsi_common.h"
79
80 #define ATI_VENDOR_ID 0x1002
81
82 #define MAX_VBS 32
83 #define MAX_VERTEX_ATTRIBS 32
84 #define MAX_RTS 8
85 #define MAX_VIEWPORTS 16
86 #define MAX_SCISSORS 16
87 #define MAX_DISCARD_RECTANGLES 4
88 #define MAX_PUSH_CONSTANTS_SIZE 128
89 #define MAX_PUSH_DESCRIPTORS 32
90 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
91 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
92 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
93 #define MAX_SAMPLES_LOG2 4
94 #define NUM_META_FS_KEYS 13
95 #define RADV_MAX_DRM_DEVICES 8
96 #define MAX_VIEWS 8
97
98 #define NUM_DEPTH_CLEAR_PIPELINES 3
99
100 /*
101 * This is the point we switch from using CP to compute shader
102 * for certain buffer operations.
103 */
104 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
105
106 enum radv_mem_heap {
107 RADV_MEM_HEAP_VRAM,
108 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
109 RADV_MEM_HEAP_GTT,
110 RADV_MEM_HEAP_COUNT
111 };
112
113 enum radv_mem_type {
114 RADV_MEM_TYPE_VRAM,
115 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
116 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
117 RADV_MEM_TYPE_GTT_CACHED,
118 RADV_MEM_TYPE_COUNT
119 };
120
121 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
122
123 static inline uint32_t
124 align_u32(uint32_t v, uint32_t a)
125 {
126 assert(a != 0 && a == (a & -a));
127 return (v + a - 1) & ~(a - 1);
128 }
129
130 static inline uint32_t
131 align_u32_npot(uint32_t v, uint32_t a)
132 {
133 return (v + a - 1) / a * a;
134 }
135
136 static inline uint64_t
137 align_u64(uint64_t v, uint64_t a)
138 {
139 assert(a != 0 && a == (a & -a));
140 return (v + a - 1) & ~(a - 1);
141 }
142
143 static inline int32_t
144 align_i32(int32_t v, int32_t a)
145 {
146 assert(a != 0 && a == (a & -a));
147 return (v + a - 1) & ~(a - 1);
148 }
149
150 /** Alignment must be a power of 2. */
151 static inline bool
152 radv_is_aligned(uintmax_t n, uintmax_t a)
153 {
154 assert(a == (a & -a));
155 return (n & (a - 1)) == 0;
156 }
157
158 static inline uint32_t
159 round_up_u32(uint32_t v, uint32_t a)
160 {
161 return (v + a - 1) / a;
162 }
163
164 static inline uint64_t
165 round_up_u64(uint64_t v, uint64_t a)
166 {
167 return (v + a - 1) / a;
168 }
169
170 static inline uint32_t
171 radv_minify(uint32_t n, uint32_t levels)
172 {
173 if (unlikely(n == 0))
174 return 0;
175 else
176 return MAX2(n >> levels, 1);
177 }
178 static inline float
179 radv_clamp_f(float f, float min, float max)
180 {
181 assert(min < max);
182
183 if (f > max)
184 return max;
185 else if (f < min)
186 return min;
187 else
188 return f;
189 }
190
191 static inline bool
192 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
193 {
194 if (*inout_mask & clear_mask) {
195 *inout_mask &= ~clear_mask;
196 return true;
197 } else {
198 return false;
199 }
200 }
201
202 #define for_each_bit(b, dword) \
203 for (uint32_t __dword = (dword); \
204 (b) = __builtin_ffs(__dword) - 1, __dword; \
205 __dword &= ~(1 << (b)))
206
207 #define typed_memcpy(dest, src, count) ({ \
208 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
209 memcpy((dest), (src), (count) * sizeof(*(src))); \
210 })
211
212 /* Whenever we generate an error, pass it through this function. Useful for
213 * debugging, where we can break on it. Only call at error site, not when
214 * propagating errors. Might be useful to plug in a stack trace here.
215 */
216
217 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
218
219 #ifdef DEBUG
220 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
221 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
222 #else
223 #define vk_error(error) error
224 #define vk_errorf(error, format, ...) error
225 #endif
226
227 void __radv_finishme(const char *file, int line, const char *format, ...)
228 radv_printflike(3, 4);
229 void radv_loge(const char *format, ...) radv_printflike(1, 2);
230 void radv_loge_v(const char *format, va_list va);
231
232 /**
233 * Print a FINISHME message, including its source location.
234 */
235 #define radv_finishme(format, ...) \
236 do { \
237 static bool reported = false; \
238 if (!reported) { \
239 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
240 reported = true; \
241 } \
242 } while (0)
243
244 /* A non-fatal assert. Useful for debugging. */
245 #ifdef DEBUG
246 #define radv_assert(x) ({ \
247 if (unlikely(!(x))) \
248 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
249 })
250 #else
251 #define radv_assert(x)
252 #endif
253
254 #define stub_return(v) \
255 do { \
256 radv_finishme("stub %s", __func__); \
257 return (v); \
258 } while (0)
259
260 #define stub() \
261 do { \
262 radv_finishme("stub %s", __func__); \
263 return; \
264 } while (0)
265
266 void *radv_lookup_entrypoint_unchecked(const char *name);
267 void *radv_lookup_entrypoint_checked(const char *name,
268 uint32_t core_version,
269 const struct radv_instance_extension_table *instance,
270 const struct radv_device_extension_table *device);
271
272 struct radv_physical_device {
273 VK_LOADER_DATA _loader_data;
274
275 struct radv_instance * instance;
276
277 struct radeon_winsys *ws;
278 struct radeon_info rad_info;
279 char path[20];
280 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
281 uint8_t driver_uuid[VK_UUID_SIZE];
282 uint8_t device_uuid[VK_UUID_SIZE];
283 uint8_t cache_uuid[VK_UUID_SIZE];
284
285 int local_fd;
286 struct wsi_device wsi_device;
287
288 bool has_rbplus; /* if RB+ register exist */
289 bool rbplus_allowed; /* if RB+ is allowed */
290 bool has_clear_state;
291 bool cpdma_prefetch_writes_memory;
292 bool has_scissor_bug;
293
294 bool has_out_of_order_rast;
295 bool out_of_order_rast_allowed;
296
297 /* This is the drivers on-disk cache used as a fallback as opposed to
298 * the pipeline cache defined by apps.
299 */
300 struct disk_cache * disk_cache;
301
302 VkPhysicalDeviceMemoryProperties memory_properties;
303 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
304
305 struct radv_device_extension_table supported_extensions;
306 };
307
308 struct radv_instance {
309 VK_LOADER_DATA _loader_data;
310
311 VkAllocationCallbacks alloc;
312
313 uint32_t apiVersion;
314 int physicalDeviceCount;
315 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
316
317 uint64_t debug_flags;
318 uint64_t perftest_flags;
319
320 struct vk_debug_report_instance debug_report_callbacks;
321
322 struct radv_instance_extension_table enabled_extensions;
323 };
324
325 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
326 void radv_finish_wsi(struct radv_physical_device *physical_device);
327
328 bool radv_instance_extension_supported(const char *name);
329 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
330 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
331 const char *name);
332
333 struct cache_entry;
334
335 struct radv_pipeline_cache {
336 struct radv_device * device;
337 pthread_mutex_t mutex;
338
339 uint32_t total_size;
340 uint32_t table_size;
341 uint32_t kernel_count;
342 struct cache_entry ** hash_table;
343 bool modified;
344
345 VkAllocationCallbacks alloc;
346 };
347
348 struct radv_pipeline_key {
349 uint32_t instance_rate_inputs;
350 unsigned tess_input_vertices;
351 uint32_t col_format;
352 uint32_t is_int8;
353 uint32_t is_int10;
354 uint8_t log2_ps_iter_samples;
355 uint8_t log2_num_samples;
356 uint32_t multisample : 1;
357 uint32_t has_multiview_view_index : 1;
358 };
359
360 void
361 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
362 struct radv_device *device);
363 void
364 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
365 void
366 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
367 const void *data, size_t size);
368
369 struct radv_shader_variant;
370
371 bool
372 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
373 struct radv_pipeline_cache *cache,
374 const unsigned char *sha1,
375 struct radv_shader_variant **variants);
376
377 void
378 radv_pipeline_cache_insert_shaders(struct radv_device *device,
379 struct radv_pipeline_cache *cache,
380 const unsigned char *sha1,
381 struct radv_shader_variant **variants,
382 const void *const *codes,
383 const unsigned *code_sizes);
384
385 enum radv_blit_ds_layout {
386 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
387 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
388 RADV_BLIT_DS_LAYOUT_COUNT,
389 };
390
391 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
392 {
393 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
394 }
395
396 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
397 {
398 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
399 }
400
401 enum radv_meta_dst_layout {
402 RADV_META_DST_LAYOUT_GENERAL,
403 RADV_META_DST_LAYOUT_OPTIMAL,
404 RADV_META_DST_LAYOUT_COUNT,
405 };
406
407 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
408 {
409 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
410 }
411
412 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
413 {
414 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
415 }
416
417 struct radv_meta_state {
418 VkAllocationCallbacks alloc;
419
420 struct radv_pipeline_cache cache;
421
422 /**
423 * Use array element `i` for images with `2^i` samples.
424 */
425 struct {
426 VkRenderPass render_pass[NUM_META_FS_KEYS];
427 VkPipeline color_pipelines[NUM_META_FS_KEYS];
428
429 VkRenderPass depthstencil_rp;
430 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
431 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
432 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
433 } clear[1 + MAX_SAMPLES_LOG2];
434
435 VkPipelineLayout clear_color_p_layout;
436 VkPipelineLayout clear_depth_p_layout;
437 struct {
438 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
439
440 /** Pipeline that blits from a 1D image. */
441 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
442
443 /** Pipeline that blits from a 2D image. */
444 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
445
446 /** Pipeline that blits from a 3D image. */
447 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
448
449 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
450 VkPipeline depth_only_1d_pipeline;
451 VkPipeline depth_only_2d_pipeline;
452 VkPipeline depth_only_3d_pipeline;
453
454 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
455 VkPipeline stencil_only_1d_pipeline;
456 VkPipeline stencil_only_2d_pipeline;
457 VkPipeline stencil_only_3d_pipeline;
458 VkPipelineLayout pipeline_layout;
459 VkDescriptorSetLayout ds_layout;
460 } blit;
461
462 struct {
463 VkRenderPass render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
464
465 VkPipelineLayout p_layouts[3];
466 VkDescriptorSetLayout ds_layouts[3];
467 VkPipeline pipelines[3][NUM_META_FS_KEYS];
468
469 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
470 VkPipeline depth_only_pipeline[3];
471
472 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
473 VkPipeline stencil_only_pipeline[3];
474 } blit2d;
475
476 struct {
477 VkPipelineLayout img_p_layout;
478 VkDescriptorSetLayout img_ds_layout;
479 VkPipeline pipeline;
480 VkPipeline pipeline_3d;
481 } itob;
482 struct {
483 VkPipelineLayout img_p_layout;
484 VkDescriptorSetLayout img_ds_layout;
485 VkPipeline pipeline;
486 VkPipeline pipeline_3d;
487 } btoi;
488 struct {
489 VkPipelineLayout img_p_layout;
490 VkDescriptorSetLayout img_ds_layout;
491 VkPipeline pipeline;
492 VkPipeline pipeline_3d;
493 } itoi;
494 struct {
495 VkPipelineLayout img_p_layout;
496 VkDescriptorSetLayout img_ds_layout;
497 VkPipeline pipeline;
498 VkPipeline pipeline_3d;
499 } cleari;
500
501 struct {
502 VkPipelineLayout p_layout;
503 VkPipeline pipeline[NUM_META_FS_KEYS];
504 VkRenderPass pass[NUM_META_FS_KEYS];
505 } resolve;
506
507 struct {
508 VkDescriptorSetLayout ds_layout;
509 VkPipelineLayout p_layout;
510 struct {
511 VkPipeline pipeline;
512 VkPipeline i_pipeline;
513 VkPipeline srgb_pipeline;
514 } rc[MAX_SAMPLES_LOG2];
515 } resolve_compute;
516
517 struct {
518 VkDescriptorSetLayout ds_layout;
519 VkPipelineLayout p_layout;
520
521 struct {
522 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
523 VkPipeline pipeline[NUM_META_FS_KEYS];
524 } rc[MAX_SAMPLES_LOG2];
525 } resolve_fragment;
526
527 struct {
528 VkPipelineLayout p_layout;
529 VkPipeline decompress_pipeline;
530 VkPipeline resummarize_pipeline;
531 VkRenderPass pass;
532 } depth_decomp[1 + MAX_SAMPLES_LOG2];
533
534 struct {
535 VkPipelineLayout p_layout;
536 VkPipeline cmask_eliminate_pipeline;
537 VkPipeline fmask_decompress_pipeline;
538 VkPipeline dcc_decompress_pipeline;
539 VkRenderPass pass;
540
541 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
542 VkPipelineLayout dcc_decompress_compute_p_layout;
543 VkPipeline dcc_decompress_compute_pipeline;
544 } fast_clear_flush;
545
546 struct {
547 VkPipelineLayout fill_p_layout;
548 VkPipelineLayout copy_p_layout;
549 VkDescriptorSetLayout fill_ds_layout;
550 VkDescriptorSetLayout copy_ds_layout;
551 VkPipeline fill_pipeline;
552 VkPipeline copy_pipeline;
553 } buffer;
554
555 struct {
556 VkDescriptorSetLayout ds_layout;
557 VkPipelineLayout p_layout;
558 VkPipeline occlusion_query_pipeline;
559 VkPipeline pipeline_statistics_query_pipeline;
560 } query;
561 };
562
563 /* queue types */
564 #define RADV_QUEUE_GENERAL 0
565 #define RADV_QUEUE_COMPUTE 1
566 #define RADV_QUEUE_TRANSFER 2
567
568 #define RADV_MAX_QUEUE_FAMILIES 3
569
570 enum ring_type radv_queue_family_to_ring(int f);
571
572 struct radv_queue {
573 VK_LOADER_DATA _loader_data;
574 struct radv_device * device;
575 struct radeon_winsys_ctx *hw_ctx;
576 enum radeon_ctx_priority priority;
577 uint32_t queue_family_index;
578 int queue_idx;
579 VkDeviceQueueCreateFlags flags;
580
581 uint32_t scratch_size;
582 uint32_t compute_scratch_size;
583 uint32_t esgs_ring_size;
584 uint32_t gsvs_ring_size;
585 bool has_tess_rings;
586 bool has_sample_positions;
587
588 struct radeon_winsys_bo *scratch_bo;
589 struct radeon_winsys_bo *descriptor_bo;
590 struct radeon_winsys_bo *compute_scratch_bo;
591 struct radeon_winsys_bo *esgs_ring_bo;
592 struct radeon_winsys_bo *gsvs_ring_bo;
593 struct radeon_winsys_bo *tess_rings_bo;
594 struct radeon_winsys_cs *initial_preamble_cs;
595 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
596 struct radeon_winsys_cs *continue_preamble_cs;
597 };
598
599 struct radv_device {
600 VK_LOADER_DATA _loader_data;
601
602 VkAllocationCallbacks alloc;
603
604 struct radv_instance * instance;
605 struct radeon_winsys *ws;
606
607 struct radv_meta_state meta_state;
608
609 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
610 int queue_count[RADV_MAX_QUEUE_FAMILIES];
611 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
612
613 bool always_use_syncobj;
614 bool llvm_supports_spill;
615 bool has_distributed_tess;
616 bool pbb_allowed;
617 bool dfsm_allowed;
618 uint32_t tess_offchip_block_dw_size;
619 uint32_t scratch_waves;
620 uint32_t dispatch_initiator;
621
622 uint32_t gs_table_depth;
623
624 /* MSAA sample locations.
625 * The first index is the sample index.
626 * The second index is the coordinate: X, Y. */
627 float sample_locations_1x[1][2];
628 float sample_locations_2x[2][2];
629 float sample_locations_4x[4][2];
630 float sample_locations_8x[8][2];
631 float sample_locations_16x[16][2];
632
633 /* CIK and later */
634 uint32_t gfx_init_size_dw;
635 struct radeon_winsys_bo *gfx_init;
636
637 struct radeon_winsys_bo *trace_bo;
638 uint32_t *trace_id_ptr;
639
640 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
641 bool keep_shader_info;
642
643 struct radv_physical_device *physical_device;
644
645 /* Backup in-memory cache to be used if the app doesn't provide one */
646 struct radv_pipeline_cache * mem_cache;
647
648 /*
649 * use different counters so MSAA MRTs get consecutive surface indices,
650 * even if MASK is allocated in between.
651 */
652 uint32_t image_mrt_offset_counter;
653 uint32_t fmask_mrt_offset_counter;
654 struct list_head shader_slabs;
655 mtx_t shader_slab_mutex;
656
657 /* For detecting VM faults reported by dmesg. */
658 uint64_t dmesg_timestamp;
659
660 struct radv_device_extension_table enabled_extensions;
661 };
662
663 struct radv_device_memory {
664 struct radeon_winsys_bo *bo;
665 /* for dedicated allocations */
666 struct radv_image *image;
667 struct radv_buffer *buffer;
668 uint32_t type_index;
669 VkDeviceSize map_size;
670 void * map;
671 void * user_ptr;
672 };
673
674
675 struct radv_descriptor_range {
676 uint64_t va;
677 uint32_t size;
678 };
679
680 struct radv_descriptor_set {
681 const struct radv_descriptor_set_layout *layout;
682 uint32_t size;
683
684 struct radeon_winsys_bo *bo;
685 uint64_t va;
686 uint32_t *mapped_ptr;
687 struct radv_descriptor_range *dynamic_descriptors;
688
689 struct radeon_winsys_bo *descriptors[0];
690 };
691
692 struct radv_push_descriptor_set
693 {
694 struct radv_descriptor_set set;
695 uint32_t capacity;
696 };
697
698 struct radv_descriptor_pool_entry {
699 uint32_t offset;
700 uint32_t size;
701 struct radv_descriptor_set *set;
702 };
703
704 struct radv_descriptor_pool {
705 struct radeon_winsys_bo *bo;
706 uint8_t *mapped_ptr;
707 uint64_t current_offset;
708 uint64_t size;
709
710 uint8_t *host_memory_base;
711 uint8_t *host_memory_ptr;
712 uint8_t *host_memory_end;
713
714 uint32_t entry_count;
715 uint32_t max_entry_count;
716 struct radv_descriptor_pool_entry entries[0];
717 };
718
719 struct radv_descriptor_update_template_entry {
720 VkDescriptorType descriptor_type;
721
722 /* The number of descriptors to update */
723 uint32_t descriptor_count;
724
725 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
726 uint32_t dst_offset;
727
728 /* In dwords. Not valid/used for dynamic descriptors */
729 uint32_t dst_stride;
730
731 uint32_t buffer_offset;
732
733 /* Only valid for combined image samplers and samplers */
734 uint16_t has_sampler;
735
736 /* In bytes */
737 size_t src_offset;
738 size_t src_stride;
739
740 /* For push descriptors */
741 const uint32_t *immutable_samplers;
742 };
743
744 struct radv_descriptor_update_template {
745 uint32_t entry_count;
746 VkPipelineBindPoint bind_point;
747 struct radv_descriptor_update_template_entry entry[0];
748 };
749
750 struct radv_buffer {
751 VkDeviceSize size;
752
753 VkBufferUsageFlags usage;
754 VkBufferCreateFlags flags;
755
756 /* Set when bound */
757 struct radeon_winsys_bo * bo;
758 VkDeviceSize offset;
759
760 bool shareable;
761 };
762
763 enum radv_dynamic_state_bits {
764 RADV_DYNAMIC_VIEWPORT = 1 << 0,
765 RADV_DYNAMIC_SCISSOR = 1 << 1,
766 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
767 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
768 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
769 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
770 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
771 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
772 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
773 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
774 RADV_DYNAMIC_ALL = (1 << 10) - 1,
775 };
776
777 enum radv_cmd_dirty_bits {
778 /* Keep the dynamic state dirty bits in sync with
779 * enum radv_dynamic_state_bits */
780 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
781 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
782 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
783 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
784 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
785 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
786 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
787 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
788 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
789 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
790 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
791 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
792 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
793 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
794 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
795 };
796
797 enum radv_cmd_flush_bits {
798 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
799 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
800 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
801 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
802 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
803 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
804 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
805 /* Same as above, but only writes back and doesn't invalidate */
806 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
807 /* Framebuffer caches */
808 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
809 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
810 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
811 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
812 /* Engine synchronization. */
813 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
814 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
815 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
816 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
817
818 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
819 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
820 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
821 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
822 };
823
824 struct radv_vertex_binding {
825 struct radv_buffer * buffer;
826 VkDeviceSize offset;
827 };
828
829 struct radv_viewport_state {
830 uint32_t count;
831 VkViewport viewports[MAX_VIEWPORTS];
832 };
833
834 struct radv_scissor_state {
835 uint32_t count;
836 VkRect2D scissors[MAX_SCISSORS];
837 };
838
839 struct radv_discard_rectangle_state {
840 uint32_t count;
841 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
842 };
843
844 struct radv_dynamic_state {
845 /**
846 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
847 * Defines the set of saved dynamic state.
848 */
849 uint32_t mask;
850
851 struct radv_viewport_state viewport;
852
853 struct radv_scissor_state scissor;
854
855 float line_width;
856
857 struct {
858 float bias;
859 float clamp;
860 float slope;
861 } depth_bias;
862
863 float blend_constants[4];
864
865 struct {
866 float min;
867 float max;
868 } depth_bounds;
869
870 struct {
871 uint32_t front;
872 uint32_t back;
873 } stencil_compare_mask;
874
875 struct {
876 uint32_t front;
877 uint32_t back;
878 } stencil_write_mask;
879
880 struct {
881 uint32_t front;
882 uint32_t back;
883 } stencil_reference;
884
885 struct radv_discard_rectangle_state discard_rectangle;
886 };
887
888 extern const struct radv_dynamic_state default_dynamic_state;
889
890 const char *
891 radv_get_debug_option_name(int id);
892
893 const char *
894 radv_get_perftest_option_name(int id);
895
896 /**
897 * Attachment state when recording a renderpass instance.
898 *
899 * The clear value is valid only if there exists a pending clear.
900 */
901 struct radv_attachment_state {
902 VkImageAspectFlags pending_clear_aspects;
903 uint32_t cleared_views;
904 VkClearValue clear_value;
905 VkImageLayout current_layout;
906 };
907
908 struct radv_descriptor_state {
909 struct radv_descriptor_set *sets[MAX_SETS];
910 uint32_t dirty;
911 uint32_t valid;
912 struct radv_push_descriptor_set push_set;
913 bool push_dirty;
914 };
915
916 struct radv_cmd_state {
917 /* Vertex descriptors */
918 bool vb_prefetch_dirty;
919 uint64_t vb_va;
920 unsigned vb_size;
921
922 bool predicating;
923 uint32_t dirty;
924
925 struct radv_pipeline * pipeline;
926 struct radv_pipeline * emitted_pipeline;
927 struct radv_pipeline * compute_pipeline;
928 struct radv_pipeline * emitted_compute_pipeline;
929 struct radv_framebuffer * framebuffer;
930 struct radv_render_pass * pass;
931 const struct radv_subpass * subpass;
932 struct radv_dynamic_state dynamic;
933 struct radv_attachment_state * attachments;
934 VkRect2D render_area;
935
936 /* Index buffer */
937 struct radv_buffer *index_buffer;
938 uint64_t index_offset;
939 uint32_t index_type;
940 uint32_t max_index_count;
941 uint64_t index_va;
942 int32_t last_index_type;
943
944 int32_t last_primitive_reset_en;
945 uint32_t last_primitive_reset_index;
946 enum radv_cmd_flush_bits flush_bits;
947 unsigned active_occlusion_queries;
948 float offset_scale;
949 uint32_t trace_id;
950 uint32_t last_ia_multi_vgt_param;
951
952 uint32_t last_num_instances;
953 uint32_t last_first_instance;
954 uint32_t last_vertex_offset;
955 };
956
957 struct radv_cmd_pool {
958 VkAllocationCallbacks alloc;
959 struct list_head cmd_buffers;
960 struct list_head free_cmd_buffers;
961 uint32_t queue_family_index;
962 };
963
964 struct radv_cmd_buffer_upload {
965 uint8_t *map;
966 unsigned offset;
967 uint64_t size;
968 struct radeon_winsys_bo *upload_bo;
969 struct list_head list;
970 };
971
972 enum radv_cmd_buffer_status {
973 RADV_CMD_BUFFER_STATUS_INVALID,
974 RADV_CMD_BUFFER_STATUS_INITIAL,
975 RADV_CMD_BUFFER_STATUS_RECORDING,
976 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
977 RADV_CMD_BUFFER_STATUS_PENDING,
978 };
979
980 struct radv_cmd_buffer {
981 VK_LOADER_DATA _loader_data;
982
983 struct radv_device * device;
984
985 struct radv_cmd_pool * pool;
986 struct list_head pool_link;
987
988 VkCommandBufferUsageFlags usage_flags;
989 VkCommandBufferLevel level;
990 enum radv_cmd_buffer_status status;
991 struct radeon_winsys_cs *cs;
992 struct radv_cmd_state state;
993 struct radv_vertex_binding vertex_bindings[MAX_VBS];
994 uint32_t queue_family_index;
995
996 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
997 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
998 VkShaderStageFlags push_constant_stages;
999 struct radv_descriptor_set meta_push_descriptors;
1000
1001 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1002
1003 struct radv_cmd_buffer_upload upload;
1004
1005 uint32_t scratch_size_needed;
1006 uint32_t compute_scratch_size_needed;
1007 uint32_t esgs_ring_size_needed;
1008 uint32_t gsvs_ring_size_needed;
1009 bool tess_rings_needed;
1010 bool sample_positions_needed;
1011
1012 VkResult record_result;
1013
1014 int ring_offsets_idx; /* just used for verification */
1015 uint32_t gfx9_fence_offset;
1016 struct radeon_winsys_bo *gfx9_fence_bo;
1017 uint32_t gfx9_fence_idx;
1018
1019 /**
1020 * Whether a query pool has been resetted and we have to flush caches.
1021 */
1022 bool pending_reset_query;
1023 };
1024
1025 struct radv_image;
1026
1027 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1028
1029 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
1030 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
1031
1032 void cik_create_gfx_config(struct radv_device *device);
1033
1034 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
1035 int count, const VkViewport *viewports);
1036 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
1037 int count, const VkRect2D *scissors,
1038 const VkViewport *viewports, bool can_use_guardband);
1039 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1040 bool instanced_draw, bool indirect_draw,
1041 uint32_t draw_vertex_count);
1042 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
1043 bool predicated,
1044 enum chip_class chip_class,
1045 bool is_mec,
1046 unsigned event, unsigned event_flags,
1047 unsigned data_sel,
1048 uint64_t va,
1049 uint32_t old_fence,
1050 uint32_t new_fence);
1051
1052 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
1053 bool predicated,
1054 uint64_t va, uint32_t ref,
1055 uint32_t mask);
1056 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
1057 enum chip_class chip_class,
1058 uint32_t *fence_ptr, uint64_t va,
1059 bool is_mec,
1060 enum radv_cmd_flush_bits flush_bits);
1061 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1062 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1063 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1064 uint64_t src_va, uint64_t dest_va,
1065 uint64_t size);
1066 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1067 unsigned size);
1068 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1069 uint64_t size, unsigned value);
1070 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1071 bool
1072 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1073 unsigned size,
1074 unsigned alignment,
1075 unsigned *out_offset,
1076 void **ptr);
1077 void
1078 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1079 const struct radv_subpass *subpass,
1080 bool transitions);
1081 bool
1082 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1083 unsigned size, unsigned alignmnet,
1084 const void *data, unsigned *out_offset);
1085
1086 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1087 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1088 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1089 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1090 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1091 unsigned radv_cayman_get_maxdist(int log_samples);
1092 void radv_device_init_msaa(struct radv_device *device);
1093 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1094 struct radv_image *image,
1095 VkClearDepthStencilValue ds_clear_value,
1096 VkImageAspectFlags aspects);
1097 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1098 struct radv_image *image,
1099 int idx,
1100 uint32_t color_values[2]);
1101 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1102 struct radv_image *image,
1103 bool value);
1104 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1105 struct radeon_winsys_bo *bo,
1106 uint64_t offset, uint64_t size, uint32_t value);
1107 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1108 bool radv_get_memory_fd(struct radv_device *device,
1109 struct radv_device_memory *memory,
1110 int *pFD);
1111
1112 static inline struct radv_descriptor_state *
1113 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1114 VkPipelineBindPoint bind_point)
1115 {
1116 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1117 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1118 return &cmd_buffer->descriptors[bind_point];
1119 }
1120
1121 /*
1122 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1123 *
1124 * Limitations: Can't call normal dispatch functions without binding or rebinding
1125 * the compute pipeline.
1126 */
1127 void radv_unaligned_dispatch(
1128 struct radv_cmd_buffer *cmd_buffer,
1129 uint32_t x,
1130 uint32_t y,
1131 uint32_t z);
1132
1133 struct radv_event {
1134 struct radeon_winsys_bo *bo;
1135 uint64_t *map;
1136 };
1137
1138 struct radv_shader_module;
1139
1140 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1141 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1142 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1143 void
1144 radv_hash_shaders(unsigned char *hash,
1145 const VkPipelineShaderStageCreateInfo **stages,
1146 const struct radv_pipeline_layout *layout,
1147 const struct radv_pipeline_key *key,
1148 uint32_t flags);
1149
1150 static inline gl_shader_stage
1151 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1152 {
1153 assert(__builtin_popcount(vk_stage) == 1);
1154 return ffs(vk_stage) - 1;
1155 }
1156
1157 static inline VkShaderStageFlagBits
1158 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1159 {
1160 return (1 << mesa_stage);
1161 }
1162
1163 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1164
1165 #define radv_foreach_stage(stage, stage_bits) \
1166 for (gl_shader_stage stage, \
1167 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1168 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1169 __tmp &= ~(1 << (stage)))
1170
1171 unsigned radv_format_meta_fs_key(VkFormat format);
1172
1173 struct radv_multisample_state {
1174 uint32_t db_eqaa;
1175 uint32_t pa_sc_line_cntl;
1176 uint32_t pa_sc_mode_cntl_0;
1177 uint32_t pa_sc_mode_cntl_1;
1178 uint32_t pa_sc_aa_config;
1179 uint32_t pa_sc_aa_mask[2];
1180 unsigned num_samples;
1181 };
1182
1183 struct radv_prim_vertex_count {
1184 uint8_t min;
1185 uint8_t incr;
1186 };
1187
1188 struct radv_vertex_elements_info {
1189 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1190 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1191 uint32_t binding[MAX_VERTEX_ATTRIBS];
1192 uint32_t offset[MAX_VERTEX_ATTRIBS];
1193 uint32_t count;
1194 };
1195
1196 struct radv_ia_multi_vgt_param_helpers {
1197 uint32_t base;
1198 bool partial_es_wave;
1199 uint8_t primgroup_size;
1200 bool wd_switch_on_eop;
1201 bool ia_switch_on_eoi;
1202 bool partial_vs_wave;
1203 };
1204
1205 #define SI_GS_PER_ES 128
1206
1207 struct radv_pipeline {
1208 struct radv_device * device;
1209 struct radv_dynamic_state dynamic_state;
1210
1211 struct radv_pipeline_layout * layout;
1212
1213 bool need_indirect_descriptor_sets;
1214 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1215 struct radv_shader_variant *gs_copy_shader;
1216 VkShaderStageFlags active_stages;
1217
1218 struct radeon_winsys_cs cs;
1219
1220 struct radv_vertex_elements_info vertex_elements;
1221
1222 uint32_t binding_stride[MAX_VBS];
1223
1224 uint32_t user_data_0[MESA_SHADER_STAGES];
1225 union {
1226 struct {
1227 struct radv_multisample_state ms;
1228 uint32_t spi_baryc_cntl;
1229 bool prim_restart_enable;
1230 unsigned esgs_ring_size;
1231 unsigned gsvs_ring_size;
1232 uint32_t vtx_base_sgpr;
1233 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1234 uint8_t vtx_emit_num;
1235 struct radv_prim_vertex_count prim_vertex_count;
1236 bool can_use_guardband;
1237 uint32_t needed_dynamic_state;
1238 bool disable_out_of_order_rast_for_occlusion;
1239 } graphics;
1240 };
1241
1242 unsigned max_waves;
1243 unsigned scratch_bytes_per_wave;
1244 };
1245
1246 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1247 {
1248 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1249 }
1250
1251 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1252 {
1253 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1254 }
1255
1256 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1257 gl_shader_stage stage,
1258 int idx);
1259
1260 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1261
1262 struct radv_graphics_pipeline_create_info {
1263 bool use_rectlist;
1264 bool db_depth_clear;
1265 bool db_stencil_clear;
1266 bool db_depth_disable_expclear;
1267 bool db_stencil_disable_expclear;
1268 bool db_flush_depth_inplace;
1269 bool db_flush_stencil_inplace;
1270 bool db_resummarize;
1271 uint32_t custom_blend_mode;
1272 };
1273
1274 VkResult
1275 radv_graphics_pipeline_create(VkDevice device,
1276 VkPipelineCache cache,
1277 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1278 const struct radv_graphics_pipeline_create_info *extra,
1279 const VkAllocationCallbacks *alloc,
1280 VkPipeline *pPipeline);
1281
1282 struct vk_format_description;
1283 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1284 int first_non_void);
1285 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1286 int first_non_void);
1287 uint32_t radv_translate_colorformat(VkFormat format);
1288 uint32_t radv_translate_color_numformat(VkFormat format,
1289 const struct vk_format_description *desc,
1290 int first_non_void);
1291 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1292 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1293 uint32_t radv_translate_dbformat(VkFormat format);
1294 uint32_t radv_translate_tex_dataformat(VkFormat format,
1295 const struct vk_format_description *desc,
1296 int first_non_void);
1297 uint32_t radv_translate_tex_numformat(VkFormat format,
1298 const struct vk_format_description *desc,
1299 int first_non_void);
1300 bool radv_format_pack_clear_color(VkFormat format,
1301 uint32_t clear_vals[2],
1302 VkClearColorValue *value);
1303 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1304 bool radv_dcc_formats_compatible(VkFormat format1,
1305 VkFormat format2);
1306
1307 struct radv_fmask_info {
1308 uint64_t offset;
1309 uint64_t size;
1310 unsigned alignment;
1311 unsigned pitch_in_pixels;
1312 unsigned bank_height;
1313 unsigned slice_tile_max;
1314 unsigned tile_mode_index;
1315 unsigned tile_swizzle;
1316 };
1317
1318 struct radv_cmask_info {
1319 uint64_t offset;
1320 uint64_t size;
1321 unsigned alignment;
1322 unsigned slice_tile_max;
1323 };
1324
1325 struct radv_image {
1326 VkImageType type;
1327 /* The original VkFormat provided by the client. This may not match any
1328 * of the actual surface formats.
1329 */
1330 VkFormat vk_format;
1331 VkImageAspectFlags aspects;
1332 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1333 struct ac_surf_info info;
1334 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1335 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1336
1337 VkDeviceSize size;
1338 uint32_t alignment;
1339
1340 unsigned queue_family_mask;
1341 bool exclusive;
1342 bool shareable;
1343
1344 /* Set when bound */
1345 struct radeon_winsys_bo *bo;
1346 VkDeviceSize offset;
1347 uint64_t dcc_offset;
1348 uint64_t htile_offset;
1349 bool tc_compatible_htile;
1350 struct radeon_surf surface;
1351
1352 struct radv_fmask_info fmask;
1353 struct radv_cmask_info cmask;
1354 uint64_t clear_value_offset;
1355 uint64_t dcc_pred_offset;
1356
1357 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1358 VkDeviceMemory owned_memory;
1359 };
1360
1361 /* Whether the image has a htile that is known consistent with the contents of
1362 * the image. */
1363 bool radv_layout_has_htile(const struct radv_image *image,
1364 VkImageLayout layout,
1365 unsigned queue_mask);
1366
1367 /* Whether the image has a htile that is known consistent with the contents of
1368 * the image and is allowed to be in compressed form.
1369 *
1370 * If this is false reads that don't use the htile should be able to return
1371 * correct results.
1372 */
1373 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1374 VkImageLayout layout,
1375 unsigned queue_mask);
1376
1377 bool radv_layout_can_fast_clear(const struct radv_image *image,
1378 VkImageLayout layout,
1379 unsigned queue_mask);
1380
1381 bool radv_layout_dcc_compressed(const struct radv_image *image,
1382 VkImageLayout layout,
1383 unsigned queue_mask);
1384
1385 static inline bool
1386 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1387 {
1388 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1389 }
1390
1391 static inline bool
1392 radv_htile_enabled(const struct radv_image *image, unsigned level)
1393 {
1394 return image->surface.htile_size && level == 0;
1395 }
1396
1397 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1398
1399 static inline uint32_t
1400 radv_get_layerCount(const struct radv_image *image,
1401 const VkImageSubresourceRange *range)
1402 {
1403 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1404 image->info.array_size - range->baseArrayLayer : range->layerCount;
1405 }
1406
1407 static inline uint32_t
1408 radv_get_levelCount(const struct radv_image *image,
1409 const VkImageSubresourceRange *range)
1410 {
1411 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1412 image->info.levels - range->baseMipLevel : range->levelCount;
1413 }
1414
1415 struct radeon_bo_metadata;
1416 void
1417 radv_init_metadata(struct radv_device *device,
1418 struct radv_image *image,
1419 struct radeon_bo_metadata *metadata);
1420
1421 struct radv_image_view {
1422 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1423 struct radeon_winsys_bo *bo;
1424
1425 VkImageViewType type;
1426 VkImageAspectFlags aspect_mask;
1427 VkFormat vk_format;
1428 uint32_t base_layer;
1429 uint32_t layer_count;
1430 uint32_t base_mip;
1431 uint32_t level_count;
1432 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1433
1434 uint32_t descriptor[16];
1435
1436 /* Descriptor for use as a storage image as opposed to a sampled image.
1437 * This has a few differences for cube maps (e.g. type).
1438 */
1439 uint32_t storage_descriptor[16];
1440 };
1441
1442 struct radv_image_create_info {
1443 const VkImageCreateInfo *vk_info;
1444 bool scanout;
1445 bool no_metadata_planes;
1446 };
1447
1448 VkResult radv_image_create(VkDevice _device,
1449 const struct radv_image_create_info *info,
1450 const VkAllocationCallbacks* alloc,
1451 VkImage *pImage);
1452
1453 VkResult
1454 radv_image_from_gralloc(VkDevice device_h,
1455 const VkImageCreateInfo *base_info,
1456 const VkNativeBufferANDROID *gralloc_info,
1457 const VkAllocationCallbacks *alloc,
1458 VkImage *out_image_h);
1459
1460 void radv_image_view_init(struct radv_image_view *view,
1461 struct radv_device *device,
1462 const VkImageViewCreateInfo* pCreateInfo);
1463
1464 struct radv_buffer_view {
1465 struct radeon_winsys_bo *bo;
1466 VkFormat vk_format;
1467 uint64_t range; /**< VkBufferViewCreateInfo::range */
1468 uint32_t state[4];
1469 };
1470 void radv_buffer_view_init(struct radv_buffer_view *view,
1471 struct radv_device *device,
1472 const VkBufferViewCreateInfo* pCreateInfo);
1473
1474 static inline struct VkExtent3D
1475 radv_sanitize_image_extent(const VkImageType imageType,
1476 const struct VkExtent3D imageExtent)
1477 {
1478 switch (imageType) {
1479 case VK_IMAGE_TYPE_1D:
1480 return (VkExtent3D) { imageExtent.width, 1, 1 };
1481 case VK_IMAGE_TYPE_2D:
1482 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1483 case VK_IMAGE_TYPE_3D:
1484 return imageExtent;
1485 default:
1486 unreachable("invalid image type");
1487 }
1488 }
1489
1490 static inline struct VkOffset3D
1491 radv_sanitize_image_offset(const VkImageType imageType,
1492 const struct VkOffset3D imageOffset)
1493 {
1494 switch (imageType) {
1495 case VK_IMAGE_TYPE_1D:
1496 return (VkOffset3D) { imageOffset.x, 0, 0 };
1497 case VK_IMAGE_TYPE_2D:
1498 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1499 case VK_IMAGE_TYPE_3D:
1500 return imageOffset;
1501 default:
1502 unreachable("invalid image type");
1503 }
1504 }
1505
1506 static inline bool
1507 radv_image_extent_compare(const struct radv_image *image,
1508 const VkExtent3D *extent)
1509 {
1510 if (extent->width != image->info.width ||
1511 extent->height != image->info.height ||
1512 extent->depth != image->info.depth)
1513 return false;
1514 return true;
1515 }
1516
1517 struct radv_sampler {
1518 uint32_t state[4];
1519 };
1520
1521 struct radv_color_buffer_info {
1522 uint64_t cb_color_base;
1523 uint64_t cb_color_cmask;
1524 uint64_t cb_color_fmask;
1525 uint64_t cb_dcc_base;
1526 uint32_t cb_color_pitch;
1527 uint32_t cb_color_slice;
1528 uint32_t cb_color_view;
1529 uint32_t cb_color_info;
1530 uint32_t cb_color_attrib;
1531 uint32_t cb_color_attrib2;
1532 uint32_t cb_dcc_control;
1533 uint32_t cb_color_cmask_slice;
1534 uint32_t cb_color_fmask_slice;
1535 };
1536
1537 struct radv_ds_buffer_info {
1538 uint64_t db_z_read_base;
1539 uint64_t db_stencil_read_base;
1540 uint64_t db_z_write_base;
1541 uint64_t db_stencil_write_base;
1542 uint64_t db_htile_data_base;
1543 uint32_t db_depth_info;
1544 uint32_t db_z_info;
1545 uint32_t db_stencil_info;
1546 uint32_t db_depth_view;
1547 uint32_t db_depth_size;
1548 uint32_t db_depth_slice;
1549 uint32_t db_htile_surface;
1550 uint32_t pa_su_poly_offset_db_fmt_cntl;
1551 uint32_t db_z_info2;
1552 uint32_t db_stencil_info2;
1553 float offset_scale;
1554 };
1555
1556 struct radv_attachment_info {
1557 union {
1558 struct radv_color_buffer_info cb;
1559 struct radv_ds_buffer_info ds;
1560 };
1561 struct radv_image_view *attachment;
1562 };
1563
1564 struct radv_framebuffer {
1565 uint32_t width;
1566 uint32_t height;
1567 uint32_t layers;
1568
1569 uint32_t attachment_count;
1570 struct radv_attachment_info attachments[0];
1571 };
1572
1573 struct radv_subpass_barrier {
1574 VkPipelineStageFlags src_stage_mask;
1575 VkAccessFlags src_access_mask;
1576 VkAccessFlags dst_access_mask;
1577 };
1578
1579 struct radv_subpass {
1580 uint32_t input_count;
1581 uint32_t color_count;
1582 VkAttachmentReference * input_attachments;
1583 VkAttachmentReference * color_attachments;
1584 VkAttachmentReference * resolve_attachments;
1585 VkAttachmentReference depth_stencil_attachment;
1586
1587 /** Subpass has at least one resolve attachment */
1588 bool has_resolve;
1589
1590 struct radv_subpass_barrier start_barrier;
1591
1592 uint32_t view_mask;
1593 VkSampleCountFlagBits max_sample_count;
1594 };
1595
1596 struct radv_render_pass_attachment {
1597 VkFormat format;
1598 uint32_t samples;
1599 VkAttachmentLoadOp load_op;
1600 VkAttachmentLoadOp stencil_load_op;
1601 VkImageLayout initial_layout;
1602 VkImageLayout final_layout;
1603 uint32_t view_mask;
1604 };
1605
1606 struct radv_render_pass {
1607 uint32_t attachment_count;
1608 uint32_t subpass_count;
1609 VkAttachmentReference * subpass_attachments;
1610 struct radv_render_pass_attachment * attachments;
1611 struct radv_subpass_barrier end_barrier;
1612 struct radv_subpass subpasses[0];
1613 };
1614
1615 VkResult radv_device_init_meta(struct radv_device *device);
1616 void radv_device_finish_meta(struct radv_device *device);
1617
1618 struct radv_query_pool {
1619 struct radeon_winsys_bo *bo;
1620 uint32_t stride;
1621 uint32_t availability_offset;
1622 uint64_t size;
1623 char *ptr;
1624 VkQueryType type;
1625 uint32_t pipeline_stats_mask;
1626 };
1627
1628 struct radv_semaphore {
1629 /* use a winsys sem for non-exportable */
1630 struct radeon_winsys_sem *sem;
1631 uint32_t syncobj;
1632 uint32_t temp_syncobj;
1633 };
1634
1635 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1636 int num_wait_sems,
1637 const VkSemaphore *wait_sems,
1638 int num_signal_sems,
1639 const VkSemaphore *signal_sems,
1640 VkFence fence);
1641 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1642
1643 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1644 VkPipelineBindPoint bind_point,
1645 struct radv_descriptor_set *set,
1646 unsigned idx);
1647
1648 void
1649 radv_update_descriptor_sets(struct radv_device *device,
1650 struct radv_cmd_buffer *cmd_buffer,
1651 VkDescriptorSet overrideSet,
1652 uint32_t descriptorWriteCount,
1653 const VkWriteDescriptorSet *pDescriptorWrites,
1654 uint32_t descriptorCopyCount,
1655 const VkCopyDescriptorSet *pDescriptorCopies);
1656
1657 void
1658 radv_update_descriptor_set_with_template(struct radv_device *device,
1659 struct radv_cmd_buffer *cmd_buffer,
1660 struct radv_descriptor_set *set,
1661 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1662 const void *pData);
1663
1664 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1665 VkPipelineBindPoint pipelineBindPoint,
1666 VkPipelineLayout _layout,
1667 uint32_t set,
1668 uint32_t descriptorWriteCount,
1669 const VkWriteDescriptorSet *pDescriptorWrites);
1670
1671 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1672 struct radv_image *image, uint32_t value);
1673 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1674 struct radv_image *image, uint32_t value);
1675
1676 struct radv_fence {
1677 struct radeon_winsys_fence *fence;
1678 bool submitted;
1679 bool signalled;
1680
1681 uint32_t syncobj;
1682 uint32_t temp_syncobj;
1683 };
1684
1685 /* radv_nir_to_llvm.c */
1686 struct radv_shader_variant_info;
1687 struct radv_nir_compiler_options;
1688
1689 void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
1690 struct nir_shader *geom_shader,
1691 struct ac_shader_binary *binary,
1692 struct ac_shader_config *config,
1693 struct radv_shader_variant_info *shader_info,
1694 const struct radv_nir_compiler_options *option);
1695
1696 void radv_compile_nir_shader(LLVMTargetMachineRef tm,
1697 struct ac_shader_binary *binary,
1698 struct ac_shader_config *config,
1699 struct radv_shader_variant_info *shader_info,
1700 struct nir_shader *const *nir,
1701 int nir_count,
1702 const struct radv_nir_compiler_options *options);
1703
1704 /* radv_shader_info.h */
1705 struct radv_shader_info;
1706
1707 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1708 const struct radv_nir_compiler_options *options,
1709 struct radv_shader_info *info);
1710
1711 struct radeon_winsys_sem;
1712
1713 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1714 \
1715 static inline struct __radv_type * \
1716 __radv_type ## _from_handle(__VkType _handle) \
1717 { \
1718 return (struct __radv_type *) _handle; \
1719 } \
1720 \
1721 static inline __VkType \
1722 __radv_type ## _to_handle(struct __radv_type *_obj) \
1723 { \
1724 return (__VkType) _obj; \
1725 }
1726
1727 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1728 \
1729 static inline struct __radv_type * \
1730 __radv_type ## _from_handle(__VkType _handle) \
1731 { \
1732 return (struct __radv_type *)(uintptr_t) _handle; \
1733 } \
1734 \
1735 static inline __VkType \
1736 __radv_type ## _to_handle(struct __radv_type *_obj) \
1737 { \
1738 return (__VkType)(uintptr_t) _obj; \
1739 }
1740
1741 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1742 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1743
1744 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1745 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1746 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1747 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1748 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1749
1750 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1751 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1752 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1753 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1754 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1755 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1756 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1757 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1758 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1759 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1760 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1761 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1762 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1763 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1764 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1765 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1766 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1767 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1768 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1769 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1770 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1771
1772 #endif /* RADV_PRIVATE_H */