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radv/gfx10: add Wave32 support for fragment shaders
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
53 #include "vk_alloc.h"
54 #include "vk_debug_report.h"
55
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
66 #include "sid.h"
67
68 #include <llvm-c/TargetMachine.h>
69
70 /* Pre-declarations needed for WSI entrypoints */
71 struct wl_surface;
72 struct wl_display;
73 typedef struct xcb_connection_t xcb_connection_t;
74 typedef uint32_t xcb_visualid_t;
75 typedef uint32_t xcb_window_t;
76
77 #include <vulkan/vulkan.h>
78 #include <vulkan/vulkan_intel.h>
79 #include <vulkan/vk_icd.h>
80 #include <vulkan/vk_android_native_buffer.h>
81
82 #include "radv_entrypoints.h"
83
84 #include "wsi_common.h"
85 #include "wsi_common_display.h"
86
87 struct gfx10_format {
88 unsigned img_format:9;
89
90 /* Various formats are only supported with workarounds for vertex fetch,
91 * and some 32_32_32 formats are supported natively, but only for buffers
92 * (possibly with some image support, actually, but no filtering). */
93 bool buffers_only:1;
94 };
95
96 #include "gfx10_format_table.h"
97
98 enum radv_mem_heap {
99 RADV_MEM_HEAP_VRAM,
100 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
101 RADV_MEM_HEAP_GTT,
102 RADV_MEM_HEAP_COUNT
103 };
104
105 enum radv_mem_type {
106 RADV_MEM_TYPE_VRAM,
107 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
108 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
109 RADV_MEM_TYPE_GTT_CACHED,
110 RADV_MEM_TYPE_COUNT
111 };
112
113 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
114
115 static inline uint32_t
116 align_u32(uint32_t v, uint32_t a)
117 {
118 assert(a != 0 && a == (a & -a));
119 return (v + a - 1) & ~(a - 1);
120 }
121
122 static inline uint32_t
123 align_u32_npot(uint32_t v, uint32_t a)
124 {
125 return (v + a - 1) / a * a;
126 }
127
128 static inline uint64_t
129 align_u64(uint64_t v, uint64_t a)
130 {
131 assert(a != 0 && a == (a & -a));
132 return (v + a - 1) & ~(a - 1);
133 }
134
135 static inline int32_t
136 align_i32(int32_t v, int32_t a)
137 {
138 assert(a != 0 && a == (a & -a));
139 return (v + a - 1) & ~(a - 1);
140 }
141
142 /** Alignment must be a power of 2. */
143 static inline bool
144 radv_is_aligned(uintmax_t n, uintmax_t a)
145 {
146 assert(a == (a & -a));
147 return (n & (a - 1)) == 0;
148 }
149
150 static inline uint32_t
151 round_up_u32(uint32_t v, uint32_t a)
152 {
153 return (v + a - 1) / a;
154 }
155
156 static inline uint64_t
157 round_up_u64(uint64_t v, uint64_t a)
158 {
159 return (v + a - 1) / a;
160 }
161
162 static inline uint32_t
163 radv_minify(uint32_t n, uint32_t levels)
164 {
165 if (unlikely(n == 0))
166 return 0;
167 else
168 return MAX2(n >> levels, 1);
169 }
170 static inline float
171 radv_clamp_f(float f, float min, float max)
172 {
173 assert(min < max);
174
175 if (f > max)
176 return max;
177 else if (f < min)
178 return min;
179 else
180 return f;
181 }
182
183 static inline bool
184 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
185 {
186 if (*inout_mask & clear_mask) {
187 *inout_mask &= ~clear_mask;
188 return true;
189 } else {
190 return false;
191 }
192 }
193
194 #define for_each_bit(b, dword) \
195 for (uint32_t __dword = (dword); \
196 (b) = __builtin_ffs(__dword) - 1, __dword; \
197 __dword &= ~(1 << (b)))
198
199 #define typed_memcpy(dest, src, count) ({ \
200 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
201 memcpy((dest), (src), (count) * sizeof(*(src))); \
202 })
203
204 /* Whenever we generate an error, pass it through this function. Useful for
205 * debugging, where we can break on it. Only call at error site, not when
206 * propagating errors. Might be useful to plug in a stack trace here.
207 */
208
209 struct radv_instance;
210
211 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
212
213 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
214 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
215
216 void __radv_finishme(const char *file, int line, const char *format, ...)
217 radv_printflike(3, 4);
218 void radv_loge(const char *format, ...) radv_printflike(1, 2);
219 void radv_loge_v(const char *format, va_list va);
220 void radv_logi(const char *format, ...) radv_printflike(1, 2);
221 void radv_logi_v(const char *format, va_list va);
222
223 /**
224 * Print a FINISHME message, including its source location.
225 */
226 #define radv_finishme(format, ...) \
227 do { \
228 static bool reported = false; \
229 if (!reported) { \
230 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
231 reported = true; \
232 } \
233 } while (0)
234
235 /* A non-fatal assert. Useful for debugging. */
236 #ifdef DEBUG
237 #define radv_assert(x) ({ \
238 if (unlikely(!(x))) \
239 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
240 })
241 #else
242 #define radv_assert(x)
243 #endif
244
245 #define stub_return(v) \
246 do { \
247 radv_finishme("stub %s", __func__); \
248 return (v); \
249 } while (0)
250
251 #define stub() \
252 do { \
253 radv_finishme("stub %s", __func__); \
254 return; \
255 } while (0)
256
257 void *radv_lookup_entrypoint_unchecked(const char *name);
258 void *radv_lookup_entrypoint_checked(const char *name,
259 uint32_t core_version,
260 const struct radv_instance_extension_table *instance,
261 const struct radv_device_extension_table *device);
262 void *radv_lookup_physical_device_entrypoint_checked(const char *name,
263 uint32_t core_version,
264 const struct radv_instance_extension_table *instance);
265
266 struct radv_physical_device {
267 VK_LOADER_DATA _loader_data;
268
269 struct radv_instance * instance;
270
271 struct radeon_winsys *ws;
272 struct radeon_info rad_info;
273 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
274 uint8_t driver_uuid[VK_UUID_SIZE];
275 uint8_t device_uuid[VK_UUID_SIZE];
276 uint8_t cache_uuid[VK_UUID_SIZE];
277
278 int local_fd;
279 int master_fd;
280 struct wsi_device wsi_device;
281
282 bool has_rbplus; /* if RB+ register exist */
283 bool rbplus_allowed; /* if RB+ is allowed */
284 bool has_clear_state;
285 bool cpdma_prefetch_writes_memory;
286 bool has_scissor_bug;
287 bool has_tc_compat_zrange_bug;
288
289 bool has_out_of_order_rast;
290 bool out_of_order_rast_allowed;
291
292 /* Whether DCC should be enabled for MSAA textures. */
293 bool dcc_msaa_allowed;
294
295 /* Whether LOAD_CONTEXT_REG packets are supported. */
296 bool has_load_ctx_reg_pkt;
297
298 /* Whether to enable the AMD_shader_ballot extension */
299 bool use_shader_ballot;
300
301 /* Whether DISABLE_CONSTANT_ENCODE_REG is supported. */
302 bool has_dcc_constant_encode;
303
304 /* Number of threads per wave. */
305 uint8_t ps_wave_size;
306 uint8_t cs_wave_size;
307
308 /* This is the drivers on-disk cache used as a fallback as opposed to
309 * the pipeline cache defined by apps.
310 */
311 struct disk_cache * disk_cache;
312
313 VkPhysicalDeviceMemoryProperties memory_properties;
314 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
315
316 drmPciBusInfo bus_info;
317
318 struct radv_device_extension_table supported_extensions;
319 };
320
321 struct radv_instance {
322 VK_LOADER_DATA _loader_data;
323
324 VkAllocationCallbacks alloc;
325
326 uint32_t apiVersion;
327 int physicalDeviceCount;
328 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
329
330 uint64_t debug_flags;
331 uint64_t perftest_flags;
332
333 struct vk_debug_report_instance debug_report_callbacks;
334
335 struct radv_instance_extension_table enabled_extensions;
336
337 struct driOptionCache dri_options;
338 struct driOptionCache available_dri_options;
339 };
340
341 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
342 void radv_finish_wsi(struct radv_physical_device *physical_device);
343
344 bool radv_instance_extension_supported(const char *name);
345 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
346 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
347 const char *name);
348
349 struct cache_entry;
350
351 struct radv_pipeline_cache {
352 struct radv_device * device;
353 pthread_mutex_t mutex;
354
355 uint32_t total_size;
356 uint32_t table_size;
357 uint32_t kernel_count;
358 struct cache_entry ** hash_table;
359 bool modified;
360
361 VkAllocationCallbacks alloc;
362 };
363
364 struct radv_pipeline_key {
365 uint32_t instance_rate_inputs;
366 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
367 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
368 uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
369 uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
370 uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
371 uint64_t vertex_alpha_adjust;
372 uint32_t vertex_post_shuffle;
373 unsigned tess_input_vertices;
374 uint32_t col_format;
375 uint32_t is_int8;
376 uint32_t is_int10;
377 uint8_t log2_ps_iter_samples;
378 uint8_t num_samples;
379 uint32_t has_multiview_view_index : 1;
380 uint32_t optimisations_disabled : 1;
381 };
382
383 struct radv_shader_binary;
384 struct radv_shader_variant;
385
386 void
387 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
388 struct radv_device *device);
389 void
390 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
391 bool
392 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
393 const void *data, size_t size);
394
395 bool
396 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
397 struct radv_pipeline_cache *cache,
398 const unsigned char *sha1,
399 struct radv_shader_variant **variants,
400 bool *found_in_application_cache);
401
402 void
403 radv_pipeline_cache_insert_shaders(struct radv_device *device,
404 struct radv_pipeline_cache *cache,
405 const unsigned char *sha1,
406 struct radv_shader_variant **variants,
407 struct radv_shader_binary *const *binaries);
408
409 enum radv_blit_ds_layout {
410 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
411 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
412 RADV_BLIT_DS_LAYOUT_COUNT,
413 };
414
415 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
416 {
417 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
418 }
419
420 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
421 {
422 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
423 }
424
425 enum radv_meta_dst_layout {
426 RADV_META_DST_LAYOUT_GENERAL,
427 RADV_META_DST_LAYOUT_OPTIMAL,
428 RADV_META_DST_LAYOUT_COUNT,
429 };
430
431 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
432 {
433 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
434 }
435
436 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
437 {
438 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
439 }
440
441 struct radv_meta_state {
442 VkAllocationCallbacks alloc;
443
444 struct radv_pipeline_cache cache;
445
446 /*
447 * For on-demand pipeline creation, makes sure that
448 * only one thread tries to build a pipeline at the same time.
449 */
450 mtx_t mtx;
451
452 /**
453 * Use array element `i` for images with `2^i` samples.
454 */
455 struct {
456 VkRenderPass render_pass[NUM_META_FS_KEYS];
457 VkPipeline color_pipelines[NUM_META_FS_KEYS];
458
459 VkRenderPass depthstencil_rp;
460 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
461 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
462 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
463 } clear[1 + MAX_SAMPLES_LOG2];
464
465 VkPipelineLayout clear_color_p_layout;
466 VkPipelineLayout clear_depth_p_layout;
467
468 /* Optimized compute fast HTILE clear for stencil or depth only. */
469 VkPipeline clear_htile_mask_pipeline;
470 VkPipelineLayout clear_htile_mask_p_layout;
471 VkDescriptorSetLayout clear_htile_mask_ds_layout;
472
473 struct {
474 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
475
476 /** Pipeline that blits from a 1D image. */
477 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
478
479 /** Pipeline that blits from a 2D image. */
480 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
481
482 /** Pipeline that blits from a 3D image. */
483 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
484
485 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
486 VkPipeline depth_only_1d_pipeline;
487 VkPipeline depth_only_2d_pipeline;
488 VkPipeline depth_only_3d_pipeline;
489
490 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
491 VkPipeline stencil_only_1d_pipeline;
492 VkPipeline stencil_only_2d_pipeline;
493 VkPipeline stencil_only_3d_pipeline;
494 VkPipelineLayout pipeline_layout;
495 VkDescriptorSetLayout ds_layout;
496 } blit;
497
498 struct {
499 VkPipelineLayout p_layouts[5];
500 VkDescriptorSetLayout ds_layouts[5];
501 VkPipeline pipelines[5][NUM_META_FS_KEYS];
502
503 VkPipeline depth_only_pipeline[5];
504
505 VkPipeline stencil_only_pipeline[5];
506 } blit2d[1 + MAX_SAMPLES_LOG2];
507
508 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
509 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
510 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
511
512 struct {
513 VkPipelineLayout img_p_layout;
514 VkDescriptorSetLayout img_ds_layout;
515 VkPipeline pipeline;
516 VkPipeline pipeline_3d;
517 } itob;
518 struct {
519 VkPipelineLayout img_p_layout;
520 VkDescriptorSetLayout img_ds_layout;
521 VkPipeline pipeline;
522 VkPipeline pipeline_3d;
523 } btoi;
524 struct {
525 VkPipelineLayout img_p_layout;
526 VkDescriptorSetLayout img_ds_layout;
527 VkPipeline pipeline;
528 } btoi_r32g32b32;
529 struct {
530 VkPipelineLayout img_p_layout;
531 VkDescriptorSetLayout img_ds_layout;
532 VkPipeline pipeline;
533 VkPipeline pipeline_3d;
534 } itoi;
535 struct {
536 VkPipelineLayout img_p_layout;
537 VkDescriptorSetLayout img_ds_layout;
538 VkPipeline pipeline;
539 } itoi_r32g32b32;
540 struct {
541 VkPipelineLayout img_p_layout;
542 VkDescriptorSetLayout img_ds_layout;
543 VkPipeline pipeline;
544 VkPipeline pipeline_3d;
545 } cleari;
546 struct {
547 VkPipelineLayout img_p_layout;
548 VkDescriptorSetLayout img_ds_layout;
549 VkPipeline pipeline;
550 } cleari_r32g32b32;
551
552 struct {
553 VkPipelineLayout p_layout;
554 VkPipeline pipeline[NUM_META_FS_KEYS];
555 VkRenderPass pass[NUM_META_FS_KEYS];
556 } resolve;
557
558 struct {
559 VkDescriptorSetLayout ds_layout;
560 VkPipelineLayout p_layout;
561 struct {
562 VkPipeline pipeline;
563 VkPipeline i_pipeline;
564 VkPipeline srgb_pipeline;
565 } rc[MAX_SAMPLES_LOG2];
566
567 VkPipeline depth_zero_pipeline;
568 struct {
569 VkPipeline average_pipeline;
570 VkPipeline max_pipeline;
571 VkPipeline min_pipeline;
572 } depth[MAX_SAMPLES_LOG2];
573
574 VkPipeline stencil_zero_pipeline;
575 struct {
576 VkPipeline max_pipeline;
577 VkPipeline min_pipeline;
578 } stencil[MAX_SAMPLES_LOG2];
579 } resolve_compute;
580
581 struct {
582 VkDescriptorSetLayout ds_layout;
583 VkPipelineLayout p_layout;
584
585 struct {
586 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
587 VkPipeline pipeline[NUM_META_FS_KEYS];
588 } rc[MAX_SAMPLES_LOG2];
589
590 VkRenderPass depth_render_pass;
591 VkPipeline depth_zero_pipeline;
592 struct {
593 VkPipeline average_pipeline;
594 VkPipeline max_pipeline;
595 VkPipeline min_pipeline;
596 } depth[MAX_SAMPLES_LOG2];
597
598 VkRenderPass stencil_render_pass;
599 VkPipeline stencil_zero_pipeline;
600 struct {
601 VkPipeline max_pipeline;
602 VkPipeline min_pipeline;
603 } stencil[MAX_SAMPLES_LOG2];
604 } resolve_fragment;
605
606 struct {
607 VkPipelineLayout p_layout;
608 VkPipeline decompress_pipeline;
609 VkPipeline resummarize_pipeline;
610 VkRenderPass pass;
611 } depth_decomp[1 + MAX_SAMPLES_LOG2];
612
613 struct {
614 VkPipelineLayout p_layout;
615 VkPipeline cmask_eliminate_pipeline;
616 VkPipeline fmask_decompress_pipeline;
617 VkPipeline dcc_decompress_pipeline;
618 VkRenderPass pass;
619
620 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
621 VkPipelineLayout dcc_decompress_compute_p_layout;
622 VkPipeline dcc_decompress_compute_pipeline;
623 } fast_clear_flush;
624
625 struct {
626 VkPipelineLayout fill_p_layout;
627 VkPipelineLayout copy_p_layout;
628 VkDescriptorSetLayout fill_ds_layout;
629 VkDescriptorSetLayout copy_ds_layout;
630 VkPipeline fill_pipeline;
631 VkPipeline copy_pipeline;
632 } buffer;
633
634 struct {
635 VkDescriptorSetLayout ds_layout;
636 VkPipelineLayout p_layout;
637 VkPipeline occlusion_query_pipeline;
638 VkPipeline pipeline_statistics_query_pipeline;
639 VkPipeline tfb_query_pipeline;
640 } query;
641
642 struct {
643 VkDescriptorSetLayout ds_layout;
644 VkPipelineLayout p_layout;
645 VkPipeline pipeline[MAX_SAMPLES_LOG2];
646 } fmask_expand;
647 };
648
649 /* queue types */
650 #define RADV_QUEUE_GENERAL 0
651 #define RADV_QUEUE_COMPUTE 1
652 #define RADV_QUEUE_TRANSFER 2
653
654 #define RADV_MAX_QUEUE_FAMILIES 3
655
656 enum ring_type radv_queue_family_to_ring(int f);
657
658 struct radv_queue {
659 VK_LOADER_DATA _loader_data;
660 struct radv_device * device;
661 struct radeon_winsys_ctx *hw_ctx;
662 enum radeon_ctx_priority priority;
663 uint32_t queue_family_index;
664 int queue_idx;
665 VkDeviceQueueCreateFlags flags;
666
667 uint32_t scratch_size;
668 uint32_t compute_scratch_size;
669 uint32_t esgs_ring_size;
670 uint32_t gsvs_ring_size;
671 bool has_tess_rings;
672 bool has_sample_positions;
673
674 struct radeon_winsys_bo *scratch_bo;
675 struct radeon_winsys_bo *descriptor_bo;
676 struct radeon_winsys_bo *compute_scratch_bo;
677 struct radeon_winsys_bo *esgs_ring_bo;
678 struct radeon_winsys_bo *gsvs_ring_bo;
679 struct radeon_winsys_bo *tess_rings_bo;
680 struct radeon_cmdbuf *initial_preamble_cs;
681 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
682 struct radeon_cmdbuf *continue_preamble_cs;
683 };
684
685 struct radv_bo_list {
686 struct radv_winsys_bo_list list;
687 unsigned capacity;
688 pthread_mutex_t mutex;
689 };
690
691 struct radv_device {
692 VK_LOADER_DATA _loader_data;
693
694 VkAllocationCallbacks alloc;
695
696 struct radv_instance * instance;
697 struct radeon_winsys *ws;
698
699 struct radv_meta_state meta_state;
700
701 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
702 int queue_count[RADV_MAX_QUEUE_FAMILIES];
703 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
704
705 bool always_use_syncobj;
706 bool has_distributed_tess;
707 bool pbb_allowed;
708 bool dfsm_allowed;
709 uint32_t tess_offchip_block_dw_size;
710 uint32_t scratch_waves;
711 uint32_t dispatch_initiator;
712
713 uint32_t gs_table_depth;
714
715 /* MSAA sample locations.
716 * The first index is the sample index.
717 * The second index is the coordinate: X, Y. */
718 float sample_locations_1x[1][2];
719 float sample_locations_2x[2][2];
720 float sample_locations_4x[4][2];
721 float sample_locations_8x[8][2];
722
723 /* GFX7 and later */
724 uint32_t gfx_init_size_dw;
725 struct radeon_winsys_bo *gfx_init;
726
727 struct radeon_winsys_bo *trace_bo;
728 uint32_t *trace_id_ptr;
729
730 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
731 bool keep_shader_info;
732
733 struct radv_physical_device *physical_device;
734
735 /* Backup in-memory cache to be used if the app doesn't provide one */
736 struct radv_pipeline_cache * mem_cache;
737
738 /*
739 * use different counters so MSAA MRTs get consecutive surface indices,
740 * even if MASK is allocated in between.
741 */
742 uint32_t image_mrt_offset_counter;
743 uint32_t fmask_mrt_offset_counter;
744 struct list_head shader_slabs;
745 mtx_t shader_slab_mutex;
746
747 /* For detecting VM faults reported by dmesg. */
748 uint64_t dmesg_timestamp;
749
750 struct radv_device_extension_table enabled_extensions;
751
752 /* Whether the driver uses a global BO list. */
753 bool use_global_bo_list;
754
755 struct radv_bo_list bo_list;
756
757 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
758 int force_aniso;
759 };
760
761 struct radv_device_memory {
762 struct radeon_winsys_bo *bo;
763 /* for dedicated allocations */
764 struct radv_image *image;
765 struct radv_buffer *buffer;
766 uint32_t type_index;
767 VkDeviceSize map_size;
768 void * map;
769 void * user_ptr;
770 };
771
772
773 struct radv_descriptor_range {
774 uint64_t va;
775 uint32_t size;
776 };
777
778 struct radv_descriptor_set {
779 const struct radv_descriptor_set_layout *layout;
780 uint32_t size;
781
782 struct radeon_winsys_bo *bo;
783 uint64_t va;
784 uint32_t *mapped_ptr;
785 struct radv_descriptor_range *dynamic_descriptors;
786
787 struct radeon_winsys_bo *descriptors[0];
788 };
789
790 struct radv_push_descriptor_set
791 {
792 struct radv_descriptor_set set;
793 uint32_t capacity;
794 };
795
796 struct radv_descriptor_pool_entry {
797 uint32_t offset;
798 uint32_t size;
799 struct radv_descriptor_set *set;
800 };
801
802 struct radv_descriptor_pool {
803 struct radeon_winsys_bo *bo;
804 uint8_t *mapped_ptr;
805 uint64_t current_offset;
806 uint64_t size;
807
808 uint8_t *host_memory_base;
809 uint8_t *host_memory_ptr;
810 uint8_t *host_memory_end;
811
812 uint32_t entry_count;
813 uint32_t max_entry_count;
814 struct radv_descriptor_pool_entry entries[0];
815 };
816
817 struct radv_descriptor_update_template_entry {
818 VkDescriptorType descriptor_type;
819
820 /* The number of descriptors to update */
821 uint32_t descriptor_count;
822
823 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
824 uint32_t dst_offset;
825
826 /* In dwords. Not valid/used for dynamic descriptors */
827 uint32_t dst_stride;
828
829 uint32_t buffer_offset;
830
831 /* Only valid for combined image samplers and samplers */
832 uint8_t has_sampler;
833 uint8_t sampler_offset;
834
835 /* In bytes */
836 size_t src_offset;
837 size_t src_stride;
838
839 /* For push descriptors */
840 const uint32_t *immutable_samplers;
841 };
842
843 struct radv_descriptor_update_template {
844 uint32_t entry_count;
845 VkPipelineBindPoint bind_point;
846 struct radv_descriptor_update_template_entry entry[0];
847 };
848
849 struct radv_buffer {
850 VkDeviceSize size;
851
852 VkBufferUsageFlags usage;
853 VkBufferCreateFlags flags;
854
855 /* Set when bound */
856 struct radeon_winsys_bo * bo;
857 VkDeviceSize offset;
858
859 bool shareable;
860 };
861
862 enum radv_dynamic_state_bits {
863 RADV_DYNAMIC_VIEWPORT = 1 << 0,
864 RADV_DYNAMIC_SCISSOR = 1 << 1,
865 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
866 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
867 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
868 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
869 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
870 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
871 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
872 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
873 RADV_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
874 RADV_DYNAMIC_ALL = (1 << 11) - 1,
875 };
876
877 enum radv_cmd_dirty_bits {
878 /* Keep the dynamic state dirty bits in sync with
879 * enum radv_dynamic_state_bits */
880 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
881 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
882 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
883 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
884 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
885 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
886 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
887 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
888 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
889 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
890 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
891 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 11) - 1,
892 RADV_CMD_DIRTY_PIPELINE = 1 << 11,
893 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 12,
894 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 13,
895 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 14,
896 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 15,
897 };
898
899 enum radv_cmd_flush_bits {
900 /* Instruction cache. */
901 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
902 /* Scalar L1 cache. */
903 RADV_CMD_FLAG_INV_SCACHE = 1 << 1,
904 /* Vector L1 cache. */
905 RADV_CMD_FLAG_INV_VCACHE = 1 << 2,
906 /* L2 cache + L2 metadata cache writeback & invalidate.
907 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
908 RADV_CMD_FLAG_INV_L2 = 1 << 3,
909 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
910 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
911 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
912 RADV_CMD_FLAG_WB_L2 = 1 << 4,
913 /* Framebuffer caches */
914 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
915 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
916 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
917 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
918 /* Engine synchronization. */
919 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
920 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
921 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
922 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
923 /* Pipeline query controls. */
924 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
925 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
926 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
927
928 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
929 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
930 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
931 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
932 };
933
934 struct radv_vertex_binding {
935 struct radv_buffer * buffer;
936 VkDeviceSize offset;
937 };
938
939 struct radv_streamout_binding {
940 struct radv_buffer *buffer;
941 VkDeviceSize offset;
942 VkDeviceSize size;
943 };
944
945 struct radv_streamout_state {
946 /* Mask of bound streamout buffers. */
947 uint8_t enabled_mask;
948
949 /* External state that comes from the last vertex stage, it must be
950 * set explicitely when binding a new graphics pipeline.
951 */
952 uint16_t stride_in_dw[MAX_SO_BUFFERS];
953 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
954
955 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
956 uint32_t hw_enabled_mask;
957
958 /* State of VGT_STRMOUT_(CONFIG|EN) */
959 bool streamout_enabled;
960 };
961
962 struct radv_viewport_state {
963 uint32_t count;
964 VkViewport viewports[MAX_VIEWPORTS];
965 };
966
967 struct radv_scissor_state {
968 uint32_t count;
969 VkRect2D scissors[MAX_SCISSORS];
970 };
971
972 struct radv_discard_rectangle_state {
973 uint32_t count;
974 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
975 };
976
977 struct radv_sample_locations_state {
978 VkSampleCountFlagBits per_pixel;
979 VkExtent2D grid_size;
980 uint32_t count;
981 VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
982 };
983
984 struct radv_dynamic_state {
985 /**
986 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
987 * Defines the set of saved dynamic state.
988 */
989 uint32_t mask;
990
991 struct radv_viewport_state viewport;
992
993 struct radv_scissor_state scissor;
994
995 float line_width;
996
997 struct {
998 float bias;
999 float clamp;
1000 float slope;
1001 } depth_bias;
1002
1003 float blend_constants[4];
1004
1005 struct {
1006 float min;
1007 float max;
1008 } depth_bounds;
1009
1010 struct {
1011 uint32_t front;
1012 uint32_t back;
1013 } stencil_compare_mask;
1014
1015 struct {
1016 uint32_t front;
1017 uint32_t back;
1018 } stencil_write_mask;
1019
1020 struct {
1021 uint32_t front;
1022 uint32_t back;
1023 } stencil_reference;
1024
1025 struct radv_discard_rectangle_state discard_rectangle;
1026
1027 struct radv_sample_locations_state sample_location;
1028 };
1029
1030 extern const struct radv_dynamic_state default_dynamic_state;
1031
1032 const char *
1033 radv_get_debug_option_name(int id);
1034
1035 const char *
1036 radv_get_perftest_option_name(int id);
1037
1038 /**
1039 * Attachment state when recording a renderpass instance.
1040 *
1041 * The clear value is valid only if there exists a pending clear.
1042 */
1043 struct radv_attachment_state {
1044 VkImageAspectFlags pending_clear_aspects;
1045 uint32_t cleared_views;
1046 VkClearValue clear_value;
1047 VkImageLayout current_layout;
1048 struct radv_sample_locations_state sample_location;
1049 };
1050
1051 struct radv_descriptor_state {
1052 struct radv_descriptor_set *sets[MAX_SETS];
1053 uint32_t dirty;
1054 uint32_t valid;
1055 struct radv_push_descriptor_set push_set;
1056 bool push_dirty;
1057 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1058 };
1059
1060 struct radv_subpass_sample_locs_state {
1061 uint32_t subpass_idx;
1062 struct radv_sample_locations_state sample_location;
1063 };
1064
1065 struct radv_cmd_state {
1066 /* Vertex descriptors */
1067 uint64_t vb_va;
1068 unsigned vb_size;
1069
1070 bool predicating;
1071 uint32_t dirty;
1072
1073 uint32_t prefetch_L2_mask;
1074
1075 struct radv_pipeline * pipeline;
1076 struct radv_pipeline * emitted_pipeline;
1077 struct radv_pipeline * compute_pipeline;
1078 struct radv_pipeline * emitted_compute_pipeline;
1079 struct radv_framebuffer * framebuffer;
1080 struct radv_render_pass * pass;
1081 const struct radv_subpass * subpass;
1082 struct radv_dynamic_state dynamic;
1083 struct radv_attachment_state * attachments;
1084 struct radv_streamout_state streamout;
1085 VkRect2D render_area;
1086
1087 uint32_t num_subpass_sample_locs;
1088 struct radv_subpass_sample_locs_state * subpass_sample_locs;
1089
1090 /* Index buffer */
1091 struct radv_buffer *index_buffer;
1092 uint64_t index_offset;
1093 uint32_t index_type;
1094 uint32_t max_index_count;
1095 uint64_t index_va;
1096 int32_t last_index_type;
1097
1098 int32_t last_primitive_reset_en;
1099 uint32_t last_primitive_reset_index;
1100 enum radv_cmd_flush_bits flush_bits;
1101 unsigned active_occlusion_queries;
1102 bool perfect_occlusion_queries_enabled;
1103 unsigned active_pipeline_queries;
1104 float offset_scale;
1105 uint32_t trace_id;
1106 uint32_t last_ia_multi_vgt_param;
1107
1108 uint32_t last_num_instances;
1109 uint32_t last_first_instance;
1110 uint32_t last_vertex_offset;
1111
1112 /* Whether CP DMA is busy/idle. */
1113 bool dma_is_busy;
1114
1115 /* Conditional rendering info. */
1116 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1117 uint64_t predication_va;
1118
1119 bool context_roll_without_scissor_emitted;
1120 };
1121
1122 struct radv_cmd_pool {
1123 VkAllocationCallbacks alloc;
1124 struct list_head cmd_buffers;
1125 struct list_head free_cmd_buffers;
1126 uint32_t queue_family_index;
1127 };
1128
1129 struct radv_cmd_buffer_upload {
1130 uint8_t *map;
1131 unsigned offset;
1132 uint64_t size;
1133 struct radeon_winsys_bo *upload_bo;
1134 struct list_head list;
1135 };
1136
1137 enum radv_cmd_buffer_status {
1138 RADV_CMD_BUFFER_STATUS_INVALID,
1139 RADV_CMD_BUFFER_STATUS_INITIAL,
1140 RADV_CMD_BUFFER_STATUS_RECORDING,
1141 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1142 RADV_CMD_BUFFER_STATUS_PENDING,
1143 };
1144
1145 struct radv_cmd_buffer {
1146 VK_LOADER_DATA _loader_data;
1147
1148 struct radv_device * device;
1149
1150 struct radv_cmd_pool * pool;
1151 struct list_head pool_link;
1152
1153 VkCommandBufferUsageFlags usage_flags;
1154 VkCommandBufferLevel level;
1155 enum radv_cmd_buffer_status status;
1156 struct radeon_cmdbuf *cs;
1157 struct radv_cmd_state state;
1158 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1159 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1160 uint32_t queue_family_index;
1161
1162 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1163 VkShaderStageFlags push_constant_stages;
1164 struct radv_descriptor_set meta_push_descriptors;
1165
1166 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1167
1168 struct radv_cmd_buffer_upload upload;
1169
1170 uint32_t scratch_size_needed;
1171 uint32_t compute_scratch_size_needed;
1172 uint32_t esgs_ring_size_needed;
1173 uint32_t gsvs_ring_size_needed;
1174 bool tess_rings_needed;
1175 bool sample_positions_needed;
1176
1177 VkResult record_result;
1178
1179 uint64_t gfx9_fence_va;
1180 uint32_t gfx9_fence_idx;
1181 uint64_t gfx9_eop_bug_va;
1182
1183 /**
1184 * Whether a query pool has been resetted and we have to flush caches.
1185 */
1186 bool pending_reset_query;
1187
1188 /**
1189 * Bitmask of pending active query flushes.
1190 */
1191 enum radv_cmd_flush_bits active_query_flush_bits;
1192 };
1193
1194 struct radv_image;
1195 struct radv_image_view;
1196
1197 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1198
1199 void si_emit_graphics(struct radv_physical_device *physical_device,
1200 struct radeon_cmdbuf *cs);
1201 void si_emit_compute(struct radv_physical_device *physical_device,
1202 struct radeon_cmdbuf *cs);
1203
1204 void cik_create_gfx_config(struct radv_device *device);
1205
1206 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1207 int count, const VkViewport *viewports);
1208 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1209 int count, const VkRect2D *scissors,
1210 const VkViewport *viewports, bool can_use_guardband);
1211 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1212 bool instanced_draw, bool indirect_draw,
1213 bool count_from_stream_output,
1214 uint32_t draw_vertex_count);
1215 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1216 enum chip_class chip_class,
1217 bool is_mec,
1218 unsigned event, unsigned event_flags,
1219 unsigned dst_sel, unsigned data_sel,
1220 uint64_t va,
1221 uint32_t new_fence,
1222 uint64_t gfx9_eop_bug_va);
1223
1224 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1225 uint32_t ref, uint32_t mask);
1226 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1227 enum chip_class chip_class,
1228 uint32_t *fence_ptr, uint64_t va,
1229 bool is_mec,
1230 enum radv_cmd_flush_bits flush_bits,
1231 uint64_t gfx9_eop_bug_va);
1232 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1233 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1234 bool inverted, uint64_t va);
1235 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1236 uint64_t src_va, uint64_t dest_va,
1237 uint64_t size);
1238 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1239 unsigned size);
1240 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1241 uint64_t size, unsigned value);
1242 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1243
1244 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1245 bool
1246 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1247 unsigned size,
1248 unsigned alignment,
1249 unsigned *out_offset,
1250 void **ptr);
1251 void
1252 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1253 const struct radv_subpass *subpass);
1254 bool
1255 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1256 unsigned size, unsigned alignmnet,
1257 const void *data, unsigned *out_offset);
1258
1259 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1260 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1261 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1262 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
1263 VkImageAspectFlags aspects,
1264 VkResolveModeFlagBitsKHR resolve_mode);
1265 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1266 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
1267 VkImageAspectFlags aspects,
1268 VkResolveModeFlagBitsKHR resolve_mode);
1269 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
1270 unsigned radv_get_default_max_sample_dist(int log_samples);
1271 void radv_device_init_msaa(struct radv_device *device);
1272
1273 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1274 struct radv_image *image,
1275 VkClearDepthStencilValue ds_clear_value,
1276 VkImageAspectFlags aspects);
1277
1278 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1279 const struct radv_image_view *iview,
1280 int cb_idx,
1281 uint32_t color_values[2]);
1282
1283 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1284 struct radv_image *image,
1285 const VkImageSubresourceRange *range, bool value);
1286
1287 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1288 struct radv_image *image,
1289 const VkImageSubresourceRange *range, bool value);
1290
1291 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1292 struct radeon_winsys_bo *bo,
1293 uint64_t offset, uint64_t size, uint32_t value);
1294 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1295 bool radv_get_memory_fd(struct radv_device *device,
1296 struct radv_device_memory *memory,
1297 int *pFD);
1298
1299 static inline void
1300 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1301 unsigned sh_offset, unsigned pointer_count,
1302 bool use_32bit_pointers)
1303 {
1304 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1305 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1306 }
1307
1308 static inline void
1309 radv_emit_shader_pointer_body(struct radv_device *device,
1310 struct radeon_cmdbuf *cs,
1311 uint64_t va, bool use_32bit_pointers)
1312 {
1313 radeon_emit(cs, va);
1314
1315 if (use_32bit_pointers) {
1316 assert(va == 0 ||
1317 (va >> 32) == device->physical_device->rad_info.address32_hi);
1318 } else {
1319 radeon_emit(cs, va >> 32);
1320 }
1321 }
1322
1323 static inline void
1324 radv_emit_shader_pointer(struct radv_device *device,
1325 struct radeon_cmdbuf *cs,
1326 uint32_t sh_offset, uint64_t va, bool global)
1327 {
1328 bool use_32bit_pointers = !global;
1329
1330 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1331 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1332 }
1333
1334 static inline struct radv_descriptor_state *
1335 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1336 VkPipelineBindPoint bind_point)
1337 {
1338 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1339 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1340 return &cmd_buffer->descriptors[bind_point];
1341 }
1342
1343 /*
1344 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1345 *
1346 * Limitations: Can't call normal dispatch functions without binding or rebinding
1347 * the compute pipeline.
1348 */
1349 void radv_unaligned_dispatch(
1350 struct radv_cmd_buffer *cmd_buffer,
1351 uint32_t x,
1352 uint32_t y,
1353 uint32_t z);
1354
1355 struct radv_event {
1356 struct radeon_winsys_bo *bo;
1357 uint64_t *map;
1358 };
1359
1360 struct radv_shader_module;
1361
1362 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1363 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1364 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1365 #define RADV_HASH_SHADER_NO_NGG (1 << 3)
1366
1367 void
1368 radv_hash_shaders(unsigned char *hash,
1369 const VkPipelineShaderStageCreateInfo **stages,
1370 const struct radv_pipeline_layout *layout,
1371 const struct radv_pipeline_key *key,
1372 uint32_t flags);
1373
1374 static inline gl_shader_stage
1375 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1376 {
1377 assert(__builtin_popcount(vk_stage) == 1);
1378 return ffs(vk_stage) - 1;
1379 }
1380
1381 static inline VkShaderStageFlagBits
1382 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1383 {
1384 return (1 << mesa_stage);
1385 }
1386
1387 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1388
1389 #define radv_foreach_stage(stage, stage_bits) \
1390 for (gl_shader_stage stage, \
1391 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1392 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1393 __tmp &= ~(1 << (stage)))
1394
1395 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1396 unsigned radv_format_meta_fs_key(VkFormat format);
1397
1398 struct radv_multisample_state {
1399 uint32_t db_eqaa;
1400 uint32_t pa_sc_line_cntl;
1401 uint32_t pa_sc_mode_cntl_0;
1402 uint32_t pa_sc_mode_cntl_1;
1403 uint32_t pa_sc_aa_config;
1404 uint32_t pa_sc_aa_mask[2];
1405 unsigned num_samples;
1406 };
1407
1408 struct radv_prim_vertex_count {
1409 uint8_t min;
1410 uint8_t incr;
1411 };
1412
1413 struct radv_vertex_elements_info {
1414 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1415 };
1416
1417 struct radv_ia_multi_vgt_param_helpers {
1418 uint32_t base;
1419 bool partial_es_wave;
1420 uint8_t primgroup_size;
1421 bool wd_switch_on_eop;
1422 bool ia_switch_on_eoi;
1423 bool partial_vs_wave;
1424 };
1425
1426 struct radv_binning_state {
1427 uint32_t pa_sc_binner_cntl_0;
1428 uint32_t db_dfsm_control;
1429 };
1430
1431 #define SI_GS_PER_ES 128
1432
1433 struct radv_pipeline {
1434 struct radv_device * device;
1435 struct radv_dynamic_state dynamic_state;
1436
1437 struct radv_pipeline_layout * layout;
1438
1439 bool need_indirect_descriptor_sets;
1440 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1441 struct radv_shader_variant *gs_copy_shader;
1442 VkShaderStageFlags active_stages;
1443
1444 struct radeon_cmdbuf cs;
1445 uint32_t ctx_cs_hash;
1446 struct radeon_cmdbuf ctx_cs;
1447
1448 struct radv_vertex_elements_info vertex_elements;
1449
1450 uint32_t binding_stride[MAX_VBS];
1451 uint8_t num_vertex_bindings;
1452
1453 uint32_t user_data_0[MESA_SHADER_STAGES];
1454 union {
1455 struct {
1456 struct radv_multisample_state ms;
1457 struct radv_binning_state binning;
1458 uint32_t spi_baryc_cntl;
1459 bool prim_restart_enable;
1460 unsigned esgs_ring_size;
1461 unsigned gsvs_ring_size;
1462 uint32_t vtx_base_sgpr;
1463 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1464 uint8_t vtx_emit_num;
1465 struct radv_prim_vertex_count prim_vertex_count;
1466 bool can_use_guardband;
1467 uint32_t needed_dynamic_state;
1468 bool disable_out_of_order_rast_for_occlusion;
1469
1470 /* Used for rbplus */
1471 uint32_t col_format;
1472 uint32_t cb_target_mask;
1473 } graphics;
1474 };
1475
1476 unsigned max_waves;
1477 unsigned scratch_bytes_per_wave;
1478
1479 /* Not NULL if graphics pipeline uses streamout. */
1480 struct radv_shader_variant *streamout_shader;
1481 };
1482
1483 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1484 {
1485 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1486 }
1487
1488 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1489 {
1490 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1491 }
1492
1493 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline);
1494
1495 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline);
1496
1497 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1498 gl_shader_stage stage,
1499 int idx);
1500
1501 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1502 gl_shader_stage stage);
1503
1504 struct radv_graphics_pipeline_create_info {
1505 bool use_rectlist;
1506 bool db_depth_clear;
1507 bool db_stencil_clear;
1508 bool db_depth_disable_expclear;
1509 bool db_stencil_disable_expclear;
1510 bool db_flush_depth_inplace;
1511 bool db_flush_stencil_inplace;
1512 bool db_resummarize;
1513 uint32_t custom_blend_mode;
1514 };
1515
1516 VkResult
1517 radv_graphics_pipeline_create(VkDevice device,
1518 VkPipelineCache cache,
1519 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1520 const struct radv_graphics_pipeline_create_info *extra,
1521 const VkAllocationCallbacks *alloc,
1522 VkPipeline *pPipeline);
1523
1524 struct vk_format_description;
1525 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1526 int first_non_void);
1527 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1528 int first_non_void);
1529 bool radv_is_buffer_format_supported(VkFormat format, bool *scaled);
1530 uint32_t radv_translate_colorformat(VkFormat format);
1531 uint32_t radv_translate_color_numformat(VkFormat format,
1532 const struct vk_format_description *desc,
1533 int first_non_void);
1534 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1535 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1536 uint32_t radv_translate_dbformat(VkFormat format);
1537 uint32_t radv_translate_tex_dataformat(VkFormat format,
1538 const struct vk_format_description *desc,
1539 int first_non_void);
1540 uint32_t radv_translate_tex_numformat(VkFormat format,
1541 const struct vk_format_description *desc,
1542 int first_non_void);
1543 bool radv_format_pack_clear_color(VkFormat format,
1544 uint32_t clear_vals[2],
1545 VkClearColorValue *value);
1546 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1547 bool radv_dcc_formats_compatible(VkFormat format1,
1548 VkFormat format2);
1549 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
1550
1551 struct radv_fmask_info {
1552 uint64_t offset;
1553 uint64_t size;
1554 unsigned alignment;
1555 unsigned pitch_in_pixels;
1556 unsigned bank_height;
1557 unsigned slice_tile_max;
1558 unsigned tile_mode_index;
1559 unsigned tile_swizzle;
1560 uint64_t slice_size;
1561 };
1562
1563 struct radv_cmask_info {
1564 uint64_t offset;
1565 uint64_t size;
1566 unsigned alignment;
1567 unsigned slice_tile_max;
1568 unsigned slice_size;
1569 };
1570
1571
1572 struct radv_image_plane {
1573 VkFormat format;
1574 struct radeon_surf surface;
1575 uint64_t offset;
1576 };
1577
1578 struct radv_image {
1579 VkImageType type;
1580 /* The original VkFormat provided by the client. This may not match any
1581 * of the actual surface formats.
1582 */
1583 VkFormat vk_format;
1584 VkImageAspectFlags aspects;
1585 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1586 struct ac_surf_info info;
1587 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1588 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1589
1590 VkDeviceSize size;
1591 uint32_t alignment;
1592
1593 unsigned queue_family_mask;
1594 bool exclusive;
1595 bool shareable;
1596
1597 /* Set when bound */
1598 struct radeon_winsys_bo *bo;
1599 VkDeviceSize offset;
1600 uint64_t dcc_offset;
1601 uint64_t htile_offset;
1602 bool tc_compatible_htile;
1603 bool tc_compatible_cmask;
1604
1605 struct radv_fmask_info fmask;
1606 struct radv_cmask_info cmask;
1607 uint64_t clear_value_offset;
1608 uint64_t fce_pred_offset;
1609 uint64_t dcc_pred_offset;
1610
1611 /*
1612 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1613 * stored at this offset is UINT_MAX, the driver will emit
1614 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1615 * SET_CONTEXT_REG packet.
1616 */
1617 uint64_t tc_compat_zrange_offset;
1618
1619 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1620 VkDeviceMemory owned_memory;
1621
1622 unsigned plane_count;
1623 struct radv_image_plane planes[0];
1624 };
1625
1626 /* Whether the image has a htile that is known consistent with the contents of
1627 * the image. */
1628 bool radv_layout_has_htile(const struct radv_image *image,
1629 VkImageLayout layout,
1630 unsigned queue_mask);
1631
1632 /* Whether the image has a htile that is known consistent with the contents of
1633 * the image and is allowed to be in compressed form.
1634 *
1635 * If this is false reads that don't use the htile should be able to return
1636 * correct results.
1637 */
1638 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1639 VkImageLayout layout,
1640 unsigned queue_mask);
1641
1642 bool radv_layout_can_fast_clear(const struct radv_image *image,
1643 VkImageLayout layout,
1644 unsigned queue_mask);
1645
1646 bool radv_layout_dcc_compressed(const struct radv_image *image,
1647 VkImageLayout layout,
1648 unsigned queue_mask);
1649
1650 /**
1651 * Return whether the image has CMASK metadata for color surfaces.
1652 */
1653 static inline bool
1654 radv_image_has_cmask(const struct radv_image *image)
1655 {
1656 return image->cmask.size;
1657 }
1658
1659 /**
1660 * Return whether the image has FMASK metadata for color surfaces.
1661 */
1662 static inline bool
1663 radv_image_has_fmask(const struct radv_image *image)
1664 {
1665 return image->fmask.size;
1666 }
1667
1668 /**
1669 * Return whether the image has DCC metadata for color surfaces.
1670 */
1671 static inline bool
1672 radv_image_has_dcc(const struct radv_image *image)
1673 {
1674 return image->planes[0].surface.dcc_size;
1675 }
1676
1677 /**
1678 * Return whether the image is TC-compatible CMASK.
1679 */
1680 static inline bool
1681 radv_image_is_tc_compat_cmask(const struct radv_image *image)
1682 {
1683 return radv_image_has_fmask(image) && image->tc_compatible_cmask;
1684 }
1685
1686 /**
1687 * Return whether DCC metadata is enabled for a level.
1688 */
1689 static inline bool
1690 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1691 {
1692 return radv_image_has_dcc(image) &&
1693 level < image->planes[0].surface.num_dcc_levels;
1694 }
1695
1696 /**
1697 * Return whether the image has CB metadata.
1698 */
1699 static inline bool
1700 radv_image_has_CB_metadata(const struct radv_image *image)
1701 {
1702 return radv_image_has_cmask(image) ||
1703 radv_image_has_fmask(image) ||
1704 radv_image_has_dcc(image);
1705 }
1706
1707 /**
1708 * Return whether the image has HTILE metadata for depth surfaces.
1709 */
1710 static inline bool
1711 radv_image_has_htile(const struct radv_image *image)
1712 {
1713 return image->planes[0].surface.htile_size;
1714 }
1715
1716 /**
1717 * Return whether HTILE metadata is enabled for a level.
1718 */
1719 static inline bool
1720 radv_htile_enabled(const struct radv_image *image, unsigned level)
1721 {
1722 return radv_image_has_htile(image) && level == 0;
1723 }
1724
1725 /**
1726 * Return whether the image is TC-compatible HTILE.
1727 */
1728 static inline bool
1729 radv_image_is_tc_compat_htile(const struct radv_image *image)
1730 {
1731 return radv_image_has_htile(image) && image->tc_compatible_htile;
1732 }
1733
1734 static inline uint64_t
1735 radv_image_get_fast_clear_va(const struct radv_image *image,
1736 uint32_t base_level)
1737 {
1738 uint64_t va = radv_buffer_get_va(image->bo);
1739 va += image->offset + image->clear_value_offset + base_level * 8;
1740 return va;
1741 }
1742
1743 static inline uint64_t
1744 radv_image_get_fce_pred_va(const struct radv_image *image,
1745 uint32_t base_level)
1746 {
1747 uint64_t va = radv_buffer_get_va(image->bo);
1748 va += image->offset + image->fce_pred_offset + base_level * 8;
1749 return va;
1750 }
1751
1752 static inline uint64_t
1753 radv_image_get_dcc_pred_va(const struct radv_image *image,
1754 uint32_t base_level)
1755 {
1756 uint64_t va = radv_buffer_get_va(image->bo);
1757 va += image->offset + image->dcc_pred_offset + base_level * 8;
1758 return va;
1759 }
1760
1761 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1762
1763 static inline uint32_t
1764 radv_get_layerCount(const struct radv_image *image,
1765 const VkImageSubresourceRange *range)
1766 {
1767 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1768 image->info.array_size - range->baseArrayLayer : range->layerCount;
1769 }
1770
1771 static inline uint32_t
1772 radv_get_levelCount(const struct radv_image *image,
1773 const VkImageSubresourceRange *range)
1774 {
1775 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1776 image->info.levels - range->baseMipLevel : range->levelCount;
1777 }
1778
1779 struct radeon_bo_metadata;
1780 void
1781 radv_init_metadata(struct radv_device *device,
1782 struct radv_image *image,
1783 struct radeon_bo_metadata *metadata);
1784
1785 void
1786 radv_image_override_offset_stride(struct radv_device *device,
1787 struct radv_image *image,
1788 uint64_t offset, uint32_t stride);
1789
1790 union radv_descriptor {
1791 struct {
1792 uint32_t plane0_descriptor[8];
1793 uint32_t fmask_descriptor[8];
1794 };
1795 struct {
1796 uint32_t plane_descriptors[3][8];
1797 };
1798 };
1799
1800 struct radv_image_view {
1801 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1802 struct radeon_winsys_bo *bo;
1803
1804 VkImageViewType type;
1805 VkImageAspectFlags aspect_mask;
1806 VkFormat vk_format;
1807 unsigned plane_id;
1808 bool multiple_planes;
1809 uint32_t base_layer;
1810 uint32_t layer_count;
1811 uint32_t base_mip;
1812 uint32_t level_count;
1813 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1814
1815 union radv_descriptor descriptor;
1816
1817 /* Descriptor for use as a storage image as opposed to a sampled image.
1818 * This has a few differences for cube maps (e.g. type).
1819 */
1820 union radv_descriptor storage_descriptor;
1821 };
1822
1823 struct radv_image_create_info {
1824 const VkImageCreateInfo *vk_info;
1825 bool scanout;
1826 bool no_metadata_planes;
1827 const struct radeon_bo_metadata *bo_metadata;
1828 };
1829
1830 VkResult radv_image_create(VkDevice _device,
1831 const struct radv_image_create_info *info,
1832 const VkAllocationCallbacks* alloc,
1833 VkImage *pImage);
1834
1835 VkResult
1836 radv_image_from_gralloc(VkDevice device_h,
1837 const VkImageCreateInfo *base_info,
1838 const VkNativeBufferANDROID *gralloc_info,
1839 const VkAllocationCallbacks *alloc,
1840 VkImage *out_image_h);
1841
1842 void radv_image_view_init(struct radv_image_view *view,
1843 struct radv_device *device,
1844 const VkImageViewCreateInfo* pCreateInfo);
1845
1846 VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
1847
1848 struct radv_sampler_ycbcr_conversion {
1849 VkFormat format;
1850 VkSamplerYcbcrModelConversion ycbcr_model;
1851 VkSamplerYcbcrRange ycbcr_range;
1852 VkComponentMapping components;
1853 VkChromaLocation chroma_offsets[2];
1854 VkFilter chroma_filter;
1855 };
1856
1857 struct radv_buffer_view {
1858 struct radeon_winsys_bo *bo;
1859 VkFormat vk_format;
1860 uint64_t range; /**< VkBufferViewCreateInfo::range */
1861 uint32_t state[4];
1862 };
1863 void radv_buffer_view_init(struct radv_buffer_view *view,
1864 struct radv_device *device,
1865 const VkBufferViewCreateInfo* pCreateInfo);
1866
1867 static inline struct VkExtent3D
1868 radv_sanitize_image_extent(const VkImageType imageType,
1869 const struct VkExtent3D imageExtent)
1870 {
1871 switch (imageType) {
1872 case VK_IMAGE_TYPE_1D:
1873 return (VkExtent3D) { imageExtent.width, 1, 1 };
1874 case VK_IMAGE_TYPE_2D:
1875 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1876 case VK_IMAGE_TYPE_3D:
1877 return imageExtent;
1878 default:
1879 unreachable("invalid image type");
1880 }
1881 }
1882
1883 static inline struct VkOffset3D
1884 radv_sanitize_image_offset(const VkImageType imageType,
1885 const struct VkOffset3D imageOffset)
1886 {
1887 switch (imageType) {
1888 case VK_IMAGE_TYPE_1D:
1889 return (VkOffset3D) { imageOffset.x, 0, 0 };
1890 case VK_IMAGE_TYPE_2D:
1891 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1892 case VK_IMAGE_TYPE_3D:
1893 return imageOffset;
1894 default:
1895 unreachable("invalid image type");
1896 }
1897 }
1898
1899 static inline bool
1900 radv_image_extent_compare(const struct radv_image *image,
1901 const VkExtent3D *extent)
1902 {
1903 if (extent->width != image->info.width ||
1904 extent->height != image->info.height ||
1905 extent->depth != image->info.depth)
1906 return false;
1907 return true;
1908 }
1909
1910 struct radv_sampler {
1911 uint32_t state[4];
1912 struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
1913 };
1914
1915 struct radv_color_buffer_info {
1916 uint64_t cb_color_base;
1917 uint64_t cb_color_cmask;
1918 uint64_t cb_color_fmask;
1919 uint64_t cb_dcc_base;
1920 uint32_t cb_color_slice;
1921 uint32_t cb_color_view;
1922 uint32_t cb_color_info;
1923 uint32_t cb_color_attrib;
1924 uint32_t cb_color_attrib2; /* GFX9 and later */
1925 uint32_t cb_color_attrib3; /* GFX10 and later */
1926 uint32_t cb_dcc_control;
1927 uint32_t cb_color_cmask_slice;
1928 uint32_t cb_color_fmask_slice;
1929 union {
1930 uint32_t cb_color_pitch; // GFX6-GFX8
1931 uint32_t cb_mrt_epitch; // GFX9+
1932 };
1933 };
1934
1935 struct radv_ds_buffer_info {
1936 uint64_t db_z_read_base;
1937 uint64_t db_stencil_read_base;
1938 uint64_t db_z_write_base;
1939 uint64_t db_stencil_write_base;
1940 uint64_t db_htile_data_base;
1941 uint32_t db_depth_info;
1942 uint32_t db_z_info;
1943 uint32_t db_stencil_info;
1944 uint32_t db_depth_view;
1945 uint32_t db_depth_size;
1946 uint32_t db_depth_slice;
1947 uint32_t db_htile_surface;
1948 uint32_t pa_su_poly_offset_db_fmt_cntl;
1949 uint32_t db_z_info2; /* GFX9 only */
1950 uint32_t db_stencil_info2; /* GFX9 only */
1951 float offset_scale;
1952 };
1953
1954 struct radv_attachment_info {
1955 union {
1956 struct radv_color_buffer_info cb;
1957 struct radv_ds_buffer_info ds;
1958 };
1959 struct radv_image_view *attachment;
1960 };
1961
1962 struct radv_framebuffer {
1963 uint32_t width;
1964 uint32_t height;
1965 uint32_t layers;
1966
1967 uint32_t attachment_count;
1968 struct radv_attachment_info attachments[0];
1969 };
1970
1971 struct radv_subpass_barrier {
1972 VkPipelineStageFlags src_stage_mask;
1973 VkAccessFlags src_access_mask;
1974 VkAccessFlags dst_access_mask;
1975 };
1976
1977 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1978 const struct radv_subpass_barrier *barrier);
1979
1980 struct radv_subpass_attachment {
1981 uint32_t attachment;
1982 VkImageLayout layout;
1983 };
1984
1985 struct radv_subpass {
1986 uint32_t attachment_count;
1987 struct radv_subpass_attachment * attachments;
1988
1989 uint32_t input_count;
1990 uint32_t color_count;
1991 struct radv_subpass_attachment * input_attachments;
1992 struct radv_subpass_attachment * color_attachments;
1993 struct radv_subpass_attachment * resolve_attachments;
1994 struct radv_subpass_attachment * depth_stencil_attachment;
1995 struct radv_subpass_attachment * ds_resolve_attachment;
1996 VkResolveModeFlagBitsKHR depth_resolve_mode;
1997 VkResolveModeFlagBitsKHR stencil_resolve_mode;
1998
1999 /** Subpass has at least one color resolve attachment */
2000 bool has_color_resolve;
2001
2002 /** Subpass has at least one color attachment */
2003 bool has_color_att;
2004
2005 struct radv_subpass_barrier start_barrier;
2006
2007 uint32_t view_mask;
2008 VkSampleCountFlagBits max_sample_count;
2009 };
2010
2011 uint32_t
2012 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer);
2013
2014 struct radv_render_pass_attachment {
2015 VkFormat format;
2016 uint32_t samples;
2017 VkAttachmentLoadOp load_op;
2018 VkAttachmentLoadOp stencil_load_op;
2019 VkImageLayout initial_layout;
2020 VkImageLayout final_layout;
2021
2022 /* The subpass id in which the attachment will be used first/last. */
2023 uint32_t first_subpass_idx;
2024 uint32_t last_subpass_idx;
2025 };
2026
2027 struct radv_render_pass {
2028 uint32_t attachment_count;
2029 uint32_t subpass_count;
2030 struct radv_subpass_attachment * subpass_attachments;
2031 struct radv_render_pass_attachment * attachments;
2032 struct radv_subpass_barrier end_barrier;
2033 struct radv_subpass subpasses[0];
2034 };
2035
2036 VkResult radv_device_init_meta(struct radv_device *device);
2037 void radv_device_finish_meta(struct radv_device *device);
2038
2039 struct radv_query_pool {
2040 struct radeon_winsys_bo *bo;
2041 uint32_t stride;
2042 uint32_t availability_offset;
2043 uint64_t size;
2044 char *ptr;
2045 VkQueryType type;
2046 uint32_t pipeline_stats_mask;
2047 };
2048
2049 struct radv_semaphore {
2050 /* use a winsys sem for non-exportable */
2051 struct radeon_winsys_sem *sem;
2052 uint32_t syncobj;
2053 uint32_t temp_syncobj;
2054 };
2055
2056 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2057 VkPipelineBindPoint bind_point,
2058 struct radv_descriptor_set *set,
2059 unsigned idx);
2060
2061 void
2062 radv_update_descriptor_sets(struct radv_device *device,
2063 struct radv_cmd_buffer *cmd_buffer,
2064 VkDescriptorSet overrideSet,
2065 uint32_t descriptorWriteCount,
2066 const VkWriteDescriptorSet *pDescriptorWrites,
2067 uint32_t descriptorCopyCount,
2068 const VkCopyDescriptorSet *pDescriptorCopies);
2069
2070 void
2071 radv_update_descriptor_set_with_template(struct radv_device *device,
2072 struct radv_cmd_buffer *cmd_buffer,
2073 struct radv_descriptor_set *set,
2074 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2075 const void *pData);
2076
2077 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2078 VkPipelineBindPoint pipelineBindPoint,
2079 VkPipelineLayout _layout,
2080 uint32_t set,
2081 uint32_t descriptorWriteCount,
2082 const VkWriteDescriptorSet *pDescriptorWrites);
2083
2084 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2085 struct radv_image *image,
2086 const VkImageSubresourceRange *range, uint32_t value);
2087
2088 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
2089 struct radv_image *image,
2090 const VkImageSubresourceRange *range);
2091
2092 struct radv_fence {
2093 struct radeon_winsys_fence *fence;
2094 struct wsi_fence *fence_wsi;
2095
2096 uint32_t syncobj;
2097 uint32_t temp_syncobj;
2098 };
2099
2100 /* radv_nir_to_llvm.c */
2101 struct radv_shader_variant_info;
2102 struct radv_nir_compiler_options;
2103
2104 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
2105 struct nir_shader *geom_shader,
2106 struct radv_shader_binary **rbinary,
2107 struct radv_shader_variant_info *shader_info,
2108 const struct radv_nir_compiler_options *option);
2109
2110 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
2111 struct radv_shader_binary **rbinary,
2112 struct radv_shader_variant_info *shader_info,
2113 struct nir_shader *const *nir,
2114 int nir_count,
2115 const struct radv_nir_compiler_options *options);
2116
2117 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
2118 gl_shader_stage stage,
2119 const struct nir_shader *nir);
2120
2121 /* radv_shader_info.h */
2122 struct radv_shader_info;
2123
2124 void radv_nir_shader_info_pass(const struct nir_shader *nir,
2125 const struct radv_nir_compiler_options *options,
2126 struct radv_shader_info *info);
2127
2128 void radv_nir_shader_info_init(struct radv_shader_info *info);
2129
2130 struct radeon_winsys_sem;
2131
2132 uint64_t radv_get_current_time(void);
2133
2134 static inline uint32_t
2135 si_conv_gl_prim_to_vertices(unsigned gl_prim)
2136 {
2137 switch (gl_prim) {
2138 case 0: /* GL_POINTS */
2139 return 1;
2140 case 1: /* GL_LINES */
2141 case 3: /* GL_LINE_STRIP */
2142 return 2;
2143 case 4: /* GL_TRIANGLES */
2144 case 5: /* GL_TRIANGLE_STRIP */
2145 return 3;
2146 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2147 return 4;
2148 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2149 return 6;
2150 case 7: /* GL_QUADS */
2151 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2152 default:
2153 assert(0);
2154 return 0;
2155 }
2156 }
2157
2158 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2159 \
2160 static inline struct __radv_type * \
2161 __radv_type ## _from_handle(__VkType _handle) \
2162 { \
2163 return (struct __radv_type *) _handle; \
2164 } \
2165 \
2166 static inline __VkType \
2167 __radv_type ## _to_handle(struct __radv_type *_obj) \
2168 { \
2169 return (__VkType) _obj; \
2170 }
2171
2172 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2173 \
2174 static inline struct __radv_type * \
2175 __radv_type ## _from_handle(__VkType _handle) \
2176 { \
2177 return (struct __radv_type *)(uintptr_t) _handle; \
2178 } \
2179 \
2180 static inline __VkType \
2181 __radv_type ## _to_handle(struct __radv_type *_obj) \
2182 { \
2183 return (__VkType)(uintptr_t) _obj; \
2184 }
2185
2186 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2187 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2188
2189 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
2190 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
2191 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
2192 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
2193 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
2194
2195 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
2196 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
2197 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
2198 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
2199 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
2200 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
2201 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
2202 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
2203 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
2204 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
2205 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
2206 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
2207 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
2208 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
2209 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
2210 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2211 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2212 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2213 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2214 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
2215 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2216 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2217
2218 #endif /* RADV_PRIVATE_H */