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radv/gfx9: add support for 3d images to blit 2d paths
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
59
60 #include <llvm-c/TargetMachine.h>
61
62 /* Pre-declarations needed for WSI entrypoints */
63 struct wl_surface;
64 struct wl_display;
65 typedef struct xcb_connection_t xcb_connection_t;
66 typedef uint32_t xcb_visualid_t;
67 typedef uint32_t xcb_window_t;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "radv_entrypoints.h"
74
75 #include "wsi_common.h"
76
77 #define ATI_VENDOR_ID 0x1002
78
79 #define MAX_VBS 32
80 #define MAX_VERTEX_ATTRIBS 32
81 #define MAX_RTS 8
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
90 #define MAX_VIEWS 8
91
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
93
94 enum radv_mem_heap {
95 RADV_MEM_HEAP_VRAM,
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
97 RADV_MEM_HEAP_GTT,
98 RADV_MEM_HEAP_COUNT
99 };
100
101 enum radv_mem_type {
102 RADV_MEM_TYPE_VRAM,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
105 RADV_MEM_TYPE_GTT_CACHED,
106 RADV_MEM_TYPE_COUNT
107 };
108
109 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
110
111 static inline uint32_t
112 align_u32(uint32_t v, uint32_t a)
113 {
114 assert(a != 0 && a == (a & -a));
115 return (v + a - 1) & ~(a - 1);
116 }
117
118 static inline uint32_t
119 align_u32_npot(uint32_t v, uint32_t a)
120 {
121 return (v + a - 1) / a * a;
122 }
123
124 static inline uint64_t
125 align_u64(uint64_t v, uint64_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 static inline int32_t
132 align_i32(int32_t v, int32_t a)
133 {
134 assert(a != 0 && a == (a & -a));
135 return (v + a - 1) & ~(a - 1);
136 }
137
138 /** Alignment must be a power of 2. */
139 static inline bool
140 radv_is_aligned(uintmax_t n, uintmax_t a)
141 {
142 assert(a == (a & -a));
143 return (n & (a - 1)) == 0;
144 }
145
146 static inline uint32_t
147 round_up_u32(uint32_t v, uint32_t a)
148 {
149 return (v + a - 1) / a;
150 }
151
152 static inline uint64_t
153 round_up_u64(uint64_t v, uint64_t a)
154 {
155 return (v + a - 1) / a;
156 }
157
158 static inline uint32_t
159 radv_minify(uint32_t n, uint32_t levels)
160 {
161 if (unlikely(n == 0))
162 return 0;
163 else
164 return MAX2(n >> levels, 1);
165 }
166 static inline float
167 radv_clamp_f(float f, float min, float max)
168 {
169 assert(min < max);
170
171 if (f > max)
172 return max;
173 else if (f < min)
174 return min;
175 else
176 return f;
177 }
178
179 static inline bool
180 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
181 {
182 if (*inout_mask & clear_mask) {
183 *inout_mask &= ~clear_mask;
184 return true;
185 } else {
186 return false;
187 }
188 }
189
190 #define for_each_bit(b, dword) \
191 for (uint32_t __dword = (dword); \
192 (b) = __builtin_ffs(__dword) - 1, __dword; \
193 __dword &= ~(1 << (b)))
194
195 #define typed_memcpy(dest, src, count) ({ \
196 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
197 memcpy((dest), (src), (count) * sizeof(*(src))); \
198 })
199
200 /* Whenever we generate an error, pass it through this function. Useful for
201 * debugging, where we can break on it. Only call at error site, not when
202 * propagating errors. Might be useful to plug in a stack trace here.
203 */
204
205 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
206
207 #ifdef DEBUG
208 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
209 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
210 #else
211 #define vk_error(error) error
212 #define vk_errorf(error, format, ...) error
213 #endif
214
215 void __radv_finishme(const char *file, int line, const char *format, ...)
216 radv_printflike(3, 4);
217 void radv_loge(const char *format, ...) radv_printflike(1, 2);
218 void radv_loge_v(const char *format, va_list va);
219
220 /**
221 * Print a FINISHME message, including its source location.
222 */
223 #define radv_finishme(format, ...) \
224 do { \
225 static bool reported = false; \
226 if (!reported) { \
227 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
228 reported = true; \
229 } \
230 } while (0)
231
232 /* A non-fatal assert. Useful for debugging. */
233 #ifdef DEBUG
234 #define radv_assert(x) ({ \
235 if (unlikely(!(x))) \
236 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
237 })
238 #else
239 #define radv_assert(x)
240 #endif
241
242 #define stub_return(v) \
243 do { \
244 radv_finishme("stub %s", __func__); \
245 return (v); \
246 } while (0)
247
248 #define stub() \
249 do { \
250 radv_finishme("stub %s", __func__); \
251 return; \
252 } while (0)
253
254 void *radv_lookup_entrypoint(const char *name);
255
256 struct radv_physical_device {
257 VK_LOADER_DATA _loader_data;
258
259 struct radv_instance * instance;
260
261 struct radeon_winsys *ws;
262 struct radeon_info rad_info;
263 char path[20];
264 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
265 uint8_t driver_uuid[VK_UUID_SIZE];
266 uint8_t device_uuid[VK_UUID_SIZE];
267 uint8_t cache_uuid[VK_UUID_SIZE];
268
269 int local_fd;
270 struct wsi_device wsi_device;
271
272 bool has_rbplus; /* if RB+ register exist */
273 bool rbplus_allowed; /* if RB+ is allowed */
274 bool has_clear_state;
275
276 /* This is the drivers on-disk cache used as a fallback as opposed to
277 * the pipeline cache defined by apps.
278 */
279 struct disk_cache * disk_cache;
280
281 VkPhysicalDeviceMemoryProperties memory_properties;
282 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
283 };
284
285 struct radv_instance {
286 VK_LOADER_DATA _loader_data;
287
288 VkAllocationCallbacks alloc;
289
290 uint32_t apiVersion;
291 int physicalDeviceCount;
292 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
293
294 uint64_t debug_flags;
295 uint64_t perftest_flags;
296 };
297
298 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
299 void radv_finish_wsi(struct radv_physical_device *physical_device);
300
301 bool radv_instance_extension_supported(const char *name);
302 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
303 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
304 const char *name);
305
306 struct cache_entry;
307
308 struct radv_pipeline_cache {
309 struct radv_device * device;
310 pthread_mutex_t mutex;
311
312 uint32_t total_size;
313 uint32_t table_size;
314 uint32_t kernel_count;
315 struct cache_entry ** hash_table;
316 bool modified;
317
318 VkAllocationCallbacks alloc;
319 };
320
321 struct radv_pipeline_key {
322 uint32_t instance_rate_inputs;
323 unsigned tess_input_vertices;
324 uint32_t col_format;
325 uint32_t is_int8;
326 uint32_t is_int10;
327 uint32_t multisample : 1;
328 uint32_t has_multiview_view_index : 1;
329 };
330
331 void
332 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
333 struct radv_device *device);
334 void
335 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
336 void
337 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
338 const void *data, size_t size);
339
340 struct radv_shader_variant;
341
342 bool
343 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
344 struct radv_pipeline_cache *cache,
345 const unsigned char *sha1,
346 struct radv_shader_variant **variants);
347
348 void
349 radv_pipeline_cache_insert_shaders(struct radv_device *device,
350 struct radv_pipeline_cache *cache,
351 const unsigned char *sha1,
352 struct radv_shader_variant **variants,
353 const void *const *codes,
354 const unsigned *code_sizes);
355
356 struct radv_meta_state {
357 VkAllocationCallbacks alloc;
358
359 struct radv_pipeline_cache cache;
360
361 /**
362 * Use array element `i` for images with `2^i` samples.
363 */
364 struct {
365 VkRenderPass render_pass[NUM_META_FS_KEYS];
366 VkPipeline color_pipelines[NUM_META_FS_KEYS];
367
368 VkRenderPass depthstencil_rp;
369 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
370 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
371 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
372 } clear[1 + MAX_SAMPLES_LOG2];
373
374 VkPipelineLayout clear_color_p_layout;
375 VkPipelineLayout clear_depth_p_layout;
376 struct {
377 VkRenderPass render_pass[NUM_META_FS_KEYS];
378
379 /** Pipeline that blits from a 1D image. */
380 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
381
382 /** Pipeline that blits from a 2D image. */
383 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
384
385 /** Pipeline that blits from a 3D image. */
386 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
387
388 VkRenderPass depth_only_rp;
389 VkPipeline depth_only_1d_pipeline;
390 VkPipeline depth_only_2d_pipeline;
391 VkPipeline depth_only_3d_pipeline;
392
393 VkRenderPass stencil_only_rp;
394 VkPipeline stencil_only_1d_pipeline;
395 VkPipeline stencil_only_2d_pipeline;
396 VkPipeline stencil_only_3d_pipeline;
397 VkPipelineLayout pipeline_layout;
398 VkDescriptorSetLayout ds_layout;
399 } blit;
400
401 struct {
402 VkRenderPass render_passes[NUM_META_FS_KEYS];
403
404 VkPipelineLayout p_layouts[3];
405 VkDescriptorSetLayout ds_layouts[3];
406 VkPipeline pipelines[3][NUM_META_FS_KEYS];
407
408 VkRenderPass depth_only_rp;
409 VkPipeline depth_only_pipeline[3];
410
411 VkRenderPass stencil_only_rp;
412 VkPipeline stencil_only_pipeline[3];
413 } blit2d;
414
415 struct {
416 VkPipelineLayout img_p_layout;
417 VkDescriptorSetLayout img_ds_layout;
418 VkPipeline pipeline;
419 VkPipeline pipeline_3d;
420 } itob;
421 struct {
422 VkPipelineLayout img_p_layout;
423 VkDescriptorSetLayout img_ds_layout;
424 VkPipeline pipeline;
425 } btoi;
426 struct {
427 VkPipelineLayout img_p_layout;
428 VkDescriptorSetLayout img_ds_layout;
429 VkPipeline pipeline;
430 } itoi;
431 struct {
432 VkPipelineLayout img_p_layout;
433 VkDescriptorSetLayout img_ds_layout;
434 VkPipeline pipeline;
435 } cleari;
436
437 struct {
438 VkPipelineLayout p_layout;
439 VkPipeline pipeline;
440 VkRenderPass pass;
441 } resolve;
442
443 struct {
444 VkDescriptorSetLayout ds_layout;
445 VkPipelineLayout p_layout;
446 struct {
447 VkPipeline pipeline;
448 VkPipeline i_pipeline;
449 VkPipeline srgb_pipeline;
450 } rc[MAX_SAMPLES_LOG2];
451 } resolve_compute;
452
453 struct {
454 VkDescriptorSetLayout ds_layout;
455 VkPipelineLayout p_layout;
456
457 struct {
458 VkRenderPass render_pass[NUM_META_FS_KEYS];
459 VkPipeline pipeline[NUM_META_FS_KEYS];
460 } rc[MAX_SAMPLES_LOG2];
461 } resolve_fragment;
462
463 struct {
464 VkPipelineLayout p_layout;
465 VkPipeline decompress_pipeline;
466 VkPipeline resummarize_pipeline;
467 VkRenderPass pass;
468 } depth_decomp[1 + MAX_SAMPLES_LOG2];
469
470 struct {
471 VkPipelineLayout p_layout;
472 VkPipeline cmask_eliminate_pipeline;
473 VkPipeline fmask_decompress_pipeline;
474 VkRenderPass pass;
475 } fast_clear_flush;
476
477 struct {
478 VkPipelineLayout fill_p_layout;
479 VkPipelineLayout copy_p_layout;
480 VkDescriptorSetLayout fill_ds_layout;
481 VkDescriptorSetLayout copy_ds_layout;
482 VkPipeline fill_pipeline;
483 VkPipeline copy_pipeline;
484 } buffer;
485
486 struct {
487 VkDescriptorSetLayout ds_layout;
488 VkPipelineLayout p_layout;
489 VkPipeline occlusion_query_pipeline;
490 VkPipeline pipeline_statistics_query_pipeline;
491 } query;
492 };
493
494 /* queue types */
495 #define RADV_QUEUE_GENERAL 0
496 #define RADV_QUEUE_COMPUTE 1
497 #define RADV_QUEUE_TRANSFER 2
498
499 #define RADV_MAX_QUEUE_FAMILIES 3
500
501 enum ring_type radv_queue_family_to_ring(int f);
502
503 struct radv_queue {
504 VK_LOADER_DATA _loader_data;
505 struct radv_device * device;
506 struct radeon_winsys_ctx *hw_ctx;
507 enum radeon_ctx_priority priority;
508 uint32_t queue_family_index;
509 int queue_idx;
510
511 uint32_t scratch_size;
512 uint32_t compute_scratch_size;
513 uint32_t esgs_ring_size;
514 uint32_t gsvs_ring_size;
515 bool has_tess_rings;
516 bool has_sample_positions;
517
518 struct radeon_winsys_bo *scratch_bo;
519 struct radeon_winsys_bo *descriptor_bo;
520 struct radeon_winsys_bo *compute_scratch_bo;
521 struct radeon_winsys_bo *esgs_ring_bo;
522 struct radeon_winsys_bo *gsvs_ring_bo;
523 struct radeon_winsys_bo *tess_factor_ring_bo;
524 struct radeon_winsys_bo *tess_offchip_ring_bo;
525 struct radeon_winsys_cs *initial_preamble_cs;
526 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
527 struct radeon_winsys_cs *continue_preamble_cs;
528 };
529
530 struct radv_device {
531 VK_LOADER_DATA _loader_data;
532
533 VkAllocationCallbacks alloc;
534
535 struct radv_instance * instance;
536 struct radeon_winsys *ws;
537
538 struct radv_meta_state meta_state;
539
540 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
541 int queue_count[RADV_MAX_QUEUE_FAMILIES];
542 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
543
544 bool llvm_supports_spill;
545 bool has_distributed_tess;
546 bool dfsm_allowed;
547 uint32_t tess_offchip_block_dw_size;
548 uint32_t scratch_waves;
549 uint32_t dispatch_initiator;
550
551 uint32_t gs_table_depth;
552
553 /* MSAA sample locations.
554 * The first index is the sample index.
555 * The second index is the coordinate: X, Y. */
556 float sample_locations_1x[1][2];
557 float sample_locations_2x[2][2];
558 float sample_locations_4x[4][2];
559 float sample_locations_8x[8][2];
560 float sample_locations_16x[16][2];
561
562 /* CIK and later */
563 uint32_t gfx_init_size_dw;
564 struct radeon_winsys_bo *gfx_init;
565
566 struct radeon_winsys_bo *trace_bo;
567 uint32_t *trace_id_ptr;
568
569 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
570 bool keep_shader_info;
571
572 struct radv_physical_device *physical_device;
573
574 /* Backup in-memory cache to be used if the app doesn't provide one */
575 struct radv_pipeline_cache * mem_cache;
576
577 /*
578 * use different counters so MSAA MRTs get consecutive surface indices,
579 * even if MASK is allocated in between.
580 */
581 uint32_t image_mrt_offset_counter;
582 uint32_t fmask_mrt_offset_counter;
583 struct list_head shader_slabs;
584 mtx_t shader_slab_mutex;
585
586 /* For detecting VM faults reported by dmesg. */
587 uint64_t dmesg_timestamp;
588 };
589
590 struct radv_device_memory {
591 struct radeon_winsys_bo *bo;
592 /* for dedicated allocations */
593 struct radv_image *image;
594 struct radv_buffer *buffer;
595 uint32_t type_index;
596 VkDeviceSize map_size;
597 void * map;
598 };
599
600
601 struct radv_descriptor_range {
602 uint64_t va;
603 uint32_t size;
604 };
605
606 struct radv_descriptor_set {
607 const struct radv_descriptor_set_layout *layout;
608 uint32_t size;
609
610 struct radeon_winsys_bo *bo;
611 uint64_t va;
612 uint32_t *mapped_ptr;
613 struct radv_descriptor_range *dynamic_descriptors;
614
615 struct radeon_winsys_bo *descriptors[0];
616 };
617
618 struct radv_push_descriptor_set
619 {
620 struct radv_descriptor_set set;
621 uint32_t capacity;
622 };
623
624 struct radv_descriptor_pool_entry {
625 uint32_t offset;
626 uint32_t size;
627 struct radv_descriptor_set *set;
628 };
629
630 struct radv_descriptor_pool {
631 struct radeon_winsys_bo *bo;
632 uint8_t *mapped_ptr;
633 uint64_t current_offset;
634 uint64_t size;
635
636 uint8_t *host_memory_base;
637 uint8_t *host_memory_ptr;
638 uint8_t *host_memory_end;
639
640 uint32_t entry_count;
641 uint32_t max_entry_count;
642 struct radv_descriptor_pool_entry entries[0];
643 };
644
645 struct radv_descriptor_update_template_entry {
646 VkDescriptorType descriptor_type;
647
648 /* The number of descriptors to update */
649 uint32_t descriptor_count;
650
651 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
652 uint32_t dst_offset;
653
654 /* In dwords. Not valid/used for dynamic descriptors */
655 uint32_t dst_stride;
656
657 uint32_t buffer_offset;
658
659 /* Only valid for combined image samplers and samplers */
660 uint16_t has_sampler;
661
662 /* In bytes */
663 size_t src_offset;
664 size_t src_stride;
665
666 /* For push descriptors */
667 const uint32_t *immutable_samplers;
668 };
669
670 struct radv_descriptor_update_template {
671 uint32_t entry_count;
672 struct radv_descriptor_update_template_entry entry[0];
673 };
674
675 struct radv_buffer {
676 struct radv_device * device;
677 VkDeviceSize size;
678
679 VkBufferUsageFlags usage;
680 VkBufferCreateFlags flags;
681
682 /* Set when bound */
683 struct radeon_winsys_bo * bo;
684 VkDeviceSize offset;
685
686 bool shareable;
687 };
688
689
690 enum radv_cmd_dirty_bits {
691 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
692 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
693 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
694 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
695 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
696 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
697 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
698 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
699 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
700 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
701 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
702 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
703 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 11,
704 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 12,
705 };
706
707 enum radv_cmd_flush_bits {
708 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
709 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
710 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
711 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
712 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
713 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
714 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
715 /* Same as above, but only writes back and doesn't invalidate */
716 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
717 /* Framebuffer caches */
718 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
719 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
720 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
721 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
722 /* Engine synchronization. */
723 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
724 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
725 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
726 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
727
728 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
729 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
730 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
731 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
732 };
733
734 struct radv_vertex_binding {
735 struct radv_buffer * buffer;
736 VkDeviceSize offset;
737 };
738
739 struct radv_viewport_state {
740 uint32_t count;
741 VkViewport viewports[MAX_VIEWPORTS];
742 };
743
744 struct radv_scissor_state {
745 uint32_t count;
746 VkRect2D scissors[MAX_SCISSORS];
747 };
748
749 struct radv_dynamic_state {
750 /**
751 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
752 * Defines the set of saved dynamic state.
753 */
754 uint32_t mask;
755
756 struct radv_viewport_state viewport;
757
758 struct radv_scissor_state scissor;
759
760 float line_width;
761
762 struct {
763 float bias;
764 float clamp;
765 float slope;
766 } depth_bias;
767
768 float blend_constants[4];
769
770 struct {
771 float min;
772 float max;
773 } depth_bounds;
774
775 struct {
776 uint32_t front;
777 uint32_t back;
778 } stencil_compare_mask;
779
780 struct {
781 uint32_t front;
782 uint32_t back;
783 } stencil_write_mask;
784
785 struct {
786 uint32_t front;
787 uint32_t back;
788 } stencil_reference;
789 };
790
791 extern const struct radv_dynamic_state default_dynamic_state;
792
793 const char *
794 radv_get_debug_option_name(int id);
795
796 const char *
797 radv_get_perftest_option_name(int id);
798
799 /**
800 * Attachment state when recording a renderpass instance.
801 *
802 * The clear value is valid only if there exists a pending clear.
803 */
804 struct radv_attachment_state {
805 VkImageAspectFlags pending_clear_aspects;
806 uint32_t cleared_views;
807 VkClearValue clear_value;
808 VkImageLayout current_layout;
809 };
810
811 struct radv_cmd_state {
812 /* Vertex descriptors */
813 bool vb_prefetch_dirty;
814 uint64_t vb_va;
815 unsigned vb_size;
816
817 bool push_descriptors_dirty;
818 bool predicating;
819 uint32_t dirty;
820
821 struct radv_pipeline * pipeline;
822 struct radv_pipeline * emitted_pipeline;
823 struct radv_pipeline * compute_pipeline;
824 struct radv_pipeline * emitted_compute_pipeline;
825 struct radv_framebuffer * framebuffer;
826 struct radv_render_pass * pass;
827 const struct radv_subpass * subpass;
828 struct radv_dynamic_state dynamic;
829 struct radv_attachment_state * attachments;
830 VkRect2D render_area;
831
832 /* Index buffer */
833 struct radv_buffer *index_buffer;
834 uint64_t index_offset;
835 uint32_t index_type;
836 uint32_t max_index_count;
837 uint64_t index_va;
838 int32_t last_index_type;
839
840 int32_t last_primitive_reset_en;
841 uint32_t last_primitive_reset_index;
842 enum radv_cmd_flush_bits flush_bits;
843 unsigned active_occlusion_queries;
844 float offset_scale;
845 uint32_t descriptors_dirty;
846 uint32_t valid_descriptors;
847 uint32_t trace_id;
848 uint32_t last_ia_multi_vgt_param;
849 };
850
851 struct radv_cmd_pool {
852 VkAllocationCallbacks alloc;
853 struct list_head cmd_buffers;
854 struct list_head free_cmd_buffers;
855 uint32_t queue_family_index;
856 };
857
858 struct radv_cmd_buffer_upload {
859 uint8_t *map;
860 unsigned offset;
861 uint64_t size;
862 struct radeon_winsys_bo *upload_bo;
863 struct list_head list;
864 };
865
866 enum radv_cmd_buffer_status {
867 RADV_CMD_BUFFER_STATUS_INVALID,
868 RADV_CMD_BUFFER_STATUS_INITIAL,
869 RADV_CMD_BUFFER_STATUS_RECORDING,
870 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
871 RADV_CMD_BUFFER_STATUS_PENDING,
872 };
873
874 struct radv_cmd_buffer {
875 VK_LOADER_DATA _loader_data;
876
877 struct radv_device * device;
878
879 struct radv_cmd_pool * pool;
880 struct list_head pool_link;
881
882 VkCommandBufferUsageFlags usage_flags;
883 VkCommandBufferLevel level;
884 enum radv_cmd_buffer_status status;
885 struct radeon_winsys_cs *cs;
886 struct radv_cmd_state state;
887 struct radv_vertex_binding vertex_bindings[MAX_VBS];
888 uint32_t queue_family_index;
889
890 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
891 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
892 VkShaderStageFlags push_constant_stages;
893 struct radv_push_descriptor_set push_descriptors;
894 struct radv_descriptor_set meta_push_descriptors;
895 struct radv_descriptor_set *descriptors[MAX_SETS];
896
897 struct radv_cmd_buffer_upload upload;
898
899 uint32_t scratch_size_needed;
900 uint32_t compute_scratch_size_needed;
901 uint32_t esgs_ring_size_needed;
902 uint32_t gsvs_ring_size_needed;
903 bool tess_rings_needed;
904 bool sample_positions_needed;
905
906 VkResult record_result;
907
908 int ring_offsets_idx; /* just used for verification */
909 uint32_t gfx9_fence_offset;
910 struct radeon_winsys_bo *gfx9_fence_bo;
911 uint32_t gfx9_fence_idx;
912 };
913
914 struct radv_image;
915
916 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
917
918 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
919 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
920
921 void cik_create_gfx_config(struct radv_device *device);
922
923 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
924 int count, const VkViewport *viewports);
925 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
926 int count, const VkRect2D *scissors,
927 const VkViewport *viewports, bool can_use_guardband);
928 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
929 bool instanced_draw, bool indirect_draw,
930 uint32_t draw_vertex_count);
931 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
932 bool predicated,
933 enum chip_class chip_class,
934 bool is_mec,
935 unsigned event, unsigned event_flags,
936 unsigned data_sel,
937 uint64_t va,
938 uint32_t old_fence,
939 uint32_t new_fence);
940
941 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
942 bool predicated,
943 uint64_t va, uint32_t ref,
944 uint32_t mask);
945 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
946 bool predicated,
947 enum chip_class chip_class,
948 uint32_t *fence_ptr, uint64_t va,
949 bool is_mec,
950 enum radv_cmd_flush_bits flush_bits);
951 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
952 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
953 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
954 uint64_t src_va, uint64_t dest_va,
955 uint64_t size);
956 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
957 unsigned size);
958 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
959 uint64_t size, unsigned value);
960 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
961 bool
962 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
963 unsigned size,
964 unsigned alignment,
965 unsigned *out_offset,
966 void **ptr);
967 void
968 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
969 const struct radv_subpass *subpass,
970 bool transitions);
971 bool
972 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
973 unsigned size, unsigned alignmnet,
974 const void *data, unsigned *out_offset);
975
976 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
977 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
978 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
979 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
980 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
981 unsigned radv_cayman_get_maxdist(int log_samples);
982 void radv_device_init_msaa(struct radv_device *device);
983 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
984 struct radv_image *image,
985 VkClearDepthStencilValue ds_clear_value,
986 VkImageAspectFlags aspects);
987 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
988 struct radv_image *image,
989 int idx,
990 uint32_t color_values[2]);
991 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
992 struct radv_image *image,
993 bool value);
994 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
995 struct radeon_winsys_bo *bo,
996 uint64_t offset, uint64_t size, uint32_t value);
997 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
998 bool radv_get_memory_fd(struct radv_device *device,
999 struct radv_device_memory *memory,
1000 int *pFD);
1001
1002 /*
1003 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1004 *
1005 * Limitations: Can't call normal dispatch functions without binding or rebinding
1006 * the compute pipeline.
1007 */
1008 void radv_unaligned_dispatch(
1009 struct radv_cmd_buffer *cmd_buffer,
1010 uint32_t x,
1011 uint32_t y,
1012 uint32_t z);
1013
1014 struct radv_event {
1015 struct radeon_winsys_bo *bo;
1016 uint64_t *map;
1017 };
1018
1019 struct radv_shader_module;
1020
1021 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1022 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1023 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1024 void
1025 radv_hash_shaders(unsigned char *hash,
1026 const VkPipelineShaderStageCreateInfo **stages,
1027 const struct radv_pipeline_layout *layout,
1028 const struct radv_pipeline_key *key,
1029 uint32_t flags);
1030
1031 static inline gl_shader_stage
1032 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1033 {
1034 assert(__builtin_popcount(vk_stage) == 1);
1035 return ffs(vk_stage) - 1;
1036 }
1037
1038 static inline VkShaderStageFlagBits
1039 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1040 {
1041 return (1 << mesa_stage);
1042 }
1043
1044 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1045
1046 #define radv_foreach_stage(stage, stage_bits) \
1047 for (gl_shader_stage stage, \
1048 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1049 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1050 __tmp &= ~(1 << (stage)))
1051
1052 struct radv_depth_stencil_state {
1053 uint32_t db_depth_control;
1054 uint32_t db_stencil_control;
1055 uint32_t db_render_control;
1056 uint32_t db_render_override2;
1057 };
1058
1059 struct radv_blend_state {
1060 uint32_t cb_color_control;
1061 uint32_t cb_target_mask;
1062 uint32_t sx_mrt_blend_opt[8];
1063 uint32_t cb_blend_control[8];
1064
1065 uint32_t spi_shader_col_format;
1066 uint32_t cb_shader_mask;
1067 uint32_t db_alpha_to_mask;
1068 };
1069
1070 unsigned radv_format_meta_fs_key(VkFormat format);
1071
1072 struct radv_raster_state {
1073 uint32_t pa_cl_clip_cntl;
1074 uint32_t spi_interp_control;
1075 uint32_t pa_su_vtx_cntl;
1076 uint32_t pa_su_sc_mode_cntl;
1077 };
1078
1079 struct radv_multisample_state {
1080 uint32_t db_eqaa;
1081 uint32_t pa_sc_line_cntl;
1082 uint32_t pa_sc_mode_cntl_0;
1083 uint32_t pa_sc_mode_cntl_1;
1084 uint32_t pa_sc_aa_config;
1085 uint32_t pa_sc_aa_mask[2];
1086 unsigned num_samples;
1087 };
1088
1089 struct radv_prim_vertex_count {
1090 uint8_t min;
1091 uint8_t incr;
1092 };
1093
1094 struct radv_tessellation_state {
1095 uint32_t ls_hs_config;
1096 uint32_t tcs_in_layout;
1097 uint32_t tcs_out_layout;
1098 uint32_t tcs_out_offsets;
1099 uint32_t offchip_layout;
1100 unsigned num_patches;
1101 unsigned lds_size;
1102 unsigned num_tcs_input_cp;
1103 uint32_t tf_param;
1104 };
1105
1106 struct radv_gs_state {
1107 uint32_t vgt_gs_onchip_cntl;
1108 uint32_t vgt_gs_max_prims_per_subgroup;
1109 uint32_t vgt_esgs_ring_itemsize;
1110 uint32_t lds_size;
1111 };
1112
1113 struct radv_vertex_elements_info {
1114 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1115 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1116 uint32_t binding[MAX_VERTEX_ATTRIBS];
1117 uint32_t offset[MAX_VERTEX_ATTRIBS];
1118 uint32_t count;
1119 };
1120
1121 struct radv_vs_state {
1122 uint32_t pa_cl_vs_out_cntl;
1123 uint32_t spi_shader_pos_format;
1124 uint32_t spi_vs_out_config;
1125 uint32_t vgt_reuse_off;
1126 };
1127
1128 #define SI_GS_PER_ES 128
1129
1130 struct radv_pipeline {
1131 struct radv_device * device;
1132 struct radv_dynamic_state dynamic_state;
1133
1134 struct radv_pipeline_layout * layout;
1135
1136 bool needs_data_cache;
1137 bool need_indirect_descriptor_sets;
1138 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1139 struct radv_shader_variant *gs_copy_shader;
1140 VkShaderStageFlags active_stages;
1141
1142 struct radv_vertex_elements_info vertex_elements;
1143
1144 uint32_t binding_stride[MAX_VBS];
1145
1146 uint32_t user_data_0[MESA_SHADER_STAGES];
1147 union {
1148 struct {
1149 struct radv_blend_state blend;
1150 struct radv_depth_stencil_state ds;
1151 struct radv_raster_state raster;
1152 struct radv_multisample_state ms;
1153 struct radv_tessellation_state tess;
1154 struct radv_gs_state gs;
1155 struct radv_vs_state vs;
1156 uint32_t db_shader_control;
1157 uint32_t shader_z_format;
1158 unsigned prim;
1159 unsigned gs_out;
1160 uint32_t vgt_gs_mode;
1161 bool vgt_primitiveid_en;
1162 bool prim_restart_enable;
1163 bool partial_es_wave;
1164 uint8_t primgroup_size;
1165 unsigned esgs_ring_size;
1166 unsigned gsvs_ring_size;
1167 uint32_t ps_input_cntl[32];
1168 uint32_t ps_input_cntl_num;
1169 uint32_t vgt_shader_stages_en;
1170 uint32_t vtx_base_sgpr;
1171 uint32_t base_ia_multi_vgt_param;
1172 bool wd_switch_on_eop;
1173 bool ia_switch_on_eoi;
1174 bool partial_vs_wave;
1175 uint8_t vtx_emit_num;
1176 uint32_t vtx_reuse_depth;
1177 struct radv_prim_vertex_count prim_vertex_count;
1178 bool can_use_guardband;
1179 } graphics;
1180 };
1181
1182 unsigned max_waves;
1183 unsigned scratch_bytes_per_wave;
1184 };
1185
1186 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1187 {
1188 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1189 }
1190
1191 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1192 {
1193 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1194 }
1195
1196 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1197 gl_shader_stage stage,
1198 int idx);
1199
1200 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1201
1202 struct radv_graphics_pipeline_create_info {
1203 bool use_rectlist;
1204 bool db_depth_clear;
1205 bool db_stencil_clear;
1206 bool db_depth_disable_expclear;
1207 bool db_stencil_disable_expclear;
1208 bool db_flush_depth_inplace;
1209 bool db_flush_stencil_inplace;
1210 bool db_resummarize;
1211 uint32_t custom_blend_mode;
1212 };
1213
1214 VkResult
1215 radv_graphics_pipeline_create(VkDevice device,
1216 VkPipelineCache cache,
1217 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1218 const struct radv_graphics_pipeline_create_info *extra,
1219 const VkAllocationCallbacks *alloc,
1220 VkPipeline *pPipeline);
1221
1222 struct vk_format_description;
1223 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1224 int first_non_void);
1225 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1226 int first_non_void);
1227 uint32_t radv_translate_colorformat(VkFormat format);
1228 uint32_t radv_translate_color_numformat(VkFormat format,
1229 const struct vk_format_description *desc,
1230 int first_non_void);
1231 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1232 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1233 uint32_t radv_translate_dbformat(VkFormat format);
1234 uint32_t radv_translate_tex_dataformat(VkFormat format,
1235 const struct vk_format_description *desc,
1236 int first_non_void);
1237 uint32_t radv_translate_tex_numformat(VkFormat format,
1238 const struct vk_format_description *desc,
1239 int first_non_void);
1240 bool radv_format_pack_clear_color(VkFormat format,
1241 uint32_t clear_vals[2],
1242 VkClearColorValue *value);
1243 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1244 bool radv_dcc_formats_compatible(VkFormat format1,
1245 VkFormat format2);
1246
1247 struct radv_fmask_info {
1248 uint64_t offset;
1249 uint64_t size;
1250 unsigned alignment;
1251 unsigned pitch_in_pixels;
1252 unsigned bank_height;
1253 unsigned slice_tile_max;
1254 unsigned tile_mode_index;
1255 unsigned tile_swizzle;
1256 };
1257
1258 struct radv_cmask_info {
1259 uint64_t offset;
1260 uint64_t size;
1261 unsigned alignment;
1262 unsigned slice_tile_max;
1263 };
1264
1265 struct radv_image {
1266 VkImageType type;
1267 /* The original VkFormat provided by the client. This may not match any
1268 * of the actual surface formats.
1269 */
1270 VkFormat vk_format;
1271 VkImageAspectFlags aspects;
1272 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1273 struct ac_surf_info info;
1274 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1275 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1276
1277 VkDeviceSize size;
1278 uint32_t alignment;
1279
1280 unsigned queue_family_mask;
1281 bool exclusive;
1282 bool shareable;
1283
1284 /* Set when bound */
1285 struct radeon_winsys_bo *bo;
1286 VkDeviceSize offset;
1287 uint64_t dcc_offset;
1288 uint64_t htile_offset;
1289 bool tc_compatible_htile;
1290 struct radeon_surf surface;
1291
1292 struct radv_fmask_info fmask;
1293 struct radv_cmask_info cmask;
1294 uint64_t clear_value_offset;
1295 uint64_t dcc_pred_offset;
1296 };
1297
1298 /* Whether the image has a htile that is known consistent with the contents of
1299 * the image. */
1300 bool radv_layout_has_htile(const struct radv_image *image,
1301 VkImageLayout layout,
1302 unsigned queue_mask);
1303
1304 /* Whether the image has a htile that is known consistent with the contents of
1305 * the image and is allowed to be in compressed form.
1306 *
1307 * If this is false reads that don't use the htile should be able to return
1308 * correct results.
1309 */
1310 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1311 VkImageLayout layout,
1312 unsigned queue_mask);
1313
1314 bool radv_layout_can_fast_clear(const struct radv_image *image,
1315 VkImageLayout layout,
1316 unsigned queue_mask);
1317
1318 static inline bool
1319 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1320 {
1321 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1322 }
1323
1324 static inline bool
1325 radv_htile_enabled(const struct radv_image *image, unsigned level)
1326 {
1327 return image->surface.htile_size && level == 0;
1328 }
1329
1330 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1331
1332 static inline uint32_t
1333 radv_get_layerCount(const struct radv_image *image,
1334 const VkImageSubresourceRange *range)
1335 {
1336 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1337 image->info.array_size - range->baseArrayLayer : range->layerCount;
1338 }
1339
1340 static inline uint32_t
1341 radv_get_levelCount(const struct radv_image *image,
1342 const VkImageSubresourceRange *range)
1343 {
1344 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1345 image->info.levels - range->baseMipLevel : range->levelCount;
1346 }
1347
1348 struct radeon_bo_metadata;
1349 void
1350 radv_init_metadata(struct radv_device *device,
1351 struct radv_image *image,
1352 struct radeon_bo_metadata *metadata);
1353
1354 struct radv_image_view {
1355 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1356 struct radeon_winsys_bo *bo;
1357
1358 VkImageViewType type;
1359 VkImageAspectFlags aspect_mask;
1360 VkFormat vk_format;
1361 uint32_t base_layer;
1362 uint32_t layer_count;
1363 uint32_t base_mip;
1364 uint32_t level_count;
1365 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1366
1367 uint32_t descriptor[16];
1368
1369 /* Descriptor for use as a storage image as opposed to a sampled image.
1370 * This has a few differences for cube maps (e.g. type).
1371 */
1372 uint32_t storage_descriptor[16];
1373 };
1374
1375 struct radv_image_create_info {
1376 const VkImageCreateInfo *vk_info;
1377 bool scanout;
1378 };
1379
1380 VkResult radv_image_create(VkDevice _device,
1381 const struct radv_image_create_info *info,
1382 const VkAllocationCallbacks* alloc,
1383 VkImage *pImage);
1384
1385 void radv_image_view_init(struct radv_image_view *view,
1386 struct radv_device *device,
1387 const VkImageViewCreateInfo* pCreateInfo);
1388
1389 struct radv_buffer_view {
1390 struct radeon_winsys_bo *bo;
1391 VkFormat vk_format;
1392 uint64_t range; /**< VkBufferViewCreateInfo::range */
1393 uint32_t state[4];
1394 };
1395 void radv_buffer_view_init(struct radv_buffer_view *view,
1396 struct radv_device *device,
1397 const VkBufferViewCreateInfo* pCreateInfo);
1398
1399 static inline struct VkExtent3D
1400 radv_sanitize_image_extent(const VkImageType imageType,
1401 const struct VkExtent3D imageExtent)
1402 {
1403 switch (imageType) {
1404 case VK_IMAGE_TYPE_1D:
1405 return (VkExtent3D) { imageExtent.width, 1, 1 };
1406 case VK_IMAGE_TYPE_2D:
1407 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1408 case VK_IMAGE_TYPE_3D:
1409 return imageExtent;
1410 default:
1411 unreachable("invalid image type");
1412 }
1413 }
1414
1415 static inline struct VkOffset3D
1416 radv_sanitize_image_offset(const VkImageType imageType,
1417 const struct VkOffset3D imageOffset)
1418 {
1419 switch (imageType) {
1420 case VK_IMAGE_TYPE_1D:
1421 return (VkOffset3D) { imageOffset.x, 0, 0 };
1422 case VK_IMAGE_TYPE_2D:
1423 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1424 case VK_IMAGE_TYPE_3D:
1425 return imageOffset;
1426 default:
1427 unreachable("invalid image type");
1428 }
1429 }
1430
1431 static inline bool
1432 radv_image_extent_compare(const struct radv_image *image,
1433 const VkExtent3D *extent)
1434 {
1435 if (extent->width != image->info.width ||
1436 extent->height != image->info.height ||
1437 extent->depth != image->info.depth)
1438 return false;
1439 return true;
1440 }
1441
1442 struct radv_sampler {
1443 uint32_t state[4];
1444 };
1445
1446 struct radv_color_buffer_info {
1447 uint64_t cb_color_base;
1448 uint64_t cb_color_cmask;
1449 uint64_t cb_color_fmask;
1450 uint64_t cb_dcc_base;
1451 uint32_t cb_color_pitch;
1452 uint32_t cb_color_slice;
1453 uint32_t cb_color_view;
1454 uint32_t cb_color_info;
1455 uint32_t cb_color_attrib;
1456 uint32_t cb_color_attrib2;
1457 uint32_t cb_dcc_control;
1458 uint32_t cb_color_cmask_slice;
1459 uint32_t cb_color_fmask_slice;
1460 uint32_t cb_clear_value0;
1461 uint32_t cb_clear_value1;
1462 };
1463
1464 struct radv_ds_buffer_info {
1465 uint64_t db_z_read_base;
1466 uint64_t db_stencil_read_base;
1467 uint64_t db_z_write_base;
1468 uint64_t db_stencil_write_base;
1469 uint64_t db_htile_data_base;
1470 uint32_t db_depth_info;
1471 uint32_t db_z_info;
1472 uint32_t db_stencil_info;
1473 uint32_t db_depth_view;
1474 uint32_t db_depth_size;
1475 uint32_t db_depth_slice;
1476 uint32_t db_htile_surface;
1477 uint32_t pa_su_poly_offset_db_fmt_cntl;
1478 uint32_t db_z_info2;
1479 uint32_t db_stencil_info2;
1480 float offset_scale;
1481 };
1482
1483 struct radv_attachment_info {
1484 union {
1485 struct radv_color_buffer_info cb;
1486 struct radv_ds_buffer_info ds;
1487 };
1488 struct radv_image_view *attachment;
1489 };
1490
1491 struct radv_framebuffer {
1492 uint32_t width;
1493 uint32_t height;
1494 uint32_t layers;
1495
1496 uint32_t attachment_count;
1497 struct radv_attachment_info attachments[0];
1498 };
1499
1500 struct radv_subpass_barrier {
1501 VkPipelineStageFlags src_stage_mask;
1502 VkAccessFlags src_access_mask;
1503 VkAccessFlags dst_access_mask;
1504 };
1505
1506 struct radv_subpass {
1507 uint32_t input_count;
1508 uint32_t color_count;
1509 VkAttachmentReference * input_attachments;
1510 VkAttachmentReference * color_attachments;
1511 VkAttachmentReference * resolve_attachments;
1512 VkAttachmentReference depth_stencil_attachment;
1513
1514 /** Subpass has at least one resolve attachment */
1515 bool has_resolve;
1516
1517 struct radv_subpass_barrier start_barrier;
1518
1519 uint32_t view_mask;
1520 };
1521
1522 struct radv_render_pass_attachment {
1523 VkFormat format;
1524 uint32_t samples;
1525 VkAttachmentLoadOp load_op;
1526 VkAttachmentLoadOp stencil_load_op;
1527 VkImageLayout initial_layout;
1528 VkImageLayout final_layout;
1529 uint32_t view_mask;
1530 };
1531
1532 struct radv_render_pass {
1533 uint32_t attachment_count;
1534 uint32_t subpass_count;
1535 VkAttachmentReference * subpass_attachments;
1536 struct radv_render_pass_attachment * attachments;
1537 struct radv_subpass_barrier end_barrier;
1538 struct radv_subpass subpasses[0];
1539 };
1540
1541 VkResult radv_device_init_meta(struct radv_device *device);
1542 void radv_device_finish_meta(struct radv_device *device);
1543
1544 struct radv_query_pool {
1545 struct radeon_winsys_bo *bo;
1546 uint32_t stride;
1547 uint32_t availability_offset;
1548 char *ptr;
1549 VkQueryType type;
1550 uint32_t pipeline_stats_mask;
1551 };
1552
1553 struct radv_semaphore {
1554 /* use a winsys sem for non-exportable */
1555 struct radeon_winsys_sem *sem;
1556 uint32_t syncobj;
1557 uint32_t temp_syncobj;
1558 };
1559
1560 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1561 int num_wait_sems,
1562 const VkSemaphore *wait_sems,
1563 int num_signal_sems,
1564 const VkSemaphore *signal_sems,
1565 VkFence fence);
1566 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1567
1568 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1569 struct radv_descriptor_set *set,
1570 unsigned idx);
1571
1572 void
1573 radv_update_descriptor_sets(struct radv_device *device,
1574 struct radv_cmd_buffer *cmd_buffer,
1575 VkDescriptorSet overrideSet,
1576 uint32_t descriptorWriteCount,
1577 const VkWriteDescriptorSet *pDescriptorWrites,
1578 uint32_t descriptorCopyCount,
1579 const VkCopyDescriptorSet *pDescriptorCopies);
1580
1581 void
1582 radv_update_descriptor_set_with_template(struct radv_device *device,
1583 struct radv_cmd_buffer *cmd_buffer,
1584 struct radv_descriptor_set *set,
1585 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1586 const void *pData);
1587
1588 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1589 VkPipelineBindPoint pipelineBindPoint,
1590 VkPipelineLayout _layout,
1591 uint32_t set,
1592 uint32_t descriptorWriteCount,
1593 const VkWriteDescriptorSet *pDescriptorWrites);
1594
1595 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1596 struct radv_image *image, uint32_t value);
1597 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1598 struct radv_image *image, uint32_t value);
1599
1600 struct radv_fence {
1601 struct radeon_winsys_fence *fence;
1602 bool submitted;
1603 bool signalled;
1604
1605 uint32_t syncobj;
1606 uint32_t temp_syncobj;
1607 };
1608
1609 struct radeon_winsys_sem;
1610
1611 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1612 \
1613 static inline struct __radv_type * \
1614 __radv_type ## _from_handle(__VkType _handle) \
1615 { \
1616 return (struct __radv_type *) _handle; \
1617 } \
1618 \
1619 static inline __VkType \
1620 __radv_type ## _to_handle(struct __radv_type *_obj) \
1621 { \
1622 return (__VkType) _obj; \
1623 }
1624
1625 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1626 \
1627 static inline struct __radv_type * \
1628 __radv_type ## _from_handle(__VkType _handle) \
1629 { \
1630 return (struct __radv_type *)(uintptr_t) _handle; \
1631 } \
1632 \
1633 static inline __VkType \
1634 __radv_type ## _to_handle(struct __radv_type *_obj) \
1635 { \
1636 return (__VkType)(uintptr_t) _obj; \
1637 }
1638
1639 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1640 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1641
1642 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1643 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1644 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1645 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1646 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1647
1648 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1649 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1650 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1651 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1652 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1653 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1654 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1655 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1656 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1657 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1658 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1659 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1660 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1661 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1662 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1663 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1664 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1665 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1666 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1667 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1668 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1669
1670 #endif /* RADV_PRIVATE_H */