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radv: track different status of a command buffer
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
59
60 #include <llvm-c/TargetMachine.h>
61
62 /* Pre-declarations needed for WSI entrypoints */
63 struct wl_surface;
64 struct wl_display;
65 typedef struct xcb_connection_t xcb_connection_t;
66 typedef uint32_t xcb_visualid_t;
67 typedef uint32_t xcb_window_t;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "radv_entrypoints.h"
74
75 #include "wsi_common.h"
76
77 #define ATI_VENDOR_ID 0x1002
78
79 #define MAX_VBS 32
80 #define MAX_VERTEX_ATTRIBS 32
81 #define MAX_RTS 8
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
90 #define MAX_VIEWS 8
91
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
93
94 enum radv_mem_heap {
95 RADV_MEM_HEAP_VRAM,
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
97 RADV_MEM_HEAP_GTT,
98 RADV_MEM_HEAP_COUNT
99 };
100
101 enum radv_mem_type {
102 RADV_MEM_TYPE_VRAM,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
105 RADV_MEM_TYPE_GTT_CACHED,
106 RADV_MEM_TYPE_COUNT
107 };
108
109 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
110
111 static inline uint32_t
112 align_u32(uint32_t v, uint32_t a)
113 {
114 assert(a != 0 && a == (a & -a));
115 return (v + a - 1) & ~(a - 1);
116 }
117
118 static inline uint32_t
119 align_u32_npot(uint32_t v, uint32_t a)
120 {
121 return (v + a - 1) / a * a;
122 }
123
124 static inline uint64_t
125 align_u64(uint64_t v, uint64_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 static inline int32_t
132 align_i32(int32_t v, int32_t a)
133 {
134 assert(a != 0 && a == (a & -a));
135 return (v + a - 1) & ~(a - 1);
136 }
137
138 /** Alignment must be a power of 2. */
139 static inline bool
140 radv_is_aligned(uintmax_t n, uintmax_t a)
141 {
142 assert(a == (a & -a));
143 return (n & (a - 1)) == 0;
144 }
145
146 static inline uint32_t
147 round_up_u32(uint32_t v, uint32_t a)
148 {
149 return (v + a - 1) / a;
150 }
151
152 static inline uint64_t
153 round_up_u64(uint64_t v, uint64_t a)
154 {
155 return (v + a - 1) / a;
156 }
157
158 static inline uint32_t
159 radv_minify(uint32_t n, uint32_t levels)
160 {
161 if (unlikely(n == 0))
162 return 0;
163 else
164 return MAX2(n >> levels, 1);
165 }
166 static inline float
167 radv_clamp_f(float f, float min, float max)
168 {
169 assert(min < max);
170
171 if (f > max)
172 return max;
173 else if (f < min)
174 return min;
175 else
176 return f;
177 }
178
179 static inline bool
180 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
181 {
182 if (*inout_mask & clear_mask) {
183 *inout_mask &= ~clear_mask;
184 return true;
185 } else {
186 return false;
187 }
188 }
189
190 #define for_each_bit(b, dword) \
191 for (uint32_t __dword = (dword); \
192 (b) = __builtin_ffs(__dword) - 1, __dword; \
193 __dword &= ~(1 << (b)))
194
195 #define typed_memcpy(dest, src, count) ({ \
196 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
197 memcpy((dest), (src), (count) * sizeof(*(src))); \
198 })
199
200 /* Whenever we generate an error, pass it through this function. Useful for
201 * debugging, where we can break on it. Only call at error site, not when
202 * propagating errors. Might be useful to plug in a stack trace here.
203 */
204
205 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
206
207 #ifdef DEBUG
208 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
209 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
210 #else
211 #define vk_error(error) error
212 #define vk_errorf(error, format, ...) error
213 #endif
214
215 void __radv_finishme(const char *file, int line, const char *format, ...)
216 radv_printflike(3, 4);
217 void radv_loge(const char *format, ...) radv_printflike(1, 2);
218 void radv_loge_v(const char *format, va_list va);
219
220 /**
221 * Print a FINISHME message, including its source location.
222 */
223 #define radv_finishme(format, ...) \
224 do { \
225 static bool reported = false; \
226 if (!reported) { \
227 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
228 reported = true; \
229 } \
230 } while (0)
231
232 /* A non-fatal assert. Useful for debugging. */
233 #ifdef DEBUG
234 #define radv_assert(x) ({ \
235 if (unlikely(!(x))) \
236 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
237 })
238 #else
239 #define radv_assert(x)
240 #endif
241
242 #define stub_return(v) \
243 do { \
244 radv_finishme("stub %s", __func__); \
245 return (v); \
246 } while (0)
247
248 #define stub() \
249 do { \
250 radv_finishme("stub %s", __func__); \
251 return; \
252 } while (0)
253
254 void *radv_lookup_entrypoint(const char *name);
255
256 struct radv_physical_device {
257 VK_LOADER_DATA _loader_data;
258
259 struct radv_instance * instance;
260
261 struct radeon_winsys *ws;
262 struct radeon_info rad_info;
263 char path[20];
264 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
265 uint8_t driver_uuid[VK_UUID_SIZE];
266 uint8_t device_uuid[VK_UUID_SIZE];
267 uint8_t cache_uuid[VK_UUID_SIZE];
268
269 int local_fd;
270 struct wsi_device wsi_device;
271
272 bool has_rbplus; /* if RB+ register exist */
273 bool rbplus_allowed; /* if RB+ is allowed */
274 bool has_clear_state;
275
276 /* This is the drivers on-disk cache used as a fallback as opposed to
277 * the pipeline cache defined by apps.
278 */
279 struct disk_cache * disk_cache;
280
281 VkPhysicalDeviceMemoryProperties memory_properties;
282 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
283 };
284
285 struct radv_instance {
286 VK_LOADER_DATA _loader_data;
287
288 VkAllocationCallbacks alloc;
289
290 uint32_t apiVersion;
291 int physicalDeviceCount;
292 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
293
294 uint64_t debug_flags;
295 uint64_t perftest_flags;
296 };
297
298 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
299 void radv_finish_wsi(struct radv_physical_device *physical_device);
300
301 bool radv_instance_extension_supported(const char *name);
302 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
303 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
304 const char *name);
305
306 struct cache_entry;
307
308 struct radv_pipeline_cache {
309 struct radv_device * device;
310 pthread_mutex_t mutex;
311
312 uint32_t total_size;
313 uint32_t table_size;
314 uint32_t kernel_count;
315 struct cache_entry ** hash_table;
316 bool modified;
317
318 VkAllocationCallbacks alloc;
319 };
320
321 struct radv_pipeline_key {
322 uint32_t instance_rate_inputs;
323 unsigned tess_input_vertices;
324 uint32_t col_format;
325 uint32_t is_int8;
326 uint32_t is_int10;
327 uint32_t multisample : 1;
328 uint32_t has_multiview_view_index : 1;
329 };
330
331 void
332 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
333 struct radv_device *device);
334 void
335 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
336 void
337 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
338 const void *data, size_t size);
339
340 struct radv_shader_variant;
341
342 bool
343 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
344 struct radv_pipeline_cache *cache,
345 const unsigned char *sha1,
346 struct radv_shader_variant **variants);
347
348 void
349 radv_pipeline_cache_insert_shaders(struct radv_device *device,
350 struct radv_pipeline_cache *cache,
351 const unsigned char *sha1,
352 struct radv_shader_variant **variants,
353 const void *const *codes,
354 const unsigned *code_sizes);
355
356 struct radv_meta_state {
357 VkAllocationCallbacks alloc;
358
359 struct radv_pipeline_cache cache;
360
361 /**
362 * Use array element `i` for images with `2^i` samples.
363 */
364 struct {
365 VkRenderPass render_pass[NUM_META_FS_KEYS];
366 VkPipeline color_pipelines[NUM_META_FS_KEYS];
367
368 VkRenderPass depthstencil_rp;
369 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
370 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
371 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
372 } clear[1 + MAX_SAMPLES_LOG2];
373
374 VkPipelineLayout clear_color_p_layout;
375 VkPipelineLayout clear_depth_p_layout;
376 struct {
377 VkRenderPass render_pass[NUM_META_FS_KEYS];
378
379 /** Pipeline that blits from a 1D image. */
380 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
381
382 /** Pipeline that blits from a 2D image. */
383 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
384
385 /** Pipeline that blits from a 3D image. */
386 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
387
388 VkRenderPass depth_only_rp;
389 VkPipeline depth_only_1d_pipeline;
390 VkPipeline depth_only_2d_pipeline;
391 VkPipeline depth_only_3d_pipeline;
392
393 VkRenderPass stencil_only_rp;
394 VkPipeline stencil_only_1d_pipeline;
395 VkPipeline stencil_only_2d_pipeline;
396 VkPipeline stencil_only_3d_pipeline;
397 VkPipelineLayout pipeline_layout;
398 VkDescriptorSetLayout ds_layout;
399 } blit;
400
401 struct {
402 VkRenderPass render_passes[NUM_META_FS_KEYS];
403
404 VkPipelineLayout p_layouts[2];
405 VkDescriptorSetLayout ds_layouts[2];
406 VkPipeline pipelines[2][NUM_META_FS_KEYS];
407
408 VkRenderPass depth_only_rp;
409 VkPipeline depth_only_pipeline[2];
410
411 VkRenderPass stencil_only_rp;
412 VkPipeline stencil_only_pipeline[2];
413 } blit2d;
414
415 struct {
416 VkPipelineLayout img_p_layout;
417 VkDescriptorSetLayout img_ds_layout;
418 VkPipeline pipeline;
419 } itob;
420 struct {
421 VkPipelineLayout img_p_layout;
422 VkDescriptorSetLayout img_ds_layout;
423 VkPipeline pipeline;
424 } btoi;
425 struct {
426 VkPipelineLayout img_p_layout;
427 VkDescriptorSetLayout img_ds_layout;
428 VkPipeline pipeline;
429 } itoi;
430 struct {
431 VkPipelineLayout img_p_layout;
432 VkDescriptorSetLayout img_ds_layout;
433 VkPipeline pipeline;
434 } cleari;
435
436 struct {
437 VkPipeline pipeline;
438 VkRenderPass pass;
439 } resolve;
440
441 struct {
442 VkDescriptorSetLayout ds_layout;
443 VkPipelineLayout p_layout;
444 struct {
445 VkPipeline pipeline;
446 VkPipeline i_pipeline;
447 VkPipeline srgb_pipeline;
448 } rc[MAX_SAMPLES_LOG2];
449 } resolve_compute;
450
451 struct {
452 VkDescriptorSetLayout ds_layout;
453 VkPipelineLayout p_layout;
454
455 struct {
456 VkRenderPass render_pass[NUM_META_FS_KEYS];
457 VkPipeline pipeline[NUM_META_FS_KEYS];
458 } rc[MAX_SAMPLES_LOG2];
459 } resolve_fragment;
460
461 struct {
462 VkPipeline decompress_pipeline;
463 VkPipeline resummarize_pipeline;
464 VkRenderPass pass;
465 } depth_decomp[1 + MAX_SAMPLES_LOG2];
466
467 struct {
468 VkPipeline cmask_eliminate_pipeline;
469 VkPipeline fmask_decompress_pipeline;
470 VkRenderPass pass;
471 } fast_clear_flush;
472
473 struct {
474 VkPipelineLayout fill_p_layout;
475 VkPipelineLayout copy_p_layout;
476 VkDescriptorSetLayout fill_ds_layout;
477 VkDescriptorSetLayout copy_ds_layout;
478 VkPipeline fill_pipeline;
479 VkPipeline copy_pipeline;
480 } buffer;
481
482 struct {
483 VkDescriptorSetLayout ds_layout;
484 VkPipelineLayout p_layout;
485 VkPipeline occlusion_query_pipeline;
486 VkPipeline pipeline_statistics_query_pipeline;
487 } query;
488 };
489
490 /* queue types */
491 #define RADV_QUEUE_GENERAL 0
492 #define RADV_QUEUE_COMPUTE 1
493 #define RADV_QUEUE_TRANSFER 2
494
495 #define RADV_MAX_QUEUE_FAMILIES 3
496
497 enum ring_type radv_queue_family_to_ring(int f);
498
499 struct radv_queue {
500 VK_LOADER_DATA _loader_data;
501 struct radv_device * device;
502 struct radeon_winsys_ctx *hw_ctx;
503 enum radeon_ctx_priority priority;
504 uint32_t queue_family_index;
505 int queue_idx;
506
507 uint32_t scratch_size;
508 uint32_t compute_scratch_size;
509 uint32_t esgs_ring_size;
510 uint32_t gsvs_ring_size;
511 bool has_tess_rings;
512 bool has_sample_positions;
513
514 struct radeon_winsys_bo *scratch_bo;
515 struct radeon_winsys_bo *descriptor_bo;
516 struct radeon_winsys_bo *compute_scratch_bo;
517 struct radeon_winsys_bo *esgs_ring_bo;
518 struct radeon_winsys_bo *gsvs_ring_bo;
519 struct radeon_winsys_bo *tess_factor_ring_bo;
520 struct radeon_winsys_bo *tess_offchip_ring_bo;
521 struct radeon_winsys_cs *initial_preamble_cs;
522 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
523 struct radeon_winsys_cs *continue_preamble_cs;
524 };
525
526 struct radv_device {
527 VK_LOADER_DATA _loader_data;
528
529 VkAllocationCallbacks alloc;
530
531 struct radv_instance * instance;
532 struct radeon_winsys *ws;
533
534 struct radv_meta_state meta_state;
535
536 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
537 int queue_count[RADV_MAX_QUEUE_FAMILIES];
538 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
539
540 bool llvm_supports_spill;
541 bool has_distributed_tess;
542 bool dfsm_allowed;
543 uint32_t tess_offchip_block_dw_size;
544 uint32_t scratch_waves;
545
546 uint32_t gs_table_depth;
547
548 /* MSAA sample locations.
549 * The first index is the sample index.
550 * The second index is the coordinate: X, Y. */
551 float sample_locations_1x[1][2];
552 float sample_locations_2x[2][2];
553 float sample_locations_4x[4][2];
554 float sample_locations_8x[8][2];
555 float sample_locations_16x[16][2];
556
557 /* CIK and later */
558 uint32_t gfx_init_size_dw;
559 struct radeon_winsys_bo *gfx_init;
560
561 struct radeon_winsys_bo *trace_bo;
562 uint32_t *trace_id_ptr;
563
564 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
565 bool keep_shader_info;
566
567 struct radv_physical_device *physical_device;
568
569 /* Backup in-memory cache to be used if the app doesn't provide one */
570 struct radv_pipeline_cache * mem_cache;
571
572 /*
573 * use different counters so MSAA MRTs get consecutive surface indices,
574 * even if MASK is allocated in between.
575 */
576 uint32_t image_mrt_offset_counter;
577 uint32_t fmask_mrt_offset_counter;
578 struct list_head shader_slabs;
579 mtx_t shader_slab_mutex;
580
581 /* For detecting VM faults reported by dmesg. */
582 uint64_t dmesg_timestamp;
583 };
584
585 struct radv_device_memory {
586 struct radeon_winsys_bo *bo;
587 /* for dedicated allocations */
588 struct radv_image *image;
589 struct radv_buffer *buffer;
590 uint32_t type_index;
591 VkDeviceSize map_size;
592 void * map;
593 };
594
595
596 struct radv_descriptor_range {
597 uint64_t va;
598 uint32_t size;
599 };
600
601 struct radv_descriptor_set {
602 const struct radv_descriptor_set_layout *layout;
603 uint32_t size;
604
605 struct radeon_winsys_bo *bo;
606 uint64_t va;
607 uint32_t *mapped_ptr;
608 struct radv_descriptor_range *dynamic_descriptors;
609
610 struct radeon_winsys_bo *descriptors[0];
611 };
612
613 struct radv_push_descriptor_set
614 {
615 struct radv_descriptor_set set;
616 uint32_t capacity;
617 };
618
619 struct radv_descriptor_pool_entry {
620 uint32_t offset;
621 uint32_t size;
622 struct radv_descriptor_set *set;
623 };
624
625 struct radv_descriptor_pool {
626 struct radeon_winsys_bo *bo;
627 uint8_t *mapped_ptr;
628 uint64_t current_offset;
629 uint64_t size;
630
631 uint8_t *host_memory_base;
632 uint8_t *host_memory_ptr;
633 uint8_t *host_memory_end;
634
635 uint32_t entry_count;
636 uint32_t max_entry_count;
637 struct radv_descriptor_pool_entry entries[0];
638 };
639
640 struct radv_descriptor_update_template_entry {
641 VkDescriptorType descriptor_type;
642
643 /* The number of descriptors to update */
644 uint32_t descriptor_count;
645
646 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
647 uint32_t dst_offset;
648
649 /* In dwords. Not valid/used for dynamic descriptors */
650 uint32_t dst_stride;
651
652 uint32_t buffer_offset;
653
654 /* Only valid for combined image samplers and samplers */
655 uint16_t has_sampler;
656
657 /* In bytes */
658 size_t src_offset;
659 size_t src_stride;
660
661 /* For push descriptors */
662 const uint32_t *immutable_samplers;
663 };
664
665 struct radv_descriptor_update_template {
666 uint32_t entry_count;
667 struct radv_descriptor_update_template_entry entry[0];
668 };
669
670 struct radv_buffer {
671 struct radv_device * device;
672 VkDeviceSize size;
673
674 VkBufferUsageFlags usage;
675 VkBufferCreateFlags flags;
676
677 /* Set when bound */
678 struct radeon_winsys_bo * bo;
679 VkDeviceSize offset;
680
681 bool shareable;
682 };
683
684
685 enum radv_cmd_dirty_bits {
686 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
687 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
688 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
689 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
690 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
691 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
692 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
693 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
694 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
695 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
696 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
697 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
698 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 11,
699 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 12,
700 };
701
702 enum radv_cmd_flush_bits {
703 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
704 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
705 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
706 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
707 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
708 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
709 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
710 /* Same as above, but only writes back and doesn't invalidate */
711 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
712 /* Framebuffer caches */
713 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
714 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
715 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
716 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
717 /* Engine synchronization. */
718 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
719 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
720 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
721 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
722
723 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
724 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
725 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
726 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
727 };
728
729 struct radv_vertex_binding {
730 struct radv_buffer * buffer;
731 VkDeviceSize offset;
732 };
733
734 struct radv_viewport_state {
735 uint32_t count;
736 VkViewport viewports[MAX_VIEWPORTS];
737 };
738
739 struct radv_scissor_state {
740 uint32_t count;
741 VkRect2D scissors[MAX_SCISSORS];
742 };
743
744 struct radv_dynamic_state {
745 /**
746 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
747 * Defines the set of saved dynamic state.
748 */
749 uint32_t mask;
750
751 struct radv_viewport_state viewport;
752
753 struct radv_scissor_state scissor;
754
755 float line_width;
756
757 struct {
758 float bias;
759 float clamp;
760 float slope;
761 } depth_bias;
762
763 float blend_constants[4];
764
765 struct {
766 float min;
767 float max;
768 } depth_bounds;
769
770 struct {
771 uint32_t front;
772 uint32_t back;
773 } stencil_compare_mask;
774
775 struct {
776 uint32_t front;
777 uint32_t back;
778 } stencil_write_mask;
779
780 struct {
781 uint32_t front;
782 uint32_t back;
783 } stencil_reference;
784 };
785
786 extern const struct radv_dynamic_state default_dynamic_state;
787
788 const char *
789 radv_get_debug_option_name(int id);
790
791 const char *
792 radv_get_perftest_option_name(int id);
793
794 /**
795 * Attachment state when recording a renderpass instance.
796 *
797 * The clear value is valid only if there exists a pending clear.
798 */
799 struct radv_attachment_state {
800 VkImageAspectFlags pending_clear_aspects;
801 uint32_t cleared_views;
802 VkClearValue clear_value;
803 VkImageLayout current_layout;
804 };
805
806 struct radv_cmd_state {
807 /* Vertex descriptors */
808 bool vb_prefetch_dirty;
809 uint64_t vb_va;
810 unsigned vb_size;
811
812 bool push_descriptors_dirty;
813 bool predicating;
814 uint32_t dirty;
815
816 struct radv_pipeline * pipeline;
817 struct radv_pipeline * emitted_pipeline;
818 struct radv_pipeline * compute_pipeline;
819 struct radv_pipeline * emitted_compute_pipeline;
820 struct radv_framebuffer * framebuffer;
821 struct radv_render_pass * pass;
822 const struct radv_subpass * subpass;
823 struct radv_dynamic_state dynamic;
824 struct radv_attachment_state * attachments;
825 VkRect2D render_area;
826
827 /* Index buffer */
828 struct radv_buffer *index_buffer;
829 uint64_t index_offset;
830 uint32_t index_type;
831 uint32_t max_index_count;
832 uint64_t index_va;
833
834 int32_t last_primitive_reset_en;
835 uint32_t last_primitive_reset_index;
836 enum radv_cmd_flush_bits flush_bits;
837 unsigned active_occlusion_queries;
838 float offset_scale;
839 uint32_t descriptors_dirty;
840 uint32_t valid_descriptors;
841 uint32_t trace_id;
842 uint32_t last_ia_multi_vgt_param;
843 };
844
845 struct radv_cmd_pool {
846 VkAllocationCallbacks alloc;
847 struct list_head cmd_buffers;
848 struct list_head free_cmd_buffers;
849 uint32_t queue_family_index;
850 };
851
852 struct radv_cmd_buffer_upload {
853 uint8_t *map;
854 unsigned offset;
855 uint64_t size;
856 struct radeon_winsys_bo *upload_bo;
857 struct list_head list;
858 };
859
860 enum radv_cmd_buffer_status {
861 RADV_CMD_BUFFER_STATUS_INVALID,
862 RADV_CMD_BUFFER_STATUS_INITIAL,
863 RADV_CMD_BUFFER_STATUS_RECORDING,
864 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
865 RADV_CMD_BUFFER_STATUS_PENDING,
866 };
867
868 struct radv_cmd_buffer {
869 VK_LOADER_DATA _loader_data;
870
871 struct radv_device * device;
872
873 struct radv_cmd_pool * pool;
874 struct list_head pool_link;
875
876 VkCommandBufferUsageFlags usage_flags;
877 VkCommandBufferLevel level;
878 enum radv_cmd_buffer_status status;
879 struct radeon_winsys_cs *cs;
880 struct radv_cmd_state state;
881 struct radv_vertex_binding vertex_bindings[MAX_VBS];
882 uint32_t queue_family_index;
883
884 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
885 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
886 VkShaderStageFlags push_constant_stages;
887 struct radv_push_descriptor_set push_descriptors;
888 struct radv_descriptor_set meta_push_descriptors;
889 struct radv_descriptor_set *descriptors[MAX_SETS];
890
891 struct radv_cmd_buffer_upload upload;
892
893 uint32_t scratch_size_needed;
894 uint32_t compute_scratch_size_needed;
895 uint32_t esgs_ring_size_needed;
896 uint32_t gsvs_ring_size_needed;
897 bool tess_rings_needed;
898 bool sample_positions_needed;
899
900 VkResult record_result;
901
902 int ring_offsets_idx; /* just used for verification */
903 uint32_t gfx9_fence_offset;
904 struct radeon_winsys_bo *gfx9_fence_bo;
905 uint32_t gfx9_fence_idx;
906 };
907
908 struct radv_image;
909
910 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
911
912 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
913 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
914
915 void cik_create_gfx_config(struct radv_device *device);
916
917 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
918 int count, const VkViewport *viewports);
919 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
920 int count, const VkRect2D *scissors,
921 const VkViewport *viewports, bool can_use_guardband);
922 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
923 bool instanced_draw, bool indirect_draw,
924 uint32_t draw_vertex_count);
925 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
926 bool predicated,
927 enum chip_class chip_class,
928 bool is_mec,
929 unsigned event, unsigned event_flags,
930 unsigned data_sel,
931 uint64_t va,
932 uint32_t old_fence,
933 uint32_t new_fence);
934
935 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
936 bool predicated,
937 uint64_t va, uint32_t ref,
938 uint32_t mask);
939 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
940 bool predicated,
941 enum chip_class chip_class,
942 uint32_t *fence_ptr, uint64_t va,
943 bool is_mec,
944 enum radv_cmd_flush_bits flush_bits);
945 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
946 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
947 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
948 uint64_t src_va, uint64_t dest_va,
949 uint64_t size);
950 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
951 unsigned size);
952 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
953 uint64_t size, unsigned value);
954 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
955 bool
956 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
957 unsigned size,
958 unsigned alignment,
959 unsigned *out_offset,
960 void **ptr);
961 void
962 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
963 const struct radv_subpass *subpass,
964 bool transitions);
965 bool
966 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
967 unsigned size, unsigned alignmnet,
968 const void *data, unsigned *out_offset);
969
970 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
971 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
972 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
973 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
974 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
975 unsigned radv_cayman_get_maxdist(int log_samples);
976 void radv_device_init_msaa(struct radv_device *device);
977 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
978 struct radv_image *image,
979 VkClearDepthStencilValue ds_clear_value,
980 VkImageAspectFlags aspects);
981 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
982 struct radv_image *image,
983 int idx,
984 uint32_t color_values[2]);
985 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
986 struct radv_image *image,
987 bool value);
988 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
989 struct radeon_winsys_bo *bo,
990 uint64_t offset, uint64_t size, uint32_t value);
991 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
992 bool radv_get_memory_fd(struct radv_device *device,
993 struct radv_device_memory *memory,
994 int *pFD);
995
996 /*
997 * Takes x,y,z as exact numbers of invocations, instead of blocks.
998 *
999 * Limitations: Can't call normal dispatch functions without binding or rebinding
1000 * the compute pipeline.
1001 */
1002 void radv_unaligned_dispatch(
1003 struct radv_cmd_buffer *cmd_buffer,
1004 uint32_t x,
1005 uint32_t y,
1006 uint32_t z);
1007
1008 struct radv_event {
1009 struct radeon_winsys_bo *bo;
1010 uint64_t *map;
1011 };
1012
1013 struct radv_shader_module;
1014
1015 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1016 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1017 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1018 void
1019 radv_hash_shaders(unsigned char *hash,
1020 const VkPipelineShaderStageCreateInfo **stages,
1021 const struct radv_pipeline_layout *layout,
1022 const struct radv_pipeline_key *key,
1023 uint32_t flags);
1024
1025 static inline gl_shader_stage
1026 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1027 {
1028 assert(__builtin_popcount(vk_stage) == 1);
1029 return ffs(vk_stage) - 1;
1030 }
1031
1032 static inline VkShaderStageFlagBits
1033 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1034 {
1035 return (1 << mesa_stage);
1036 }
1037
1038 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1039
1040 #define radv_foreach_stage(stage, stage_bits) \
1041 for (gl_shader_stage stage, \
1042 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1043 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1044 __tmp &= ~(1 << (stage)))
1045
1046 struct radv_depth_stencil_state {
1047 uint32_t db_depth_control;
1048 uint32_t db_stencil_control;
1049 uint32_t db_render_control;
1050 uint32_t db_render_override2;
1051 };
1052
1053 struct radv_blend_state {
1054 uint32_t cb_color_control;
1055 uint32_t cb_target_mask;
1056 uint32_t sx_mrt_blend_opt[8];
1057 uint32_t cb_blend_control[8];
1058
1059 uint32_t spi_shader_col_format;
1060 uint32_t cb_shader_mask;
1061 uint32_t db_alpha_to_mask;
1062 };
1063
1064 unsigned radv_format_meta_fs_key(VkFormat format);
1065
1066 struct radv_raster_state {
1067 uint32_t pa_cl_clip_cntl;
1068 uint32_t spi_interp_control;
1069 uint32_t pa_su_vtx_cntl;
1070 uint32_t pa_su_sc_mode_cntl;
1071 };
1072
1073 struct radv_multisample_state {
1074 uint32_t db_eqaa;
1075 uint32_t pa_sc_line_cntl;
1076 uint32_t pa_sc_mode_cntl_0;
1077 uint32_t pa_sc_mode_cntl_1;
1078 uint32_t pa_sc_aa_config;
1079 uint32_t pa_sc_aa_mask[2];
1080 unsigned num_samples;
1081 };
1082
1083 struct radv_prim_vertex_count {
1084 uint8_t min;
1085 uint8_t incr;
1086 };
1087
1088 struct radv_tessellation_state {
1089 uint32_t ls_hs_config;
1090 uint32_t tcs_in_layout;
1091 uint32_t tcs_out_layout;
1092 uint32_t tcs_out_offsets;
1093 uint32_t offchip_layout;
1094 unsigned num_patches;
1095 unsigned lds_size;
1096 unsigned num_tcs_input_cp;
1097 uint32_t tf_param;
1098 };
1099
1100 struct radv_gs_state {
1101 uint32_t vgt_gs_onchip_cntl;
1102 uint32_t vgt_gs_max_prims_per_subgroup;
1103 uint32_t vgt_esgs_ring_itemsize;
1104 uint32_t lds_size;
1105 };
1106
1107 struct radv_vertex_elements_info {
1108 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1109 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1110 uint32_t binding[MAX_VERTEX_ATTRIBS];
1111 uint32_t offset[MAX_VERTEX_ATTRIBS];
1112 uint32_t count;
1113 };
1114
1115 struct radv_vs_state {
1116 uint32_t pa_cl_vs_out_cntl;
1117 uint32_t spi_shader_pos_format;
1118 uint32_t spi_vs_out_config;
1119 uint32_t vgt_reuse_off;
1120 };
1121
1122 #define SI_GS_PER_ES 128
1123
1124 struct radv_pipeline {
1125 struct radv_device * device;
1126 struct radv_dynamic_state dynamic_state;
1127
1128 struct radv_pipeline_layout * layout;
1129
1130 bool needs_data_cache;
1131 bool need_indirect_descriptor_sets;
1132 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1133 struct radv_shader_variant *gs_copy_shader;
1134 VkShaderStageFlags active_stages;
1135
1136 struct radv_vertex_elements_info vertex_elements;
1137
1138 uint32_t binding_stride[MAX_VBS];
1139
1140 uint32_t user_data_0[MESA_SHADER_STAGES];
1141 union {
1142 struct {
1143 struct radv_blend_state blend;
1144 struct radv_depth_stencil_state ds;
1145 struct radv_raster_state raster;
1146 struct radv_multisample_state ms;
1147 struct radv_tessellation_state tess;
1148 struct radv_gs_state gs;
1149 struct radv_vs_state vs;
1150 uint32_t db_shader_control;
1151 uint32_t shader_z_format;
1152 unsigned prim;
1153 unsigned gs_out;
1154 uint32_t vgt_gs_mode;
1155 bool vgt_primitiveid_en;
1156 bool prim_restart_enable;
1157 bool partial_es_wave;
1158 uint8_t primgroup_size;
1159 unsigned esgs_ring_size;
1160 unsigned gsvs_ring_size;
1161 uint32_t ps_input_cntl[32];
1162 uint32_t ps_input_cntl_num;
1163 uint32_t vgt_shader_stages_en;
1164 uint32_t vtx_base_sgpr;
1165 uint32_t base_ia_multi_vgt_param;
1166 bool wd_switch_on_eop;
1167 bool ia_switch_on_eoi;
1168 bool partial_vs_wave;
1169 uint8_t vtx_emit_num;
1170 uint32_t vtx_reuse_depth;
1171 struct radv_prim_vertex_count prim_vertex_count;
1172 bool can_use_guardband;
1173 } graphics;
1174 };
1175
1176 unsigned max_waves;
1177 unsigned scratch_bytes_per_wave;
1178 };
1179
1180 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1181 {
1182 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1183 }
1184
1185 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1186 {
1187 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1188 }
1189
1190 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1191 gl_shader_stage stage,
1192 int idx);
1193
1194 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1195
1196 struct radv_graphics_pipeline_create_info {
1197 bool use_rectlist;
1198 bool db_depth_clear;
1199 bool db_stencil_clear;
1200 bool db_depth_disable_expclear;
1201 bool db_stencil_disable_expclear;
1202 bool db_flush_depth_inplace;
1203 bool db_flush_stencil_inplace;
1204 bool db_resummarize;
1205 uint32_t custom_blend_mode;
1206 };
1207
1208 VkResult
1209 radv_graphics_pipeline_create(VkDevice device,
1210 VkPipelineCache cache,
1211 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1212 const struct radv_graphics_pipeline_create_info *extra,
1213 const VkAllocationCallbacks *alloc,
1214 VkPipeline *pPipeline);
1215
1216 struct vk_format_description;
1217 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1218 int first_non_void);
1219 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1220 int first_non_void);
1221 uint32_t radv_translate_colorformat(VkFormat format);
1222 uint32_t radv_translate_color_numformat(VkFormat format,
1223 const struct vk_format_description *desc,
1224 int first_non_void);
1225 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1226 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1227 uint32_t radv_translate_dbformat(VkFormat format);
1228 uint32_t radv_translate_tex_dataformat(VkFormat format,
1229 const struct vk_format_description *desc,
1230 int first_non_void);
1231 uint32_t radv_translate_tex_numformat(VkFormat format,
1232 const struct vk_format_description *desc,
1233 int first_non_void);
1234 bool radv_format_pack_clear_color(VkFormat format,
1235 uint32_t clear_vals[2],
1236 VkClearColorValue *value);
1237 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1238 bool radv_dcc_formats_compatible(VkFormat format1,
1239 VkFormat format2);
1240
1241 struct radv_fmask_info {
1242 uint64_t offset;
1243 uint64_t size;
1244 unsigned alignment;
1245 unsigned pitch_in_pixels;
1246 unsigned bank_height;
1247 unsigned slice_tile_max;
1248 unsigned tile_mode_index;
1249 unsigned tile_swizzle;
1250 };
1251
1252 struct radv_cmask_info {
1253 uint64_t offset;
1254 uint64_t size;
1255 unsigned alignment;
1256 unsigned slice_tile_max;
1257 unsigned base_address_reg;
1258 };
1259
1260 struct radv_image {
1261 VkImageType type;
1262 /* The original VkFormat provided by the client. This may not match any
1263 * of the actual surface formats.
1264 */
1265 VkFormat vk_format;
1266 VkImageAspectFlags aspects;
1267 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1268 struct ac_surf_info info;
1269 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1270 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1271
1272 VkDeviceSize size;
1273 uint32_t alignment;
1274
1275 unsigned queue_family_mask;
1276 bool exclusive;
1277 bool shareable;
1278
1279 /* Set when bound */
1280 struct radeon_winsys_bo *bo;
1281 VkDeviceSize offset;
1282 uint64_t dcc_offset;
1283 uint64_t htile_offset;
1284 bool tc_compatible_htile;
1285 struct radeon_surf surface;
1286
1287 struct radv_fmask_info fmask;
1288 struct radv_cmask_info cmask;
1289 uint64_t clear_value_offset;
1290 uint64_t dcc_pred_offset;
1291 };
1292
1293 /* Whether the image has a htile that is known consistent with the contents of
1294 * the image. */
1295 bool radv_layout_has_htile(const struct radv_image *image,
1296 VkImageLayout layout,
1297 unsigned queue_mask);
1298
1299 /* Whether the image has a htile that is known consistent with the contents of
1300 * the image and is allowed to be in compressed form.
1301 *
1302 * If this is false reads that don't use the htile should be able to return
1303 * correct results.
1304 */
1305 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1306 VkImageLayout layout,
1307 unsigned queue_mask);
1308
1309 bool radv_layout_can_fast_clear(const struct radv_image *image,
1310 VkImageLayout layout,
1311 unsigned queue_mask);
1312
1313 static inline bool
1314 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1315 {
1316 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1317 }
1318
1319 static inline bool
1320 radv_htile_enabled(const struct radv_image *image, unsigned level)
1321 {
1322 return image->surface.htile_size && level == 0;
1323 }
1324
1325 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1326
1327 static inline uint32_t
1328 radv_get_layerCount(const struct radv_image *image,
1329 const VkImageSubresourceRange *range)
1330 {
1331 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1332 image->info.array_size - range->baseArrayLayer : range->layerCount;
1333 }
1334
1335 static inline uint32_t
1336 radv_get_levelCount(const struct radv_image *image,
1337 const VkImageSubresourceRange *range)
1338 {
1339 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1340 image->info.levels - range->baseMipLevel : range->levelCount;
1341 }
1342
1343 struct radeon_bo_metadata;
1344 void
1345 radv_init_metadata(struct radv_device *device,
1346 struct radv_image *image,
1347 struct radeon_bo_metadata *metadata);
1348
1349 struct radv_image_view {
1350 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1351 struct radeon_winsys_bo *bo;
1352
1353 VkImageViewType type;
1354 VkImageAspectFlags aspect_mask;
1355 VkFormat vk_format;
1356 uint32_t base_layer;
1357 uint32_t layer_count;
1358 uint32_t base_mip;
1359 uint32_t level_count;
1360 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1361
1362 uint32_t descriptor[16];
1363
1364 /* Descriptor for use as a storage image as opposed to a sampled image.
1365 * This has a few differences for cube maps (e.g. type).
1366 */
1367 uint32_t storage_descriptor[16];
1368 };
1369
1370 struct radv_image_create_info {
1371 const VkImageCreateInfo *vk_info;
1372 bool scanout;
1373 };
1374
1375 VkResult radv_image_create(VkDevice _device,
1376 const struct radv_image_create_info *info,
1377 const VkAllocationCallbacks* alloc,
1378 VkImage *pImage);
1379
1380 void radv_image_view_init(struct radv_image_view *view,
1381 struct radv_device *device,
1382 const VkImageViewCreateInfo* pCreateInfo);
1383
1384 struct radv_buffer_view {
1385 struct radeon_winsys_bo *bo;
1386 VkFormat vk_format;
1387 uint64_t range; /**< VkBufferViewCreateInfo::range */
1388 uint32_t state[4];
1389 };
1390 void radv_buffer_view_init(struct radv_buffer_view *view,
1391 struct radv_device *device,
1392 const VkBufferViewCreateInfo* pCreateInfo);
1393
1394 static inline struct VkExtent3D
1395 radv_sanitize_image_extent(const VkImageType imageType,
1396 const struct VkExtent3D imageExtent)
1397 {
1398 switch (imageType) {
1399 case VK_IMAGE_TYPE_1D:
1400 return (VkExtent3D) { imageExtent.width, 1, 1 };
1401 case VK_IMAGE_TYPE_2D:
1402 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1403 case VK_IMAGE_TYPE_3D:
1404 return imageExtent;
1405 default:
1406 unreachable("invalid image type");
1407 }
1408 }
1409
1410 static inline struct VkOffset3D
1411 radv_sanitize_image_offset(const VkImageType imageType,
1412 const struct VkOffset3D imageOffset)
1413 {
1414 switch (imageType) {
1415 case VK_IMAGE_TYPE_1D:
1416 return (VkOffset3D) { imageOffset.x, 0, 0 };
1417 case VK_IMAGE_TYPE_2D:
1418 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1419 case VK_IMAGE_TYPE_3D:
1420 return imageOffset;
1421 default:
1422 unreachable("invalid image type");
1423 }
1424 }
1425
1426 static inline bool
1427 radv_image_extent_compare(const struct radv_image *image,
1428 const VkExtent3D *extent)
1429 {
1430 if (extent->width != image->info.width ||
1431 extent->height != image->info.height ||
1432 extent->depth != image->info.depth)
1433 return false;
1434 return true;
1435 }
1436
1437 struct radv_sampler {
1438 uint32_t state[4];
1439 };
1440
1441 struct radv_color_buffer_info {
1442 uint64_t cb_color_base;
1443 uint64_t cb_color_cmask;
1444 uint64_t cb_color_fmask;
1445 uint64_t cb_dcc_base;
1446 uint32_t cb_color_pitch;
1447 uint32_t cb_color_slice;
1448 uint32_t cb_color_view;
1449 uint32_t cb_color_info;
1450 uint32_t cb_color_attrib;
1451 uint32_t cb_color_attrib2;
1452 uint32_t cb_dcc_control;
1453 uint32_t cb_color_cmask_slice;
1454 uint32_t cb_color_fmask_slice;
1455 uint32_t cb_clear_value0;
1456 uint32_t cb_clear_value1;
1457 };
1458
1459 struct radv_ds_buffer_info {
1460 uint64_t db_z_read_base;
1461 uint64_t db_stencil_read_base;
1462 uint64_t db_z_write_base;
1463 uint64_t db_stencil_write_base;
1464 uint64_t db_htile_data_base;
1465 uint32_t db_depth_info;
1466 uint32_t db_z_info;
1467 uint32_t db_stencil_info;
1468 uint32_t db_depth_view;
1469 uint32_t db_depth_size;
1470 uint32_t db_depth_slice;
1471 uint32_t db_htile_surface;
1472 uint32_t pa_su_poly_offset_db_fmt_cntl;
1473 uint32_t db_z_info2;
1474 uint32_t db_stencil_info2;
1475 float offset_scale;
1476 };
1477
1478 struct radv_attachment_info {
1479 union {
1480 struct radv_color_buffer_info cb;
1481 struct radv_ds_buffer_info ds;
1482 };
1483 struct radv_image_view *attachment;
1484 };
1485
1486 struct radv_framebuffer {
1487 uint32_t width;
1488 uint32_t height;
1489 uint32_t layers;
1490
1491 uint32_t attachment_count;
1492 struct radv_attachment_info attachments[0];
1493 };
1494
1495 struct radv_subpass_barrier {
1496 VkPipelineStageFlags src_stage_mask;
1497 VkAccessFlags src_access_mask;
1498 VkAccessFlags dst_access_mask;
1499 };
1500
1501 struct radv_subpass {
1502 uint32_t input_count;
1503 uint32_t color_count;
1504 VkAttachmentReference * input_attachments;
1505 VkAttachmentReference * color_attachments;
1506 VkAttachmentReference * resolve_attachments;
1507 VkAttachmentReference depth_stencil_attachment;
1508
1509 /** Subpass has at least one resolve attachment */
1510 bool has_resolve;
1511
1512 struct radv_subpass_barrier start_barrier;
1513
1514 uint32_t view_mask;
1515 };
1516
1517 struct radv_render_pass_attachment {
1518 VkFormat format;
1519 uint32_t samples;
1520 VkAttachmentLoadOp load_op;
1521 VkAttachmentLoadOp stencil_load_op;
1522 VkImageLayout initial_layout;
1523 VkImageLayout final_layout;
1524 uint32_t view_mask;
1525 };
1526
1527 struct radv_render_pass {
1528 uint32_t attachment_count;
1529 uint32_t subpass_count;
1530 VkAttachmentReference * subpass_attachments;
1531 struct radv_render_pass_attachment * attachments;
1532 struct radv_subpass_barrier end_barrier;
1533 struct radv_subpass subpasses[0];
1534 };
1535
1536 VkResult radv_device_init_meta(struct radv_device *device);
1537 void radv_device_finish_meta(struct radv_device *device);
1538
1539 struct radv_query_pool {
1540 struct radeon_winsys_bo *bo;
1541 uint32_t stride;
1542 uint32_t availability_offset;
1543 char *ptr;
1544 VkQueryType type;
1545 uint32_t pipeline_stats_mask;
1546 };
1547
1548 struct radv_semaphore {
1549 /* use a winsys sem for non-exportable */
1550 struct radeon_winsys_sem *sem;
1551 uint32_t syncobj;
1552 uint32_t temp_syncobj;
1553 };
1554
1555 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1556 int num_wait_sems,
1557 const VkSemaphore *wait_sems,
1558 int num_signal_sems,
1559 const VkSemaphore *signal_sems);
1560 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1561
1562 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1563 struct radv_descriptor_set *set,
1564 unsigned idx);
1565
1566 void
1567 radv_update_descriptor_sets(struct radv_device *device,
1568 struct radv_cmd_buffer *cmd_buffer,
1569 VkDescriptorSet overrideSet,
1570 uint32_t descriptorWriteCount,
1571 const VkWriteDescriptorSet *pDescriptorWrites,
1572 uint32_t descriptorCopyCount,
1573 const VkCopyDescriptorSet *pDescriptorCopies);
1574
1575 void
1576 radv_update_descriptor_set_with_template(struct radv_device *device,
1577 struct radv_cmd_buffer *cmd_buffer,
1578 struct radv_descriptor_set *set,
1579 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1580 const void *pData);
1581
1582 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1583 VkPipelineBindPoint pipelineBindPoint,
1584 VkPipelineLayout _layout,
1585 uint32_t set,
1586 uint32_t descriptorWriteCount,
1587 const VkWriteDescriptorSet *pDescriptorWrites);
1588
1589 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1590 struct radv_image *image, uint32_t value);
1591 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1592 struct radv_image *image, uint32_t value);
1593
1594 struct radv_fence {
1595 struct radeon_winsys_fence *fence;
1596 bool submitted;
1597 bool signalled;
1598 };
1599
1600 struct radeon_winsys_sem;
1601
1602 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1603 \
1604 static inline struct __radv_type * \
1605 __radv_type ## _from_handle(__VkType _handle) \
1606 { \
1607 return (struct __radv_type *) _handle; \
1608 } \
1609 \
1610 static inline __VkType \
1611 __radv_type ## _to_handle(struct __radv_type *_obj) \
1612 { \
1613 return (__VkType) _obj; \
1614 }
1615
1616 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1617 \
1618 static inline struct __radv_type * \
1619 __radv_type ## _from_handle(__VkType _handle) \
1620 { \
1621 return (struct __radv_type *)(uintptr_t) _handle; \
1622 } \
1623 \
1624 static inline __VkType \
1625 __radv_type ## _to_handle(struct __radv_type *_obj) \
1626 { \
1627 return (__VkType)(uintptr_t) _obj; \
1628 }
1629
1630 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1631 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1632
1633 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1634 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1635 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1636 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1637 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1638
1639 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1640 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1641 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1642 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1643 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1644 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1645 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1646 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1647 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1648 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1649 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1650 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1651 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1652 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1653 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1654 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1655 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1656 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1657 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1658 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1659 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1660
1661 #endif /* RADV_PRIVATE_H */