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radv: remove radv_get_image_fmask_info()
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
53 #include "vk_alloc.h"
54 #include "vk_debug_report.h"
55
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
66 #include "sid.h"
67
68 #include <llvm-c/TargetMachine.h>
69
70 /* Pre-declarations needed for WSI entrypoints */
71 struct wl_surface;
72 struct wl_display;
73 typedef struct xcb_connection_t xcb_connection_t;
74 typedef uint32_t xcb_visualid_t;
75 typedef uint32_t xcb_window_t;
76
77 #include <vulkan/vulkan.h>
78 #include <vulkan/vulkan_intel.h>
79 #include <vulkan/vk_icd.h>
80 #include <vulkan/vk_android_native_buffer.h>
81
82 #include "radv_entrypoints.h"
83
84 #include "wsi_common.h"
85 #include "wsi_common_display.h"
86
87 struct gfx10_format {
88 unsigned img_format:9;
89
90 /* Various formats are only supported with workarounds for vertex fetch,
91 * and some 32_32_32 formats are supported natively, but only for buffers
92 * (possibly with some image support, actually, but no filtering). */
93 bool buffers_only:1;
94 };
95
96 #include "gfx10_format_table.h"
97
98 enum radv_mem_heap {
99 RADV_MEM_HEAP_VRAM,
100 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
101 RADV_MEM_HEAP_GTT,
102 RADV_MEM_HEAP_COUNT
103 };
104
105 enum radv_mem_type {
106 RADV_MEM_TYPE_VRAM,
107 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
108 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
109 RADV_MEM_TYPE_GTT_CACHED,
110 RADV_MEM_TYPE_COUNT
111 };
112
113 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
114
115 static inline uint32_t
116 align_u32(uint32_t v, uint32_t a)
117 {
118 assert(a != 0 && a == (a & -a));
119 return (v + a - 1) & ~(a - 1);
120 }
121
122 static inline uint32_t
123 align_u32_npot(uint32_t v, uint32_t a)
124 {
125 return (v + a - 1) / a * a;
126 }
127
128 static inline uint64_t
129 align_u64(uint64_t v, uint64_t a)
130 {
131 assert(a != 0 && a == (a & -a));
132 return (v + a - 1) & ~(a - 1);
133 }
134
135 static inline int32_t
136 align_i32(int32_t v, int32_t a)
137 {
138 assert(a != 0 && a == (a & -a));
139 return (v + a - 1) & ~(a - 1);
140 }
141
142 /** Alignment must be a power of 2. */
143 static inline bool
144 radv_is_aligned(uintmax_t n, uintmax_t a)
145 {
146 assert(a == (a & -a));
147 return (n & (a - 1)) == 0;
148 }
149
150 static inline uint32_t
151 round_up_u32(uint32_t v, uint32_t a)
152 {
153 return (v + a - 1) / a;
154 }
155
156 static inline uint64_t
157 round_up_u64(uint64_t v, uint64_t a)
158 {
159 return (v + a - 1) / a;
160 }
161
162 static inline uint32_t
163 radv_minify(uint32_t n, uint32_t levels)
164 {
165 if (unlikely(n == 0))
166 return 0;
167 else
168 return MAX2(n >> levels, 1);
169 }
170 static inline float
171 radv_clamp_f(float f, float min, float max)
172 {
173 assert(min < max);
174
175 if (f > max)
176 return max;
177 else if (f < min)
178 return min;
179 else
180 return f;
181 }
182
183 static inline bool
184 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
185 {
186 if (*inout_mask & clear_mask) {
187 *inout_mask &= ~clear_mask;
188 return true;
189 } else {
190 return false;
191 }
192 }
193
194 #define for_each_bit(b, dword) \
195 for (uint32_t __dword = (dword); \
196 (b) = __builtin_ffs(__dword) - 1, __dword; \
197 __dword &= ~(1 << (b)))
198
199 #define typed_memcpy(dest, src, count) ({ \
200 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
201 memcpy((dest), (src), (count) * sizeof(*(src))); \
202 })
203
204 /* Whenever we generate an error, pass it through this function. Useful for
205 * debugging, where we can break on it. Only call at error site, not when
206 * propagating errors. Might be useful to plug in a stack trace here.
207 */
208
209 struct radv_instance;
210
211 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
212
213 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
214 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
215
216 void __radv_finishme(const char *file, int line, const char *format, ...)
217 radv_printflike(3, 4);
218 void radv_loge(const char *format, ...) radv_printflike(1, 2);
219 void radv_loge_v(const char *format, va_list va);
220 void radv_logi(const char *format, ...) radv_printflike(1, 2);
221 void radv_logi_v(const char *format, va_list va);
222
223 /**
224 * Print a FINISHME message, including its source location.
225 */
226 #define radv_finishme(format, ...) \
227 do { \
228 static bool reported = false; \
229 if (!reported) { \
230 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
231 reported = true; \
232 } \
233 } while (0)
234
235 /* A non-fatal assert. Useful for debugging. */
236 #ifdef DEBUG
237 #define radv_assert(x) ({ \
238 if (unlikely(!(x))) \
239 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
240 })
241 #else
242 #define radv_assert(x)
243 #endif
244
245 #define stub_return(v) \
246 do { \
247 radv_finishme("stub %s", __func__); \
248 return (v); \
249 } while (0)
250
251 #define stub() \
252 do { \
253 radv_finishme("stub %s", __func__); \
254 return; \
255 } while (0)
256
257 void *radv_lookup_entrypoint_unchecked(const char *name);
258 void *radv_lookup_entrypoint_checked(const char *name,
259 uint32_t core_version,
260 const struct radv_instance_extension_table *instance,
261 const struct radv_device_extension_table *device);
262 void *radv_lookup_physical_device_entrypoint_checked(const char *name,
263 uint32_t core_version,
264 const struct radv_instance_extension_table *instance);
265
266 struct radv_physical_device {
267 VK_LOADER_DATA _loader_data;
268
269 struct radv_instance * instance;
270
271 struct radeon_winsys *ws;
272 struct radeon_info rad_info;
273 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
274 uint8_t driver_uuid[VK_UUID_SIZE];
275 uint8_t device_uuid[VK_UUID_SIZE];
276 uint8_t cache_uuid[VK_UUID_SIZE];
277
278 int local_fd;
279 int master_fd;
280 struct wsi_device wsi_device;
281
282 bool has_rbplus; /* if RB+ register exist */
283 bool rbplus_allowed; /* if RB+ is allowed */
284 bool has_clear_state;
285 bool cpdma_prefetch_writes_memory;
286 bool has_scissor_bug;
287 bool has_tc_compat_zrange_bug;
288
289 bool has_out_of_order_rast;
290 bool out_of_order_rast_allowed;
291
292 /* Whether DCC should be enabled for MSAA textures. */
293 bool dcc_msaa_allowed;
294
295 /* Whether LOAD_CONTEXT_REG packets are supported. */
296 bool has_load_ctx_reg_pkt;
297
298 /* Whether to enable the AMD_shader_ballot extension */
299 bool use_shader_ballot;
300
301 /* Whether DISABLE_CONSTANT_ENCODE_REG is supported. */
302 bool has_dcc_constant_encode;
303
304 /* Number of threads per wave. */
305 uint8_t ps_wave_size;
306 uint8_t cs_wave_size;
307 uint8_t ge_wave_size;
308
309 /* This is the drivers on-disk cache used as a fallback as opposed to
310 * the pipeline cache defined by apps.
311 */
312 struct disk_cache * disk_cache;
313
314 VkPhysicalDeviceMemoryProperties memory_properties;
315 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
316
317 drmPciBusInfo bus_info;
318
319 struct radv_device_extension_table supported_extensions;
320 };
321
322 struct radv_instance {
323 VK_LOADER_DATA _loader_data;
324
325 VkAllocationCallbacks alloc;
326
327 uint32_t apiVersion;
328 int physicalDeviceCount;
329 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
330
331 uint64_t debug_flags;
332 uint64_t perftest_flags;
333
334 struct vk_debug_report_instance debug_report_callbacks;
335
336 struct radv_instance_extension_table enabled_extensions;
337
338 struct driOptionCache dri_options;
339 struct driOptionCache available_dri_options;
340 };
341
342 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
343 void radv_finish_wsi(struct radv_physical_device *physical_device);
344
345 bool radv_instance_extension_supported(const char *name);
346 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
347 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
348 const char *name);
349
350 struct cache_entry;
351
352 struct radv_pipeline_cache {
353 struct radv_device * device;
354 pthread_mutex_t mutex;
355
356 uint32_t total_size;
357 uint32_t table_size;
358 uint32_t kernel_count;
359 struct cache_entry ** hash_table;
360 bool modified;
361
362 VkAllocationCallbacks alloc;
363 };
364
365 struct radv_pipeline_key {
366 uint32_t instance_rate_inputs;
367 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
368 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
369 uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
370 uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
371 uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
372 uint64_t vertex_alpha_adjust;
373 uint32_t vertex_post_shuffle;
374 unsigned tess_input_vertices;
375 uint32_t col_format;
376 uint32_t is_int8;
377 uint32_t is_int10;
378 uint8_t log2_ps_iter_samples;
379 uint8_t num_samples;
380 uint32_t has_multiview_view_index : 1;
381 uint32_t optimisations_disabled : 1;
382 };
383
384 struct radv_shader_binary;
385 struct radv_shader_variant;
386
387 void
388 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
389 struct radv_device *device);
390 void
391 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
392 bool
393 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
394 const void *data, size_t size);
395
396 bool
397 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
398 struct radv_pipeline_cache *cache,
399 const unsigned char *sha1,
400 struct radv_shader_variant **variants,
401 bool *found_in_application_cache);
402
403 void
404 radv_pipeline_cache_insert_shaders(struct radv_device *device,
405 struct radv_pipeline_cache *cache,
406 const unsigned char *sha1,
407 struct radv_shader_variant **variants,
408 struct radv_shader_binary *const *binaries);
409
410 enum radv_blit_ds_layout {
411 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
412 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
413 RADV_BLIT_DS_LAYOUT_COUNT,
414 };
415
416 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
417 {
418 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
419 }
420
421 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
422 {
423 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
424 }
425
426 enum radv_meta_dst_layout {
427 RADV_META_DST_LAYOUT_GENERAL,
428 RADV_META_DST_LAYOUT_OPTIMAL,
429 RADV_META_DST_LAYOUT_COUNT,
430 };
431
432 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
433 {
434 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
435 }
436
437 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
438 {
439 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
440 }
441
442 struct radv_meta_state {
443 VkAllocationCallbacks alloc;
444
445 struct radv_pipeline_cache cache;
446
447 /*
448 * For on-demand pipeline creation, makes sure that
449 * only one thread tries to build a pipeline at the same time.
450 */
451 mtx_t mtx;
452
453 /**
454 * Use array element `i` for images with `2^i` samples.
455 */
456 struct {
457 VkRenderPass render_pass[NUM_META_FS_KEYS];
458 VkPipeline color_pipelines[NUM_META_FS_KEYS];
459
460 VkRenderPass depthstencil_rp;
461 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
462 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
463 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
464 } clear[1 + MAX_SAMPLES_LOG2];
465
466 VkPipelineLayout clear_color_p_layout;
467 VkPipelineLayout clear_depth_p_layout;
468
469 /* Optimized compute fast HTILE clear for stencil or depth only. */
470 VkPipeline clear_htile_mask_pipeline;
471 VkPipelineLayout clear_htile_mask_p_layout;
472 VkDescriptorSetLayout clear_htile_mask_ds_layout;
473
474 struct {
475 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
476
477 /** Pipeline that blits from a 1D image. */
478 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
479
480 /** Pipeline that blits from a 2D image. */
481 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
482
483 /** Pipeline that blits from a 3D image. */
484 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
485
486 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
487 VkPipeline depth_only_1d_pipeline;
488 VkPipeline depth_only_2d_pipeline;
489 VkPipeline depth_only_3d_pipeline;
490
491 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
492 VkPipeline stencil_only_1d_pipeline;
493 VkPipeline stencil_only_2d_pipeline;
494 VkPipeline stencil_only_3d_pipeline;
495 VkPipelineLayout pipeline_layout;
496 VkDescriptorSetLayout ds_layout;
497 } blit;
498
499 struct {
500 VkPipelineLayout p_layouts[5];
501 VkDescriptorSetLayout ds_layouts[5];
502 VkPipeline pipelines[5][NUM_META_FS_KEYS];
503
504 VkPipeline depth_only_pipeline[5];
505
506 VkPipeline stencil_only_pipeline[5];
507 } blit2d[1 + MAX_SAMPLES_LOG2];
508
509 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
510 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
511 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
512
513 struct {
514 VkPipelineLayout img_p_layout;
515 VkDescriptorSetLayout img_ds_layout;
516 VkPipeline pipeline;
517 VkPipeline pipeline_3d;
518 } itob;
519 struct {
520 VkPipelineLayout img_p_layout;
521 VkDescriptorSetLayout img_ds_layout;
522 VkPipeline pipeline;
523 VkPipeline pipeline_3d;
524 } btoi;
525 struct {
526 VkPipelineLayout img_p_layout;
527 VkDescriptorSetLayout img_ds_layout;
528 VkPipeline pipeline;
529 } btoi_r32g32b32;
530 struct {
531 VkPipelineLayout img_p_layout;
532 VkDescriptorSetLayout img_ds_layout;
533 VkPipeline pipeline;
534 VkPipeline pipeline_3d;
535 } itoi;
536 struct {
537 VkPipelineLayout img_p_layout;
538 VkDescriptorSetLayout img_ds_layout;
539 VkPipeline pipeline;
540 } itoi_r32g32b32;
541 struct {
542 VkPipelineLayout img_p_layout;
543 VkDescriptorSetLayout img_ds_layout;
544 VkPipeline pipeline;
545 VkPipeline pipeline_3d;
546 } cleari;
547 struct {
548 VkPipelineLayout img_p_layout;
549 VkDescriptorSetLayout img_ds_layout;
550 VkPipeline pipeline;
551 } cleari_r32g32b32;
552
553 struct {
554 VkPipelineLayout p_layout;
555 VkPipeline pipeline[NUM_META_FS_KEYS];
556 VkRenderPass pass[NUM_META_FS_KEYS];
557 } resolve;
558
559 struct {
560 VkDescriptorSetLayout ds_layout;
561 VkPipelineLayout p_layout;
562 struct {
563 VkPipeline pipeline;
564 VkPipeline i_pipeline;
565 VkPipeline srgb_pipeline;
566 } rc[MAX_SAMPLES_LOG2];
567
568 VkPipeline depth_zero_pipeline;
569 struct {
570 VkPipeline average_pipeline;
571 VkPipeline max_pipeline;
572 VkPipeline min_pipeline;
573 } depth[MAX_SAMPLES_LOG2];
574
575 VkPipeline stencil_zero_pipeline;
576 struct {
577 VkPipeline max_pipeline;
578 VkPipeline min_pipeline;
579 } stencil[MAX_SAMPLES_LOG2];
580 } resolve_compute;
581
582 struct {
583 VkDescriptorSetLayout ds_layout;
584 VkPipelineLayout p_layout;
585
586 struct {
587 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
588 VkPipeline pipeline[NUM_META_FS_KEYS];
589 } rc[MAX_SAMPLES_LOG2];
590
591 VkRenderPass depth_render_pass;
592 VkPipeline depth_zero_pipeline;
593 struct {
594 VkPipeline average_pipeline;
595 VkPipeline max_pipeline;
596 VkPipeline min_pipeline;
597 } depth[MAX_SAMPLES_LOG2];
598
599 VkRenderPass stencil_render_pass;
600 VkPipeline stencil_zero_pipeline;
601 struct {
602 VkPipeline max_pipeline;
603 VkPipeline min_pipeline;
604 } stencil[MAX_SAMPLES_LOG2];
605 } resolve_fragment;
606
607 struct {
608 VkPipelineLayout p_layout;
609 VkPipeline decompress_pipeline;
610 VkPipeline resummarize_pipeline;
611 VkRenderPass pass;
612 } depth_decomp[1 + MAX_SAMPLES_LOG2];
613
614 struct {
615 VkPipelineLayout p_layout;
616 VkPipeline cmask_eliminate_pipeline;
617 VkPipeline fmask_decompress_pipeline;
618 VkPipeline dcc_decompress_pipeline;
619 VkRenderPass pass;
620
621 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
622 VkPipelineLayout dcc_decompress_compute_p_layout;
623 VkPipeline dcc_decompress_compute_pipeline;
624 } fast_clear_flush;
625
626 struct {
627 VkPipelineLayout fill_p_layout;
628 VkPipelineLayout copy_p_layout;
629 VkDescriptorSetLayout fill_ds_layout;
630 VkDescriptorSetLayout copy_ds_layout;
631 VkPipeline fill_pipeline;
632 VkPipeline copy_pipeline;
633 } buffer;
634
635 struct {
636 VkDescriptorSetLayout ds_layout;
637 VkPipelineLayout p_layout;
638 VkPipeline occlusion_query_pipeline;
639 VkPipeline pipeline_statistics_query_pipeline;
640 VkPipeline tfb_query_pipeline;
641 } query;
642
643 struct {
644 VkDescriptorSetLayout ds_layout;
645 VkPipelineLayout p_layout;
646 VkPipeline pipeline[MAX_SAMPLES_LOG2];
647 } fmask_expand;
648 };
649
650 /* queue types */
651 #define RADV_QUEUE_GENERAL 0
652 #define RADV_QUEUE_COMPUTE 1
653 #define RADV_QUEUE_TRANSFER 2
654
655 #define RADV_MAX_QUEUE_FAMILIES 3
656
657 enum ring_type radv_queue_family_to_ring(int f);
658
659 struct radv_queue {
660 VK_LOADER_DATA _loader_data;
661 struct radv_device * device;
662 struct radeon_winsys_ctx *hw_ctx;
663 enum radeon_ctx_priority priority;
664 uint32_t queue_family_index;
665 int queue_idx;
666 VkDeviceQueueCreateFlags flags;
667
668 uint32_t scratch_size;
669 uint32_t compute_scratch_size;
670 uint32_t esgs_ring_size;
671 uint32_t gsvs_ring_size;
672 bool has_tess_rings;
673 bool has_sample_positions;
674
675 struct radeon_winsys_bo *scratch_bo;
676 struct radeon_winsys_bo *descriptor_bo;
677 struct radeon_winsys_bo *compute_scratch_bo;
678 struct radeon_winsys_bo *esgs_ring_bo;
679 struct radeon_winsys_bo *gsvs_ring_bo;
680 struct radeon_winsys_bo *tess_rings_bo;
681 struct radeon_cmdbuf *initial_preamble_cs;
682 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
683 struct radeon_cmdbuf *continue_preamble_cs;
684 };
685
686 struct radv_bo_list {
687 struct radv_winsys_bo_list list;
688 unsigned capacity;
689 pthread_mutex_t mutex;
690 };
691
692 struct radv_device {
693 VK_LOADER_DATA _loader_data;
694
695 VkAllocationCallbacks alloc;
696
697 struct radv_instance * instance;
698 struct radeon_winsys *ws;
699
700 struct radv_meta_state meta_state;
701
702 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
703 int queue_count[RADV_MAX_QUEUE_FAMILIES];
704 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
705
706 bool always_use_syncobj;
707 bool has_distributed_tess;
708 bool pbb_allowed;
709 bool dfsm_allowed;
710 uint32_t tess_offchip_block_dw_size;
711 uint32_t scratch_waves;
712 uint32_t dispatch_initiator;
713
714 uint32_t gs_table_depth;
715
716 /* MSAA sample locations.
717 * The first index is the sample index.
718 * The second index is the coordinate: X, Y. */
719 float sample_locations_1x[1][2];
720 float sample_locations_2x[2][2];
721 float sample_locations_4x[4][2];
722 float sample_locations_8x[8][2];
723
724 /* GFX7 and later */
725 uint32_t gfx_init_size_dw;
726 struct radeon_winsys_bo *gfx_init;
727
728 struct radeon_winsys_bo *trace_bo;
729 uint32_t *trace_id_ptr;
730
731 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
732 bool keep_shader_info;
733
734 struct radv_physical_device *physical_device;
735
736 /* Backup in-memory cache to be used if the app doesn't provide one */
737 struct radv_pipeline_cache * mem_cache;
738
739 /*
740 * use different counters so MSAA MRTs get consecutive surface indices,
741 * even if MASK is allocated in between.
742 */
743 uint32_t image_mrt_offset_counter;
744 uint32_t fmask_mrt_offset_counter;
745 struct list_head shader_slabs;
746 mtx_t shader_slab_mutex;
747
748 /* For detecting VM faults reported by dmesg. */
749 uint64_t dmesg_timestamp;
750
751 struct radv_device_extension_table enabled_extensions;
752
753 /* Whether the driver uses a global BO list. */
754 bool use_global_bo_list;
755
756 struct radv_bo_list bo_list;
757
758 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
759 int force_aniso;
760 };
761
762 struct radv_device_memory {
763 struct radeon_winsys_bo *bo;
764 /* for dedicated allocations */
765 struct radv_image *image;
766 struct radv_buffer *buffer;
767 uint32_t type_index;
768 VkDeviceSize map_size;
769 void * map;
770 void * user_ptr;
771 };
772
773
774 struct radv_descriptor_range {
775 uint64_t va;
776 uint32_t size;
777 };
778
779 struct radv_descriptor_set {
780 const struct radv_descriptor_set_layout *layout;
781 uint32_t size;
782
783 struct radeon_winsys_bo *bo;
784 uint64_t va;
785 uint32_t *mapped_ptr;
786 struct radv_descriptor_range *dynamic_descriptors;
787
788 struct radeon_winsys_bo *descriptors[0];
789 };
790
791 struct radv_push_descriptor_set
792 {
793 struct radv_descriptor_set set;
794 uint32_t capacity;
795 };
796
797 struct radv_descriptor_pool_entry {
798 uint32_t offset;
799 uint32_t size;
800 struct radv_descriptor_set *set;
801 };
802
803 struct radv_descriptor_pool {
804 struct radeon_winsys_bo *bo;
805 uint8_t *mapped_ptr;
806 uint64_t current_offset;
807 uint64_t size;
808
809 uint8_t *host_memory_base;
810 uint8_t *host_memory_ptr;
811 uint8_t *host_memory_end;
812
813 uint32_t entry_count;
814 uint32_t max_entry_count;
815 struct radv_descriptor_pool_entry entries[0];
816 };
817
818 struct radv_descriptor_update_template_entry {
819 VkDescriptorType descriptor_type;
820
821 /* The number of descriptors to update */
822 uint32_t descriptor_count;
823
824 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
825 uint32_t dst_offset;
826
827 /* In dwords. Not valid/used for dynamic descriptors */
828 uint32_t dst_stride;
829
830 uint32_t buffer_offset;
831
832 /* Only valid for combined image samplers and samplers */
833 uint8_t has_sampler;
834 uint8_t sampler_offset;
835
836 /* In bytes */
837 size_t src_offset;
838 size_t src_stride;
839
840 /* For push descriptors */
841 const uint32_t *immutable_samplers;
842 };
843
844 struct radv_descriptor_update_template {
845 uint32_t entry_count;
846 VkPipelineBindPoint bind_point;
847 struct radv_descriptor_update_template_entry entry[0];
848 };
849
850 struct radv_buffer {
851 VkDeviceSize size;
852
853 VkBufferUsageFlags usage;
854 VkBufferCreateFlags flags;
855
856 /* Set when bound */
857 struct radeon_winsys_bo * bo;
858 VkDeviceSize offset;
859
860 bool shareable;
861 };
862
863 enum radv_dynamic_state_bits {
864 RADV_DYNAMIC_VIEWPORT = 1 << 0,
865 RADV_DYNAMIC_SCISSOR = 1 << 1,
866 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
867 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
868 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
869 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
870 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
871 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
872 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
873 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
874 RADV_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
875 RADV_DYNAMIC_ALL = (1 << 11) - 1,
876 };
877
878 enum radv_cmd_dirty_bits {
879 /* Keep the dynamic state dirty bits in sync with
880 * enum radv_dynamic_state_bits */
881 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
882 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
883 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
884 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
885 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
886 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
887 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
888 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
889 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
890 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
891 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
892 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 11) - 1,
893 RADV_CMD_DIRTY_PIPELINE = 1 << 11,
894 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 12,
895 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 13,
896 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 14,
897 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 15,
898 };
899
900 enum radv_cmd_flush_bits {
901 /* Instruction cache. */
902 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
903 /* Scalar L1 cache. */
904 RADV_CMD_FLAG_INV_SCACHE = 1 << 1,
905 /* Vector L1 cache. */
906 RADV_CMD_FLAG_INV_VCACHE = 1 << 2,
907 /* L2 cache + L2 metadata cache writeback & invalidate.
908 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
909 RADV_CMD_FLAG_INV_L2 = 1 << 3,
910 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
911 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
912 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
913 RADV_CMD_FLAG_WB_L2 = 1 << 4,
914 /* Framebuffer caches */
915 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
916 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
917 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
918 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
919 /* Engine synchronization. */
920 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
921 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
922 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
923 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
924 /* Pipeline query controls. */
925 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
926 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
927 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
928
929 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
930 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
931 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
932 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
933 };
934
935 struct radv_vertex_binding {
936 struct radv_buffer * buffer;
937 VkDeviceSize offset;
938 };
939
940 struct radv_streamout_binding {
941 struct radv_buffer *buffer;
942 VkDeviceSize offset;
943 VkDeviceSize size;
944 };
945
946 struct radv_streamout_state {
947 /* Mask of bound streamout buffers. */
948 uint8_t enabled_mask;
949
950 /* External state that comes from the last vertex stage, it must be
951 * set explicitely when binding a new graphics pipeline.
952 */
953 uint16_t stride_in_dw[MAX_SO_BUFFERS];
954 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
955
956 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
957 uint32_t hw_enabled_mask;
958
959 /* State of VGT_STRMOUT_(CONFIG|EN) */
960 bool streamout_enabled;
961 };
962
963 struct radv_viewport_state {
964 uint32_t count;
965 VkViewport viewports[MAX_VIEWPORTS];
966 };
967
968 struct radv_scissor_state {
969 uint32_t count;
970 VkRect2D scissors[MAX_SCISSORS];
971 };
972
973 struct radv_discard_rectangle_state {
974 uint32_t count;
975 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
976 };
977
978 struct radv_sample_locations_state {
979 VkSampleCountFlagBits per_pixel;
980 VkExtent2D grid_size;
981 uint32_t count;
982 VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
983 };
984
985 struct radv_dynamic_state {
986 /**
987 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
988 * Defines the set of saved dynamic state.
989 */
990 uint32_t mask;
991
992 struct radv_viewport_state viewport;
993
994 struct radv_scissor_state scissor;
995
996 float line_width;
997
998 struct {
999 float bias;
1000 float clamp;
1001 float slope;
1002 } depth_bias;
1003
1004 float blend_constants[4];
1005
1006 struct {
1007 float min;
1008 float max;
1009 } depth_bounds;
1010
1011 struct {
1012 uint32_t front;
1013 uint32_t back;
1014 } stencil_compare_mask;
1015
1016 struct {
1017 uint32_t front;
1018 uint32_t back;
1019 } stencil_write_mask;
1020
1021 struct {
1022 uint32_t front;
1023 uint32_t back;
1024 } stencil_reference;
1025
1026 struct radv_discard_rectangle_state discard_rectangle;
1027
1028 struct radv_sample_locations_state sample_location;
1029 };
1030
1031 extern const struct radv_dynamic_state default_dynamic_state;
1032
1033 const char *
1034 radv_get_debug_option_name(int id);
1035
1036 const char *
1037 radv_get_perftest_option_name(int id);
1038
1039 /**
1040 * Attachment state when recording a renderpass instance.
1041 *
1042 * The clear value is valid only if there exists a pending clear.
1043 */
1044 struct radv_attachment_state {
1045 VkImageAspectFlags pending_clear_aspects;
1046 uint32_t cleared_views;
1047 VkClearValue clear_value;
1048 VkImageLayout current_layout;
1049 struct radv_sample_locations_state sample_location;
1050 };
1051
1052 struct radv_descriptor_state {
1053 struct radv_descriptor_set *sets[MAX_SETS];
1054 uint32_t dirty;
1055 uint32_t valid;
1056 struct radv_push_descriptor_set push_set;
1057 bool push_dirty;
1058 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1059 };
1060
1061 struct radv_subpass_sample_locs_state {
1062 uint32_t subpass_idx;
1063 struct radv_sample_locations_state sample_location;
1064 };
1065
1066 struct radv_cmd_state {
1067 /* Vertex descriptors */
1068 uint64_t vb_va;
1069 unsigned vb_size;
1070
1071 bool predicating;
1072 uint32_t dirty;
1073
1074 uint32_t prefetch_L2_mask;
1075
1076 struct radv_pipeline * pipeline;
1077 struct radv_pipeline * emitted_pipeline;
1078 struct radv_pipeline * compute_pipeline;
1079 struct radv_pipeline * emitted_compute_pipeline;
1080 struct radv_framebuffer * framebuffer;
1081 struct radv_render_pass * pass;
1082 const struct radv_subpass * subpass;
1083 struct radv_dynamic_state dynamic;
1084 struct radv_attachment_state * attachments;
1085 struct radv_streamout_state streamout;
1086 VkRect2D render_area;
1087
1088 uint32_t num_subpass_sample_locs;
1089 struct radv_subpass_sample_locs_state * subpass_sample_locs;
1090
1091 /* Index buffer */
1092 struct radv_buffer *index_buffer;
1093 uint64_t index_offset;
1094 uint32_t index_type;
1095 uint32_t max_index_count;
1096 uint64_t index_va;
1097 int32_t last_index_type;
1098
1099 int32_t last_primitive_reset_en;
1100 uint32_t last_primitive_reset_index;
1101 enum radv_cmd_flush_bits flush_bits;
1102 unsigned active_occlusion_queries;
1103 bool perfect_occlusion_queries_enabled;
1104 unsigned active_pipeline_queries;
1105 float offset_scale;
1106 uint32_t trace_id;
1107 uint32_t last_ia_multi_vgt_param;
1108
1109 uint32_t last_num_instances;
1110 uint32_t last_first_instance;
1111 uint32_t last_vertex_offset;
1112
1113 /* Whether CP DMA is busy/idle. */
1114 bool dma_is_busy;
1115
1116 /* Conditional rendering info. */
1117 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1118 uint64_t predication_va;
1119
1120 bool context_roll_without_scissor_emitted;
1121 };
1122
1123 struct radv_cmd_pool {
1124 VkAllocationCallbacks alloc;
1125 struct list_head cmd_buffers;
1126 struct list_head free_cmd_buffers;
1127 uint32_t queue_family_index;
1128 };
1129
1130 struct radv_cmd_buffer_upload {
1131 uint8_t *map;
1132 unsigned offset;
1133 uint64_t size;
1134 struct radeon_winsys_bo *upload_bo;
1135 struct list_head list;
1136 };
1137
1138 enum radv_cmd_buffer_status {
1139 RADV_CMD_BUFFER_STATUS_INVALID,
1140 RADV_CMD_BUFFER_STATUS_INITIAL,
1141 RADV_CMD_BUFFER_STATUS_RECORDING,
1142 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1143 RADV_CMD_BUFFER_STATUS_PENDING,
1144 };
1145
1146 struct radv_cmd_buffer {
1147 VK_LOADER_DATA _loader_data;
1148
1149 struct radv_device * device;
1150
1151 struct radv_cmd_pool * pool;
1152 struct list_head pool_link;
1153
1154 VkCommandBufferUsageFlags usage_flags;
1155 VkCommandBufferLevel level;
1156 enum radv_cmd_buffer_status status;
1157 struct radeon_cmdbuf *cs;
1158 struct radv_cmd_state state;
1159 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1160 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1161 uint32_t queue_family_index;
1162
1163 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1164 VkShaderStageFlags push_constant_stages;
1165 struct radv_descriptor_set meta_push_descriptors;
1166
1167 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1168
1169 struct radv_cmd_buffer_upload upload;
1170
1171 uint32_t scratch_size_needed;
1172 uint32_t compute_scratch_size_needed;
1173 uint32_t esgs_ring_size_needed;
1174 uint32_t gsvs_ring_size_needed;
1175 bool tess_rings_needed;
1176 bool sample_positions_needed;
1177
1178 VkResult record_result;
1179
1180 uint64_t gfx9_fence_va;
1181 uint32_t gfx9_fence_idx;
1182 uint64_t gfx9_eop_bug_va;
1183
1184 /**
1185 * Whether a query pool has been resetted and we have to flush caches.
1186 */
1187 bool pending_reset_query;
1188
1189 /**
1190 * Bitmask of pending active query flushes.
1191 */
1192 enum radv_cmd_flush_bits active_query_flush_bits;
1193 };
1194
1195 struct radv_image;
1196 struct radv_image_view;
1197
1198 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1199
1200 void si_emit_graphics(struct radv_physical_device *physical_device,
1201 struct radeon_cmdbuf *cs);
1202 void si_emit_compute(struct radv_physical_device *physical_device,
1203 struct radeon_cmdbuf *cs);
1204
1205 void cik_create_gfx_config(struct radv_device *device);
1206
1207 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1208 int count, const VkViewport *viewports);
1209 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1210 int count, const VkRect2D *scissors,
1211 const VkViewport *viewports, bool can_use_guardband);
1212 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1213 bool instanced_draw, bool indirect_draw,
1214 bool count_from_stream_output,
1215 uint32_t draw_vertex_count);
1216 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1217 enum chip_class chip_class,
1218 bool is_mec,
1219 unsigned event, unsigned event_flags,
1220 unsigned dst_sel, unsigned data_sel,
1221 uint64_t va,
1222 uint32_t new_fence,
1223 uint64_t gfx9_eop_bug_va);
1224
1225 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1226 uint32_t ref, uint32_t mask);
1227 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1228 enum chip_class chip_class,
1229 uint32_t *fence_ptr, uint64_t va,
1230 bool is_mec,
1231 enum radv_cmd_flush_bits flush_bits,
1232 uint64_t gfx9_eop_bug_va);
1233 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1234 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1235 bool inverted, uint64_t va);
1236 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1237 uint64_t src_va, uint64_t dest_va,
1238 uint64_t size);
1239 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1240 unsigned size);
1241 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1242 uint64_t size, unsigned value);
1243 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1244
1245 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1246 bool
1247 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1248 unsigned size,
1249 unsigned alignment,
1250 unsigned *out_offset,
1251 void **ptr);
1252 void
1253 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1254 const struct radv_subpass *subpass);
1255 bool
1256 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1257 unsigned size, unsigned alignmnet,
1258 const void *data, unsigned *out_offset);
1259
1260 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1261 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1262 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1263 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
1264 VkImageAspectFlags aspects,
1265 VkResolveModeFlagBitsKHR resolve_mode);
1266 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1267 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
1268 VkImageAspectFlags aspects,
1269 VkResolveModeFlagBitsKHR resolve_mode);
1270 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
1271 unsigned radv_get_default_max_sample_dist(int log_samples);
1272 void radv_device_init_msaa(struct radv_device *device);
1273
1274 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1275 struct radv_image *image,
1276 VkClearDepthStencilValue ds_clear_value,
1277 VkImageAspectFlags aspects);
1278
1279 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1280 const struct radv_image_view *iview,
1281 int cb_idx,
1282 uint32_t color_values[2]);
1283
1284 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1285 struct radv_image *image,
1286 const VkImageSubresourceRange *range, bool value);
1287
1288 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1289 struct radv_image *image,
1290 const VkImageSubresourceRange *range, bool value);
1291
1292 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1293 struct radeon_winsys_bo *bo,
1294 uint64_t offset, uint64_t size, uint32_t value);
1295 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1296 bool radv_get_memory_fd(struct radv_device *device,
1297 struct radv_device_memory *memory,
1298 int *pFD);
1299
1300 static inline void
1301 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1302 unsigned sh_offset, unsigned pointer_count,
1303 bool use_32bit_pointers)
1304 {
1305 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1306 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1307 }
1308
1309 static inline void
1310 radv_emit_shader_pointer_body(struct radv_device *device,
1311 struct radeon_cmdbuf *cs,
1312 uint64_t va, bool use_32bit_pointers)
1313 {
1314 radeon_emit(cs, va);
1315
1316 if (use_32bit_pointers) {
1317 assert(va == 0 ||
1318 (va >> 32) == device->physical_device->rad_info.address32_hi);
1319 } else {
1320 radeon_emit(cs, va >> 32);
1321 }
1322 }
1323
1324 static inline void
1325 radv_emit_shader_pointer(struct radv_device *device,
1326 struct radeon_cmdbuf *cs,
1327 uint32_t sh_offset, uint64_t va, bool global)
1328 {
1329 bool use_32bit_pointers = !global;
1330
1331 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1332 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1333 }
1334
1335 static inline struct radv_descriptor_state *
1336 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1337 VkPipelineBindPoint bind_point)
1338 {
1339 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1340 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1341 return &cmd_buffer->descriptors[bind_point];
1342 }
1343
1344 /*
1345 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1346 *
1347 * Limitations: Can't call normal dispatch functions without binding or rebinding
1348 * the compute pipeline.
1349 */
1350 void radv_unaligned_dispatch(
1351 struct radv_cmd_buffer *cmd_buffer,
1352 uint32_t x,
1353 uint32_t y,
1354 uint32_t z);
1355
1356 struct radv_event {
1357 struct radeon_winsys_bo *bo;
1358 uint64_t *map;
1359 };
1360
1361 struct radv_shader_module;
1362
1363 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1364 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1365 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1366 #define RADV_HASH_SHADER_NO_NGG (1 << 3)
1367
1368 void
1369 radv_hash_shaders(unsigned char *hash,
1370 const VkPipelineShaderStageCreateInfo **stages,
1371 const struct radv_pipeline_layout *layout,
1372 const struct radv_pipeline_key *key,
1373 uint32_t flags);
1374
1375 static inline gl_shader_stage
1376 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1377 {
1378 assert(__builtin_popcount(vk_stage) == 1);
1379 return ffs(vk_stage) - 1;
1380 }
1381
1382 static inline VkShaderStageFlagBits
1383 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1384 {
1385 return (1 << mesa_stage);
1386 }
1387
1388 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1389
1390 #define radv_foreach_stage(stage, stage_bits) \
1391 for (gl_shader_stage stage, \
1392 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1393 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1394 __tmp &= ~(1 << (stage)))
1395
1396 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1397 unsigned radv_format_meta_fs_key(VkFormat format);
1398
1399 struct radv_multisample_state {
1400 uint32_t db_eqaa;
1401 uint32_t pa_sc_line_cntl;
1402 uint32_t pa_sc_mode_cntl_0;
1403 uint32_t pa_sc_mode_cntl_1;
1404 uint32_t pa_sc_aa_config;
1405 uint32_t pa_sc_aa_mask[2];
1406 unsigned num_samples;
1407 };
1408
1409 struct radv_prim_vertex_count {
1410 uint8_t min;
1411 uint8_t incr;
1412 };
1413
1414 struct radv_vertex_elements_info {
1415 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1416 };
1417
1418 struct radv_ia_multi_vgt_param_helpers {
1419 uint32_t base;
1420 bool partial_es_wave;
1421 uint8_t primgroup_size;
1422 bool wd_switch_on_eop;
1423 bool ia_switch_on_eoi;
1424 bool partial_vs_wave;
1425 };
1426
1427 struct radv_binning_state {
1428 uint32_t pa_sc_binner_cntl_0;
1429 uint32_t db_dfsm_control;
1430 };
1431
1432 #define SI_GS_PER_ES 128
1433
1434 struct radv_pipeline {
1435 struct radv_device * device;
1436 struct radv_dynamic_state dynamic_state;
1437
1438 struct radv_pipeline_layout * layout;
1439
1440 bool need_indirect_descriptor_sets;
1441 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1442 struct radv_shader_variant *gs_copy_shader;
1443 VkShaderStageFlags active_stages;
1444
1445 struct radeon_cmdbuf cs;
1446 uint32_t ctx_cs_hash;
1447 struct radeon_cmdbuf ctx_cs;
1448
1449 struct radv_vertex_elements_info vertex_elements;
1450
1451 uint32_t binding_stride[MAX_VBS];
1452 uint8_t num_vertex_bindings;
1453
1454 uint32_t user_data_0[MESA_SHADER_STAGES];
1455 union {
1456 struct {
1457 struct radv_multisample_state ms;
1458 struct radv_binning_state binning;
1459 uint32_t spi_baryc_cntl;
1460 bool prim_restart_enable;
1461 unsigned esgs_ring_size;
1462 unsigned gsvs_ring_size;
1463 uint32_t vtx_base_sgpr;
1464 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1465 uint8_t vtx_emit_num;
1466 struct radv_prim_vertex_count prim_vertex_count;
1467 bool can_use_guardband;
1468 uint32_t needed_dynamic_state;
1469 bool disable_out_of_order_rast_for_occlusion;
1470
1471 /* Used for rbplus */
1472 uint32_t col_format;
1473 uint32_t cb_target_mask;
1474 } graphics;
1475 };
1476
1477 unsigned max_waves;
1478 unsigned scratch_bytes_per_wave;
1479
1480 /* Not NULL if graphics pipeline uses streamout. */
1481 struct radv_shader_variant *streamout_shader;
1482 };
1483
1484 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1485 {
1486 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1487 }
1488
1489 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1490 {
1491 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1492 }
1493
1494 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline);
1495
1496 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline);
1497
1498 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1499 gl_shader_stage stage,
1500 int idx);
1501
1502 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1503 gl_shader_stage stage);
1504
1505 struct radv_graphics_pipeline_create_info {
1506 bool use_rectlist;
1507 bool db_depth_clear;
1508 bool db_stencil_clear;
1509 bool db_depth_disable_expclear;
1510 bool db_stencil_disable_expclear;
1511 bool db_flush_depth_inplace;
1512 bool db_flush_stencil_inplace;
1513 bool db_resummarize;
1514 uint32_t custom_blend_mode;
1515 };
1516
1517 VkResult
1518 radv_graphics_pipeline_create(VkDevice device,
1519 VkPipelineCache cache,
1520 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1521 const struct radv_graphics_pipeline_create_info *extra,
1522 const VkAllocationCallbacks *alloc,
1523 VkPipeline *pPipeline);
1524
1525 struct vk_format_description;
1526 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1527 int first_non_void);
1528 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1529 int first_non_void);
1530 bool radv_is_buffer_format_supported(VkFormat format, bool *scaled);
1531 uint32_t radv_translate_colorformat(VkFormat format);
1532 uint32_t radv_translate_color_numformat(VkFormat format,
1533 const struct vk_format_description *desc,
1534 int first_non_void);
1535 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1536 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1537 uint32_t radv_translate_dbformat(VkFormat format);
1538 uint32_t radv_translate_tex_dataformat(VkFormat format,
1539 const struct vk_format_description *desc,
1540 int first_non_void);
1541 uint32_t radv_translate_tex_numformat(VkFormat format,
1542 const struct vk_format_description *desc,
1543 int first_non_void);
1544 bool radv_format_pack_clear_color(VkFormat format,
1545 uint32_t clear_vals[2],
1546 VkClearColorValue *value);
1547 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1548 bool radv_dcc_formats_compatible(VkFormat format1,
1549 VkFormat format2);
1550 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
1551
1552 struct radv_image_plane {
1553 VkFormat format;
1554 struct radeon_surf surface;
1555 uint64_t offset;
1556 };
1557
1558 struct radv_image {
1559 VkImageType type;
1560 /* The original VkFormat provided by the client. This may not match any
1561 * of the actual surface formats.
1562 */
1563 VkFormat vk_format;
1564 VkImageAspectFlags aspects;
1565 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1566 struct ac_surf_info info;
1567 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1568 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1569
1570 VkDeviceSize size;
1571 uint32_t alignment;
1572
1573 unsigned queue_family_mask;
1574 bool exclusive;
1575 bool shareable;
1576
1577 /* Set when bound */
1578 struct radeon_winsys_bo *bo;
1579 VkDeviceSize offset;
1580 uint64_t dcc_offset;
1581 uint64_t htile_offset;
1582 bool tc_compatible_htile;
1583 bool tc_compatible_cmask;
1584
1585 uint64_t cmask_offset;
1586 uint64_t fmask_offset;
1587 uint64_t clear_value_offset;
1588 uint64_t fce_pred_offset;
1589 uint64_t dcc_pred_offset;
1590
1591 /*
1592 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1593 * stored at this offset is UINT_MAX, the driver will emit
1594 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1595 * SET_CONTEXT_REG packet.
1596 */
1597 uint64_t tc_compat_zrange_offset;
1598
1599 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1600 VkDeviceMemory owned_memory;
1601
1602 unsigned plane_count;
1603 struct radv_image_plane planes[0];
1604 };
1605
1606 /* Whether the image has a htile that is known consistent with the contents of
1607 * the image. */
1608 bool radv_layout_has_htile(const struct radv_image *image,
1609 VkImageLayout layout,
1610 unsigned queue_mask);
1611
1612 /* Whether the image has a htile that is known consistent with the contents of
1613 * the image and is allowed to be in compressed form.
1614 *
1615 * If this is false reads that don't use the htile should be able to return
1616 * correct results.
1617 */
1618 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1619 VkImageLayout layout,
1620 unsigned queue_mask);
1621
1622 bool radv_layout_can_fast_clear(const struct radv_image *image,
1623 VkImageLayout layout,
1624 unsigned queue_mask);
1625
1626 bool radv_layout_dcc_compressed(const struct radv_image *image,
1627 VkImageLayout layout,
1628 unsigned queue_mask);
1629
1630 /**
1631 * Return whether the image has CMASK metadata for color surfaces.
1632 */
1633 static inline bool
1634 radv_image_has_cmask(const struct radv_image *image)
1635 {
1636 return image->planes[0].surface.cmask_size;
1637 }
1638
1639 /**
1640 * Return whether the image has FMASK metadata for color surfaces.
1641 */
1642 static inline bool
1643 radv_image_has_fmask(const struct radv_image *image)
1644 {
1645 return image->planes[0].surface.fmask_size;
1646 }
1647
1648 /**
1649 * Return whether the image has DCC metadata for color surfaces.
1650 */
1651 static inline bool
1652 radv_image_has_dcc(const struct radv_image *image)
1653 {
1654 return image->planes[0].surface.dcc_size;
1655 }
1656
1657 /**
1658 * Return whether the image is TC-compatible CMASK.
1659 */
1660 static inline bool
1661 radv_image_is_tc_compat_cmask(const struct radv_image *image)
1662 {
1663 return radv_image_has_fmask(image) && image->tc_compatible_cmask;
1664 }
1665
1666 /**
1667 * Return whether DCC metadata is enabled for a level.
1668 */
1669 static inline bool
1670 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1671 {
1672 return radv_image_has_dcc(image) &&
1673 level < image->planes[0].surface.num_dcc_levels;
1674 }
1675
1676 /**
1677 * Return whether the image has CB metadata.
1678 */
1679 static inline bool
1680 radv_image_has_CB_metadata(const struct radv_image *image)
1681 {
1682 return radv_image_has_cmask(image) ||
1683 radv_image_has_fmask(image) ||
1684 radv_image_has_dcc(image);
1685 }
1686
1687 /**
1688 * Return whether the image has HTILE metadata for depth surfaces.
1689 */
1690 static inline bool
1691 radv_image_has_htile(const struct radv_image *image)
1692 {
1693 return image->planes[0].surface.htile_size;
1694 }
1695
1696 /**
1697 * Return whether HTILE metadata is enabled for a level.
1698 */
1699 static inline bool
1700 radv_htile_enabled(const struct radv_image *image, unsigned level)
1701 {
1702 return radv_image_has_htile(image) && level == 0;
1703 }
1704
1705 /**
1706 * Return whether the image is TC-compatible HTILE.
1707 */
1708 static inline bool
1709 radv_image_is_tc_compat_htile(const struct radv_image *image)
1710 {
1711 return radv_image_has_htile(image) && image->tc_compatible_htile;
1712 }
1713
1714 static inline uint64_t
1715 radv_image_get_fast_clear_va(const struct radv_image *image,
1716 uint32_t base_level)
1717 {
1718 uint64_t va = radv_buffer_get_va(image->bo);
1719 va += image->offset + image->clear_value_offset + base_level * 8;
1720 return va;
1721 }
1722
1723 static inline uint64_t
1724 radv_image_get_fce_pred_va(const struct radv_image *image,
1725 uint32_t base_level)
1726 {
1727 uint64_t va = radv_buffer_get_va(image->bo);
1728 va += image->offset + image->fce_pred_offset + base_level * 8;
1729 return va;
1730 }
1731
1732 static inline uint64_t
1733 radv_image_get_dcc_pred_va(const struct radv_image *image,
1734 uint32_t base_level)
1735 {
1736 uint64_t va = radv_buffer_get_va(image->bo);
1737 va += image->offset + image->dcc_pred_offset + base_level * 8;
1738 return va;
1739 }
1740
1741 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1742
1743 static inline uint32_t
1744 radv_get_layerCount(const struct radv_image *image,
1745 const VkImageSubresourceRange *range)
1746 {
1747 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1748 image->info.array_size - range->baseArrayLayer : range->layerCount;
1749 }
1750
1751 static inline uint32_t
1752 radv_get_levelCount(const struct radv_image *image,
1753 const VkImageSubresourceRange *range)
1754 {
1755 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1756 image->info.levels - range->baseMipLevel : range->levelCount;
1757 }
1758
1759 struct radeon_bo_metadata;
1760 void
1761 radv_init_metadata(struct radv_device *device,
1762 struct radv_image *image,
1763 struct radeon_bo_metadata *metadata);
1764
1765 void
1766 radv_image_override_offset_stride(struct radv_device *device,
1767 struct radv_image *image,
1768 uint64_t offset, uint32_t stride);
1769
1770 union radv_descriptor {
1771 struct {
1772 uint32_t plane0_descriptor[8];
1773 uint32_t fmask_descriptor[8];
1774 };
1775 struct {
1776 uint32_t plane_descriptors[3][8];
1777 };
1778 };
1779
1780 struct radv_image_view {
1781 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1782 struct radeon_winsys_bo *bo;
1783
1784 VkImageViewType type;
1785 VkImageAspectFlags aspect_mask;
1786 VkFormat vk_format;
1787 unsigned plane_id;
1788 bool multiple_planes;
1789 uint32_t base_layer;
1790 uint32_t layer_count;
1791 uint32_t base_mip;
1792 uint32_t level_count;
1793 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1794
1795 union radv_descriptor descriptor;
1796
1797 /* Descriptor for use as a storage image as opposed to a sampled image.
1798 * This has a few differences for cube maps (e.g. type).
1799 */
1800 union radv_descriptor storage_descriptor;
1801 };
1802
1803 struct radv_image_create_info {
1804 const VkImageCreateInfo *vk_info;
1805 bool scanout;
1806 bool no_metadata_planes;
1807 const struct radeon_bo_metadata *bo_metadata;
1808 };
1809
1810 VkResult radv_image_create(VkDevice _device,
1811 const struct radv_image_create_info *info,
1812 const VkAllocationCallbacks* alloc,
1813 VkImage *pImage);
1814
1815 VkResult
1816 radv_image_from_gralloc(VkDevice device_h,
1817 const VkImageCreateInfo *base_info,
1818 const VkNativeBufferANDROID *gralloc_info,
1819 const VkAllocationCallbacks *alloc,
1820 VkImage *out_image_h);
1821
1822 void radv_image_view_init(struct radv_image_view *view,
1823 struct radv_device *device,
1824 const VkImageViewCreateInfo* pCreateInfo);
1825
1826 VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
1827
1828 struct radv_sampler_ycbcr_conversion {
1829 VkFormat format;
1830 VkSamplerYcbcrModelConversion ycbcr_model;
1831 VkSamplerYcbcrRange ycbcr_range;
1832 VkComponentMapping components;
1833 VkChromaLocation chroma_offsets[2];
1834 VkFilter chroma_filter;
1835 };
1836
1837 struct radv_buffer_view {
1838 struct radeon_winsys_bo *bo;
1839 VkFormat vk_format;
1840 uint64_t range; /**< VkBufferViewCreateInfo::range */
1841 uint32_t state[4];
1842 };
1843 void radv_buffer_view_init(struct radv_buffer_view *view,
1844 struct radv_device *device,
1845 const VkBufferViewCreateInfo* pCreateInfo);
1846
1847 static inline struct VkExtent3D
1848 radv_sanitize_image_extent(const VkImageType imageType,
1849 const struct VkExtent3D imageExtent)
1850 {
1851 switch (imageType) {
1852 case VK_IMAGE_TYPE_1D:
1853 return (VkExtent3D) { imageExtent.width, 1, 1 };
1854 case VK_IMAGE_TYPE_2D:
1855 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1856 case VK_IMAGE_TYPE_3D:
1857 return imageExtent;
1858 default:
1859 unreachable("invalid image type");
1860 }
1861 }
1862
1863 static inline struct VkOffset3D
1864 radv_sanitize_image_offset(const VkImageType imageType,
1865 const struct VkOffset3D imageOffset)
1866 {
1867 switch (imageType) {
1868 case VK_IMAGE_TYPE_1D:
1869 return (VkOffset3D) { imageOffset.x, 0, 0 };
1870 case VK_IMAGE_TYPE_2D:
1871 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1872 case VK_IMAGE_TYPE_3D:
1873 return imageOffset;
1874 default:
1875 unreachable("invalid image type");
1876 }
1877 }
1878
1879 static inline bool
1880 radv_image_extent_compare(const struct radv_image *image,
1881 const VkExtent3D *extent)
1882 {
1883 if (extent->width != image->info.width ||
1884 extent->height != image->info.height ||
1885 extent->depth != image->info.depth)
1886 return false;
1887 return true;
1888 }
1889
1890 struct radv_sampler {
1891 uint32_t state[4];
1892 struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
1893 };
1894
1895 struct radv_color_buffer_info {
1896 uint64_t cb_color_base;
1897 uint64_t cb_color_cmask;
1898 uint64_t cb_color_fmask;
1899 uint64_t cb_dcc_base;
1900 uint32_t cb_color_slice;
1901 uint32_t cb_color_view;
1902 uint32_t cb_color_info;
1903 uint32_t cb_color_attrib;
1904 uint32_t cb_color_attrib2; /* GFX9 and later */
1905 uint32_t cb_color_attrib3; /* GFX10 and later */
1906 uint32_t cb_dcc_control;
1907 uint32_t cb_color_cmask_slice;
1908 uint32_t cb_color_fmask_slice;
1909 union {
1910 uint32_t cb_color_pitch; // GFX6-GFX8
1911 uint32_t cb_mrt_epitch; // GFX9+
1912 };
1913 };
1914
1915 struct radv_ds_buffer_info {
1916 uint64_t db_z_read_base;
1917 uint64_t db_stencil_read_base;
1918 uint64_t db_z_write_base;
1919 uint64_t db_stencil_write_base;
1920 uint64_t db_htile_data_base;
1921 uint32_t db_depth_info;
1922 uint32_t db_z_info;
1923 uint32_t db_stencil_info;
1924 uint32_t db_depth_view;
1925 uint32_t db_depth_size;
1926 uint32_t db_depth_slice;
1927 uint32_t db_htile_surface;
1928 uint32_t pa_su_poly_offset_db_fmt_cntl;
1929 uint32_t db_z_info2; /* GFX9 only */
1930 uint32_t db_stencil_info2; /* GFX9 only */
1931 float offset_scale;
1932 };
1933
1934 struct radv_attachment_info {
1935 union {
1936 struct radv_color_buffer_info cb;
1937 struct radv_ds_buffer_info ds;
1938 };
1939 struct radv_image_view *attachment;
1940 };
1941
1942 struct radv_framebuffer {
1943 uint32_t width;
1944 uint32_t height;
1945 uint32_t layers;
1946
1947 uint32_t attachment_count;
1948 struct radv_attachment_info attachments[0];
1949 };
1950
1951 struct radv_subpass_barrier {
1952 VkPipelineStageFlags src_stage_mask;
1953 VkAccessFlags src_access_mask;
1954 VkAccessFlags dst_access_mask;
1955 };
1956
1957 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1958 const struct radv_subpass_barrier *barrier);
1959
1960 struct radv_subpass_attachment {
1961 uint32_t attachment;
1962 VkImageLayout layout;
1963 };
1964
1965 struct radv_subpass {
1966 uint32_t attachment_count;
1967 struct radv_subpass_attachment * attachments;
1968
1969 uint32_t input_count;
1970 uint32_t color_count;
1971 struct radv_subpass_attachment * input_attachments;
1972 struct radv_subpass_attachment * color_attachments;
1973 struct radv_subpass_attachment * resolve_attachments;
1974 struct radv_subpass_attachment * depth_stencil_attachment;
1975 struct radv_subpass_attachment * ds_resolve_attachment;
1976 VkResolveModeFlagBitsKHR depth_resolve_mode;
1977 VkResolveModeFlagBitsKHR stencil_resolve_mode;
1978
1979 /** Subpass has at least one color resolve attachment */
1980 bool has_color_resolve;
1981
1982 /** Subpass has at least one color attachment */
1983 bool has_color_att;
1984
1985 struct radv_subpass_barrier start_barrier;
1986
1987 uint32_t view_mask;
1988 VkSampleCountFlagBits max_sample_count;
1989 };
1990
1991 uint32_t
1992 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer);
1993
1994 struct radv_render_pass_attachment {
1995 VkFormat format;
1996 uint32_t samples;
1997 VkAttachmentLoadOp load_op;
1998 VkAttachmentLoadOp stencil_load_op;
1999 VkImageLayout initial_layout;
2000 VkImageLayout final_layout;
2001
2002 /* The subpass id in which the attachment will be used first/last. */
2003 uint32_t first_subpass_idx;
2004 uint32_t last_subpass_idx;
2005 };
2006
2007 struct radv_render_pass {
2008 uint32_t attachment_count;
2009 uint32_t subpass_count;
2010 struct radv_subpass_attachment * subpass_attachments;
2011 struct radv_render_pass_attachment * attachments;
2012 struct radv_subpass_barrier end_barrier;
2013 struct radv_subpass subpasses[0];
2014 };
2015
2016 VkResult radv_device_init_meta(struct radv_device *device);
2017 void radv_device_finish_meta(struct radv_device *device);
2018
2019 struct radv_query_pool {
2020 struct radeon_winsys_bo *bo;
2021 uint32_t stride;
2022 uint32_t availability_offset;
2023 uint64_t size;
2024 char *ptr;
2025 VkQueryType type;
2026 uint32_t pipeline_stats_mask;
2027 };
2028
2029 struct radv_semaphore {
2030 /* use a winsys sem for non-exportable */
2031 struct radeon_winsys_sem *sem;
2032 uint32_t syncobj;
2033 uint32_t temp_syncobj;
2034 };
2035
2036 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2037 VkPipelineBindPoint bind_point,
2038 struct radv_descriptor_set *set,
2039 unsigned idx);
2040
2041 void
2042 radv_update_descriptor_sets(struct radv_device *device,
2043 struct radv_cmd_buffer *cmd_buffer,
2044 VkDescriptorSet overrideSet,
2045 uint32_t descriptorWriteCount,
2046 const VkWriteDescriptorSet *pDescriptorWrites,
2047 uint32_t descriptorCopyCount,
2048 const VkCopyDescriptorSet *pDescriptorCopies);
2049
2050 void
2051 radv_update_descriptor_set_with_template(struct radv_device *device,
2052 struct radv_cmd_buffer *cmd_buffer,
2053 struct radv_descriptor_set *set,
2054 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2055 const void *pData);
2056
2057 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2058 VkPipelineBindPoint pipelineBindPoint,
2059 VkPipelineLayout _layout,
2060 uint32_t set,
2061 uint32_t descriptorWriteCount,
2062 const VkWriteDescriptorSet *pDescriptorWrites);
2063
2064 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2065 struct radv_image *image,
2066 const VkImageSubresourceRange *range, uint32_t value);
2067
2068 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
2069 struct radv_image *image,
2070 const VkImageSubresourceRange *range);
2071
2072 struct radv_fence {
2073 struct radeon_winsys_fence *fence;
2074 struct wsi_fence *fence_wsi;
2075
2076 uint32_t syncobj;
2077 uint32_t temp_syncobj;
2078 };
2079
2080 /* radv_nir_to_llvm.c */
2081 struct radv_shader_variant_info;
2082 struct radv_nir_compiler_options;
2083
2084 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
2085 struct nir_shader *geom_shader,
2086 struct radv_shader_binary **rbinary,
2087 struct radv_shader_variant_info *shader_info,
2088 const struct radv_nir_compiler_options *option);
2089
2090 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
2091 struct radv_shader_binary **rbinary,
2092 struct radv_shader_variant_info *shader_info,
2093 struct nir_shader *const *nir,
2094 int nir_count,
2095 const struct radv_nir_compiler_options *options);
2096
2097 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
2098 gl_shader_stage stage,
2099 const struct nir_shader *nir);
2100
2101 /* radv_shader_info.h */
2102 struct radv_shader_info;
2103
2104 void radv_nir_shader_info_pass(const struct nir_shader *nir,
2105 const struct radv_nir_compiler_options *options,
2106 struct radv_shader_info *info);
2107
2108 void radv_nir_shader_info_init(struct radv_shader_info *info);
2109
2110 struct radeon_winsys_sem;
2111
2112 uint64_t radv_get_current_time(void);
2113
2114 static inline uint32_t
2115 si_conv_gl_prim_to_vertices(unsigned gl_prim)
2116 {
2117 switch (gl_prim) {
2118 case 0: /* GL_POINTS */
2119 return 1;
2120 case 1: /* GL_LINES */
2121 case 3: /* GL_LINE_STRIP */
2122 return 2;
2123 case 4: /* GL_TRIANGLES */
2124 case 5: /* GL_TRIANGLE_STRIP */
2125 return 3;
2126 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2127 return 4;
2128 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2129 return 6;
2130 case 7: /* GL_QUADS */
2131 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2132 default:
2133 assert(0);
2134 return 0;
2135 }
2136 }
2137
2138 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2139 \
2140 static inline struct __radv_type * \
2141 __radv_type ## _from_handle(__VkType _handle) \
2142 { \
2143 return (struct __radv_type *) _handle; \
2144 } \
2145 \
2146 static inline __VkType \
2147 __radv_type ## _to_handle(struct __radv_type *_obj) \
2148 { \
2149 return (__VkType) _obj; \
2150 }
2151
2152 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2153 \
2154 static inline struct __radv_type * \
2155 __radv_type ## _from_handle(__VkType _handle) \
2156 { \
2157 return (struct __radv_type *)(uintptr_t) _handle; \
2158 } \
2159 \
2160 static inline __VkType \
2161 __radv_type ## _to_handle(struct __radv_type *_obj) \
2162 { \
2163 return (__VkType)(uintptr_t) _obj; \
2164 }
2165
2166 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2167 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2168
2169 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
2170 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
2171 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
2172 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
2173 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
2174
2175 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
2176 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
2177 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
2178 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
2179 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
2180 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
2181 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
2182 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
2183 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
2184 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
2185 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
2186 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
2187 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
2188 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
2189 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
2190 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2191 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2192 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2193 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2194 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
2195 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2196 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2197
2198 #endif /* RADV_PRIVATE_H */