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radv: add has_scissor_bug for Vega10 and Raven
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
59
60 #include <llvm-c/TargetMachine.h>
61
62 /* Pre-declarations needed for WSI entrypoints */
63 struct wl_surface;
64 struct wl_display;
65 typedef struct xcb_connection_t xcb_connection_t;
66 typedef uint32_t xcb_visualid_t;
67 typedef uint32_t xcb_window_t;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "radv_entrypoints.h"
74
75 #include "wsi_common.h"
76
77 #define ATI_VENDOR_ID 0x1002
78
79 #define MAX_VBS 32
80 #define MAX_VERTEX_ATTRIBS 32
81 #define MAX_RTS 8
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
90 #define MAX_VIEWS 8
91
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
93
94 enum radv_mem_heap {
95 RADV_MEM_HEAP_VRAM,
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
97 RADV_MEM_HEAP_GTT,
98 RADV_MEM_HEAP_COUNT
99 };
100
101 enum radv_mem_type {
102 RADV_MEM_TYPE_VRAM,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
105 RADV_MEM_TYPE_GTT_CACHED,
106 RADV_MEM_TYPE_COUNT
107 };
108
109 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
110
111 static inline uint32_t
112 align_u32(uint32_t v, uint32_t a)
113 {
114 assert(a != 0 && a == (a & -a));
115 return (v + a - 1) & ~(a - 1);
116 }
117
118 static inline uint32_t
119 align_u32_npot(uint32_t v, uint32_t a)
120 {
121 return (v + a - 1) / a * a;
122 }
123
124 static inline uint64_t
125 align_u64(uint64_t v, uint64_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 static inline int32_t
132 align_i32(int32_t v, int32_t a)
133 {
134 assert(a != 0 && a == (a & -a));
135 return (v + a - 1) & ~(a - 1);
136 }
137
138 /** Alignment must be a power of 2. */
139 static inline bool
140 radv_is_aligned(uintmax_t n, uintmax_t a)
141 {
142 assert(a == (a & -a));
143 return (n & (a - 1)) == 0;
144 }
145
146 static inline uint32_t
147 round_up_u32(uint32_t v, uint32_t a)
148 {
149 return (v + a - 1) / a;
150 }
151
152 static inline uint64_t
153 round_up_u64(uint64_t v, uint64_t a)
154 {
155 return (v + a - 1) / a;
156 }
157
158 static inline uint32_t
159 radv_minify(uint32_t n, uint32_t levels)
160 {
161 if (unlikely(n == 0))
162 return 0;
163 else
164 return MAX2(n >> levels, 1);
165 }
166 static inline float
167 radv_clamp_f(float f, float min, float max)
168 {
169 assert(min < max);
170
171 if (f > max)
172 return max;
173 else if (f < min)
174 return min;
175 else
176 return f;
177 }
178
179 static inline bool
180 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
181 {
182 if (*inout_mask & clear_mask) {
183 *inout_mask &= ~clear_mask;
184 return true;
185 } else {
186 return false;
187 }
188 }
189
190 #define for_each_bit(b, dword) \
191 for (uint32_t __dword = (dword); \
192 (b) = __builtin_ffs(__dword) - 1, __dword; \
193 __dword &= ~(1 << (b)))
194
195 #define typed_memcpy(dest, src, count) ({ \
196 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
197 memcpy((dest), (src), (count) * sizeof(*(src))); \
198 })
199
200 /* Whenever we generate an error, pass it through this function. Useful for
201 * debugging, where we can break on it. Only call at error site, not when
202 * propagating errors. Might be useful to plug in a stack trace here.
203 */
204
205 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
206
207 #ifdef DEBUG
208 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
209 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
210 #else
211 #define vk_error(error) error
212 #define vk_errorf(error, format, ...) error
213 #endif
214
215 void __radv_finishme(const char *file, int line, const char *format, ...)
216 radv_printflike(3, 4);
217 void radv_loge(const char *format, ...) radv_printflike(1, 2);
218 void radv_loge_v(const char *format, va_list va);
219
220 /**
221 * Print a FINISHME message, including its source location.
222 */
223 #define radv_finishme(format, ...) \
224 do { \
225 static bool reported = false; \
226 if (!reported) { \
227 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
228 reported = true; \
229 } \
230 } while (0)
231
232 /* A non-fatal assert. Useful for debugging. */
233 #ifdef DEBUG
234 #define radv_assert(x) ({ \
235 if (unlikely(!(x))) \
236 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
237 })
238 #else
239 #define radv_assert(x)
240 #endif
241
242 #define stub_return(v) \
243 do { \
244 radv_finishme("stub %s", __func__); \
245 return (v); \
246 } while (0)
247
248 #define stub() \
249 do { \
250 radv_finishme("stub %s", __func__); \
251 return; \
252 } while (0)
253
254 void *radv_lookup_entrypoint(const char *name);
255
256 struct radv_physical_device {
257 VK_LOADER_DATA _loader_data;
258
259 struct radv_instance * instance;
260
261 struct radeon_winsys *ws;
262 struct radeon_info rad_info;
263 char path[20];
264 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
265 uint8_t driver_uuid[VK_UUID_SIZE];
266 uint8_t device_uuid[VK_UUID_SIZE];
267 uint8_t cache_uuid[VK_UUID_SIZE];
268
269 int local_fd;
270 struct wsi_device wsi_device;
271
272 bool has_rbplus; /* if RB+ register exist */
273 bool rbplus_allowed; /* if RB+ is allowed */
274 bool has_clear_state;
275 bool cpdma_prefetch_writes_memory;
276 bool has_scissor_bug;
277
278 /* This is the drivers on-disk cache used as a fallback as opposed to
279 * the pipeline cache defined by apps.
280 */
281 struct disk_cache * disk_cache;
282
283 VkPhysicalDeviceMemoryProperties memory_properties;
284 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
285 };
286
287 struct radv_instance {
288 VK_LOADER_DATA _loader_data;
289
290 VkAllocationCallbacks alloc;
291
292 uint32_t apiVersion;
293 int physicalDeviceCount;
294 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
295
296 uint64_t debug_flags;
297 uint64_t perftest_flags;
298 };
299
300 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
301 void radv_finish_wsi(struct radv_physical_device *physical_device);
302
303 bool radv_instance_extension_supported(const char *name);
304 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
305 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
306 const char *name);
307
308 struct cache_entry;
309
310 struct radv_pipeline_cache {
311 struct radv_device * device;
312 pthread_mutex_t mutex;
313
314 uint32_t total_size;
315 uint32_t table_size;
316 uint32_t kernel_count;
317 struct cache_entry ** hash_table;
318 bool modified;
319
320 VkAllocationCallbacks alloc;
321 };
322
323 struct radv_pipeline_key {
324 uint32_t instance_rate_inputs;
325 unsigned tess_input_vertices;
326 uint32_t col_format;
327 uint32_t is_int8;
328 uint32_t is_int10;
329 uint32_t multisample : 1;
330 uint32_t has_multiview_view_index : 1;
331 };
332
333 void
334 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
335 struct radv_device *device);
336 void
337 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
338 void
339 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
340 const void *data, size_t size);
341
342 struct radv_shader_variant;
343
344 bool
345 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
346 struct radv_pipeline_cache *cache,
347 const unsigned char *sha1,
348 struct radv_shader_variant **variants);
349
350 void
351 radv_pipeline_cache_insert_shaders(struct radv_device *device,
352 struct radv_pipeline_cache *cache,
353 const unsigned char *sha1,
354 struct radv_shader_variant **variants,
355 const void *const *codes,
356 const unsigned *code_sizes);
357
358 enum radv_blit_ds_layout {
359 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
360 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
361 RADV_BLIT_DS_LAYOUT_COUNT,
362 };
363
364 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
365 {
366 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
367 }
368
369 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
370 {
371 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
372 }
373
374 enum radv_meta_dst_layout {
375 RADV_META_DST_LAYOUT_GENERAL,
376 RADV_META_DST_LAYOUT_OPTIMAL,
377 RADV_META_DST_LAYOUT_COUNT,
378 };
379
380 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
381 {
382 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
383 }
384
385 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
386 {
387 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
388 }
389
390 struct radv_meta_state {
391 VkAllocationCallbacks alloc;
392
393 struct radv_pipeline_cache cache;
394
395 /**
396 * Use array element `i` for images with `2^i` samples.
397 */
398 struct {
399 VkRenderPass render_pass[NUM_META_FS_KEYS];
400 VkPipeline color_pipelines[NUM_META_FS_KEYS];
401
402 VkRenderPass depthstencil_rp;
403 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
404 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
405 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
406 } clear[1 + MAX_SAMPLES_LOG2];
407
408 VkPipelineLayout clear_color_p_layout;
409 VkPipelineLayout clear_depth_p_layout;
410 struct {
411 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
412
413 /** Pipeline that blits from a 1D image. */
414 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
415
416 /** Pipeline that blits from a 2D image. */
417 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
418
419 /** Pipeline that blits from a 3D image. */
420 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
421
422 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
423 VkPipeline depth_only_1d_pipeline;
424 VkPipeline depth_only_2d_pipeline;
425 VkPipeline depth_only_3d_pipeline;
426
427 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
428 VkPipeline stencil_only_1d_pipeline;
429 VkPipeline stencil_only_2d_pipeline;
430 VkPipeline stencil_only_3d_pipeline;
431 VkPipelineLayout pipeline_layout;
432 VkDescriptorSetLayout ds_layout;
433 } blit;
434
435 struct {
436 VkRenderPass render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
437
438 VkPipelineLayout p_layouts[3];
439 VkDescriptorSetLayout ds_layouts[3];
440 VkPipeline pipelines[3][NUM_META_FS_KEYS];
441
442 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
443 VkPipeline depth_only_pipeline[3];
444
445 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
446 VkPipeline stencil_only_pipeline[3];
447 } blit2d;
448
449 struct {
450 VkPipelineLayout img_p_layout;
451 VkDescriptorSetLayout img_ds_layout;
452 VkPipeline pipeline;
453 VkPipeline pipeline_3d;
454 } itob;
455 struct {
456 VkPipelineLayout img_p_layout;
457 VkDescriptorSetLayout img_ds_layout;
458 VkPipeline pipeline;
459 VkPipeline pipeline_3d;
460 } btoi;
461 struct {
462 VkPipelineLayout img_p_layout;
463 VkDescriptorSetLayout img_ds_layout;
464 VkPipeline pipeline;
465 VkPipeline pipeline_3d;
466 } itoi;
467 struct {
468 VkPipelineLayout img_p_layout;
469 VkDescriptorSetLayout img_ds_layout;
470 VkPipeline pipeline;
471 VkPipeline pipeline_3d;
472 } cleari;
473
474 struct {
475 VkPipelineLayout p_layout;
476 VkPipeline pipeline;
477 VkRenderPass pass;
478 } resolve;
479
480 struct {
481 VkDescriptorSetLayout ds_layout;
482 VkPipelineLayout p_layout;
483 struct {
484 VkPipeline pipeline;
485 VkPipeline i_pipeline;
486 VkPipeline srgb_pipeline;
487 } rc[MAX_SAMPLES_LOG2];
488 } resolve_compute;
489
490 struct {
491 VkDescriptorSetLayout ds_layout;
492 VkPipelineLayout p_layout;
493
494 struct {
495 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
496 VkPipeline pipeline[NUM_META_FS_KEYS];
497 } rc[MAX_SAMPLES_LOG2];
498 } resolve_fragment;
499
500 struct {
501 VkPipelineLayout p_layout;
502 VkPipeline decompress_pipeline;
503 VkPipeline resummarize_pipeline;
504 VkRenderPass pass;
505 } depth_decomp[1 + MAX_SAMPLES_LOG2];
506
507 struct {
508 VkPipelineLayout p_layout;
509 VkPipeline cmask_eliminate_pipeline;
510 VkPipeline fmask_decompress_pipeline;
511 VkPipeline dcc_decompress_pipeline;
512 VkRenderPass pass;
513
514 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
515 VkPipelineLayout dcc_decompress_compute_p_layout;
516 VkPipeline dcc_decompress_compute_pipeline;
517 } fast_clear_flush;
518
519 struct {
520 VkPipelineLayout fill_p_layout;
521 VkPipelineLayout copy_p_layout;
522 VkDescriptorSetLayout fill_ds_layout;
523 VkDescriptorSetLayout copy_ds_layout;
524 VkPipeline fill_pipeline;
525 VkPipeline copy_pipeline;
526 } buffer;
527
528 struct {
529 VkDescriptorSetLayout ds_layout;
530 VkPipelineLayout p_layout;
531 VkPipeline occlusion_query_pipeline;
532 VkPipeline pipeline_statistics_query_pipeline;
533 } query;
534 };
535
536 /* queue types */
537 #define RADV_QUEUE_GENERAL 0
538 #define RADV_QUEUE_COMPUTE 1
539 #define RADV_QUEUE_TRANSFER 2
540
541 #define RADV_MAX_QUEUE_FAMILIES 3
542
543 enum ring_type radv_queue_family_to_ring(int f);
544
545 struct radv_queue {
546 VK_LOADER_DATA _loader_data;
547 struct radv_device * device;
548 struct radeon_winsys_ctx *hw_ctx;
549 enum radeon_ctx_priority priority;
550 uint32_t queue_family_index;
551 int queue_idx;
552
553 uint32_t scratch_size;
554 uint32_t compute_scratch_size;
555 uint32_t esgs_ring_size;
556 uint32_t gsvs_ring_size;
557 bool has_tess_rings;
558 bool has_sample_positions;
559
560 struct radeon_winsys_bo *scratch_bo;
561 struct radeon_winsys_bo *descriptor_bo;
562 struct radeon_winsys_bo *compute_scratch_bo;
563 struct radeon_winsys_bo *esgs_ring_bo;
564 struct radeon_winsys_bo *gsvs_ring_bo;
565 struct radeon_winsys_bo *tess_factor_ring_bo;
566 struct radeon_winsys_bo *tess_offchip_ring_bo;
567 struct radeon_winsys_cs *initial_preamble_cs;
568 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
569 struct radeon_winsys_cs *continue_preamble_cs;
570 };
571
572 struct radv_device {
573 VK_LOADER_DATA _loader_data;
574
575 VkAllocationCallbacks alloc;
576
577 struct radv_instance * instance;
578 struct radeon_winsys *ws;
579
580 struct radv_meta_state meta_state;
581
582 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
583 int queue_count[RADV_MAX_QUEUE_FAMILIES];
584 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
585
586 bool llvm_supports_spill;
587 bool has_distributed_tess;
588 bool pbb_allowed;
589 bool dfsm_allowed;
590 uint32_t tess_offchip_block_dw_size;
591 uint32_t scratch_waves;
592 uint32_t dispatch_initiator;
593
594 uint32_t gs_table_depth;
595
596 /* MSAA sample locations.
597 * The first index is the sample index.
598 * The second index is the coordinate: X, Y. */
599 float sample_locations_1x[1][2];
600 float sample_locations_2x[2][2];
601 float sample_locations_4x[4][2];
602 float sample_locations_8x[8][2];
603 float sample_locations_16x[16][2];
604
605 /* CIK and later */
606 uint32_t gfx_init_size_dw;
607 struct radeon_winsys_bo *gfx_init;
608
609 struct radeon_winsys_bo *trace_bo;
610 uint32_t *trace_id_ptr;
611
612 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
613 bool keep_shader_info;
614
615 struct radv_physical_device *physical_device;
616
617 /* Backup in-memory cache to be used if the app doesn't provide one */
618 struct radv_pipeline_cache * mem_cache;
619
620 /*
621 * use different counters so MSAA MRTs get consecutive surface indices,
622 * even if MASK is allocated in between.
623 */
624 uint32_t image_mrt_offset_counter;
625 uint32_t fmask_mrt_offset_counter;
626 struct list_head shader_slabs;
627 mtx_t shader_slab_mutex;
628
629 /* For detecting VM faults reported by dmesg. */
630 uint64_t dmesg_timestamp;
631 };
632
633 struct radv_device_memory {
634 struct radeon_winsys_bo *bo;
635 /* for dedicated allocations */
636 struct radv_image *image;
637 struct radv_buffer *buffer;
638 uint32_t type_index;
639 VkDeviceSize map_size;
640 void * map;
641 };
642
643
644 struct radv_descriptor_range {
645 uint64_t va;
646 uint32_t size;
647 };
648
649 struct radv_descriptor_set {
650 const struct radv_descriptor_set_layout *layout;
651 uint32_t size;
652
653 struct radeon_winsys_bo *bo;
654 uint64_t va;
655 uint32_t *mapped_ptr;
656 struct radv_descriptor_range *dynamic_descriptors;
657
658 struct radeon_winsys_bo *descriptors[0];
659 };
660
661 struct radv_push_descriptor_set
662 {
663 struct radv_descriptor_set set;
664 uint32_t capacity;
665 };
666
667 struct radv_descriptor_pool_entry {
668 uint32_t offset;
669 uint32_t size;
670 struct radv_descriptor_set *set;
671 };
672
673 struct radv_descriptor_pool {
674 struct radeon_winsys_bo *bo;
675 uint8_t *mapped_ptr;
676 uint64_t current_offset;
677 uint64_t size;
678
679 uint8_t *host_memory_base;
680 uint8_t *host_memory_ptr;
681 uint8_t *host_memory_end;
682
683 uint32_t entry_count;
684 uint32_t max_entry_count;
685 struct radv_descriptor_pool_entry entries[0];
686 };
687
688 struct radv_descriptor_update_template_entry {
689 VkDescriptorType descriptor_type;
690
691 /* The number of descriptors to update */
692 uint32_t descriptor_count;
693
694 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
695 uint32_t dst_offset;
696
697 /* In dwords. Not valid/used for dynamic descriptors */
698 uint32_t dst_stride;
699
700 uint32_t buffer_offset;
701
702 /* Only valid for combined image samplers and samplers */
703 uint16_t has_sampler;
704
705 /* In bytes */
706 size_t src_offset;
707 size_t src_stride;
708
709 /* For push descriptors */
710 const uint32_t *immutable_samplers;
711 };
712
713 struct radv_descriptor_update_template {
714 uint32_t entry_count;
715 struct radv_descriptor_update_template_entry entry[0];
716 };
717
718 struct radv_buffer {
719 struct radv_device * device;
720 VkDeviceSize size;
721
722 VkBufferUsageFlags usage;
723 VkBufferCreateFlags flags;
724
725 /* Set when bound */
726 struct radeon_winsys_bo * bo;
727 VkDeviceSize offset;
728
729 bool shareable;
730 };
731
732
733 enum radv_cmd_dirty_bits {
734 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
735 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
736 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
737 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
738 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
739 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
740 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
741 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
742 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
743 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
744 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
745 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
746 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 11,
747 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 12,
748 };
749
750 enum radv_cmd_flush_bits {
751 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
752 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
753 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
754 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
755 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
756 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
757 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
758 /* Same as above, but only writes back and doesn't invalidate */
759 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
760 /* Framebuffer caches */
761 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
762 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
763 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
764 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
765 /* Engine synchronization. */
766 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
767 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
768 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
769 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
770
771 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
772 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
773 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
774 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
775 };
776
777 struct radv_vertex_binding {
778 struct radv_buffer * buffer;
779 VkDeviceSize offset;
780 };
781
782 struct radv_viewport_state {
783 uint32_t count;
784 VkViewport viewports[MAX_VIEWPORTS];
785 };
786
787 struct radv_scissor_state {
788 uint32_t count;
789 VkRect2D scissors[MAX_SCISSORS];
790 };
791
792 struct radv_dynamic_state {
793 /**
794 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
795 * Defines the set of saved dynamic state.
796 */
797 uint32_t mask;
798
799 struct radv_viewport_state viewport;
800
801 struct radv_scissor_state scissor;
802
803 float line_width;
804
805 struct {
806 float bias;
807 float clamp;
808 float slope;
809 } depth_bias;
810
811 float blend_constants[4];
812
813 struct {
814 float min;
815 float max;
816 } depth_bounds;
817
818 struct {
819 uint32_t front;
820 uint32_t back;
821 } stencil_compare_mask;
822
823 struct {
824 uint32_t front;
825 uint32_t back;
826 } stencil_write_mask;
827
828 struct {
829 uint32_t front;
830 uint32_t back;
831 } stencil_reference;
832 };
833
834 extern const struct radv_dynamic_state default_dynamic_state;
835
836 const char *
837 radv_get_debug_option_name(int id);
838
839 const char *
840 radv_get_perftest_option_name(int id);
841
842 /**
843 * Attachment state when recording a renderpass instance.
844 *
845 * The clear value is valid only if there exists a pending clear.
846 */
847 struct radv_attachment_state {
848 VkImageAspectFlags pending_clear_aspects;
849 uint32_t cleared_views;
850 VkClearValue clear_value;
851 VkImageLayout current_layout;
852 };
853
854 struct radv_cmd_state {
855 /* Vertex descriptors */
856 bool vb_prefetch_dirty;
857 uint64_t vb_va;
858 unsigned vb_size;
859
860 bool push_descriptors_dirty;
861 bool predicating;
862 uint32_t dirty;
863
864 struct radv_pipeline * pipeline;
865 struct radv_pipeline * emitted_pipeline;
866 struct radv_pipeline * compute_pipeline;
867 struct radv_pipeline * emitted_compute_pipeline;
868 struct radv_framebuffer * framebuffer;
869 struct radv_render_pass * pass;
870 const struct radv_subpass * subpass;
871 struct radv_dynamic_state dynamic;
872 struct radv_attachment_state * attachments;
873 VkRect2D render_area;
874
875 /* Index buffer */
876 struct radv_buffer *index_buffer;
877 uint64_t index_offset;
878 uint32_t index_type;
879 uint32_t max_index_count;
880 uint64_t index_va;
881 int32_t last_index_type;
882
883 int32_t last_primitive_reset_en;
884 uint32_t last_primitive_reset_index;
885 enum radv_cmd_flush_bits flush_bits;
886 unsigned active_occlusion_queries;
887 float offset_scale;
888 uint32_t descriptors_dirty;
889 uint32_t valid_descriptors;
890 uint32_t trace_id;
891 uint32_t last_ia_multi_vgt_param;
892 };
893
894 struct radv_cmd_pool {
895 VkAllocationCallbacks alloc;
896 struct list_head cmd_buffers;
897 struct list_head free_cmd_buffers;
898 uint32_t queue_family_index;
899 };
900
901 struct radv_cmd_buffer_upload {
902 uint8_t *map;
903 unsigned offset;
904 uint64_t size;
905 struct radeon_winsys_bo *upload_bo;
906 struct list_head list;
907 };
908
909 enum radv_cmd_buffer_status {
910 RADV_CMD_BUFFER_STATUS_INVALID,
911 RADV_CMD_BUFFER_STATUS_INITIAL,
912 RADV_CMD_BUFFER_STATUS_RECORDING,
913 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
914 RADV_CMD_BUFFER_STATUS_PENDING,
915 };
916
917 struct radv_cmd_buffer {
918 VK_LOADER_DATA _loader_data;
919
920 struct radv_device * device;
921
922 struct radv_cmd_pool * pool;
923 struct list_head pool_link;
924
925 VkCommandBufferUsageFlags usage_flags;
926 VkCommandBufferLevel level;
927 enum radv_cmd_buffer_status status;
928 struct radeon_winsys_cs *cs;
929 struct radv_cmd_state state;
930 struct radv_vertex_binding vertex_bindings[MAX_VBS];
931 uint32_t queue_family_index;
932
933 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
934 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
935 VkShaderStageFlags push_constant_stages;
936 struct radv_push_descriptor_set push_descriptors;
937 struct radv_descriptor_set meta_push_descriptors;
938 struct radv_descriptor_set *descriptors[MAX_SETS];
939
940 struct radv_cmd_buffer_upload upload;
941
942 uint32_t scratch_size_needed;
943 uint32_t compute_scratch_size_needed;
944 uint32_t esgs_ring_size_needed;
945 uint32_t gsvs_ring_size_needed;
946 bool tess_rings_needed;
947 bool sample_positions_needed;
948
949 VkResult record_result;
950
951 int ring_offsets_idx; /* just used for verification */
952 uint32_t gfx9_fence_offset;
953 struct radeon_winsys_bo *gfx9_fence_bo;
954 uint32_t gfx9_fence_idx;
955 };
956
957 struct radv_image;
958
959 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
960
961 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
962 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
963
964 void cik_create_gfx_config(struct radv_device *device);
965
966 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
967 int count, const VkViewport *viewports);
968 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
969 int count, const VkRect2D *scissors,
970 const VkViewport *viewports, bool can_use_guardband);
971 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
972 bool instanced_draw, bool indirect_draw,
973 uint32_t draw_vertex_count);
974 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
975 bool predicated,
976 enum chip_class chip_class,
977 bool is_mec,
978 unsigned event, unsigned event_flags,
979 unsigned data_sel,
980 uint64_t va,
981 uint32_t old_fence,
982 uint32_t new_fence);
983
984 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
985 bool predicated,
986 uint64_t va, uint32_t ref,
987 uint32_t mask);
988 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
989 bool predicated,
990 enum chip_class chip_class,
991 uint32_t *fence_ptr, uint64_t va,
992 bool is_mec,
993 enum radv_cmd_flush_bits flush_bits);
994 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
995 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
996 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
997 uint64_t src_va, uint64_t dest_va,
998 uint64_t size);
999 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1000 unsigned size);
1001 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1002 uint64_t size, unsigned value);
1003 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1004 bool
1005 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1006 unsigned size,
1007 unsigned alignment,
1008 unsigned *out_offset,
1009 void **ptr);
1010 void
1011 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1012 const struct radv_subpass *subpass,
1013 bool transitions);
1014 bool
1015 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1016 unsigned size, unsigned alignmnet,
1017 const void *data, unsigned *out_offset);
1018
1019 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1020 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1021 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1022 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1023 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1024 unsigned radv_cayman_get_maxdist(int log_samples);
1025 void radv_device_init_msaa(struct radv_device *device);
1026 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1027 struct radv_image *image,
1028 VkClearDepthStencilValue ds_clear_value,
1029 VkImageAspectFlags aspects);
1030 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1031 struct radv_image *image,
1032 int idx,
1033 uint32_t color_values[2]);
1034 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1035 struct radv_image *image,
1036 bool value);
1037 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1038 struct radeon_winsys_bo *bo,
1039 uint64_t offset, uint64_t size, uint32_t value);
1040 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1041 bool radv_get_memory_fd(struct radv_device *device,
1042 struct radv_device_memory *memory,
1043 int *pFD);
1044
1045 /*
1046 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1047 *
1048 * Limitations: Can't call normal dispatch functions without binding or rebinding
1049 * the compute pipeline.
1050 */
1051 void radv_unaligned_dispatch(
1052 struct radv_cmd_buffer *cmd_buffer,
1053 uint32_t x,
1054 uint32_t y,
1055 uint32_t z);
1056
1057 struct radv_event {
1058 struct radeon_winsys_bo *bo;
1059 uint64_t *map;
1060 };
1061
1062 struct radv_shader_module;
1063
1064 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1065 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1066 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1067 void
1068 radv_hash_shaders(unsigned char *hash,
1069 const VkPipelineShaderStageCreateInfo **stages,
1070 const struct radv_pipeline_layout *layout,
1071 const struct radv_pipeline_key *key,
1072 uint32_t flags);
1073
1074 static inline gl_shader_stage
1075 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1076 {
1077 assert(__builtin_popcount(vk_stage) == 1);
1078 return ffs(vk_stage) - 1;
1079 }
1080
1081 static inline VkShaderStageFlagBits
1082 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1083 {
1084 return (1 << mesa_stage);
1085 }
1086
1087 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1088
1089 #define radv_foreach_stage(stage, stage_bits) \
1090 for (gl_shader_stage stage, \
1091 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1092 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1093 __tmp &= ~(1 << (stage)))
1094
1095 struct radv_depth_stencil_state {
1096 uint32_t db_depth_control;
1097 uint32_t db_stencil_control;
1098 uint32_t db_render_control;
1099 uint32_t db_render_override2;
1100 };
1101
1102 struct radv_blend_state {
1103 uint32_t cb_color_control;
1104 uint32_t cb_target_mask;
1105 uint32_t sx_mrt_blend_opt[8];
1106 uint32_t cb_blend_control[8];
1107
1108 uint32_t spi_shader_col_format;
1109 uint32_t cb_shader_mask;
1110 uint32_t db_alpha_to_mask;
1111 };
1112
1113 unsigned radv_format_meta_fs_key(VkFormat format);
1114
1115 struct radv_raster_state {
1116 uint32_t pa_cl_clip_cntl;
1117 uint32_t spi_interp_control;
1118 uint32_t pa_su_vtx_cntl;
1119 uint32_t pa_su_sc_mode_cntl;
1120 };
1121
1122 struct radv_multisample_state {
1123 uint32_t db_eqaa;
1124 uint32_t pa_sc_line_cntl;
1125 uint32_t pa_sc_mode_cntl_0;
1126 uint32_t pa_sc_mode_cntl_1;
1127 uint32_t pa_sc_aa_config;
1128 uint32_t pa_sc_aa_mask[2];
1129 unsigned num_samples;
1130 };
1131
1132 struct radv_prim_vertex_count {
1133 uint8_t min;
1134 uint8_t incr;
1135 };
1136
1137 struct radv_tessellation_state {
1138 uint32_t ls_hs_config;
1139 uint32_t tcs_in_layout;
1140 uint32_t tcs_out_layout;
1141 uint32_t tcs_out_offsets;
1142 uint32_t offchip_layout;
1143 unsigned num_patches;
1144 unsigned lds_size;
1145 unsigned num_tcs_input_cp;
1146 uint32_t tf_param;
1147 };
1148
1149 struct radv_gs_state {
1150 uint32_t vgt_gs_onchip_cntl;
1151 uint32_t vgt_gs_max_prims_per_subgroup;
1152 uint32_t vgt_esgs_ring_itemsize;
1153 uint32_t lds_size;
1154 };
1155
1156 struct radv_vertex_elements_info {
1157 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1158 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1159 uint32_t binding[MAX_VERTEX_ATTRIBS];
1160 uint32_t offset[MAX_VERTEX_ATTRIBS];
1161 uint32_t count;
1162 };
1163
1164 struct radv_vs_state {
1165 uint32_t pa_cl_vs_out_cntl;
1166 uint32_t spi_shader_pos_format;
1167 uint32_t spi_vs_out_config;
1168 uint32_t vgt_reuse_off;
1169 };
1170
1171 struct radv_binning_state {
1172 uint32_t pa_sc_binner_cntl_0;
1173 uint32_t db_dfsm_control;
1174 };
1175
1176 #define SI_GS_PER_ES 128
1177
1178 struct radv_pipeline {
1179 struct radv_device * device;
1180 struct radv_dynamic_state dynamic_state;
1181
1182 struct radv_pipeline_layout * layout;
1183
1184 bool needs_data_cache;
1185 bool need_indirect_descriptor_sets;
1186 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1187 struct radv_shader_variant *gs_copy_shader;
1188 VkShaderStageFlags active_stages;
1189
1190 struct radv_vertex_elements_info vertex_elements;
1191
1192 uint32_t binding_stride[MAX_VBS];
1193
1194 uint32_t user_data_0[MESA_SHADER_STAGES];
1195 union {
1196 struct {
1197 struct radv_blend_state blend;
1198 struct radv_depth_stencil_state ds;
1199 struct radv_raster_state raster;
1200 struct radv_multisample_state ms;
1201 struct radv_tessellation_state tess;
1202 struct radv_gs_state gs;
1203 struct radv_vs_state vs;
1204 struct radv_binning_state bin;
1205 uint32_t db_shader_control;
1206 uint32_t shader_z_format;
1207 unsigned prim;
1208 unsigned gs_out;
1209 uint32_t vgt_gs_mode;
1210 bool vgt_primitiveid_en;
1211 bool prim_restart_enable;
1212 bool partial_es_wave;
1213 uint8_t primgroup_size;
1214 unsigned esgs_ring_size;
1215 unsigned gsvs_ring_size;
1216 uint32_t ps_input_cntl[32];
1217 uint32_t ps_input_cntl_num;
1218 uint32_t vgt_shader_stages_en;
1219 uint32_t vtx_base_sgpr;
1220 uint32_t base_ia_multi_vgt_param;
1221 bool wd_switch_on_eop;
1222 bool ia_switch_on_eoi;
1223 bool partial_vs_wave;
1224 uint8_t vtx_emit_num;
1225 uint32_t vtx_reuse_depth;
1226 struct radv_prim_vertex_count prim_vertex_count;
1227 bool can_use_guardband;
1228 } graphics;
1229 };
1230
1231 unsigned max_waves;
1232 unsigned scratch_bytes_per_wave;
1233 };
1234
1235 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1236 {
1237 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1238 }
1239
1240 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1241 {
1242 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1243 }
1244
1245 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1246 gl_shader_stage stage,
1247 int idx);
1248
1249 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1250
1251 struct radv_graphics_pipeline_create_info {
1252 bool use_rectlist;
1253 bool db_depth_clear;
1254 bool db_stencil_clear;
1255 bool db_depth_disable_expclear;
1256 bool db_stencil_disable_expclear;
1257 bool db_flush_depth_inplace;
1258 bool db_flush_stencil_inplace;
1259 bool db_resummarize;
1260 uint32_t custom_blend_mode;
1261 };
1262
1263 VkResult
1264 radv_graphics_pipeline_create(VkDevice device,
1265 VkPipelineCache cache,
1266 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1267 const struct radv_graphics_pipeline_create_info *extra,
1268 const VkAllocationCallbacks *alloc,
1269 VkPipeline *pPipeline);
1270
1271 struct vk_format_description;
1272 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1273 int first_non_void);
1274 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1275 int first_non_void);
1276 uint32_t radv_translate_colorformat(VkFormat format);
1277 uint32_t radv_translate_color_numformat(VkFormat format,
1278 const struct vk_format_description *desc,
1279 int first_non_void);
1280 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1281 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1282 uint32_t radv_translate_dbformat(VkFormat format);
1283 uint32_t radv_translate_tex_dataformat(VkFormat format,
1284 const struct vk_format_description *desc,
1285 int first_non_void);
1286 uint32_t radv_translate_tex_numformat(VkFormat format,
1287 const struct vk_format_description *desc,
1288 int first_non_void);
1289 bool radv_format_pack_clear_color(VkFormat format,
1290 uint32_t clear_vals[2],
1291 VkClearColorValue *value);
1292 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1293 bool radv_dcc_formats_compatible(VkFormat format1,
1294 VkFormat format2);
1295
1296 struct radv_fmask_info {
1297 uint64_t offset;
1298 uint64_t size;
1299 unsigned alignment;
1300 unsigned pitch_in_pixels;
1301 unsigned bank_height;
1302 unsigned slice_tile_max;
1303 unsigned tile_mode_index;
1304 unsigned tile_swizzle;
1305 };
1306
1307 struct radv_cmask_info {
1308 uint64_t offset;
1309 uint64_t size;
1310 unsigned alignment;
1311 unsigned slice_tile_max;
1312 };
1313
1314 struct radv_image {
1315 VkImageType type;
1316 /* The original VkFormat provided by the client. This may not match any
1317 * of the actual surface formats.
1318 */
1319 VkFormat vk_format;
1320 VkImageAspectFlags aspects;
1321 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1322 struct ac_surf_info info;
1323 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1324 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1325
1326 VkDeviceSize size;
1327 uint32_t alignment;
1328
1329 unsigned queue_family_mask;
1330 bool exclusive;
1331 bool shareable;
1332
1333 /* Set when bound */
1334 struct radeon_winsys_bo *bo;
1335 VkDeviceSize offset;
1336 uint64_t dcc_offset;
1337 uint64_t htile_offset;
1338 bool tc_compatible_htile;
1339 struct radeon_surf surface;
1340
1341 struct radv_fmask_info fmask;
1342 struct radv_cmask_info cmask;
1343 uint64_t clear_value_offset;
1344 uint64_t dcc_pred_offset;
1345 };
1346
1347 /* Whether the image has a htile that is known consistent with the contents of
1348 * the image. */
1349 bool radv_layout_has_htile(const struct radv_image *image,
1350 VkImageLayout layout,
1351 unsigned queue_mask);
1352
1353 /* Whether the image has a htile that is known consistent with the contents of
1354 * the image and is allowed to be in compressed form.
1355 *
1356 * If this is false reads that don't use the htile should be able to return
1357 * correct results.
1358 */
1359 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1360 VkImageLayout layout,
1361 unsigned queue_mask);
1362
1363 bool radv_layout_can_fast_clear(const struct radv_image *image,
1364 VkImageLayout layout,
1365 unsigned queue_mask);
1366
1367 bool radv_layout_dcc_compressed(const struct radv_image *image,
1368 VkImageLayout layout,
1369 unsigned queue_mask);
1370
1371 static inline bool
1372 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1373 {
1374 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1375 }
1376
1377 static inline bool
1378 radv_htile_enabled(const struct radv_image *image, unsigned level)
1379 {
1380 return image->surface.htile_size && level == 0;
1381 }
1382
1383 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1384
1385 static inline uint32_t
1386 radv_get_layerCount(const struct radv_image *image,
1387 const VkImageSubresourceRange *range)
1388 {
1389 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1390 image->info.array_size - range->baseArrayLayer : range->layerCount;
1391 }
1392
1393 static inline uint32_t
1394 radv_get_levelCount(const struct radv_image *image,
1395 const VkImageSubresourceRange *range)
1396 {
1397 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1398 image->info.levels - range->baseMipLevel : range->levelCount;
1399 }
1400
1401 struct radeon_bo_metadata;
1402 void
1403 radv_init_metadata(struct radv_device *device,
1404 struct radv_image *image,
1405 struct radeon_bo_metadata *metadata);
1406
1407 struct radv_image_view {
1408 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1409 struct radeon_winsys_bo *bo;
1410
1411 VkImageViewType type;
1412 VkImageAspectFlags aspect_mask;
1413 VkFormat vk_format;
1414 uint32_t base_layer;
1415 uint32_t layer_count;
1416 uint32_t base_mip;
1417 uint32_t level_count;
1418 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1419
1420 uint32_t descriptor[16];
1421
1422 /* Descriptor for use as a storage image as opposed to a sampled image.
1423 * This has a few differences for cube maps (e.g. type).
1424 */
1425 uint32_t storage_descriptor[16];
1426 };
1427
1428 struct radv_image_create_info {
1429 const VkImageCreateInfo *vk_info;
1430 bool scanout;
1431 };
1432
1433 VkResult radv_image_create(VkDevice _device,
1434 const struct radv_image_create_info *info,
1435 const VkAllocationCallbacks* alloc,
1436 VkImage *pImage);
1437
1438 void radv_image_view_init(struct radv_image_view *view,
1439 struct radv_device *device,
1440 const VkImageViewCreateInfo* pCreateInfo);
1441
1442 struct radv_buffer_view {
1443 struct radeon_winsys_bo *bo;
1444 VkFormat vk_format;
1445 uint64_t range; /**< VkBufferViewCreateInfo::range */
1446 uint32_t state[4];
1447 };
1448 void radv_buffer_view_init(struct radv_buffer_view *view,
1449 struct radv_device *device,
1450 const VkBufferViewCreateInfo* pCreateInfo);
1451
1452 static inline struct VkExtent3D
1453 radv_sanitize_image_extent(const VkImageType imageType,
1454 const struct VkExtent3D imageExtent)
1455 {
1456 switch (imageType) {
1457 case VK_IMAGE_TYPE_1D:
1458 return (VkExtent3D) { imageExtent.width, 1, 1 };
1459 case VK_IMAGE_TYPE_2D:
1460 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1461 case VK_IMAGE_TYPE_3D:
1462 return imageExtent;
1463 default:
1464 unreachable("invalid image type");
1465 }
1466 }
1467
1468 static inline struct VkOffset3D
1469 radv_sanitize_image_offset(const VkImageType imageType,
1470 const struct VkOffset3D imageOffset)
1471 {
1472 switch (imageType) {
1473 case VK_IMAGE_TYPE_1D:
1474 return (VkOffset3D) { imageOffset.x, 0, 0 };
1475 case VK_IMAGE_TYPE_2D:
1476 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1477 case VK_IMAGE_TYPE_3D:
1478 return imageOffset;
1479 default:
1480 unreachable("invalid image type");
1481 }
1482 }
1483
1484 static inline bool
1485 radv_image_extent_compare(const struct radv_image *image,
1486 const VkExtent3D *extent)
1487 {
1488 if (extent->width != image->info.width ||
1489 extent->height != image->info.height ||
1490 extent->depth != image->info.depth)
1491 return false;
1492 return true;
1493 }
1494
1495 struct radv_sampler {
1496 uint32_t state[4];
1497 };
1498
1499 struct radv_color_buffer_info {
1500 uint64_t cb_color_base;
1501 uint64_t cb_color_cmask;
1502 uint64_t cb_color_fmask;
1503 uint64_t cb_dcc_base;
1504 uint32_t cb_color_pitch;
1505 uint32_t cb_color_slice;
1506 uint32_t cb_color_view;
1507 uint32_t cb_color_info;
1508 uint32_t cb_color_attrib;
1509 uint32_t cb_color_attrib2;
1510 uint32_t cb_dcc_control;
1511 uint32_t cb_color_cmask_slice;
1512 uint32_t cb_color_fmask_slice;
1513 };
1514
1515 struct radv_ds_buffer_info {
1516 uint64_t db_z_read_base;
1517 uint64_t db_stencil_read_base;
1518 uint64_t db_z_write_base;
1519 uint64_t db_stencil_write_base;
1520 uint64_t db_htile_data_base;
1521 uint32_t db_depth_info;
1522 uint32_t db_z_info;
1523 uint32_t db_stencil_info;
1524 uint32_t db_depth_view;
1525 uint32_t db_depth_size;
1526 uint32_t db_depth_slice;
1527 uint32_t db_htile_surface;
1528 uint32_t pa_su_poly_offset_db_fmt_cntl;
1529 uint32_t db_z_info2;
1530 uint32_t db_stencil_info2;
1531 float offset_scale;
1532 };
1533
1534 struct radv_attachment_info {
1535 union {
1536 struct radv_color_buffer_info cb;
1537 struct radv_ds_buffer_info ds;
1538 };
1539 struct radv_image_view *attachment;
1540 };
1541
1542 struct radv_framebuffer {
1543 uint32_t width;
1544 uint32_t height;
1545 uint32_t layers;
1546
1547 uint32_t attachment_count;
1548 struct radv_attachment_info attachments[0];
1549 };
1550
1551 struct radv_subpass_barrier {
1552 VkPipelineStageFlags src_stage_mask;
1553 VkAccessFlags src_access_mask;
1554 VkAccessFlags dst_access_mask;
1555 };
1556
1557 struct radv_subpass {
1558 uint32_t input_count;
1559 uint32_t color_count;
1560 VkAttachmentReference * input_attachments;
1561 VkAttachmentReference * color_attachments;
1562 VkAttachmentReference * resolve_attachments;
1563 VkAttachmentReference depth_stencil_attachment;
1564
1565 /** Subpass has at least one resolve attachment */
1566 bool has_resolve;
1567
1568 struct radv_subpass_barrier start_barrier;
1569
1570 uint32_t view_mask;
1571 };
1572
1573 struct radv_render_pass_attachment {
1574 VkFormat format;
1575 uint32_t samples;
1576 VkAttachmentLoadOp load_op;
1577 VkAttachmentLoadOp stencil_load_op;
1578 VkImageLayout initial_layout;
1579 VkImageLayout final_layout;
1580 uint32_t view_mask;
1581 };
1582
1583 struct radv_render_pass {
1584 uint32_t attachment_count;
1585 uint32_t subpass_count;
1586 VkAttachmentReference * subpass_attachments;
1587 struct radv_render_pass_attachment * attachments;
1588 struct radv_subpass_barrier end_barrier;
1589 struct radv_subpass subpasses[0];
1590 };
1591
1592 VkResult radv_device_init_meta(struct radv_device *device);
1593 void radv_device_finish_meta(struct radv_device *device);
1594
1595 struct radv_query_pool {
1596 struct radeon_winsys_bo *bo;
1597 uint32_t stride;
1598 uint32_t availability_offset;
1599 char *ptr;
1600 VkQueryType type;
1601 uint32_t pipeline_stats_mask;
1602 };
1603
1604 struct radv_semaphore {
1605 /* use a winsys sem for non-exportable */
1606 struct radeon_winsys_sem *sem;
1607 uint32_t syncobj;
1608 uint32_t temp_syncobj;
1609 };
1610
1611 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1612 int num_wait_sems,
1613 const VkSemaphore *wait_sems,
1614 int num_signal_sems,
1615 const VkSemaphore *signal_sems,
1616 VkFence fence);
1617 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1618
1619 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1620 struct radv_descriptor_set *set,
1621 unsigned idx);
1622
1623 void
1624 radv_update_descriptor_sets(struct radv_device *device,
1625 struct radv_cmd_buffer *cmd_buffer,
1626 VkDescriptorSet overrideSet,
1627 uint32_t descriptorWriteCount,
1628 const VkWriteDescriptorSet *pDescriptorWrites,
1629 uint32_t descriptorCopyCount,
1630 const VkCopyDescriptorSet *pDescriptorCopies);
1631
1632 void
1633 radv_update_descriptor_set_with_template(struct radv_device *device,
1634 struct radv_cmd_buffer *cmd_buffer,
1635 struct radv_descriptor_set *set,
1636 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1637 const void *pData);
1638
1639 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1640 VkPipelineBindPoint pipelineBindPoint,
1641 VkPipelineLayout _layout,
1642 uint32_t set,
1643 uint32_t descriptorWriteCount,
1644 const VkWriteDescriptorSet *pDescriptorWrites);
1645
1646 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1647 struct radv_image *image, uint32_t value);
1648 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1649 struct radv_image *image, uint32_t value);
1650
1651 struct radv_fence {
1652 struct radeon_winsys_fence *fence;
1653 bool submitted;
1654 bool signalled;
1655
1656 uint32_t syncobj;
1657 uint32_t temp_syncobj;
1658 };
1659
1660 struct radeon_winsys_sem;
1661
1662 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1663 \
1664 static inline struct __radv_type * \
1665 __radv_type ## _from_handle(__VkType _handle) \
1666 { \
1667 return (struct __radv_type *) _handle; \
1668 } \
1669 \
1670 static inline __VkType \
1671 __radv_type ## _to_handle(struct __radv_type *_obj) \
1672 { \
1673 return (__VkType) _obj; \
1674 }
1675
1676 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1677 \
1678 static inline struct __radv_type * \
1679 __radv_type ## _from_handle(__VkType _handle) \
1680 { \
1681 return (struct __radv_type *)(uintptr_t) _handle; \
1682 } \
1683 \
1684 static inline __VkType \
1685 __radv_type ## _to_handle(struct __radv_type *_obj) \
1686 { \
1687 return (__VkType)(uintptr_t) _obj; \
1688 }
1689
1690 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1691 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1692
1693 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1694 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1695 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1696 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1697 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1698
1699 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1700 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1701 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1702 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1703 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1704 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1705 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1706 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1707 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1708 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1709 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1710 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1711 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1712 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1713 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1714 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1715 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1716 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1717 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1718 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1719 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1720
1721 #endif /* RADV_PRIVATE_H */