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radv: Add support for image views with multiple planes.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
53 #include "vk_alloc.h"
54 #include "vk_debug_report.h"
55
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_descriptor_set.h"
64 #include "radv_extensions.h"
65 #include "radv_cs.h"
66
67 #include <llvm-c/TargetMachine.h>
68
69 /* Pre-declarations needed for WSI entrypoints */
70 struct wl_surface;
71 struct wl_display;
72 typedef struct xcb_connection_t xcb_connection_t;
73 typedef uint32_t xcb_visualid_t;
74 typedef uint32_t xcb_window_t;
75
76 #include <vulkan/vulkan.h>
77 #include <vulkan/vulkan_intel.h>
78 #include <vulkan/vk_icd.h>
79 #include <vulkan/vk_android_native_buffer.h>
80
81 #include "radv_entrypoints.h"
82
83 #include "wsi_common.h"
84 #include "wsi_common_display.h"
85
86 #define ATI_VENDOR_ID 0x1002
87
88 #define MAX_VBS 32
89 #define MAX_VERTEX_ATTRIBS 32
90 #define MAX_RTS 8
91 #define MAX_VIEWPORTS 16
92 #define MAX_SCISSORS 16
93 #define MAX_DISCARD_RECTANGLES 4
94 #define MAX_PUSH_CONSTANTS_SIZE 128
95 #define MAX_PUSH_DESCRIPTORS 32
96 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
97 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
98 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
99 #define MAX_SAMPLES_LOG2 4
100 #define NUM_META_FS_KEYS 12
101 #define RADV_MAX_DRM_DEVICES 8
102 #define MAX_VIEWS 8
103 #define MAX_SO_STREAMS 4
104 #define MAX_SO_BUFFERS 4
105 #define MAX_SO_OUTPUTS 64
106 #define MAX_INLINE_UNIFORM_BLOCK_SIZE (4ull * 1024 * 1024)
107 #define MAX_INLINE_UNIFORM_BLOCK_COUNT 64
108
109 #define NUM_DEPTH_CLEAR_PIPELINES 3
110
111 /*
112 * This is the point we switch from using CP to compute shader
113 * for certain buffer operations.
114 */
115 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
116
117 #define RADV_BUFFER_UPDATE_THRESHOLD 1024
118
119 enum radv_mem_heap {
120 RADV_MEM_HEAP_VRAM,
121 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
122 RADV_MEM_HEAP_GTT,
123 RADV_MEM_HEAP_COUNT
124 };
125
126 enum radv_mem_type {
127 RADV_MEM_TYPE_VRAM,
128 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
129 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
130 RADV_MEM_TYPE_GTT_CACHED,
131 RADV_MEM_TYPE_COUNT
132 };
133
134 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
135
136 static inline uint32_t
137 align_u32(uint32_t v, uint32_t a)
138 {
139 assert(a != 0 && a == (a & -a));
140 return (v + a - 1) & ~(a - 1);
141 }
142
143 static inline uint32_t
144 align_u32_npot(uint32_t v, uint32_t a)
145 {
146 return (v + a - 1) / a * a;
147 }
148
149 static inline uint64_t
150 align_u64(uint64_t v, uint64_t a)
151 {
152 assert(a != 0 && a == (a & -a));
153 return (v + a - 1) & ~(a - 1);
154 }
155
156 static inline int32_t
157 align_i32(int32_t v, int32_t a)
158 {
159 assert(a != 0 && a == (a & -a));
160 return (v + a - 1) & ~(a - 1);
161 }
162
163 /** Alignment must be a power of 2. */
164 static inline bool
165 radv_is_aligned(uintmax_t n, uintmax_t a)
166 {
167 assert(a == (a & -a));
168 return (n & (a - 1)) == 0;
169 }
170
171 static inline uint32_t
172 round_up_u32(uint32_t v, uint32_t a)
173 {
174 return (v + a - 1) / a;
175 }
176
177 static inline uint64_t
178 round_up_u64(uint64_t v, uint64_t a)
179 {
180 return (v + a - 1) / a;
181 }
182
183 static inline uint32_t
184 radv_minify(uint32_t n, uint32_t levels)
185 {
186 if (unlikely(n == 0))
187 return 0;
188 else
189 return MAX2(n >> levels, 1);
190 }
191 static inline float
192 radv_clamp_f(float f, float min, float max)
193 {
194 assert(min < max);
195
196 if (f > max)
197 return max;
198 else if (f < min)
199 return min;
200 else
201 return f;
202 }
203
204 static inline bool
205 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
206 {
207 if (*inout_mask & clear_mask) {
208 *inout_mask &= ~clear_mask;
209 return true;
210 } else {
211 return false;
212 }
213 }
214
215 #define for_each_bit(b, dword) \
216 for (uint32_t __dword = (dword); \
217 (b) = __builtin_ffs(__dword) - 1, __dword; \
218 __dword &= ~(1 << (b)))
219
220 #define typed_memcpy(dest, src, count) ({ \
221 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
222 memcpy((dest), (src), (count) * sizeof(*(src))); \
223 })
224
225 /* Whenever we generate an error, pass it through this function. Useful for
226 * debugging, where we can break on it. Only call at error site, not when
227 * propagating errors. Might be useful to plug in a stack trace here.
228 */
229
230 struct radv_instance;
231
232 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
233
234 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
235 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
236
237 void __radv_finishme(const char *file, int line, const char *format, ...)
238 radv_printflike(3, 4);
239 void radv_loge(const char *format, ...) radv_printflike(1, 2);
240 void radv_loge_v(const char *format, va_list va);
241 void radv_logi(const char *format, ...) radv_printflike(1, 2);
242 void radv_logi_v(const char *format, va_list va);
243
244 /**
245 * Print a FINISHME message, including its source location.
246 */
247 #define radv_finishme(format, ...) \
248 do { \
249 static bool reported = false; \
250 if (!reported) { \
251 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
252 reported = true; \
253 } \
254 } while (0)
255
256 /* A non-fatal assert. Useful for debugging. */
257 #ifdef DEBUG
258 #define radv_assert(x) ({ \
259 if (unlikely(!(x))) \
260 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
261 })
262 #else
263 #define radv_assert(x)
264 #endif
265
266 #define stub_return(v) \
267 do { \
268 radv_finishme("stub %s", __func__); \
269 return (v); \
270 } while (0)
271
272 #define stub() \
273 do { \
274 radv_finishme("stub %s", __func__); \
275 return; \
276 } while (0)
277
278 void *radv_lookup_entrypoint_unchecked(const char *name);
279 void *radv_lookup_entrypoint_checked(const char *name,
280 uint32_t core_version,
281 const struct radv_instance_extension_table *instance,
282 const struct radv_device_extension_table *device);
283
284 struct radv_physical_device {
285 VK_LOADER_DATA _loader_data;
286
287 struct radv_instance * instance;
288
289 struct radeon_winsys *ws;
290 struct radeon_info rad_info;
291 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
292 uint8_t driver_uuid[VK_UUID_SIZE];
293 uint8_t device_uuid[VK_UUID_SIZE];
294 uint8_t cache_uuid[VK_UUID_SIZE];
295
296 int local_fd;
297 int master_fd;
298 struct wsi_device wsi_device;
299
300 bool has_rbplus; /* if RB+ register exist */
301 bool rbplus_allowed; /* if RB+ is allowed */
302 bool has_clear_state;
303 bool cpdma_prefetch_writes_memory;
304 bool has_scissor_bug;
305
306 bool has_out_of_order_rast;
307 bool out_of_order_rast_allowed;
308
309 /* Whether DCC should be enabled for MSAA textures. */
310 bool dcc_msaa_allowed;
311
312 /* Whether LOAD_CONTEXT_REG packets are supported. */
313 bool has_load_ctx_reg_pkt;
314
315 /* This is the drivers on-disk cache used as a fallback as opposed to
316 * the pipeline cache defined by apps.
317 */
318 struct disk_cache * disk_cache;
319
320 VkPhysicalDeviceMemoryProperties memory_properties;
321 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
322
323 drmPciBusInfo bus_info;
324
325 struct radv_device_extension_table supported_extensions;
326 };
327
328 struct radv_instance {
329 VK_LOADER_DATA _loader_data;
330
331 VkAllocationCallbacks alloc;
332
333 uint32_t apiVersion;
334 int physicalDeviceCount;
335 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
336
337 uint64_t debug_flags;
338 uint64_t perftest_flags;
339
340 struct vk_debug_report_instance debug_report_callbacks;
341
342 struct radv_instance_extension_table enabled_extensions;
343
344 struct driOptionCache dri_options;
345 struct driOptionCache available_dri_options;
346 };
347
348 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
349 void radv_finish_wsi(struct radv_physical_device *physical_device);
350
351 bool radv_instance_extension_supported(const char *name);
352 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
353 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
354 const char *name);
355
356 struct cache_entry;
357
358 struct radv_pipeline_cache {
359 struct radv_device * device;
360 pthread_mutex_t mutex;
361
362 uint32_t total_size;
363 uint32_t table_size;
364 uint32_t kernel_count;
365 struct cache_entry ** hash_table;
366 bool modified;
367
368 VkAllocationCallbacks alloc;
369 };
370
371 struct radv_pipeline_key {
372 uint32_t instance_rate_inputs;
373 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
374 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
375 uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
376 uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
377 uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
378 uint64_t vertex_alpha_adjust;
379 uint32_t vertex_post_shuffle;
380 unsigned tess_input_vertices;
381 uint32_t col_format;
382 uint32_t is_int8;
383 uint32_t is_int10;
384 uint8_t log2_ps_iter_samples;
385 uint8_t num_samples;
386 uint32_t has_multiview_view_index : 1;
387 uint32_t optimisations_disabled : 1;
388 };
389
390 void
391 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
392 struct radv_device *device);
393 void
394 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
395 bool
396 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
397 const void *data, size_t size);
398
399 struct radv_shader_variant;
400
401 bool
402 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
403 struct radv_pipeline_cache *cache,
404 const unsigned char *sha1,
405 struct radv_shader_variant **variants,
406 bool *found_in_application_cache);
407
408 void
409 radv_pipeline_cache_insert_shaders(struct radv_device *device,
410 struct radv_pipeline_cache *cache,
411 const unsigned char *sha1,
412 struct radv_shader_variant **variants,
413 const void *const *codes,
414 const unsigned *code_sizes);
415
416 enum radv_blit_ds_layout {
417 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
418 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
419 RADV_BLIT_DS_LAYOUT_COUNT,
420 };
421
422 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
423 {
424 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
425 }
426
427 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
428 {
429 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
430 }
431
432 enum radv_meta_dst_layout {
433 RADV_META_DST_LAYOUT_GENERAL,
434 RADV_META_DST_LAYOUT_OPTIMAL,
435 RADV_META_DST_LAYOUT_COUNT,
436 };
437
438 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
439 {
440 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
441 }
442
443 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
444 {
445 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
446 }
447
448 struct radv_meta_state {
449 VkAllocationCallbacks alloc;
450
451 struct radv_pipeline_cache cache;
452
453 /*
454 * For on-demand pipeline creation, makes sure that
455 * only one thread tries to build a pipeline at the same time.
456 */
457 mtx_t mtx;
458
459 /**
460 * Use array element `i` for images with `2^i` samples.
461 */
462 struct {
463 VkRenderPass render_pass[NUM_META_FS_KEYS];
464 VkPipeline color_pipelines[NUM_META_FS_KEYS];
465
466 VkRenderPass depthstencil_rp;
467 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
468 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
469 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
470 } clear[1 + MAX_SAMPLES_LOG2];
471
472 VkPipelineLayout clear_color_p_layout;
473 VkPipelineLayout clear_depth_p_layout;
474
475 /* Optimized compute fast HTILE clear for stencil or depth only. */
476 VkPipeline clear_htile_mask_pipeline;
477 VkPipelineLayout clear_htile_mask_p_layout;
478 VkDescriptorSetLayout clear_htile_mask_ds_layout;
479
480 struct {
481 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
482
483 /** Pipeline that blits from a 1D image. */
484 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
485
486 /** Pipeline that blits from a 2D image. */
487 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
488
489 /** Pipeline that blits from a 3D image. */
490 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
491
492 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
493 VkPipeline depth_only_1d_pipeline;
494 VkPipeline depth_only_2d_pipeline;
495 VkPipeline depth_only_3d_pipeline;
496
497 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
498 VkPipeline stencil_only_1d_pipeline;
499 VkPipeline stencil_only_2d_pipeline;
500 VkPipeline stencil_only_3d_pipeline;
501 VkPipelineLayout pipeline_layout;
502 VkDescriptorSetLayout ds_layout;
503 } blit;
504
505 struct {
506 VkPipelineLayout p_layouts[5];
507 VkDescriptorSetLayout ds_layouts[5];
508 VkPipeline pipelines[5][NUM_META_FS_KEYS];
509
510 VkPipeline depth_only_pipeline[5];
511
512 VkPipeline stencil_only_pipeline[5];
513 } blit2d[1 + MAX_SAMPLES_LOG2];
514
515 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
516 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
517 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
518
519 struct {
520 VkPipelineLayout img_p_layout;
521 VkDescriptorSetLayout img_ds_layout;
522 VkPipeline pipeline;
523 VkPipeline pipeline_3d;
524 } itob;
525 struct {
526 VkPipelineLayout img_p_layout;
527 VkDescriptorSetLayout img_ds_layout;
528 VkPipeline pipeline;
529 VkPipeline pipeline_3d;
530 } btoi;
531 struct {
532 VkPipelineLayout img_p_layout;
533 VkDescriptorSetLayout img_ds_layout;
534 VkPipeline pipeline;
535 } btoi_r32g32b32;
536 struct {
537 VkPipelineLayout img_p_layout;
538 VkDescriptorSetLayout img_ds_layout;
539 VkPipeline pipeline;
540 VkPipeline pipeline_3d;
541 } itoi;
542 struct {
543 VkPipelineLayout img_p_layout;
544 VkDescriptorSetLayout img_ds_layout;
545 VkPipeline pipeline;
546 } itoi_r32g32b32;
547 struct {
548 VkPipelineLayout img_p_layout;
549 VkDescriptorSetLayout img_ds_layout;
550 VkPipeline pipeline;
551 VkPipeline pipeline_3d;
552 } cleari;
553 struct {
554 VkPipelineLayout img_p_layout;
555 VkDescriptorSetLayout img_ds_layout;
556 VkPipeline pipeline;
557 } cleari_r32g32b32;
558
559 struct {
560 VkPipelineLayout p_layout;
561 VkPipeline pipeline[NUM_META_FS_KEYS];
562 VkRenderPass pass[NUM_META_FS_KEYS];
563 } resolve;
564
565 struct {
566 VkDescriptorSetLayout ds_layout;
567 VkPipelineLayout p_layout;
568 struct {
569 VkPipeline pipeline;
570 VkPipeline i_pipeline;
571 VkPipeline srgb_pipeline;
572 } rc[MAX_SAMPLES_LOG2];
573 } resolve_compute;
574
575 struct {
576 VkDescriptorSetLayout ds_layout;
577 VkPipelineLayout p_layout;
578
579 struct {
580 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
581 VkPipeline pipeline[NUM_META_FS_KEYS];
582 } rc[MAX_SAMPLES_LOG2];
583 } resolve_fragment;
584
585 struct {
586 VkPipelineLayout p_layout;
587 VkPipeline decompress_pipeline;
588 VkPipeline resummarize_pipeline;
589 VkRenderPass pass;
590 } depth_decomp[1 + MAX_SAMPLES_LOG2];
591
592 struct {
593 VkPipelineLayout p_layout;
594 VkPipeline cmask_eliminate_pipeline;
595 VkPipeline fmask_decompress_pipeline;
596 VkPipeline dcc_decompress_pipeline;
597 VkRenderPass pass;
598
599 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
600 VkPipelineLayout dcc_decompress_compute_p_layout;
601 VkPipeline dcc_decompress_compute_pipeline;
602 } fast_clear_flush;
603
604 struct {
605 VkPipelineLayout fill_p_layout;
606 VkPipelineLayout copy_p_layout;
607 VkDescriptorSetLayout fill_ds_layout;
608 VkDescriptorSetLayout copy_ds_layout;
609 VkPipeline fill_pipeline;
610 VkPipeline copy_pipeline;
611 } buffer;
612
613 struct {
614 VkDescriptorSetLayout ds_layout;
615 VkPipelineLayout p_layout;
616 VkPipeline occlusion_query_pipeline;
617 VkPipeline pipeline_statistics_query_pipeline;
618 VkPipeline tfb_query_pipeline;
619 } query;
620
621 struct {
622 VkDescriptorSetLayout ds_layout;
623 VkPipelineLayout p_layout;
624 VkPipeline pipeline[MAX_SAMPLES_LOG2];
625 } fmask_expand;
626 };
627
628 /* queue types */
629 #define RADV_QUEUE_GENERAL 0
630 #define RADV_QUEUE_COMPUTE 1
631 #define RADV_QUEUE_TRANSFER 2
632
633 #define RADV_MAX_QUEUE_FAMILIES 3
634
635 enum ring_type radv_queue_family_to_ring(int f);
636
637 struct radv_queue {
638 VK_LOADER_DATA _loader_data;
639 struct radv_device * device;
640 struct radeon_winsys_ctx *hw_ctx;
641 enum radeon_ctx_priority priority;
642 uint32_t queue_family_index;
643 int queue_idx;
644 VkDeviceQueueCreateFlags flags;
645
646 uint32_t scratch_size;
647 uint32_t compute_scratch_size;
648 uint32_t esgs_ring_size;
649 uint32_t gsvs_ring_size;
650 bool has_tess_rings;
651 bool has_sample_positions;
652
653 struct radeon_winsys_bo *scratch_bo;
654 struct radeon_winsys_bo *descriptor_bo;
655 struct radeon_winsys_bo *compute_scratch_bo;
656 struct radeon_winsys_bo *esgs_ring_bo;
657 struct radeon_winsys_bo *gsvs_ring_bo;
658 struct radeon_winsys_bo *tess_rings_bo;
659 struct radeon_cmdbuf *initial_preamble_cs;
660 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
661 struct radeon_cmdbuf *continue_preamble_cs;
662 };
663
664 struct radv_bo_list {
665 struct radv_winsys_bo_list list;
666 unsigned capacity;
667 pthread_mutex_t mutex;
668 };
669
670 struct radv_device {
671 VK_LOADER_DATA _loader_data;
672
673 VkAllocationCallbacks alloc;
674
675 struct radv_instance * instance;
676 struct radeon_winsys *ws;
677
678 struct radv_meta_state meta_state;
679
680 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
681 int queue_count[RADV_MAX_QUEUE_FAMILIES];
682 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
683
684 bool always_use_syncobj;
685 bool has_distributed_tess;
686 bool pbb_allowed;
687 bool dfsm_allowed;
688 uint32_t tess_offchip_block_dw_size;
689 uint32_t scratch_waves;
690 uint32_t dispatch_initiator;
691
692 uint32_t gs_table_depth;
693
694 /* MSAA sample locations.
695 * The first index is the sample index.
696 * The second index is the coordinate: X, Y. */
697 float sample_locations_1x[1][2];
698 float sample_locations_2x[2][2];
699 float sample_locations_4x[4][2];
700 float sample_locations_8x[8][2];
701 float sample_locations_16x[16][2];
702
703 /* CIK and later */
704 uint32_t gfx_init_size_dw;
705 struct radeon_winsys_bo *gfx_init;
706
707 struct radeon_winsys_bo *trace_bo;
708 uint32_t *trace_id_ptr;
709
710 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
711 bool keep_shader_info;
712
713 struct radv_physical_device *physical_device;
714
715 /* Backup in-memory cache to be used if the app doesn't provide one */
716 struct radv_pipeline_cache * mem_cache;
717
718 /*
719 * use different counters so MSAA MRTs get consecutive surface indices,
720 * even if MASK is allocated in between.
721 */
722 uint32_t image_mrt_offset_counter;
723 uint32_t fmask_mrt_offset_counter;
724 struct list_head shader_slabs;
725 mtx_t shader_slab_mutex;
726
727 /* For detecting VM faults reported by dmesg. */
728 uint64_t dmesg_timestamp;
729
730 struct radv_device_extension_table enabled_extensions;
731
732 /* Whether the driver uses a global BO list. */
733 bool use_global_bo_list;
734
735 struct radv_bo_list bo_list;
736
737 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
738 int force_aniso;
739 };
740
741 struct radv_device_memory {
742 struct radeon_winsys_bo *bo;
743 /* for dedicated allocations */
744 struct radv_image *image;
745 struct radv_buffer *buffer;
746 uint32_t type_index;
747 VkDeviceSize map_size;
748 void * map;
749 void * user_ptr;
750 };
751
752
753 struct radv_descriptor_range {
754 uint64_t va;
755 uint32_t size;
756 };
757
758 struct radv_descriptor_set {
759 const struct radv_descriptor_set_layout *layout;
760 uint32_t size;
761
762 struct radeon_winsys_bo *bo;
763 uint64_t va;
764 uint32_t *mapped_ptr;
765 struct radv_descriptor_range *dynamic_descriptors;
766
767 struct radeon_winsys_bo *descriptors[0];
768 };
769
770 struct radv_push_descriptor_set
771 {
772 struct radv_descriptor_set set;
773 uint32_t capacity;
774 };
775
776 struct radv_descriptor_pool_entry {
777 uint32_t offset;
778 uint32_t size;
779 struct radv_descriptor_set *set;
780 };
781
782 struct radv_descriptor_pool {
783 struct radeon_winsys_bo *bo;
784 uint8_t *mapped_ptr;
785 uint64_t current_offset;
786 uint64_t size;
787
788 uint8_t *host_memory_base;
789 uint8_t *host_memory_ptr;
790 uint8_t *host_memory_end;
791
792 uint32_t entry_count;
793 uint32_t max_entry_count;
794 struct radv_descriptor_pool_entry entries[0];
795 };
796
797 struct radv_descriptor_update_template_entry {
798 VkDescriptorType descriptor_type;
799
800 /* The number of descriptors to update */
801 uint32_t descriptor_count;
802
803 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
804 uint32_t dst_offset;
805
806 /* In dwords. Not valid/used for dynamic descriptors */
807 uint32_t dst_stride;
808
809 uint32_t buffer_offset;
810
811 /* Only valid for combined image samplers and samplers */
812 uint16_t has_sampler;
813
814 /* In bytes */
815 size_t src_offset;
816 size_t src_stride;
817
818 /* For push descriptors */
819 const uint32_t *immutable_samplers;
820 };
821
822 struct radv_descriptor_update_template {
823 uint32_t entry_count;
824 VkPipelineBindPoint bind_point;
825 struct radv_descriptor_update_template_entry entry[0];
826 };
827
828 struct radv_buffer {
829 VkDeviceSize size;
830
831 VkBufferUsageFlags usage;
832 VkBufferCreateFlags flags;
833
834 /* Set when bound */
835 struct radeon_winsys_bo * bo;
836 VkDeviceSize offset;
837
838 bool shareable;
839 };
840
841 enum radv_dynamic_state_bits {
842 RADV_DYNAMIC_VIEWPORT = 1 << 0,
843 RADV_DYNAMIC_SCISSOR = 1 << 1,
844 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
845 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
846 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
847 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
848 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
849 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
850 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
851 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
852 RADV_DYNAMIC_ALL = (1 << 10) - 1,
853 };
854
855 enum radv_cmd_dirty_bits {
856 /* Keep the dynamic state dirty bits in sync with
857 * enum radv_dynamic_state_bits */
858 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
859 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
860 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
861 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
862 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
863 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
864 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
865 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
866 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
867 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
868 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
869 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
870 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
871 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
872 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
873 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 14,
874 };
875
876 enum radv_cmd_flush_bits {
877 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
878 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
879 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
880 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
881 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
882 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
883 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
884 /* Same as above, but only writes back and doesn't invalidate */
885 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
886 /* Framebuffer caches */
887 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
888 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
889 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
890 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
891 /* Engine synchronization. */
892 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
893 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
894 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
895 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
896 /* Pipeline query controls. */
897 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
898 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
899 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
900
901 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
902 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
903 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
904 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
905 };
906
907 struct radv_vertex_binding {
908 struct radv_buffer * buffer;
909 VkDeviceSize offset;
910 };
911
912 struct radv_streamout_binding {
913 struct radv_buffer *buffer;
914 VkDeviceSize offset;
915 VkDeviceSize size;
916 };
917
918 struct radv_streamout_state {
919 /* Mask of bound streamout buffers. */
920 uint8_t enabled_mask;
921
922 /* External state that comes from the last vertex stage, it must be
923 * set explicitely when binding a new graphics pipeline.
924 */
925 uint16_t stride_in_dw[MAX_SO_BUFFERS];
926 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
927
928 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
929 uint32_t hw_enabled_mask;
930
931 /* State of VGT_STRMOUT_(CONFIG|EN) */
932 bool streamout_enabled;
933 };
934
935 struct radv_viewport_state {
936 uint32_t count;
937 VkViewport viewports[MAX_VIEWPORTS];
938 };
939
940 struct radv_scissor_state {
941 uint32_t count;
942 VkRect2D scissors[MAX_SCISSORS];
943 };
944
945 struct radv_discard_rectangle_state {
946 uint32_t count;
947 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
948 };
949
950 struct radv_dynamic_state {
951 /**
952 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
953 * Defines the set of saved dynamic state.
954 */
955 uint32_t mask;
956
957 struct radv_viewport_state viewport;
958
959 struct radv_scissor_state scissor;
960
961 float line_width;
962
963 struct {
964 float bias;
965 float clamp;
966 float slope;
967 } depth_bias;
968
969 float blend_constants[4];
970
971 struct {
972 float min;
973 float max;
974 } depth_bounds;
975
976 struct {
977 uint32_t front;
978 uint32_t back;
979 } stencil_compare_mask;
980
981 struct {
982 uint32_t front;
983 uint32_t back;
984 } stencil_write_mask;
985
986 struct {
987 uint32_t front;
988 uint32_t back;
989 } stencil_reference;
990
991 struct radv_discard_rectangle_state discard_rectangle;
992 };
993
994 extern const struct radv_dynamic_state default_dynamic_state;
995
996 const char *
997 radv_get_debug_option_name(int id);
998
999 const char *
1000 radv_get_perftest_option_name(int id);
1001
1002 /**
1003 * Attachment state when recording a renderpass instance.
1004 *
1005 * The clear value is valid only if there exists a pending clear.
1006 */
1007 struct radv_attachment_state {
1008 VkImageAspectFlags pending_clear_aspects;
1009 uint32_t cleared_views;
1010 VkClearValue clear_value;
1011 VkImageLayout current_layout;
1012 };
1013
1014 struct radv_descriptor_state {
1015 struct radv_descriptor_set *sets[MAX_SETS];
1016 uint32_t dirty;
1017 uint32_t valid;
1018 struct radv_push_descriptor_set push_set;
1019 bool push_dirty;
1020 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1021 };
1022
1023 struct radv_cmd_state {
1024 /* Vertex descriptors */
1025 uint64_t vb_va;
1026 unsigned vb_size;
1027
1028 bool predicating;
1029 uint32_t dirty;
1030
1031 uint32_t prefetch_L2_mask;
1032
1033 struct radv_pipeline * pipeline;
1034 struct radv_pipeline * emitted_pipeline;
1035 struct radv_pipeline * compute_pipeline;
1036 struct radv_pipeline * emitted_compute_pipeline;
1037 struct radv_framebuffer * framebuffer;
1038 struct radv_render_pass * pass;
1039 const struct radv_subpass * subpass;
1040 struct radv_dynamic_state dynamic;
1041 struct radv_attachment_state * attachments;
1042 struct radv_streamout_state streamout;
1043 VkRect2D render_area;
1044
1045 /* Index buffer */
1046 struct radv_buffer *index_buffer;
1047 uint64_t index_offset;
1048 uint32_t index_type;
1049 uint32_t max_index_count;
1050 uint64_t index_va;
1051 int32_t last_index_type;
1052
1053 int32_t last_primitive_reset_en;
1054 uint32_t last_primitive_reset_index;
1055 enum radv_cmd_flush_bits flush_bits;
1056 unsigned active_occlusion_queries;
1057 bool perfect_occlusion_queries_enabled;
1058 unsigned active_pipeline_queries;
1059 float offset_scale;
1060 uint32_t trace_id;
1061 uint32_t last_ia_multi_vgt_param;
1062
1063 uint32_t last_num_instances;
1064 uint32_t last_first_instance;
1065 uint32_t last_vertex_offset;
1066
1067 /* Whether CP DMA is busy/idle. */
1068 bool dma_is_busy;
1069
1070 /* Conditional rendering info. */
1071 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1072 uint64_t predication_va;
1073
1074 bool context_roll_without_scissor_emitted;
1075 };
1076
1077 struct radv_cmd_pool {
1078 VkAllocationCallbacks alloc;
1079 struct list_head cmd_buffers;
1080 struct list_head free_cmd_buffers;
1081 uint32_t queue_family_index;
1082 };
1083
1084 struct radv_cmd_buffer_upload {
1085 uint8_t *map;
1086 unsigned offset;
1087 uint64_t size;
1088 struct radeon_winsys_bo *upload_bo;
1089 struct list_head list;
1090 };
1091
1092 enum radv_cmd_buffer_status {
1093 RADV_CMD_BUFFER_STATUS_INVALID,
1094 RADV_CMD_BUFFER_STATUS_INITIAL,
1095 RADV_CMD_BUFFER_STATUS_RECORDING,
1096 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1097 RADV_CMD_BUFFER_STATUS_PENDING,
1098 };
1099
1100 struct radv_cmd_buffer {
1101 VK_LOADER_DATA _loader_data;
1102
1103 struct radv_device * device;
1104
1105 struct radv_cmd_pool * pool;
1106 struct list_head pool_link;
1107
1108 VkCommandBufferUsageFlags usage_flags;
1109 VkCommandBufferLevel level;
1110 enum radv_cmd_buffer_status status;
1111 struct radeon_cmdbuf *cs;
1112 struct radv_cmd_state state;
1113 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1114 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1115 uint32_t queue_family_index;
1116
1117 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1118 VkShaderStageFlags push_constant_stages;
1119 struct radv_descriptor_set meta_push_descriptors;
1120
1121 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1122
1123 struct radv_cmd_buffer_upload upload;
1124
1125 uint32_t scratch_size_needed;
1126 uint32_t compute_scratch_size_needed;
1127 uint32_t esgs_ring_size_needed;
1128 uint32_t gsvs_ring_size_needed;
1129 bool tess_rings_needed;
1130 bool sample_positions_needed;
1131
1132 VkResult record_result;
1133
1134 uint64_t gfx9_fence_va;
1135 uint32_t gfx9_fence_idx;
1136 uint64_t gfx9_eop_bug_va;
1137
1138 /**
1139 * Whether a query pool has been resetted and we have to flush caches.
1140 */
1141 bool pending_reset_query;
1142 };
1143
1144 struct radv_image;
1145
1146 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1147
1148 void si_emit_graphics(struct radv_physical_device *physical_device,
1149 struct radeon_cmdbuf *cs);
1150 void si_emit_compute(struct radv_physical_device *physical_device,
1151 struct radeon_cmdbuf *cs);
1152
1153 void cik_create_gfx_config(struct radv_device *device);
1154
1155 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1156 int count, const VkViewport *viewports);
1157 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1158 int count, const VkRect2D *scissors,
1159 const VkViewport *viewports, bool can_use_guardband);
1160 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1161 bool instanced_draw, bool indirect_draw,
1162 uint32_t draw_vertex_count);
1163 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1164 enum chip_class chip_class,
1165 bool is_mec,
1166 unsigned event, unsigned event_flags,
1167 unsigned data_sel,
1168 uint64_t va,
1169 uint32_t new_fence,
1170 uint64_t gfx9_eop_bug_va);
1171
1172 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1173 uint32_t ref, uint32_t mask);
1174 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1175 enum chip_class chip_class,
1176 uint32_t *fence_ptr, uint64_t va,
1177 bool is_mec,
1178 enum radv_cmd_flush_bits flush_bits,
1179 uint64_t gfx9_eop_bug_va);
1180 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1181 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1182 bool inverted, uint64_t va);
1183 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1184 uint64_t src_va, uint64_t dest_va,
1185 uint64_t size);
1186 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1187 unsigned size);
1188 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1189 uint64_t size, unsigned value);
1190 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1191
1192 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1193 bool
1194 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1195 unsigned size,
1196 unsigned alignment,
1197 unsigned *out_offset,
1198 void **ptr);
1199 void
1200 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1201 const struct radv_subpass *subpass);
1202 bool
1203 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1204 unsigned size, unsigned alignmnet,
1205 const void *data, unsigned *out_offset);
1206
1207 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1208 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1209 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1210 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1211 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
1212 unsigned radv_cayman_get_maxdist(int log_samples);
1213 void radv_device_init_msaa(struct radv_device *device);
1214
1215 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1216 struct radv_image *image,
1217 VkClearDepthStencilValue ds_clear_value,
1218 VkImageAspectFlags aspects);
1219
1220 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1221 struct radv_image *image,
1222 int cb_idx,
1223 uint32_t color_values[2]);
1224
1225 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1226 struct radv_image *image, bool value);
1227
1228 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1229 struct radv_image *image, bool value);
1230
1231 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1232 struct radeon_winsys_bo *bo,
1233 uint64_t offset, uint64_t size, uint32_t value);
1234 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1235 bool radv_get_memory_fd(struct radv_device *device,
1236 struct radv_device_memory *memory,
1237 int *pFD);
1238
1239 static inline void
1240 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1241 unsigned sh_offset, unsigned pointer_count,
1242 bool use_32bit_pointers)
1243 {
1244 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1245 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1246 }
1247
1248 static inline void
1249 radv_emit_shader_pointer_body(struct radv_device *device,
1250 struct radeon_cmdbuf *cs,
1251 uint64_t va, bool use_32bit_pointers)
1252 {
1253 radeon_emit(cs, va);
1254
1255 if (use_32bit_pointers) {
1256 assert(va == 0 ||
1257 (va >> 32) == device->physical_device->rad_info.address32_hi);
1258 } else {
1259 radeon_emit(cs, va >> 32);
1260 }
1261 }
1262
1263 static inline void
1264 radv_emit_shader_pointer(struct radv_device *device,
1265 struct radeon_cmdbuf *cs,
1266 uint32_t sh_offset, uint64_t va, bool global)
1267 {
1268 bool use_32bit_pointers = !global;
1269
1270 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1271 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1272 }
1273
1274 static inline struct radv_descriptor_state *
1275 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1276 VkPipelineBindPoint bind_point)
1277 {
1278 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1279 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1280 return &cmd_buffer->descriptors[bind_point];
1281 }
1282
1283 /*
1284 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1285 *
1286 * Limitations: Can't call normal dispatch functions without binding or rebinding
1287 * the compute pipeline.
1288 */
1289 void radv_unaligned_dispatch(
1290 struct radv_cmd_buffer *cmd_buffer,
1291 uint32_t x,
1292 uint32_t y,
1293 uint32_t z);
1294
1295 struct radv_event {
1296 struct radeon_winsys_bo *bo;
1297 uint64_t *map;
1298 };
1299
1300 struct radv_shader_module;
1301
1302 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1303 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1304 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1305 void
1306 radv_hash_shaders(unsigned char *hash,
1307 const VkPipelineShaderStageCreateInfo **stages,
1308 const struct radv_pipeline_layout *layout,
1309 const struct radv_pipeline_key *key,
1310 uint32_t flags);
1311
1312 static inline gl_shader_stage
1313 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1314 {
1315 assert(__builtin_popcount(vk_stage) == 1);
1316 return ffs(vk_stage) - 1;
1317 }
1318
1319 static inline VkShaderStageFlagBits
1320 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1321 {
1322 return (1 << mesa_stage);
1323 }
1324
1325 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1326
1327 #define radv_foreach_stage(stage, stage_bits) \
1328 for (gl_shader_stage stage, \
1329 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1330 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1331 __tmp &= ~(1 << (stage)))
1332
1333 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1334 unsigned radv_format_meta_fs_key(VkFormat format);
1335
1336 struct radv_multisample_state {
1337 uint32_t db_eqaa;
1338 uint32_t pa_sc_line_cntl;
1339 uint32_t pa_sc_mode_cntl_0;
1340 uint32_t pa_sc_mode_cntl_1;
1341 uint32_t pa_sc_aa_config;
1342 uint32_t pa_sc_aa_mask[2];
1343 unsigned num_samples;
1344 };
1345
1346 struct radv_prim_vertex_count {
1347 uint8_t min;
1348 uint8_t incr;
1349 };
1350
1351 struct radv_vertex_elements_info {
1352 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1353 };
1354
1355 struct radv_ia_multi_vgt_param_helpers {
1356 uint32_t base;
1357 bool partial_es_wave;
1358 uint8_t primgroup_size;
1359 bool wd_switch_on_eop;
1360 bool ia_switch_on_eoi;
1361 bool partial_vs_wave;
1362 };
1363
1364 #define SI_GS_PER_ES 128
1365
1366 struct radv_pipeline {
1367 struct radv_device * device;
1368 struct radv_dynamic_state dynamic_state;
1369
1370 struct radv_pipeline_layout * layout;
1371
1372 bool need_indirect_descriptor_sets;
1373 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1374 struct radv_shader_variant *gs_copy_shader;
1375 VkShaderStageFlags active_stages;
1376
1377 struct radeon_cmdbuf cs;
1378 uint32_t ctx_cs_hash;
1379 struct radeon_cmdbuf ctx_cs;
1380
1381 struct radv_vertex_elements_info vertex_elements;
1382
1383 uint32_t binding_stride[MAX_VBS];
1384 uint8_t num_vertex_bindings;
1385
1386 uint32_t user_data_0[MESA_SHADER_STAGES];
1387 union {
1388 struct {
1389 struct radv_multisample_state ms;
1390 uint32_t spi_baryc_cntl;
1391 bool prim_restart_enable;
1392 unsigned esgs_ring_size;
1393 unsigned gsvs_ring_size;
1394 uint32_t vtx_base_sgpr;
1395 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1396 uint8_t vtx_emit_num;
1397 struct radv_prim_vertex_count prim_vertex_count;
1398 bool can_use_guardband;
1399 uint32_t needed_dynamic_state;
1400 bool disable_out_of_order_rast_for_occlusion;
1401
1402 /* Used for rbplus */
1403 uint32_t col_format;
1404 uint32_t cb_target_mask;
1405 } graphics;
1406 };
1407
1408 unsigned max_waves;
1409 unsigned scratch_bytes_per_wave;
1410
1411 /* Not NULL if graphics pipeline uses streamout. */
1412 struct radv_shader_variant *streamout_shader;
1413 };
1414
1415 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1416 {
1417 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1418 }
1419
1420 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1421 {
1422 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1423 }
1424
1425 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1426 gl_shader_stage stage,
1427 int idx);
1428
1429 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1430 gl_shader_stage stage);
1431
1432 struct radv_graphics_pipeline_create_info {
1433 bool use_rectlist;
1434 bool db_depth_clear;
1435 bool db_stencil_clear;
1436 bool db_depth_disable_expclear;
1437 bool db_stencil_disable_expclear;
1438 bool db_flush_depth_inplace;
1439 bool db_flush_stencil_inplace;
1440 bool db_resummarize;
1441 uint32_t custom_blend_mode;
1442 };
1443
1444 VkResult
1445 radv_graphics_pipeline_create(VkDevice device,
1446 VkPipelineCache cache,
1447 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1448 const struct radv_graphics_pipeline_create_info *extra,
1449 const VkAllocationCallbacks *alloc,
1450 VkPipeline *pPipeline);
1451
1452 struct vk_format_description;
1453 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1454 int first_non_void);
1455 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1456 int first_non_void);
1457 uint32_t radv_translate_colorformat(VkFormat format);
1458 uint32_t radv_translate_color_numformat(VkFormat format,
1459 const struct vk_format_description *desc,
1460 int first_non_void);
1461 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1462 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1463 uint32_t radv_translate_dbformat(VkFormat format);
1464 uint32_t radv_translate_tex_dataformat(VkFormat format,
1465 const struct vk_format_description *desc,
1466 int first_non_void);
1467 uint32_t radv_translate_tex_numformat(VkFormat format,
1468 const struct vk_format_description *desc,
1469 int first_non_void);
1470 bool radv_format_pack_clear_color(VkFormat format,
1471 uint32_t clear_vals[2],
1472 VkClearColorValue *value);
1473 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1474 bool radv_dcc_formats_compatible(VkFormat format1,
1475 VkFormat format2);
1476 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
1477
1478 struct radv_fmask_info {
1479 uint64_t offset;
1480 uint64_t size;
1481 unsigned alignment;
1482 unsigned pitch_in_pixels;
1483 unsigned bank_height;
1484 unsigned slice_tile_max;
1485 unsigned tile_mode_index;
1486 unsigned tile_swizzle;
1487 };
1488
1489 struct radv_cmask_info {
1490 uint64_t offset;
1491 uint64_t size;
1492 unsigned alignment;
1493 unsigned slice_tile_max;
1494 };
1495
1496
1497 struct radv_image_plane {
1498 VkFormat format;
1499 struct radeon_surf surface;
1500 uint64_t offset;
1501 };
1502
1503 struct radv_image {
1504 VkImageType type;
1505 /* The original VkFormat provided by the client. This may not match any
1506 * of the actual surface formats.
1507 */
1508 VkFormat vk_format;
1509 VkImageAspectFlags aspects;
1510 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1511 struct ac_surf_info info;
1512 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1513 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1514
1515 VkDeviceSize size;
1516 uint32_t alignment;
1517
1518 unsigned queue_family_mask;
1519 bool exclusive;
1520 bool shareable;
1521
1522 /* Set when bound */
1523 struct radeon_winsys_bo *bo;
1524 VkDeviceSize offset;
1525 uint64_t dcc_offset;
1526 uint64_t htile_offset;
1527 bool tc_compatible_htile;
1528
1529 struct radv_fmask_info fmask;
1530 struct radv_cmask_info cmask;
1531 uint64_t clear_value_offset;
1532 uint64_t fce_pred_offset;
1533 uint64_t dcc_pred_offset;
1534
1535 /*
1536 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1537 * stored at this offset is UINT_MAX, the driver will emit
1538 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1539 * SET_CONTEXT_REG packet.
1540 */
1541 uint64_t tc_compat_zrange_offset;
1542
1543 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1544 VkDeviceMemory owned_memory;
1545
1546 unsigned plane_count;
1547 struct radv_image_plane planes[0];
1548 };
1549
1550 /* Whether the image has a htile that is known consistent with the contents of
1551 * the image. */
1552 bool radv_layout_has_htile(const struct radv_image *image,
1553 VkImageLayout layout,
1554 unsigned queue_mask);
1555
1556 /* Whether the image has a htile that is known consistent with the contents of
1557 * the image and is allowed to be in compressed form.
1558 *
1559 * If this is false reads that don't use the htile should be able to return
1560 * correct results.
1561 */
1562 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1563 VkImageLayout layout,
1564 unsigned queue_mask);
1565
1566 bool radv_layout_can_fast_clear(const struct radv_image *image,
1567 VkImageLayout layout,
1568 unsigned queue_mask);
1569
1570 bool radv_layout_dcc_compressed(const struct radv_image *image,
1571 VkImageLayout layout,
1572 unsigned queue_mask);
1573
1574 /**
1575 * Return whether the image has CMASK metadata for color surfaces.
1576 */
1577 static inline bool
1578 radv_image_has_cmask(const struct radv_image *image)
1579 {
1580 return image->cmask.size;
1581 }
1582
1583 /**
1584 * Return whether the image has FMASK metadata for color surfaces.
1585 */
1586 static inline bool
1587 radv_image_has_fmask(const struct radv_image *image)
1588 {
1589 return image->fmask.size;
1590 }
1591
1592 /**
1593 * Return whether the image has DCC metadata for color surfaces.
1594 */
1595 static inline bool
1596 radv_image_has_dcc(const struct radv_image *image)
1597 {
1598 return image->planes[0].surface.dcc_size;
1599 }
1600
1601 /**
1602 * Return whether DCC metadata is enabled for a level.
1603 */
1604 static inline bool
1605 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1606 {
1607 return radv_image_has_dcc(image) &&
1608 level < image->planes[0].surface.num_dcc_levels;
1609 }
1610
1611 /**
1612 * Return whether the image has CB metadata.
1613 */
1614 static inline bool
1615 radv_image_has_CB_metadata(const struct radv_image *image)
1616 {
1617 return radv_image_has_cmask(image) ||
1618 radv_image_has_fmask(image) ||
1619 radv_image_has_dcc(image);
1620 }
1621
1622 /**
1623 * Return whether the image has HTILE metadata for depth surfaces.
1624 */
1625 static inline bool
1626 radv_image_has_htile(const struct radv_image *image)
1627 {
1628 return image->planes[0].surface.htile_size;
1629 }
1630
1631 /**
1632 * Return whether HTILE metadata is enabled for a level.
1633 */
1634 static inline bool
1635 radv_htile_enabled(const struct radv_image *image, unsigned level)
1636 {
1637 return radv_image_has_htile(image) && level == 0;
1638 }
1639
1640 /**
1641 * Return whether the image is TC-compatible HTILE.
1642 */
1643 static inline bool
1644 radv_image_is_tc_compat_htile(const struct radv_image *image)
1645 {
1646 return radv_image_has_htile(image) && image->tc_compatible_htile;
1647 }
1648
1649 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1650
1651 static inline uint32_t
1652 radv_get_layerCount(const struct radv_image *image,
1653 const VkImageSubresourceRange *range)
1654 {
1655 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1656 image->info.array_size - range->baseArrayLayer : range->layerCount;
1657 }
1658
1659 static inline uint32_t
1660 radv_get_levelCount(const struct radv_image *image,
1661 const VkImageSubresourceRange *range)
1662 {
1663 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1664 image->info.levels - range->baseMipLevel : range->levelCount;
1665 }
1666
1667 struct radeon_bo_metadata;
1668 void
1669 radv_init_metadata(struct radv_device *device,
1670 struct radv_image *image,
1671 struct radeon_bo_metadata *metadata);
1672
1673 union radv_descriptor {
1674 struct {
1675 uint32_t plane0_descriptor[8];
1676 uint32_t fmask_descriptor[8];
1677 };
1678 struct {
1679 uint32_t plane_descriptors[3][8];
1680 };
1681 };
1682
1683 struct radv_image_view {
1684 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1685 struct radeon_winsys_bo *bo;
1686
1687 VkImageViewType type;
1688 VkImageAspectFlags aspect_mask;
1689 VkFormat vk_format;
1690 unsigned plane_id;
1691 bool multiple_planes;
1692 uint32_t base_layer;
1693 uint32_t layer_count;
1694 uint32_t base_mip;
1695 uint32_t level_count;
1696 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1697
1698 union radv_descriptor descriptor;
1699
1700 /* Descriptor for use as a storage image as opposed to a sampled image.
1701 * This has a few differences for cube maps (e.g. type).
1702 */
1703 union radv_descriptor storage_descriptor;
1704 };
1705
1706 struct radv_image_create_info {
1707 const VkImageCreateInfo *vk_info;
1708 bool scanout;
1709 bool no_metadata_planes;
1710 };
1711
1712 VkResult radv_image_create(VkDevice _device,
1713 const struct radv_image_create_info *info,
1714 const VkAllocationCallbacks* alloc,
1715 VkImage *pImage);
1716
1717 VkResult
1718 radv_image_from_gralloc(VkDevice device_h,
1719 const VkImageCreateInfo *base_info,
1720 const VkNativeBufferANDROID *gralloc_info,
1721 const VkAllocationCallbacks *alloc,
1722 VkImage *out_image_h);
1723
1724 void radv_image_view_init(struct radv_image_view *view,
1725 struct radv_device *device,
1726 const VkImageViewCreateInfo* pCreateInfo);
1727
1728 VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
1729
1730 struct radv_sampler_ycbcr_conversion {
1731 VkFormat format;
1732 VkSamplerYcbcrModelConversion ycbcr_model;
1733 VkSamplerYcbcrRange ycbcr_range;
1734 VkComponentMapping components;
1735 VkChromaLocation chroma_offsets[2];
1736 VkFilter chroma_filter;
1737 };
1738
1739 struct radv_buffer_view {
1740 struct radeon_winsys_bo *bo;
1741 VkFormat vk_format;
1742 uint64_t range; /**< VkBufferViewCreateInfo::range */
1743 uint32_t state[4];
1744 };
1745 void radv_buffer_view_init(struct radv_buffer_view *view,
1746 struct radv_device *device,
1747 const VkBufferViewCreateInfo* pCreateInfo);
1748
1749 static inline struct VkExtent3D
1750 radv_sanitize_image_extent(const VkImageType imageType,
1751 const struct VkExtent3D imageExtent)
1752 {
1753 switch (imageType) {
1754 case VK_IMAGE_TYPE_1D:
1755 return (VkExtent3D) { imageExtent.width, 1, 1 };
1756 case VK_IMAGE_TYPE_2D:
1757 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1758 case VK_IMAGE_TYPE_3D:
1759 return imageExtent;
1760 default:
1761 unreachable("invalid image type");
1762 }
1763 }
1764
1765 static inline struct VkOffset3D
1766 radv_sanitize_image_offset(const VkImageType imageType,
1767 const struct VkOffset3D imageOffset)
1768 {
1769 switch (imageType) {
1770 case VK_IMAGE_TYPE_1D:
1771 return (VkOffset3D) { imageOffset.x, 0, 0 };
1772 case VK_IMAGE_TYPE_2D:
1773 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1774 case VK_IMAGE_TYPE_3D:
1775 return imageOffset;
1776 default:
1777 unreachable("invalid image type");
1778 }
1779 }
1780
1781 static inline bool
1782 radv_image_extent_compare(const struct radv_image *image,
1783 const VkExtent3D *extent)
1784 {
1785 if (extent->width != image->info.width ||
1786 extent->height != image->info.height ||
1787 extent->depth != image->info.depth)
1788 return false;
1789 return true;
1790 }
1791
1792 struct radv_sampler {
1793 uint32_t state[4];
1794 struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
1795 };
1796
1797 struct radv_color_buffer_info {
1798 uint64_t cb_color_base;
1799 uint64_t cb_color_cmask;
1800 uint64_t cb_color_fmask;
1801 uint64_t cb_dcc_base;
1802 uint32_t cb_color_slice;
1803 uint32_t cb_color_view;
1804 uint32_t cb_color_info;
1805 uint32_t cb_color_attrib;
1806 uint32_t cb_color_attrib2;
1807 uint32_t cb_dcc_control;
1808 uint32_t cb_color_cmask_slice;
1809 uint32_t cb_color_fmask_slice;
1810 union {
1811 uint32_t cb_color_pitch; // GFX6-GFX8
1812 uint32_t cb_mrt_epitch; // GFX9+
1813 };
1814 };
1815
1816 struct radv_ds_buffer_info {
1817 uint64_t db_z_read_base;
1818 uint64_t db_stencil_read_base;
1819 uint64_t db_z_write_base;
1820 uint64_t db_stencil_write_base;
1821 uint64_t db_htile_data_base;
1822 uint32_t db_depth_info;
1823 uint32_t db_z_info;
1824 uint32_t db_stencil_info;
1825 uint32_t db_depth_view;
1826 uint32_t db_depth_size;
1827 uint32_t db_depth_slice;
1828 uint32_t db_htile_surface;
1829 uint32_t pa_su_poly_offset_db_fmt_cntl;
1830 uint32_t db_z_info2;
1831 uint32_t db_stencil_info2;
1832 float offset_scale;
1833 };
1834
1835 struct radv_attachment_info {
1836 union {
1837 struct radv_color_buffer_info cb;
1838 struct radv_ds_buffer_info ds;
1839 };
1840 struct radv_image_view *attachment;
1841 };
1842
1843 struct radv_framebuffer {
1844 uint32_t width;
1845 uint32_t height;
1846 uint32_t layers;
1847
1848 uint32_t attachment_count;
1849 struct radv_attachment_info attachments[0];
1850 };
1851
1852 struct radv_subpass_barrier {
1853 VkPipelineStageFlags src_stage_mask;
1854 VkAccessFlags src_access_mask;
1855 VkAccessFlags dst_access_mask;
1856 };
1857
1858 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1859 const struct radv_subpass_barrier *barrier);
1860
1861 struct radv_subpass_attachment {
1862 uint32_t attachment;
1863 VkImageLayout layout;
1864 };
1865
1866 struct radv_subpass {
1867 uint32_t attachment_count;
1868 struct radv_subpass_attachment * attachments;
1869
1870 uint32_t input_count;
1871 uint32_t color_count;
1872 struct radv_subpass_attachment * input_attachments;
1873 struct radv_subpass_attachment * color_attachments;
1874 struct radv_subpass_attachment * resolve_attachments;
1875 struct radv_subpass_attachment * depth_stencil_attachment;
1876
1877 /** Subpass has at least one resolve attachment */
1878 bool has_resolve;
1879
1880 /** Subpass has at least one color attachment */
1881 bool has_color_att;
1882
1883 struct radv_subpass_barrier start_barrier;
1884
1885 uint32_t view_mask;
1886 VkSampleCountFlagBits max_sample_count;
1887 };
1888
1889 struct radv_render_pass_attachment {
1890 VkFormat format;
1891 uint32_t samples;
1892 VkAttachmentLoadOp load_op;
1893 VkAttachmentLoadOp stencil_load_op;
1894 VkImageLayout initial_layout;
1895 VkImageLayout final_layout;
1896
1897 /* The subpass id in which the attachment will be used last. */
1898 uint32_t last_subpass_idx;
1899 };
1900
1901 struct radv_render_pass {
1902 uint32_t attachment_count;
1903 uint32_t subpass_count;
1904 struct radv_subpass_attachment * subpass_attachments;
1905 struct radv_render_pass_attachment * attachments;
1906 struct radv_subpass_barrier end_barrier;
1907 struct radv_subpass subpasses[0];
1908 };
1909
1910 VkResult radv_device_init_meta(struct radv_device *device);
1911 void radv_device_finish_meta(struct radv_device *device);
1912
1913 struct radv_query_pool {
1914 struct radeon_winsys_bo *bo;
1915 uint32_t stride;
1916 uint32_t availability_offset;
1917 uint64_t size;
1918 char *ptr;
1919 VkQueryType type;
1920 uint32_t pipeline_stats_mask;
1921 };
1922
1923 struct radv_semaphore {
1924 /* use a winsys sem for non-exportable */
1925 struct radeon_winsys_sem *sem;
1926 uint32_t syncobj;
1927 uint32_t temp_syncobj;
1928 };
1929
1930 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1931 VkPipelineBindPoint bind_point,
1932 struct radv_descriptor_set *set,
1933 unsigned idx);
1934
1935 void
1936 radv_update_descriptor_sets(struct radv_device *device,
1937 struct radv_cmd_buffer *cmd_buffer,
1938 VkDescriptorSet overrideSet,
1939 uint32_t descriptorWriteCount,
1940 const VkWriteDescriptorSet *pDescriptorWrites,
1941 uint32_t descriptorCopyCount,
1942 const VkCopyDescriptorSet *pDescriptorCopies);
1943
1944 void
1945 radv_update_descriptor_set_with_template(struct radv_device *device,
1946 struct radv_cmd_buffer *cmd_buffer,
1947 struct radv_descriptor_set *set,
1948 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1949 const void *pData);
1950
1951 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1952 VkPipelineBindPoint pipelineBindPoint,
1953 VkPipelineLayout _layout,
1954 uint32_t set,
1955 uint32_t descriptorWriteCount,
1956 const VkWriteDescriptorSet *pDescriptorWrites);
1957
1958 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1959 struct radv_image *image, uint32_t value);
1960
1961 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
1962 struct radv_image *image);
1963
1964 struct radv_fence {
1965 struct radeon_winsys_fence *fence;
1966 struct wsi_fence *fence_wsi;
1967 bool submitted;
1968 bool signalled;
1969
1970 uint32_t syncobj;
1971 uint32_t temp_syncobj;
1972 };
1973
1974 /* radv_nir_to_llvm.c */
1975 struct radv_shader_variant_info;
1976 struct radv_nir_compiler_options;
1977
1978 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
1979 struct nir_shader *geom_shader,
1980 struct ac_shader_binary *binary,
1981 struct ac_shader_config *config,
1982 struct radv_shader_variant_info *shader_info,
1983 const struct radv_nir_compiler_options *option);
1984
1985 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
1986 struct ac_shader_binary *binary,
1987 struct ac_shader_config *config,
1988 struct radv_shader_variant_info *shader_info,
1989 struct nir_shader *const *nir,
1990 int nir_count,
1991 const struct radv_nir_compiler_options *options);
1992
1993 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
1994 const struct nir_shader *nir);
1995
1996 /* radv_shader_info.h */
1997 struct radv_shader_info;
1998
1999 void radv_nir_shader_info_pass(const struct nir_shader *nir,
2000 const struct radv_nir_compiler_options *options,
2001 struct radv_shader_info *info);
2002
2003 void radv_nir_shader_info_init(struct radv_shader_info *info);
2004
2005 struct radeon_winsys_sem;
2006
2007 uint64_t radv_get_current_time(void);
2008
2009 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2010 \
2011 static inline struct __radv_type * \
2012 __radv_type ## _from_handle(__VkType _handle) \
2013 { \
2014 return (struct __radv_type *) _handle; \
2015 } \
2016 \
2017 static inline __VkType \
2018 __radv_type ## _to_handle(struct __radv_type *_obj) \
2019 { \
2020 return (__VkType) _obj; \
2021 }
2022
2023 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2024 \
2025 static inline struct __radv_type * \
2026 __radv_type ## _from_handle(__VkType _handle) \
2027 { \
2028 return (struct __radv_type *)(uintptr_t) _handle; \
2029 } \
2030 \
2031 static inline __VkType \
2032 __radv_type ## _to_handle(struct __radv_type *_obj) \
2033 { \
2034 return (__VkType)(uintptr_t) _obj; \
2035 }
2036
2037 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2038 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2039
2040 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
2041 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
2042 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
2043 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
2044 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
2045
2046 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
2047 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
2048 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
2049 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
2050 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
2051 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
2052 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
2053 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
2054 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
2055 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
2056 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
2057 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
2058 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
2059 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
2060 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
2061 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2062 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2063 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2064 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2065 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
2066 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2067 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2068
2069 #endif /* RADV_PRIVATE_H */