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radv: remove old_fence parameter from si_cs_emit_write_event_eop()
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "ac_llvm_util.h"
62 #include "radv_descriptor_set.h"
63 #include "radv_extensions.h"
64 #include "radv_cs.h"
65
66 #include <llvm-c/TargetMachine.h>
67
68 /* Pre-declarations needed for WSI entrypoints */
69 struct wl_surface;
70 struct wl_display;
71 typedef struct xcb_connection_t xcb_connection_t;
72 typedef uint32_t xcb_visualid_t;
73 typedef uint32_t xcb_window_t;
74
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vk_icd.h>
78 #include <vulkan/vk_android_native_buffer.h>
79
80 #include "radv_entrypoints.h"
81
82 #include "wsi_common.h"
83 #include "wsi_common_display.h"
84
85 #define ATI_VENDOR_ID 0x1002
86
87 #define MAX_VBS 32
88 #define MAX_VERTEX_ATTRIBS 32
89 #define MAX_RTS 8
90 #define MAX_VIEWPORTS 16
91 #define MAX_SCISSORS 16
92 #define MAX_DISCARD_RECTANGLES 4
93 #define MAX_PUSH_CONSTANTS_SIZE 128
94 #define MAX_PUSH_DESCRIPTORS 32
95 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
96 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
97 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
98 #define MAX_SAMPLES_LOG2 4
99 #define NUM_META_FS_KEYS 12
100 #define RADV_MAX_DRM_DEVICES 8
101 #define MAX_VIEWS 8
102 #define MAX_SO_STREAMS 4
103 #define MAX_SO_BUFFERS 4
104 #define MAX_SO_OUTPUTS 64
105
106 #define NUM_DEPTH_CLEAR_PIPELINES 3
107
108 /*
109 * This is the point we switch from using CP to compute shader
110 * for certain buffer operations.
111 */
112 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
113
114 #define RADV_BUFFER_UPDATE_THRESHOLD 1024
115
116 enum radv_mem_heap {
117 RADV_MEM_HEAP_VRAM,
118 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
119 RADV_MEM_HEAP_GTT,
120 RADV_MEM_HEAP_COUNT
121 };
122
123 enum radv_mem_type {
124 RADV_MEM_TYPE_VRAM,
125 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
126 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
127 RADV_MEM_TYPE_GTT_CACHED,
128 RADV_MEM_TYPE_COUNT
129 };
130
131 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
132
133 static inline uint32_t
134 align_u32(uint32_t v, uint32_t a)
135 {
136 assert(a != 0 && a == (a & -a));
137 return (v + a - 1) & ~(a - 1);
138 }
139
140 static inline uint32_t
141 align_u32_npot(uint32_t v, uint32_t a)
142 {
143 return (v + a - 1) / a * a;
144 }
145
146 static inline uint64_t
147 align_u64(uint64_t v, uint64_t a)
148 {
149 assert(a != 0 && a == (a & -a));
150 return (v + a - 1) & ~(a - 1);
151 }
152
153 static inline int32_t
154 align_i32(int32_t v, int32_t a)
155 {
156 assert(a != 0 && a == (a & -a));
157 return (v + a - 1) & ~(a - 1);
158 }
159
160 /** Alignment must be a power of 2. */
161 static inline bool
162 radv_is_aligned(uintmax_t n, uintmax_t a)
163 {
164 assert(a == (a & -a));
165 return (n & (a - 1)) == 0;
166 }
167
168 static inline uint32_t
169 round_up_u32(uint32_t v, uint32_t a)
170 {
171 return (v + a - 1) / a;
172 }
173
174 static inline uint64_t
175 round_up_u64(uint64_t v, uint64_t a)
176 {
177 return (v + a - 1) / a;
178 }
179
180 static inline uint32_t
181 radv_minify(uint32_t n, uint32_t levels)
182 {
183 if (unlikely(n == 0))
184 return 0;
185 else
186 return MAX2(n >> levels, 1);
187 }
188 static inline float
189 radv_clamp_f(float f, float min, float max)
190 {
191 assert(min < max);
192
193 if (f > max)
194 return max;
195 else if (f < min)
196 return min;
197 else
198 return f;
199 }
200
201 static inline bool
202 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
203 {
204 if (*inout_mask & clear_mask) {
205 *inout_mask &= ~clear_mask;
206 return true;
207 } else {
208 return false;
209 }
210 }
211
212 #define for_each_bit(b, dword) \
213 for (uint32_t __dword = (dword); \
214 (b) = __builtin_ffs(__dword) - 1, __dword; \
215 __dword &= ~(1 << (b)))
216
217 #define typed_memcpy(dest, src, count) ({ \
218 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
219 memcpy((dest), (src), (count) * sizeof(*(src))); \
220 })
221
222 /* Whenever we generate an error, pass it through this function. Useful for
223 * debugging, where we can break on it. Only call at error site, not when
224 * propagating errors. Might be useful to plug in a stack trace here.
225 */
226
227 struct radv_instance;
228
229 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
230
231 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
232 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
233
234 void __radv_finishme(const char *file, int line, const char *format, ...)
235 radv_printflike(3, 4);
236 void radv_loge(const char *format, ...) radv_printflike(1, 2);
237 void radv_loge_v(const char *format, va_list va);
238 void radv_logi(const char *format, ...) radv_printflike(1, 2);
239 void radv_logi_v(const char *format, va_list va);
240
241 /**
242 * Print a FINISHME message, including its source location.
243 */
244 #define radv_finishme(format, ...) \
245 do { \
246 static bool reported = false; \
247 if (!reported) { \
248 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
249 reported = true; \
250 } \
251 } while (0)
252
253 /* A non-fatal assert. Useful for debugging. */
254 #ifdef DEBUG
255 #define radv_assert(x) ({ \
256 if (unlikely(!(x))) \
257 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
258 })
259 #else
260 #define radv_assert(x)
261 #endif
262
263 #define stub_return(v) \
264 do { \
265 radv_finishme("stub %s", __func__); \
266 return (v); \
267 } while (0)
268
269 #define stub() \
270 do { \
271 radv_finishme("stub %s", __func__); \
272 return; \
273 } while (0)
274
275 void *radv_lookup_entrypoint_unchecked(const char *name);
276 void *radv_lookup_entrypoint_checked(const char *name,
277 uint32_t core_version,
278 const struct radv_instance_extension_table *instance,
279 const struct radv_device_extension_table *device);
280
281 struct radv_physical_device {
282 VK_LOADER_DATA _loader_data;
283
284 struct radv_instance * instance;
285
286 struct radeon_winsys *ws;
287 struct radeon_info rad_info;
288 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
289 uint8_t driver_uuid[VK_UUID_SIZE];
290 uint8_t device_uuid[VK_UUID_SIZE];
291 uint8_t cache_uuid[VK_UUID_SIZE];
292
293 int local_fd;
294 int master_fd;
295 struct wsi_device wsi_device;
296
297 bool has_rbplus; /* if RB+ register exist */
298 bool rbplus_allowed; /* if RB+ is allowed */
299 bool has_clear_state;
300 bool cpdma_prefetch_writes_memory;
301 bool has_scissor_bug;
302
303 bool has_out_of_order_rast;
304 bool out_of_order_rast_allowed;
305
306 /* Whether DCC should be enabled for MSAA textures. */
307 bool dcc_msaa_allowed;
308
309 /* This is the drivers on-disk cache used as a fallback as opposed to
310 * the pipeline cache defined by apps.
311 */
312 struct disk_cache * disk_cache;
313
314 VkPhysicalDeviceMemoryProperties memory_properties;
315 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
316
317 drmPciBusInfo bus_info;
318
319 struct radv_device_extension_table supported_extensions;
320 };
321
322 struct radv_instance {
323 VK_LOADER_DATA _loader_data;
324
325 VkAllocationCallbacks alloc;
326
327 uint32_t apiVersion;
328 int physicalDeviceCount;
329 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
330
331 uint64_t debug_flags;
332 uint64_t perftest_flags;
333
334 struct vk_debug_report_instance debug_report_callbacks;
335
336 struct radv_instance_extension_table enabled_extensions;
337 };
338
339 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
340 void radv_finish_wsi(struct radv_physical_device *physical_device);
341
342 bool radv_instance_extension_supported(const char *name);
343 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
344 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
345 const char *name);
346
347 struct cache_entry;
348
349 struct radv_pipeline_cache {
350 struct radv_device * device;
351 pthread_mutex_t mutex;
352
353 uint32_t total_size;
354 uint32_t table_size;
355 uint32_t kernel_count;
356 struct cache_entry ** hash_table;
357 bool modified;
358
359 VkAllocationCallbacks alloc;
360 };
361
362 struct radv_pipeline_key {
363 uint32_t instance_rate_inputs;
364 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
365 uint64_t vertex_alpha_adjust;
366 unsigned tess_input_vertices;
367 uint32_t col_format;
368 uint32_t is_int8;
369 uint32_t is_int10;
370 uint8_t log2_ps_iter_samples;
371 uint8_t num_samples;
372 uint32_t has_multiview_view_index : 1;
373 uint32_t optimisations_disabled : 1;
374 };
375
376 void
377 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
378 struct radv_device *device);
379 void
380 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
381 bool
382 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
383 const void *data, size_t size);
384
385 struct radv_shader_variant;
386
387 bool
388 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
389 struct radv_pipeline_cache *cache,
390 const unsigned char *sha1,
391 struct radv_shader_variant **variants);
392
393 void
394 radv_pipeline_cache_insert_shaders(struct radv_device *device,
395 struct radv_pipeline_cache *cache,
396 const unsigned char *sha1,
397 struct radv_shader_variant **variants,
398 const void *const *codes,
399 const unsigned *code_sizes);
400
401 enum radv_blit_ds_layout {
402 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
403 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
404 RADV_BLIT_DS_LAYOUT_COUNT,
405 };
406
407 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
408 {
409 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
410 }
411
412 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
413 {
414 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
415 }
416
417 enum radv_meta_dst_layout {
418 RADV_META_DST_LAYOUT_GENERAL,
419 RADV_META_DST_LAYOUT_OPTIMAL,
420 RADV_META_DST_LAYOUT_COUNT,
421 };
422
423 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
424 {
425 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
426 }
427
428 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
429 {
430 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
431 }
432
433 struct radv_meta_state {
434 VkAllocationCallbacks alloc;
435
436 struct radv_pipeline_cache cache;
437
438 /*
439 * For on-demand pipeline creation, makes sure that
440 * only one thread tries to build a pipeline at the same time.
441 */
442 mtx_t mtx;
443
444 /**
445 * Use array element `i` for images with `2^i` samples.
446 */
447 struct {
448 VkRenderPass render_pass[NUM_META_FS_KEYS];
449 VkPipeline color_pipelines[NUM_META_FS_KEYS];
450
451 VkRenderPass depthstencil_rp;
452 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
453 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
454 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
455 } clear[1 + MAX_SAMPLES_LOG2];
456
457 VkPipelineLayout clear_color_p_layout;
458 VkPipelineLayout clear_depth_p_layout;
459
460 /* Optimized compute fast HTILE clear for stencil or depth only. */
461 VkPipeline clear_htile_mask_pipeline;
462 VkPipelineLayout clear_htile_mask_p_layout;
463 VkDescriptorSetLayout clear_htile_mask_ds_layout;
464
465 struct {
466 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
467
468 /** Pipeline that blits from a 1D image. */
469 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
470
471 /** Pipeline that blits from a 2D image. */
472 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
473
474 /** Pipeline that blits from a 3D image. */
475 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
476
477 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
478 VkPipeline depth_only_1d_pipeline;
479 VkPipeline depth_only_2d_pipeline;
480 VkPipeline depth_only_3d_pipeline;
481
482 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
483 VkPipeline stencil_only_1d_pipeline;
484 VkPipeline stencil_only_2d_pipeline;
485 VkPipeline stencil_only_3d_pipeline;
486 VkPipelineLayout pipeline_layout;
487 VkDescriptorSetLayout ds_layout;
488 } blit;
489
490 struct {
491 VkPipelineLayout p_layouts[5];
492 VkDescriptorSetLayout ds_layouts[5];
493 VkPipeline pipelines[5][NUM_META_FS_KEYS];
494
495 VkPipeline depth_only_pipeline[5];
496
497 VkPipeline stencil_only_pipeline[5];
498 } blit2d[1 + MAX_SAMPLES_LOG2];
499
500 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
501 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
502 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
503
504 struct {
505 VkPipelineLayout img_p_layout;
506 VkDescriptorSetLayout img_ds_layout;
507 VkPipeline pipeline;
508 VkPipeline pipeline_3d;
509 } itob;
510 struct {
511 VkPipelineLayout img_p_layout;
512 VkDescriptorSetLayout img_ds_layout;
513 VkPipeline pipeline;
514 VkPipeline pipeline_3d;
515 } btoi;
516 struct {
517 VkPipelineLayout img_p_layout;
518 VkDescriptorSetLayout img_ds_layout;
519 VkPipeline pipeline;
520 } btoi_r32g32b32;
521 struct {
522 VkPipelineLayout img_p_layout;
523 VkDescriptorSetLayout img_ds_layout;
524 VkPipeline pipeline;
525 VkPipeline pipeline_3d;
526 } itoi;
527 struct {
528 VkPipelineLayout img_p_layout;
529 VkDescriptorSetLayout img_ds_layout;
530 VkPipeline pipeline;
531 } itoi_r32g32b32;
532 struct {
533 VkPipelineLayout img_p_layout;
534 VkDescriptorSetLayout img_ds_layout;
535 VkPipeline pipeline;
536 VkPipeline pipeline_3d;
537 } cleari;
538 struct {
539 VkPipelineLayout img_p_layout;
540 VkDescriptorSetLayout img_ds_layout;
541 VkPipeline pipeline;
542 } cleari_r32g32b32;
543
544 struct {
545 VkPipelineLayout p_layout;
546 VkPipeline pipeline[NUM_META_FS_KEYS];
547 VkRenderPass pass[NUM_META_FS_KEYS];
548 } resolve;
549
550 struct {
551 VkDescriptorSetLayout ds_layout;
552 VkPipelineLayout p_layout;
553 struct {
554 VkPipeline pipeline;
555 VkPipeline i_pipeline;
556 VkPipeline srgb_pipeline;
557 } rc[MAX_SAMPLES_LOG2];
558 } resolve_compute;
559
560 struct {
561 VkDescriptorSetLayout ds_layout;
562 VkPipelineLayout p_layout;
563
564 struct {
565 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
566 VkPipeline pipeline[NUM_META_FS_KEYS];
567 } rc[MAX_SAMPLES_LOG2];
568 } resolve_fragment;
569
570 struct {
571 VkPipelineLayout p_layout;
572 VkPipeline decompress_pipeline;
573 VkPipeline resummarize_pipeline;
574 VkRenderPass pass;
575 } depth_decomp[1 + MAX_SAMPLES_LOG2];
576
577 struct {
578 VkPipelineLayout p_layout;
579 VkPipeline cmask_eliminate_pipeline;
580 VkPipeline fmask_decompress_pipeline;
581 VkPipeline dcc_decompress_pipeline;
582 VkRenderPass pass;
583
584 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
585 VkPipelineLayout dcc_decompress_compute_p_layout;
586 VkPipeline dcc_decompress_compute_pipeline;
587 } fast_clear_flush;
588
589 struct {
590 VkPipelineLayout fill_p_layout;
591 VkPipelineLayout copy_p_layout;
592 VkDescriptorSetLayout fill_ds_layout;
593 VkDescriptorSetLayout copy_ds_layout;
594 VkPipeline fill_pipeline;
595 VkPipeline copy_pipeline;
596 } buffer;
597
598 struct {
599 VkDescriptorSetLayout ds_layout;
600 VkPipelineLayout p_layout;
601 VkPipeline occlusion_query_pipeline;
602 VkPipeline pipeline_statistics_query_pipeline;
603 VkPipeline tfb_query_pipeline;
604 } query;
605
606 struct {
607 VkDescriptorSetLayout ds_layout;
608 VkPipelineLayout p_layout;
609 VkPipeline pipeline[MAX_SAMPLES_LOG2];
610 } fmask_expand;
611 };
612
613 /* queue types */
614 #define RADV_QUEUE_GENERAL 0
615 #define RADV_QUEUE_COMPUTE 1
616 #define RADV_QUEUE_TRANSFER 2
617
618 #define RADV_MAX_QUEUE_FAMILIES 3
619
620 enum ring_type radv_queue_family_to_ring(int f);
621
622 struct radv_queue {
623 VK_LOADER_DATA _loader_data;
624 struct radv_device * device;
625 struct radeon_winsys_ctx *hw_ctx;
626 enum radeon_ctx_priority priority;
627 uint32_t queue_family_index;
628 int queue_idx;
629 VkDeviceQueueCreateFlags flags;
630
631 uint32_t scratch_size;
632 uint32_t compute_scratch_size;
633 uint32_t esgs_ring_size;
634 uint32_t gsvs_ring_size;
635 bool has_tess_rings;
636 bool has_sample_positions;
637
638 struct radeon_winsys_bo *scratch_bo;
639 struct radeon_winsys_bo *descriptor_bo;
640 struct radeon_winsys_bo *compute_scratch_bo;
641 struct radeon_winsys_bo *esgs_ring_bo;
642 struct radeon_winsys_bo *gsvs_ring_bo;
643 struct radeon_winsys_bo *tess_rings_bo;
644 struct radeon_cmdbuf *initial_preamble_cs;
645 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
646 struct radeon_cmdbuf *continue_preamble_cs;
647 };
648
649 struct radv_bo_list {
650 struct radv_winsys_bo_list list;
651 unsigned capacity;
652 pthread_mutex_t mutex;
653 };
654
655 struct radv_device {
656 VK_LOADER_DATA _loader_data;
657
658 VkAllocationCallbacks alloc;
659
660 struct radv_instance * instance;
661 struct radeon_winsys *ws;
662
663 struct radv_meta_state meta_state;
664
665 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
666 int queue_count[RADV_MAX_QUEUE_FAMILIES];
667 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
668
669 bool always_use_syncobj;
670 bool has_distributed_tess;
671 bool pbb_allowed;
672 bool dfsm_allowed;
673 uint32_t tess_offchip_block_dw_size;
674 uint32_t scratch_waves;
675 uint32_t dispatch_initiator;
676
677 uint32_t gs_table_depth;
678
679 /* MSAA sample locations.
680 * The first index is the sample index.
681 * The second index is the coordinate: X, Y. */
682 float sample_locations_1x[1][2];
683 float sample_locations_2x[2][2];
684 float sample_locations_4x[4][2];
685 float sample_locations_8x[8][2];
686 float sample_locations_16x[16][2];
687
688 /* CIK and later */
689 uint32_t gfx_init_size_dw;
690 struct radeon_winsys_bo *gfx_init;
691
692 struct radeon_winsys_bo *trace_bo;
693 uint32_t *trace_id_ptr;
694
695 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
696 bool keep_shader_info;
697
698 struct radv_physical_device *physical_device;
699
700 /* Backup in-memory cache to be used if the app doesn't provide one */
701 struct radv_pipeline_cache * mem_cache;
702
703 /*
704 * use different counters so MSAA MRTs get consecutive surface indices,
705 * even if MASK is allocated in between.
706 */
707 uint32_t image_mrt_offset_counter;
708 uint32_t fmask_mrt_offset_counter;
709 struct list_head shader_slabs;
710 mtx_t shader_slab_mutex;
711
712 /* For detecting VM faults reported by dmesg. */
713 uint64_t dmesg_timestamp;
714
715 struct radv_device_extension_table enabled_extensions;
716
717 /* Whether the driver uses a global BO list. */
718 bool use_global_bo_list;
719
720 struct radv_bo_list bo_list;
721
722 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
723 int force_aniso;
724 };
725
726 struct radv_device_memory {
727 struct radeon_winsys_bo *bo;
728 /* for dedicated allocations */
729 struct radv_image *image;
730 struct radv_buffer *buffer;
731 uint32_t type_index;
732 VkDeviceSize map_size;
733 void * map;
734 void * user_ptr;
735 };
736
737
738 struct radv_descriptor_range {
739 uint64_t va;
740 uint32_t size;
741 };
742
743 struct radv_descriptor_set {
744 const struct radv_descriptor_set_layout *layout;
745 uint32_t size;
746
747 struct radeon_winsys_bo *bo;
748 uint64_t va;
749 uint32_t *mapped_ptr;
750 struct radv_descriptor_range *dynamic_descriptors;
751
752 struct radeon_winsys_bo *descriptors[0];
753 };
754
755 struct radv_push_descriptor_set
756 {
757 struct radv_descriptor_set set;
758 uint32_t capacity;
759 };
760
761 struct radv_descriptor_pool_entry {
762 uint32_t offset;
763 uint32_t size;
764 struct radv_descriptor_set *set;
765 };
766
767 struct radv_descriptor_pool {
768 struct radeon_winsys_bo *bo;
769 uint8_t *mapped_ptr;
770 uint64_t current_offset;
771 uint64_t size;
772
773 uint8_t *host_memory_base;
774 uint8_t *host_memory_ptr;
775 uint8_t *host_memory_end;
776
777 uint32_t entry_count;
778 uint32_t max_entry_count;
779 struct radv_descriptor_pool_entry entries[0];
780 };
781
782 struct radv_descriptor_update_template_entry {
783 VkDescriptorType descriptor_type;
784
785 /* The number of descriptors to update */
786 uint32_t descriptor_count;
787
788 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
789 uint32_t dst_offset;
790
791 /* In dwords. Not valid/used for dynamic descriptors */
792 uint32_t dst_stride;
793
794 uint32_t buffer_offset;
795
796 /* Only valid for combined image samplers and samplers */
797 uint16_t has_sampler;
798
799 /* In bytes */
800 size_t src_offset;
801 size_t src_stride;
802
803 /* For push descriptors */
804 const uint32_t *immutable_samplers;
805 };
806
807 struct radv_descriptor_update_template {
808 uint32_t entry_count;
809 VkPipelineBindPoint bind_point;
810 struct radv_descriptor_update_template_entry entry[0];
811 };
812
813 struct radv_buffer {
814 VkDeviceSize size;
815
816 VkBufferUsageFlags usage;
817 VkBufferCreateFlags flags;
818
819 /* Set when bound */
820 struct radeon_winsys_bo * bo;
821 VkDeviceSize offset;
822
823 bool shareable;
824 };
825
826 enum radv_dynamic_state_bits {
827 RADV_DYNAMIC_VIEWPORT = 1 << 0,
828 RADV_DYNAMIC_SCISSOR = 1 << 1,
829 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
830 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
831 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
832 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
833 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
834 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
835 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
836 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
837 RADV_DYNAMIC_ALL = (1 << 10) - 1,
838 };
839
840 enum radv_cmd_dirty_bits {
841 /* Keep the dynamic state dirty bits in sync with
842 * enum radv_dynamic_state_bits */
843 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
844 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
845 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
846 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
847 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
848 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
849 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
850 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
851 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
852 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
853 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
854 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
855 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
856 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
857 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
858 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 14,
859 };
860
861 enum radv_cmd_flush_bits {
862 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
863 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
864 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
865 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
866 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
867 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
868 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
869 /* Same as above, but only writes back and doesn't invalidate */
870 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
871 /* Framebuffer caches */
872 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
873 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
874 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
875 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
876 /* Engine synchronization. */
877 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
878 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
879 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
880 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
881 /* Pipeline query controls. */
882 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
883 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
884 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
885
886 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
887 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
888 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
889 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
890 };
891
892 struct radv_vertex_binding {
893 struct radv_buffer * buffer;
894 VkDeviceSize offset;
895 };
896
897 struct radv_streamout_binding {
898 struct radv_buffer *buffer;
899 VkDeviceSize offset;
900 VkDeviceSize size;
901 };
902
903 struct radv_streamout_state {
904 /* Mask of bound streamout buffers. */
905 uint8_t enabled_mask;
906
907 /* External state that comes from the last vertex stage, it must be
908 * set explicitely when binding a new graphics pipeline.
909 */
910 uint16_t stride_in_dw[MAX_SO_BUFFERS];
911 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
912
913 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
914 uint32_t hw_enabled_mask;
915
916 /* State of VGT_STRMOUT_(CONFIG|EN) */
917 bool streamout_enabled;
918 };
919
920 struct radv_viewport_state {
921 uint32_t count;
922 VkViewport viewports[MAX_VIEWPORTS];
923 };
924
925 struct radv_scissor_state {
926 uint32_t count;
927 VkRect2D scissors[MAX_SCISSORS];
928 };
929
930 struct radv_discard_rectangle_state {
931 uint32_t count;
932 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
933 };
934
935 struct radv_dynamic_state {
936 /**
937 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
938 * Defines the set of saved dynamic state.
939 */
940 uint32_t mask;
941
942 struct radv_viewport_state viewport;
943
944 struct radv_scissor_state scissor;
945
946 float line_width;
947
948 struct {
949 float bias;
950 float clamp;
951 float slope;
952 } depth_bias;
953
954 float blend_constants[4];
955
956 struct {
957 float min;
958 float max;
959 } depth_bounds;
960
961 struct {
962 uint32_t front;
963 uint32_t back;
964 } stencil_compare_mask;
965
966 struct {
967 uint32_t front;
968 uint32_t back;
969 } stencil_write_mask;
970
971 struct {
972 uint32_t front;
973 uint32_t back;
974 } stencil_reference;
975
976 struct radv_discard_rectangle_state discard_rectangle;
977 };
978
979 extern const struct radv_dynamic_state default_dynamic_state;
980
981 const char *
982 radv_get_debug_option_name(int id);
983
984 const char *
985 radv_get_perftest_option_name(int id);
986
987 /**
988 * Attachment state when recording a renderpass instance.
989 *
990 * The clear value is valid only if there exists a pending clear.
991 */
992 struct radv_attachment_state {
993 VkImageAspectFlags pending_clear_aspects;
994 uint32_t cleared_views;
995 VkClearValue clear_value;
996 VkImageLayout current_layout;
997 };
998
999 struct radv_descriptor_state {
1000 struct radv_descriptor_set *sets[MAX_SETS];
1001 uint32_t dirty;
1002 uint32_t valid;
1003 struct radv_push_descriptor_set push_set;
1004 bool push_dirty;
1005 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1006 };
1007
1008 struct radv_cmd_state {
1009 /* Vertex descriptors */
1010 uint64_t vb_va;
1011 unsigned vb_size;
1012
1013 bool predicating;
1014 uint32_t dirty;
1015
1016 uint32_t prefetch_L2_mask;
1017
1018 struct radv_pipeline * pipeline;
1019 struct radv_pipeline * emitted_pipeline;
1020 struct radv_pipeline * compute_pipeline;
1021 struct radv_pipeline * emitted_compute_pipeline;
1022 struct radv_framebuffer * framebuffer;
1023 struct radv_render_pass * pass;
1024 const struct radv_subpass * subpass;
1025 struct radv_dynamic_state dynamic;
1026 struct radv_attachment_state * attachments;
1027 struct radv_streamout_state streamout;
1028 VkRect2D render_area;
1029
1030 /* Index buffer */
1031 struct radv_buffer *index_buffer;
1032 uint64_t index_offset;
1033 uint32_t index_type;
1034 uint32_t max_index_count;
1035 uint64_t index_va;
1036 int32_t last_index_type;
1037
1038 int32_t last_primitive_reset_en;
1039 uint32_t last_primitive_reset_index;
1040 enum radv_cmd_flush_bits flush_bits;
1041 unsigned active_occlusion_queries;
1042 bool perfect_occlusion_queries_enabled;
1043 unsigned active_pipeline_queries;
1044 float offset_scale;
1045 uint32_t trace_id;
1046 uint32_t last_ia_multi_vgt_param;
1047
1048 uint32_t last_num_instances;
1049 uint32_t last_first_instance;
1050 uint32_t last_vertex_offset;
1051
1052 /* Whether CP DMA is busy/idle. */
1053 bool dma_is_busy;
1054
1055 /* Conditional rendering info. */
1056 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1057 uint64_t predication_va;
1058
1059 bool context_roll_without_scissor_emitted;
1060 };
1061
1062 struct radv_cmd_pool {
1063 VkAllocationCallbacks alloc;
1064 struct list_head cmd_buffers;
1065 struct list_head free_cmd_buffers;
1066 uint32_t queue_family_index;
1067 };
1068
1069 struct radv_cmd_buffer_upload {
1070 uint8_t *map;
1071 unsigned offset;
1072 uint64_t size;
1073 struct radeon_winsys_bo *upload_bo;
1074 struct list_head list;
1075 };
1076
1077 enum radv_cmd_buffer_status {
1078 RADV_CMD_BUFFER_STATUS_INVALID,
1079 RADV_CMD_BUFFER_STATUS_INITIAL,
1080 RADV_CMD_BUFFER_STATUS_RECORDING,
1081 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1082 RADV_CMD_BUFFER_STATUS_PENDING,
1083 };
1084
1085 struct radv_cmd_buffer {
1086 VK_LOADER_DATA _loader_data;
1087
1088 struct radv_device * device;
1089
1090 struct radv_cmd_pool * pool;
1091 struct list_head pool_link;
1092
1093 VkCommandBufferUsageFlags usage_flags;
1094 VkCommandBufferLevel level;
1095 enum radv_cmd_buffer_status status;
1096 struct radeon_cmdbuf *cs;
1097 struct radv_cmd_state state;
1098 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1099 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1100 uint32_t queue_family_index;
1101
1102 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1103 VkShaderStageFlags push_constant_stages;
1104 struct radv_descriptor_set meta_push_descriptors;
1105
1106 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1107
1108 struct radv_cmd_buffer_upload upload;
1109
1110 uint32_t scratch_size_needed;
1111 uint32_t compute_scratch_size_needed;
1112 uint32_t esgs_ring_size_needed;
1113 uint32_t gsvs_ring_size_needed;
1114 bool tess_rings_needed;
1115 bool sample_positions_needed;
1116
1117 VkResult record_result;
1118
1119 uint32_t gfx9_fence_offset;
1120 struct radeon_winsys_bo *gfx9_fence_bo;
1121 uint32_t gfx9_fence_idx;
1122 uint64_t gfx9_eop_bug_va;
1123
1124 /**
1125 * Whether a query pool has been resetted and we have to flush caches.
1126 */
1127 bool pending_reset_query;
1128 };
1129
1130 struct radv_image;
1131
1132 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1133
1134 void si_emit_graphics(struct radv_physical_device *physical_device,
1135 struct radeon_cmdbuf *cs);
1136 void si_emit_compute(struct radv_physical_device *physical_device,
1137 struct radeon_cmdbuf *cs);
1138
1139 void cik_create_gfx_config(struct radv_device *device);
1140
1141 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1142 int count, const VkViewport *viewports);
1143 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1144 int count, const VkRect2D *scissors,
1145 const VkViewport *viewports, bool can_use_guardband);
1146 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1147 bool instanced_draw, bool indirect_draw,
1148 uint32_t draw_vertex_count);
1149 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1150 enum chip_class chip_class,
1151 bool is_mec,
1152 unsigned event, unsigned event_flags,
1153 unsigned data_sel,
1154 uint64_t va,
1155 uint32_t new_fence,
1156 uint64_t gfx9_eop_bug_va);
1157
1158 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1159 uint32_t ref, uint32_t mask);
1160 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1161 enum chip_class chip_class,
1162 uint32_t *fence_ptr, uint64_t va,
1163 bool is_mec,
1164 enum radv_cmd_flush_bits flush_bits,
1165 uint64_t gfx9_eop_bug_va);
1166 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1167 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1168 bool inverted, uint64_t va);
1169 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1170 uint64_t src_va, uint64_t dest_va,
1171 uint64_t size);
1172 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1173 unsigned size);
1174 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1175 uint64_t size, unsigned value);
1176 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1177
1178 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1179 bool
1180 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1181 unsigned size,
1182 unsigned alignment,
1183 unsigned *out_offset,
1184 void **ptr);
1185 void
1186 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1187 const struct radv_subpass *subpass,
1188 bool transitions);
1189 bool
1190 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1191 unsigned size, unsigned alignmnet,
1192 const void *data, unsigned *out_offset);
1193
1194 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1195 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1196 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1197 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1198 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
1199 unsigned radv_cayman_get_maxdist(int log_samples);
1200 void radv_device_init_msaa(struct radv_device *device);
1201
1202 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1203 struct radv_image *image,
1204 VkClearDepthStencilValue ds_clear_value,
1205 VkImageAspectFlags aspects);
1206
1207 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1208 struct radv_image *image,
1209 int cb_idx,
1210 uint32_t color_values[2]);
1211
1212 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1213 struct radv_image *image, bool value);
1214
1215 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1216 struct radv_image *image, bool value);
1217
1218 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1219 struct radeon_winsys_bo *bo,
1220 uint64_t offset, uint64_t size, uint32_t value);
1221 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1222 bool radv_get_memory_fd(struct radv_device *device,
1223 struct radv_device_memory *memory,
1224 int *pFD);
1225
1226 static inline void
1227 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1228 unsigned sh_offset, unsigned pointer_count,
1229 bool use_32bit_pointers)
1230 {
1231 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1232 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1233 }
1234
1235 static inline void
1236 radv_emit_shader_pointer_body(struct radv_device *device,
1237 struct radeon_cmdbuf *cs,
1238 uint64_t va, bool use_32bit_pointers)
1239 {
1240 radeon_emit(cs, va);
1241
1242 if (use_32bit_pointers) {
1243 assert(va == 0 ||
1244 (va >> 32) == device->physical_device->rad_info.address32_hi);
1245 } else {
1246 radeon_emit(cs, va >> 32);
1247 }
1248 }
1249
1250 static inline void
1251 radv_emit_shader_pointer(struct radv_device *device,
1252 struct radeon_cmdbuf *cs,
1253 uint32_t sh_offset, uint64_t va, bool global)
1254 {
1255 bool use_32bit_pointers = !global;
1256
1257 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1258 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1259 }
1260
1261 static inline struct radv_descriptor_state *
1262 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1263 VkPipelineBindPoint bind_point)
1264 {
1265 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1266 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1267 return &cmd_buffer->descriptors[bind_point];
1268 }
1269
1270 /*
1271 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1272 *
1273 * Limitations: Can't call normal dispatch functions without binding or rebinding
1274 * the compute pipeline.
1275 */
1276 void radv_unaligned_dispatch(
1277 struct radv_cmd_buffer *cmd_buffer,
1278 uint32_t x,
1279 uint32_t y,
1280 uint32_t z);
1281
1282 struct radv_event {
1283 struct radeon_winsys_bo *bo;
1284 uint64_t *map;
1285 };
1286
1287 struct radv_shader_module;
1288
1289 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1290 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1291 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1292 void
1293 radv_hash_shaders(unsigned char *hash,
1294 const VkPipelineShaderStageCreateInfo **stages,
1295 const struct radv_pipeline_layout *layout,
1296 const struct radv_pipeline_key *key,
1297 uint32_t flags);
1298
1299 static inline gl_shader_stage
1300 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1301 {
1302 assert(__builtin_popcount(vk_stage) == 1);
1303 return ffs(vk_stage) - 1;
1304 }
1305
1306 static inline VkShaderStageFlagBits
1307 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1308 {
1309 return (1 << mesa_stage);
1310 }
1311
1312 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1313
1314 #define radv_foreach_stage(stage, stage_bits) \
1315 for (gl_shader_stage stage, \
1316 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1317 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1318 __tmp &= ~(1 << (stage)))
1319
1320 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1321 unsigned radv_format_meta_fs_key(VkFormat format);
1322
1323 struct radv_multisample_state {
1324 uint32_t db_eqaa;
1325 uint32_t pa_sc_line_cntl;
1326 uint32_t pa_sc_mode_cntl_0;
1327 uint32_t pa_sc_mode_cntl_1;
1328 uint32_t pa_sc_aa_config;
1329 uint32_t pa_sc_aa_mask[2];
1330 unsigned num_samples;
1331 };
1332
1333 struct radv_prim_vertex_count {
1334 uint8_t min;
1335 uint8_t incr;
1336 };
1337
1338 struct radv_vertex_elements_info {
1339 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1340 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1341 uint32_t binding[MAX_VERTEX_ATTRIBS];
1342 uint32_t offset[MAX_VERTEX_ATTRIBS];
1343 uint32_t count;
1344 };
1345
1346 struct radv_ia_multi_vgt_param_helpers {
1347 uint32_t base;
1348 bool partial_es_wave;
1349 uint8_t primgroup_size;
1350 bool wd_switch_on_eop;
1351 bool ia_switch_on_eoi;
1352 bool partial_vs_wave;
1353 };
1354
1355 #define SI_GS_PER_ES 128
1356
1357 struct radv_pipeline {
1358 struct radv_device * device;
1359 struct radv_dynamic_state dynamic_state;
1360
1361 struct radv_pipeline_layout * layout;
1362
1363 bool need_indirect_descriptor_sets;
1364 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1365 struct radv_shader_variant *gs_copy_shader;
1366 VkShaderStageFlags active_stages;
1367
1368 struct radeon_cmdbuf cs;
1369 uint32_t ctx_cs_hash;
1370 struct radeon_cmdbuf ctx_cs;
1371
1372 struct radv_vertex_elements_info vertex_elements;
1373
1374 uint32_t binding_stride[MAX_VBS];
1375
1376 uint32_t user_data_0[MESA_SHADER_STAGES];
1377 union {
1378 struct {
1379 struct radv_multisample_state ms;
1380 uint32_t spi_baryc_cntl;
1381 bool prim_restart_enable;
1382 unsigned esgs_ring_size;
1383 unsigned gsvs_ring_size;
1384 uint32_t vtx_base_sgpr;
1385 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1386 uint8_t vtx_emit_num;
1387 struct radv_prim_vertex_count prim_vertex_count;
1388 bool can_use_guardband;
1389 uint32_t needed_dynamic_state;
1390 bool disable_out_of_order_rast_for_occlusion;
1391
1392 /* Used for rbplus */
1393 uint32_t col_format;
1394 uint32_t cb_target_mask;
1395 } graphics;
1396 };
1397
1398 unsigned max_waves;
1399 unsigned scratch_bytes_per_wave;
1400
1401 /* Not NULL if graphics pipeline uses streamout. */
1402 struct radv_shader_variant *streamout_shader;
1403 };
1404
1405 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1406 {
1407 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1408 }
1409
1410 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1411 {
1412 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1413 }
1414
1415 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1416 gl_shader_stage stage,
1417 int idx);
1418
1419 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1420 gl_shader_stage stage);
1421
1422 struct radv_graphics_pipeline_create_info {
1423 bool use_rectlist;
1424 bool db_depth_clear;
1425 bool db_stencil_clear;
1426 bool db_depth_disable_expclear;
1427 bool db_stencil_disable_expclear;
1428 bool db_flush_depth_inplace;
1429 bool db_flush_stencil_inplace;
1430 bool db_resummarize;
1431 uint32_t custom_blend_mode;
1432 };
1433
1434 VkResult
1435 radv_graphics_pipeline_create(VkDevice device,
1436 VkPipelineCache cache,
1437 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1438 const struct radv_graphics_pipeline_create_info *extra,
1439 const VkAllocationCallbacks *alloc,
1440 VkPipeline *pPipeline);
1441
1442 struct vk_format_description;
1443 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1444 int first_non_void);
1445 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1446 int first_non_void);
1447 uint32_t radv_translate_colorformat(VkFormat format);
1448 uint32_t radv_translate_color_numformat(VkFormat format,
1449 const struct vk_format_description *desc,
1450 int first_non_void);
1451 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1452 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1453 uint32_t radv_translate_dbformat(VkFormat format);
1454 uint32_t radv_translate_tex_dataformat(VkFormat format,
1455 const struct vk_format_description *desc,
1456 int first_non_void);
1457 uint32_t radv_translate_tex_numformat(VkFormat format,
1458 const struct vk_format_description *desc,
1459 int first_non_void);
1460 bool radv_format_pack_clear_color(VkFormat format,
1461 uint32_t clear_vals[2],
1462 VkClearColorValue *value);
1463 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1464 bool radv_dcc_formats_compatible(VkFormat format1,
1465 VkFormat format2);
1466
1467 struct radv_fmask_info {
1468 uint64_t offset;
1469 uint64_t size;
1470 unsigned alignment;
1471 unsigned pitch_in_pixels;
1472 unsigned bank_height;
1473 unsigned slice_tile_max;
1474 unsigned tile_mode_index;
1475 unsigned tile_swizzle;
1476 };
1477
1478 struct radv_cmask_info {
1479 uint64_t offset;
1480 uint64_t size;
1481 unsigned alignment;
1482 unsigned slice_tile_max;
1483 };
1484
1485 struct radv_image {
1486 VkImageType type;
1487 /* The original VkFormat provided by the client. This may not match any
1488 * of the actual surface formats.
1489 */
1490 VkFormat vk_format;
1491 VkImageAspectFlags aspects;
1492 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1493 struct ac_surf_info info;
1494 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1495 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1496
1497 VkDeviceSize size;
1498 uint32_t alignment;
1499
1500 unsigned queue_family_mask;
1501 bool exclusive;
1502 bool shareable;
1503
1504 /* Set when bound */
1505 struct radeon_winsys_bo *bo;
1506 VkDeviceSize offset;
1507 uint64_t dcc_offset;
1508 uint64_t htile_offset;
1509 bool tc_compatible_htile;
1510 struct radeon_surf surface;
1511
1512 struct radv_fmask_info fmask;
1513 struct radv_cmask_info cmask;
1514 uint64_t clear_value_offset;
1515 uint64_t fce_pred_offset;
1516 uint64_t dcc_pred_offset;
1517
1518 /*
1519 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1520 * stored at this offset is UINT_MAX, the driver will emit
1521 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1522 * SET_CONTEXT_REG packet.
1523 */
1524 uint64_t tc_compat_zrange_offset;
1525
1526 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1527 VkDeviceMemory owned_memory;
1528 };
1529
1530 /* Whether the image has a htile that is known consistent with the contents of
1531 * the image. */
1532 bool radv_layout_has_htile(const struct radv_image *image,
1533 VkImageLayout layout,
1534 unsigned queue_mask);
1535
1536 /* Whether the image has a htile that is known consistent with the contents of
1537 * the image and is allowed to be in compressed form.
1538 *
1539 * If this is false reads that don't use the htile should be able to return
1540 * correct results.
1541 */
1542 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1543 VkImageLayout layout,
1544 unsigned queue_mask);
1545
1546 bool radv_layout_can_fast_clear(const struct radv_image *image,
1547 VkImageLayout layout,
1548 unsigned queue_mask);
1549
1550 bool radv_layout_dcc_compressed(const struct radv_image *image,
1551 VkImageLayout layout,
1552 unsigned queue_mask);
1553
1554 /**
1555 * Return whether the image has CMASK metadata for color surfaces.
1556 */
1557 static inline bool
1558 radv_image_has_cmask(const struct radv_image *image)
1559 {
1560 return image->cmask.size;
1561 }
1562
1563 /**
1564 * Return whether the image has FMASK metadata for color surfaces.
1565 */
1566 static inline bool
1567 radv_image_has_fmask(const struct radv_image *image)
1568 {
1569 return image->fmask.size;
1570 }
1571
1572 /**
1573 * Return whether the image has DCC metadata for color surfaces.
1574 */
1575 static inline bool
1576 radv_image_has_dcc(const struct radv_image *image)
1577 {
1578 return image->surface.dcc_size;
1579 }
1580
1581 /**
1582 * Return whether DCC metadata is enabled for a level.
1583 */
1584 static inline bool
1585 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1586 {
1587 return radv_image_has_dcc(image) &&
1588 level < image->surface.num_dcc_levels;
1589 }
1590
1591 /**
1592 * Return whether the image has CB metadata.
1593 */
1594 static inline bool
1595 radv_image_has_CB_metadata(const struct radv_image *image)
1596 {
1597 return radv_image_has_cmask(image) ||
1598 radv_image_has_fmask(image) ||
1599 radv_image_has_dcc(image);
1600 }
1601
1602 /**
1603 * Return whether the image has HTILE metadata for depth surfaces.
1604 */
1605 static inline bool
1606 radv_image_has_htile(const struct radv_image *image)
1607 {
1608 return image->surface.htile_size;
1609 }
1610
1611 /**
1612 * Return whether HTILE metadata is enabled for a level.
1613 */
1614 static inline bool
1615 radv_htile_enabled(const struct radv_image *image, unsigned level)
1616 {
1617 return radv_image_has_htile(image) && level == 0;
1618 }
1619
1620 /**
1621 * Return whether the image is TC-compatible HTILE.
1622 */
1623 static inline bool
1624 radv_image_is_tc_compat_htile(const struct radv_image *image)
1625 {
1626 return radv_image_has_htile(image) && image->tc_compatible_htile;
1627 }
1628
1629 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1630
1631 static inline uint32_t
1632 radv_get_layerCount(const struct radv_image *image,
1633 const VkImageSubresourceRange *range)
1634 {
1635 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1636 image->info.array_size - range->baseArrayLayer : range->layerCount;
1637 }
1638
1639 static inline uint32_t
1640 radv_get_levelCount(const struct radv_image *image,
1641 const VkImageSubresourceRange *range)
1642 {
1643 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1644 image->info.levels - range->baseMipLevel : range->levelCount;
1645 }
1646
1647 struct radeon_bo_metadata;
1648 void
1649 radv_init_metadata(struct radv_device *device,
1650 struct radv_image *image,
1651 struct radeon_bo_metadata *metadata);
1652
1653 struct radv_image_view {
1654 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1655 struct radeon_winsys_bo *bo;
1656
1657 VkImageViewType type;
1658 VkImageAspectFlags aspect_mask;
1659 VkFormat vk_format;
1660 uint32_t base_layer;
1661 uint32_t layer_count;
1662 uint32_t base_mip;
1663 uint32_t level_count;
1664 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1665
1666 uint32_t descriptor[16];
1667
1668 /* Descriptor for use as a storage image as opposed to a sampled image.
1669 * This has a few differences for cube maps (e.g. type).
1670 */
1671 uint32_t storage_descriptor[16];
1672 };
1673
1674 struct radv_image_create_info {
1675 const VkImageCreateInfo *vk_info;
1676 bool scanout;
1677 bool no_metadata_planes;
1678 };
1679
1680 VkResult radv_image_create(VkDevice _device,
1681 const struct radv_image_create_info *info,
1682 const VkAllocationCallbacks* alloc,
1683 VkImage *pImage);
1684
1685 VkResult
1686 radv_image_from_gralloc(VkDevice device_h,
1687 const VkImageCreateInfo *base_info,
1688 const VkNativeBufferANDROID *gralloc_info,
1689 const VkAllocationCallbacks *alloc,
1690 VkImage *out_image_h);
1691
1692 void radv_image_view_init(struct radv_image_view *view,
1693 struct radv_device *device,
1694 const VkImageViewCreateInfo* pCreateInfo);
1695
1696 struct radv_buffer_view {
1697 struct radeon_winsys_bo *bo;
1698 VkFormat vk_format;
1699 uint64_t range; /**< VkBufferViewCreateInfo::range */
1700 uint32_t state[4];
1701 };
1702 void radv_buffer_view_init(struct radv_buffer_view *view,
1703 struct radv_device *device,
1704 const VkBufferViewCreateInfo* pCreateInfo);
1705
1706 static inline struct VkExtent3D
1707 radv_sanitize_image_extent(const VkImageType imageType,
1708 const struct VkExtent3D imageExtent)
1709 {
1710 switch (imageType) {
1711 case VK_IMAGE_TYPE_1D:
1712 return (VkExtent3D) { imageExtent.width, 1, 1 };
1713 case VK_IMAGE_TYPE_2D:
1714 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1715 case VK_IMAGE_TYPE_3D:
1716 return imageExtent;
1717 default:
1718 unreachable("invalid image type");
1719 }
1720 }
1721
1722 static inline struct VkOffset3D
1723 radv_sanitize_image_offset(const VkImageType imageType,
1724 const struct VkOffset3D imageOffset)
1725 {
1726 switch (imageType) {
1727 case VK_IMAGE_TYPE_1D:
1728 return (VkOffset3D) { imageOffset.x, 0, 0 };
1729 case VK_IMAGE_TYPE_2D:
1730 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1731 case VK_IMAGE_TYPE_3D:
1732 return imageOffset;
1733 default:
1734 unreachable("invalid image type");
1735 }
1736 }
1737
1738 static inline bool
1739 radv_image_extent_compare(const struct radv_image *image,
1740 const VkExtent3D *extent)
1741 {
1742 if (extent->width != image->info.width ||
1743 extent->height != image->info.height ||
1744 extent->depth != image->info.depth)
1745 return false;
1746 return true;
1747 }
1748
1749 struct radv_sampler {
1750 uint32_t state[4];
1751 };
1752
1753 struct radv_color_buffer_info {
1754 uint64_t cb_color_base;
1755 uint64_t cb_color_cmask;
1756 uint64_t cb_color_fmask;
1757 uint64_t cb_dcc_base;
1758 uint32_t cb_color_pitch;
1759 uint32_t cb_color_slice;
1760 uint32_t cb_color_view;
1761 uint32_t cb_color_info;
1762 uint32_t cb_color_attrib;
1763 uint32_t cb_color_attrib2;
1764 uint32_t cb_dcc_control;
1765 uint32_t cb_color_cmask_slice;
1766 uint32_t cb_color_fmask_slice;
1767 };
1768
1769 struct radv_ds_buffer_info {
1770 uint64_t db_z_read_base;
1771 uint64_t db_stencil_read_base;
1772 uint64_t db_z_write_base;
1773 uint64_t db_stencil_write_base;
1774 uint64_t db_htile_data_base;
1775 uint32_t db_depth_info;
1776 uint32_t db_z_info;
1777 uint32_t db_stencil_info;
1778 uint32_t db_depth_view;
1779 uint32_t db_depth_size;
1780 uint32_t db_depth_slice;
1781 uint32_t db_htile_surface;
1782 uint32_t pa_su_poly_offset_db_fmt_cntl;
1783 uint32_t db_z_info2;
1784 uint32_t db_stencil_info2;
1785 float offset_scale;
1786 };
1787
1788 struct radv_attachment_info {
1789 union {
1790 struct radv_color_buffer_info cb;
1791 struct radv_ds_buffer_info ds;
1792 };
1793 struct radv_image_view *attachment;
1794 };
1795
1796 struct radv_framebuffer {
1797 uint32_t width;
1798 uint32_t height;
1799 uint32_t layers;
1800
1801 uint32_t attachment_count;
1802 struct radv_attachment_info attachments[0];
1803 };
1804
1805 struct radv_subpass_barrier {
1806 VkPipelineStageFlags src_stage_mask;
1807 VkAccessFlags src_access_mask;
1808 VkAccessFlags dst_access_mask;
1809 };
1810
1811 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1812 const struct radv_subpass_barrier *barrier);
1813
1814 struct radv_subpass_attachment {
1815 uint32_t attachment;
1816 VkImageLayout layout;
1817 };
1818
1819 struct radv_subpass {
1820 uint32_t input_count;
1821 uint32_t color_count;
1822 struct radv_subpass_attachment * input_attachments;
1823 struct radv_subpass_attachment * color_attachments;
1824 struct radv_subpass_attachment * resolve_attachments;
1825 struct radv_subpass_attachment depth_stencil_attachment;
1826
1827 /** Subpass has at least one resolve attachment */
1828 bool has_resolve;
1829
1830 struct radv_subpass_barrier start_barrier;
1831
1832 uint32_t view_mask;
1833 VkSampleCountFlagBits max_sample_count;
1834 };
1835
1836 struct radv_render_pass_attachment {
1837 VkFormat format;
1838 uint32_t samples;
1839 VkAttachmentLoadOp load_op;
1840 VkAttachmentLoadOp stencil_load_op;
1841 VkImageLayout initial_layout;
1842 VkImageLayout final_layout;
1843 uint32_t view_mask;
1844 };
1845
1846 struct radv_render_pass {
1847 uint32_t attachment_count;
1848 uint32_t subpass_count;
1849 struct radv_subpass_attachment * subpass_attachments;
1850 struct radv_render_pass_attachment * attachments;
1851 struct radv_subpass_barrier end_barrier;
1852 struct radv_subpass subpasses[0];
1853 };
1854
1855 VkResult radv_device_init_meta(struct radv_device *device);
1856 void radv_device_finish_meta(struct radv_device *device);
1857
1858 struct radv_query_pool {
1859 struct radeon_winsys_bo *bo;
1860 uint32_t stride;
1861 uint32_t availability_offset;
1862 uint64_t size;
1863 char *ptr;
1864 VkQueryType type;
1865 uint32_t pipeline_stats_mask;
1866 };
1867
1868 struct radv_semaphore {
1869 /* use a winsys sem for non-exportable */
1870 struct radeon_winsys_sem *sem;
1871 uint32_t syncobj;
1872 uint32_t temp_syncobj;
1873 };
1874
1875 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1876 VkPipelineBindPoint bind_point,
1877 struct radv_descriptor_set *set,
1878 unsigned idx);
1879
1880 void
1881 radv_update_descriptor_sets(struct radv_device *device,
1882 struct radv_cmd_buffer *cmd_buffer,
1883 VkDescriptorSet overrideSet,
1884 uint32_t descriptorWriteCount,
1885 const VkWriteDescriptorSet *pDescriptorWrites,
1886 uint32_t descriptorCopyCount,
1887 const VkCopyDescriptorSet *pDescriptorCopies);
1888
1889 void
1890 radv_update_descriptor_set_with_template(struct radv_device *device,
1891 struct radv_cmd_buffer *cmd_buffer,
1892 struct radv_descriptor_set *set,
1893 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1894 const void *pData);
1895
1896 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1897 VkPipelineBindPoint pipelineBindPoint,
1898 VkPipelineLayout _layout,
1899 uint32_t set,
1900 uint32_t descriptorWriteCount,
1901 const VkWriteDescriptorSet *pDescriptorWrites);
1902
1903 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1904 struct radv_image *image, uint32_t value);
1905
1906 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
1907 struct radv_image *image);
1908
1909 struct radv_fence {
1910 struct radeon_winsys_fence *fence;
1911 struct wsi_fence *fence_wsi;
1912 bool submitted;
1913 bool signalled;
1914
1915 uint32_t syncobj;
1916 uint32_t temp_syncobj;
1917 };
1918
1919 /* radv_nir_to_llvm.c */
1920 struct radv_shader_variant_info;
1921 struct radv_nir_compiler_options;
1922
1923 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
1924 struct nir_shader *geom_shader,
1925 struct ac_shader_binary *binary,
1926 struct ac_shader_config *config,
1927 struct radv_shader_variant_info *shader_info,
1928 const struct radv_nir_compiler_options *option);
1929
1930 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
1931 struct ac_shader_binary *binary,
1932 struct ac_shader_config *config,
1933 struct radv_shader_variant_info *shader_info,
1934 struct nir_shader *const *nir,
1935 int nir_count,
1936 const struct radv_nir_compiler_options *options);
1937
1938 /* radv_shader_info.h */
1939 struct radv_shader_info;
1940
1941 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1942 const struct radv_nir_compiler_options *options,
1943 struct radv_shader_info *info);
1944
1945 struct radeon_winsys_sem;
1946
1947 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1948 \
1949 static inline struct __radv_type * \
1950 __radv_type ## _from_handle(__VkType _handle) \
1951 { \
1952 return (struct __radv_type *) _handle; \
1953 } \
1954 \
1955 static inline __VkType \
1956 __radv_type ## _to_handle(struct __radv_type *_obj) \
1957 { \
1958 return (__VkType) _obj; \
1959 }
1960
1961 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1962 \
1963 static inline struct __radv_type * \
1964 __radv_type ## _from_handle(__VkType _handle) \
1965 { \
1966 return (struct __radv_type *)(uintptr_t) _handle; \
1967 } \
1968 \
1969 static inline __VkType \
1970 __radv_type ## _to_handle(struct __radv_type *_obj) \
1971 { \
1972 return (__VkType)(uintptr_t) _obj; \
1973 }
1974
1975 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1976 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1977
1978 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1979 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1980 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1981 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1982 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1983
1984 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1985 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1986 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1987 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1988 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1989 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1990 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
1991 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1992 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1993 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1994 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1995 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1996 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1997 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1998 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1999 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2000 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2001 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2002 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2003 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2004 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2005
2006 #endif /* RADV_PRIVATE_H */