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Revert "Revert "radv: fallback to an in-memory cache when no pipline cache is provided""
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
59
60 #include <llvm-c/TargetMachine.h>
61
62 /* Pre-declarations needed for WSI entrypoints */
63 struct wl_surface;
64 struct wl_display;
65 typedef struct xcb_connection_t xcb_connection_t;
66 typedef uint32_t xcb_visualid_t;
67 typedef uint32_t xcb_window_t;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "radv_entrypoints.h"
74
75 #include "wsi_common.h"
76
77 #define ATI_VENDOR_ID 0x1002
78
79 #define MAX_VBS 32
80 #define MAX_VERTEX_ATTRIBS 32
81 #define MAX_RTS 8
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
90 #define MAX_VIEWS 8
91
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
93
94 enum radv_mem_heap {
95 RADV_MEM_HEAP_VRAM,
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
97 RADV_MEM_HEAP_GTT,
98 RADV_MEM_HEAP_COUNT
99 };
100
101 enum radv_mem_type {
102 RADV_MEM_TYPE_VRAM,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
105 RADV_MEM_TYPE_GTT_CACHED,
106 RADV_MEM_TYPE_COUNT
107 };
108
109 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
110
111 static inline uint32_t
112 align_u32(uint32_t v, uint32_t a)
113 {
114 assert(a != 0 && a == (a & -a));
115 return (v + a - 1) & ~(a - 1);
116 }
117
118 static inline uint32_t
119 align_u32_npot(uint32_t v, uint32_t a)
120 {
121 return (v + a - 1) / a * a;
122 }
123
124 static inline uint64_t
125 align_u64(uint64_t v, uint64_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 static inline int32_t
132 align_i32(int32_t v, int32_t a)
133 {
134 assert(a != 0 && a == (a & -a));
135 return (v + a - 1) & ~(a - 1);
136 }
137
138 /** Alignment must be a power of 2. */
139 static inline bool
140 radv_is_aligned(uintmax_t n, uintmax_t a)
141 {
142 assert(a == (a & -a));
143 return (n & (a - 1)) == 0;
144 }
145
146 static inline uint32_t
147 round_up_u32(uint32_t v, uint32_t a)
148 {
149 return (v + a - 1) / a;
150 }
151
152 static inline uint64_t
153 round_up_u64(uint64_t v, uint64_t a)
154 {
155 return (v + a - 1) / a;
156 }
157
158 static inline uint32_t
159 radv_minify(uint32_t n, uint32_t levels)
160 {
161 if (unlikely(n == 0))
162 return 0;
163 else
164 return MAX2(n >> levels, 1);
165 }
166 static inline float
167 radv_clamp_f(float f, float min, float max)
168 {
169 assert(min < max);
170
171 if (f > max)
172 return max;
173 else if (f < min)
174 return min;
175 else
176 return f;
177 }
178
179 static inline bool
180 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
181 {
182 if (*inout_mask & clear_mask) {
183 *inout_mask &= ~clear_mask;
184 return true;
185 } else {
186 return false;
187 }
188 }
189
190 #define for_each_bit(b, dword) \
191 for (uint32_t __dword = (dword); \
192 (b) = __builtin_ffs(__dword) - 1, __dword; \
193 __dword &= ~(1 << (b)))
194
195 #define typed_memcpy(dest, src, count) ({ \
196 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
197 memcpy((dest), (src), (count) * sizeof(*(src))); \
198 })
199
200 #define zero(x) (memset(&(x), 0, sizeof(x)))
201
202 /* Whenever we generate an error, pass it through this function. Useful for
203 * debugging, where we can break on it. Only call at error site, not when
204 * propagating errors. Might be useful to plug in a stack trace here.
205 */
206
207 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
208
209 #ifdef DEBUG
210 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
211 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
212 #else
213 #define vk_error(error) error
214 #define vk_errorf(error, format, ...) error
215 #endif
216
217 void __radv_finishme(const char *file, int line, const char *format, ...)
218 radv_printflike(3, 4);
219 void radv_loge(const char *format, ...) radv_printflike(1, 2);
220 void radv_loge_v(const char *format, va_list va);
221
222 /**
223 * Print a FINISHME message, including its source location.
224 */
225 #define radv_finishme(format, ...) \
226 do { \
227 static bool reported = false; \
228 if (!reported) { \
229 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
230 reported = true; \
231 } \
232 } while (0)
233
234 /* A non-fatal assert. Useful for debugging. */
235 #ifdef DEBUG
236 #define radv_assert(x) ({ \
237 if (unlikely(!(x))) \
238 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
239 })
240 #else
241 #define radv_assert(x)
242 #endif
243
244 #define stub_return(v) \
245 do { \
246 radv_finishme("stub %s", __func__); \
247 return (v); \
248 } while (0)
249
250 #define stub() \
251 do { \
252 radv_finishme("stub %s", __func__); \
253 return; \
254 } while (0)
255
256 void *radv_lookup_entrypoint(const char *name);
257
258 struct radv_extensions {
259 VkExtensionProperties *ext_array;
260 uint32_t num_ext;
261 };
262
263 struct radv_physical_device {
264 VK_LOADER_DATA _loader_data;
265
266 struct radv_instance * instance;
267
268 struct radeon_winsys *ws;
269 struct radeon_info rad_info;
270 char path[20];
271 const char * name;
272 uint8_t driver_uuid[VK_UUID_SIZE];
273 uint8_t device_uuid[VK_UUID_SIZE];
274 uint8_t cache_uuid[VK_UUID_SIZE];
275
276 int local_fd;
277 struct wsi_device wsi_device;
278 struct radv_extensions extensions;
279
280 bool has_rbplus; /* if RB+ register exist */
281 bool rbplus_allowed; /* if RB+ is allowed */
282 };
283
284 struct radv_instance {
285 VK_LOADER_DATA _loader_data;
286
287 VkAllocationCallbacks alloc;
288
289 uint32_t apiVersion;
290 int physicalDeviceCount;
291 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
292
293 uint64_t debug_flags;
294 uint64_t perftest_flags;
295 };
296
297 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
298 void radv_finish_wsi(struct radv_physical_device *physical_device);
299
300 struct cache_entry;
301
302 struct radv_pipeline_cache {
303 struct radv_device * device;
304 pthread_mutex_t mutex;
305
306 uint32_t total_size;
307 uint32_t table_size;
308 uint32_t kernel_count;
309 struct cache_entry ** hash_table;
310 bool modified;
311
312 VkAllocationCallbacks alloc;
313 };
314
315 void
316 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
317 struct radv_device *device);
318 void
319 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
320 void
321 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
322 const void *data, size_t size);
323
324 struct radv_shader_variant *
325 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
326 struct radv_pipeline_cache *cache,
327 const unsigned char *sha1);
328
329 struct radv_shader_variant *
330 radv_pipeline_cache_insert_shader(struct radv_device *device,
331 struct radv_pipeline_cache *cache,
332 const unsigned char *sha1,
333 struct radv_shader_variant *variant,
334 const void *code, unsigned code_size);
335
336 struct radv_meta_state {
337 VkAllocationCallbacks alloc;
338
339 struct radv_pipeline_cache cache;
340
341 /**
342 * Use array element `i` for images with `2^i` samples.
343 */
344 struct {
345 VkRenderPass render_pass[NUM_META_FS_KEYS];
346 struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
347
348 VkRenderPass depthstencil_rp;
349 struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
350 struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
351 struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
352 } clear[1 + MAX_SAMPLES_LOG2];
353
354 VkPipelineLayout clear_color_p_layout;
355 VkPipelineLayout clear_depth_p_layout;
356 struct {
357 VkRenderPass render_pass[NUM_META_FS_KEYS];
358
359 /** Pipeline that blits from a 1D image. */
360 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
361
362 /** Pipeline that blits from a 2D image. */
363 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
364
365 /** Pipeline that blits from a 3D image. */
366 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
367
368 VkRenderPass depth_only_rp;
369 VkPipeline depth_only_1d_pipeline;
370 VkPipeline depth_only_2d_pipeline;
371 VkPipeline depth_only_3d_pipeline;
372
373 VkRenderPass stencil_only_rp;
374 VkPipeline stencil_only_1d_pipeline;
375 VkPipeline stencil_only_2d_pipeline;
376 VkPipeline stencil_only_3d_pipeline;
377 VkPipelineLayout pipeline_layout;
378 VkDescriptorSetLayout ds_layout;
379 } blit;
380
381 struct {
382 VkRenderPass render_passes[NUM_META_FS_KEYS];
383
384 VkPipelineLayout p_layouts[2];
385 VkDescriptorSetLayout ds_layouts[2];
386 VkPipeline pipelines[2][NUM_META_FS_KEYS];
387
388 VkRenderPass depth_only_rp;
389 VkPipeline depth_only_pipeline[2];
390
391 VkRenderPass stencil_only_rp;
392 VkPipeline stencil_only_pipeline[2];
393 } blit2d;
394
395 struct {
396 VkPipelineLayout img_p_layout;
397 VkDescriptorSetLayout img_ds_layout;
398 VkPipeline pipeline;
399 } itob;
400 struct {
401 VkRenderPass render_pass;
402 VkPipelineLayout img_p_layout;
403 VkDescriptorSetLayout img_ds_layout;
404 VkPipeline pipeline;
405 } btoi;
406 struct {
407 VkPipelineLayout img_p_layout;
408 VkDescriptorSetLayout img_ds_layout;
409 VkPipeline pipeline;
410 } itoi;
411 struct {
412 VkPipelineLayout img_p_layout;
413 VkDescriptorSetLayout img_ds_layout;
414 VkPipeline pipeline;
415 } cleari;
416
417 struct {
418 VkPipeline pipeline;
419 VkRenderPass pass;
420 } resolve;
421
422 struct {
423 VkDescriptorSetLayout ds_layout;
424 VkPipelineLayout p_layout;
425 struct {
426 VkPipeline pipeline;
427 VkPipeline i_pipeline;
428 VkPipeline srgb_pipeline;
429 } rc[MAX_SAMPLES_LOG2];
430 } resolve_compute;
431
432 struct {
433 VkDescriptorSetLayout ds_layout;
434 VkPipelineLayout p_layout;
435
436 struct {
437 VkRenderPass render_pass[NUM_META_FS_KEYS];
438 VkPipeline pipeline[NUM_META_FS_KEYS];
439 } rc[MAX_SAMPLES_LOG2];
440 } resolve_fragment;
441
442 struct {
443 VkPipeline decompress_pipeline;
444 VkPipeline resummarize_pipeline;
445 VkRenderPass pass;
446 } depth_decomp[1 + MAX_SAMPLES_LOG2];
447
448 struct {
449 VkPipeline cmask_eliminate_pipeline;
450 VkPipeline fmask_decompress_pipeline;
451 VkRenderPass pass;
452 } fast_clear_flush;
453
454 struct {
455 VkPipelineLayout fill_p_layout;
456 VkPipelineLayout copy_p_layout;
457 VkDescriptorSetLayout fill_ds_layout;
458 VkDescriptorSetLayout copy_ds_layout;
459 VkPipeline fill_pipeline;
460 VkPipeline copy_pipeline;
461 } buffer;
462
463 struct {
464 VkDescriptorSetLayout ds_layout;
465 VkPipelineLayout p_layout;
466 VkPipeline occlusion_query_pipeline;
467 VkPipeline pipeline_statistics_query_pipeline;
468 } query;
469 };
470
471 /* queue types */
472 #define RADV_QUEUE_GENERAL 0
473 #define RADV_QUEUE_COMPUTE 1
474 #define RADV_QUEUE_TRANSFER 2
475
476 #define RADV_MAX_QUEUE_FAMILIES 3
477
478 enum ring_type radv_queue_family_to_ring(int f);
479
480 struct radv_queue {
481 VK_LOADER_DATA _loader_data;
482 struct radv_device * device;
483 struct radeon_winsys_ctx *hw_ctx;
484 int queue_family_index;
485 int queue_idx;
486
487 uint32_t scratch_size;
488 uint32_t compute_scratch_size;
489 uint32_t esgs_ring_size;
490 uint32_t gsvs_ring_size;
491 bool has_tess_rings;
492 bool has_sample_positions;
493
494 struct radeon_winsys_bo *scratch_bo;
495 struct radeon_winsys_bo *descriptor_bo;
496 struct radeon_winsys_bo *compute_scratch_bo;
497 struct radeon_winsys_bo *esgs_ring_bo;
498 struct radeon_winsys_bo *gsvs_ring_bo;
499 struct radeon_winsys_bo *tess_factor_ring_bo;
500 struct radeon_winsys_bo *tess_offchip_ring_bo;
501 struct radeon_winsys_cs *initial_preamble_cs;
502 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
503 struct radeon_winsys_cs *continue_preamble_cs;
504 };
505
506 struct radv_device {
507 VK_LOADER_DATA _loader_data;
508
509 VkAllocationCallbacks alloc;
510
511 struct radv_instance * instance;
512 struct radeon_winsys *ws;
513
514 struct radv_meta_state meta_state;
515
516 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
517 int queue_count[RADV_MAX_QUEUE_FAMILIES];
518 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
519 uint64_t debug_flags;
520
521 bool llvm_supports_spill;
522 bool has_distributed_tess;
523 uint32_t tess_offchip_block_dw_size;
524 uint32_t scratch_waves;
525
526 uint32_t gs_table_depth;
527
528 /* MSAA sample locations.
529 * The first index is the sample index.
530 * The second index is the coordinate: X, Y. */
531 float sample_locations_1x[1][2];
532 float sample_locations_2x[2][2];
533 float sample_locations_4x[4][2];
534 float sample_locations_8x[8][2];
535 float sample_locations_16x[16][2];
536
537 /* CIK and later */
538 uint32_t gfx_init_size_dw;
539 struct radeon_winsys_bo *gfx_init;
540
541 struct radeon_winsys_bo *trace_bo;
542 uint32_t *trace_id_ptr;
543
544 struct radv_physical_device *physical_device;
545
546 /* Backup in-memory cache to be used if the app doesn't provide one */
547 struct radv_pipeline_cache * mem_cache;
548
549 /*
550 * use different counters so MSAA MRTs get consecutive surface indices,
551 * even if MASK is allocated in between.
552 */
553 uint32_t image_mrt_offset_counter;
554 uint32_t fmask_mrt_offset_counter;
555 struct list_head shader_slabs;
556 mtx_t shader_slab_mutex;
557
558 /* For detecting VM faults reported by dmesg. */
559 uint64_t dmesg_timestamp;
560 };
561
562 struct radv_device_memory {
563 struct radeon_winsys_bo *bo;
564 /* for dedicated allocations */
565 struct radv_image *image;
566 struct radv_buffer *buffer;
567 uint32_t type_index;
568 VkDeviceSize map_size;
569 void * map;
570 };
571
572
573 struct radv_descriptor_range {
574 uint64_t va;
575 uint32_t size;
576 };
577
578 struct radv_descriptor_set {
579 const struct radv_descriptor_set_layout *layout;
580 uint32_t size;
581
582 struct radeon_winsys_bo *bo;
583 uint64_t va;
584 uint32_t *mapped_ptr;
585 struct radv_descriptor_range *dynamic_descriptors;
586
587 struct list_head vram_list;
588
589 struct radeon_winsys_bo *descriptors[0];
590 };
591
592 struct radv_push_descriptor_set
593 {
594 struct radv_descriptor_set set;
595 uint32_t capacity;
596 };
597
598 struct radv_descriptor_pool {
599 struct radeon_winsys_bo *bo;
600 uint8_t *mapped_ptr;
601 uint64_t current_offset;
602 uint64_t size;
603
604 struct list_head vram_list;
605
606 uint8_t *host_memory_base;
607 uint8_t *host_memory_ptr;
608 uint8_t *host_memory_end;
609 };
610
611 struct radv_descriptor_update_template_entry {
612 VkDescriptorType descriptor_type;
613
614 /* The number of descriptors to update */
615 uint32_t descriptor_count;
616
617 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
618 uint32_t dst_offset;
619
620 /* In dwords. Not valid/used for dynamic descriptors */
621 uint32_t dst_stride;
622
623 uint32_t buffer_offset;
624
625 /* Only valid for combined image samplers and samplers */
626 uint16_t has_sampler;
627
628 /* In bytes */
629 size_t src_offset;
630 size_t src_stride;
631
632 /* For push descriptors */
633 const uint32_t *immutable_samplers;
634 };
635
636 struct radv_descriptor_update_template {
637 uint32_t entry_count;
638 struct radv_descriptor_update_template_entry entry[0];
639 };
640
641 struct radv_buffer {
642 struct radv_device * device;
643 VkDeviceSize size;
644
645 VkBufferUsageFlags usage;
646 VkBufferCreateFlags flags;
647
648 /* Set when bound */
649 struct radeon_winsys_bo * bo;
650 VkDeviceSize offset;
651 };
652
653
654 enum radv_cmd_dirty_bits {
655 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
656 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
657 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
658 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
659 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
660 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
661 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
662 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
663 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
664 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
665 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
666 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
667 RADV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
668 };
669 typedef uint32_t radv_cmd_dirty_mask_t;
670
671 enum radv_cmd_flush_bits {
672 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
673 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
674 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
675 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
676 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
677 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
678 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
679 /* Same as above, but only writes back and doesn't invalidate */
680 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
681 /* Framebuffer caches */
682 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
683 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
684 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
685 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
686 /* Engine synchronization. */
687 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
688 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
689 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
690 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
691
692 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
693 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
694 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
695 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
696 };
697
698 struct radv_vertex_binding {
699 struct radv_buffer * buffer;
700 VkDeviceSize offset;
701 };
702
703 struct radv_dynamic_state {
704 struct {
705 uint32_t count;
706 VkViewport viewports[MAX_VIEWPORTS];
707 } viewport;
708
709 struct {
710 uint32_t count;
711 VkRect2D scissors[MAX_SCISSORS];
712 } scissor;
713
714 float line_width;
715
716 struct {
717 float bias;
718 float clamp;
719 float slope;
720 } depth_bias;
721
722 float blend_constants[4];
723
724 struct {
725 float min;
726 float max;
727 } depth_bounds;
728
729 struct {
730 uint32_t front;
731 uint32_t back;
732 } stencil_compare_mask;
733
734 struct {
735 uint32_t front;
736 uint32_t back;
737 } stencil_write_mask;
738
739 struct {
740 uint32_t front;
741 uint32_t back;
742 } stencil_reference;
743 };
744
745 extern const struct radv_dynamic_state default_dynamic_state;
746
747 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
748 const struct radv_dynamic_state *src,
749 uint32_t copy_mask);
750
751 const char *
752 radv_get_debug_option_name(int id);
753
754 const char *
755 radv_get_perftest_option_name(int id);
756
757 /**
758 * Attachment state when recording a renderpass instance.
759 *
760 * The clear value is valid only if there exists a pending clear.
761 */
762 struct radv_attachment_state {
763 VkImageAspectFlags pending_clear_aspects;
764 uint32_t cleared_views;
765 VkClearValue clear_value;
766 VkImageLayout current_layout;
767 };
768
769 struct radv_cmd_state {
770 bool vb_dirty;
771 radv_cmd_dirty_mask_t dirty;
772 bool push_descriptors_dirty;
773 bool predicating;
774
775 struct radv_pipeline * pipeline;
776 struct radv_pipeline * emitted_pipeline;
777 struct radv_pipeline * compute_pipeline;
778 struct radv_pipeline * emitted_compute_pipeline;
779 struct radv_framebuffer * framebuffer;
780 struct radv_render_pass * pass;
781 const struct radv_subpass * subpass;
782 struct radv_dynamic_state dynamic;
783 struct radv_vertex_binding vertex_bindings[MAX_VBS];
784 struct radv_descriptor_set * descriptors[MAX_SETS];
785 struct radv_attachment_state * attachments;
786 VkRect2D render_area;
787 uint32_t index_type;
788 uint32_t max_index_count;
789 uint64_t index_va;
790 int32_t last_primitive_reset_en;
791 uint32_t last_primitive_reset_index;
792 enum radv_cmd_flush_bits flush_bits;
793 unsigned active_occlusion_queries;
794 float offset_scale;
795 uint32_t descriptors_dirty;
796 uint32_t trace_id;
797 uint32_t last_ia_multi_vgt_param;
798 };
799
800 struct radv_cmd_pool {
801 VkAllocationCallbacks alloc;
802 struct list_head cmd_buffers;
803 struct list_head free_cmd_buffers;
804 uint32_t queue_family_index;
805 };
806
807 struct radv_cmd_buffer_upload {
808 uint8_t *map;
809 unsigned offset;
810 uint64_t size;
811 struct radeon_winsys_bo *upload_bo;
812 struct list_head list;
813 };
814
815 struct radv_cmd_buffer {
816 VK_LOADER_DATA _loader_data;
817
818 struct radv_device * device;
819
820 struct radv_cmd_pool * pool;
821 struct list_head pool_link;
822
823 VkCommandBufferUsageFlags usage_flags;
824 VkCommandBufferLevel level;
825 struct radeon_winsys_cs *cs;
826 struct radv_cmd_state state;
827 uint32_t queue_family_index;
828
829 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
830 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
831 VkShaderStageFlags push_constant_stages;
832 struct radv_push_descriptor_set push_descriptors;
833 struct radv_descriptor_set meta_push_descriptors;
834
835 struct radv_cmd_buffer_upload upload;
836
837 uint32_t scratch_size_needed;
838 uint32_t compute_scratch_size_needed;
839 uint32_t esgs_ring_size_needed;
840 uint32_t gsvs_ring_size_needed;
841 bool tess_rings_needed;
842 bool sample_positions_needed;
843
844 VkResult record_result;
845
846 int ring_offsets_idx; /* just used for verification */
847 uint32_t gfx9_fence_offset;
848 struct radeon_winsys_bo *gfx9_fence_bo;
849 uint32_t gfx9_fence_idx;
850 };
851
852 struct radv_image;
853
854 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
855
856 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
857 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
858
859 void cik_create_gfx_config(struct radv_device *device);
860
861 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
862 int count, const VkViewport *viewports);
863 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
864 int count, const VkRect2D *scissors,
865 const VkViewport *viewports, bool can_use_guardband);
866 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
867 bool instanced_draw, bool indirect_draw,
868 uint32_t draw_vertex_count);
869 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
870 bool predicated,
871 enum chip_class chip_class,
872 bool is_mec,
873 unsigned event, unsigned event_flags,
874 unsigned data_sel,
875 uint64_t va,
876 uint32_t old_fence,
877 uint32_t new_fence);
878
879 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
880 bool predicated,
881 uint64_t va, uint32_t ref,
882 uint32_t mask);
883 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
884 bool predicated,
885 enum chip_class chip_class,
886 uint32_t *fence_ptr, uint64_t va,
887 bool is_mec,
888 enum radv_cmd_flush_bits flush_bits);
889 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
890 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
891 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
892 uint64_t src_va, uint64_t dest_va,
893 uint64_t size);
894 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
895 unsigned size);
896 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
897 uint64_t size, unsigned value);
898 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
899 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
900 struct radv_descriptor_set *set,
901 unsigned idx);
902 bool
903 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
904 unsigned size,
905 unsigned alignment,
906 unsigned *out_offset,
907 void **ptr);
908 void
909 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
910 const struct radv_subpass *subpass,
911 bool transitions);
912 bool
913 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
914 unsigned size, unsigned alignmnet,
915 const void *data, unsigned *out_offset);
916 void
917 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
918 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
919 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
920 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
921 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
922 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
923 unsigned radv_cayman_get_maxdist(int log_samples);
924 void radv_device_init_msaa(struct radv_device *device);
925 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
926 struct radv_image *image,
927 VkClearDepthStencilValue ds_clear_value,
928 VkImageAspectFlags aspects);
929 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
930 struct radv_image *image,
931 int idx,
932 uint32_t color_values[2]);
933 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
934 struct radv_image *image,
935 bool value);
936 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
937 struct radeon_winsys_bo *bo,
938 uint64_t offset, uint64_t size, uint32_t value);
939 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
940 bool radv_get_memory_fd(struct radv_device *device,
941 struct radv_device_memory *memory,
942 int *pFD);
943 /*
944 * Takes x,y,z as exact numbers of invocations, instead of blocks.
945 *
946 * Limitations: Can't call normal dispatch functions without binding or rebinding
947 * the compute pipeline.
948 */
949 void radv_unaligned_dispatch(
950 struct radv_cmd_buffer *cmd_buffer,
951 uint32_t x,
952 uint32_t y,
953 uint32_t z);
954
955 struct radv_event {
956 struct radeon_winsys_bo *bo;
957 uint64_t *map;
958 };
959
960 struct radv_shader_module;
961 struct ac_shader_variant_key;
962
963 void
964 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
965 const char *entrypoint,
966 const VkSpecializationInfo *spec_info,
967 const struct radv_pipeline_layout *layout,
968 const struct ac_shader_variant_key *key,
969 uint32_t is_geom_copy_shader);
970
971 static inline gl_shader_stage
972 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
973 {
974 assert(__builtin_popcount(vk_stage) == 1);
975 return ffs(vk_stage) - 1;
976 }
977
978 static inline VkShaderStageFlagBits
979 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
980 {
981 return (1 << mesa_stage);
982 }
983
984 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
985
986 #define radv_foreach_stage(stage, stage_bits) \
987 for (gl_shader_stage stage, \
988 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
989 stage = __builtin_ffs(__tmp) - 1, __tmp; \
990 __tmp &= ~(1 << (stage)))
991
992 struct radv_depth_stencil_state {
993 uint32_t db_depth_control;
994 uint32_t db_stencil_control;
995 uint32_t db_render_control;
996 uint32_t db_render_override2;
997 };
998
999 struct radv_blend_state {
1000 uint32_t cb_color_control;
1001 uint32_t cb_target_mask;
1002 uint32_t sx_mrt_blend_opt[8];
1003 uint32_t cb_blend_control[8];
1004
1005 uint32_t spi_shader_col_format;
1006 uint32_t cb_shader_mask;
1007 uint32_t db_alpha_to_mask;
1008 };
1009
1010 unsigned radv_format_meta_fs_key(VkFormat format);
1011
1012 struct radv_raster_state {
1013 uint32_t pa_cl_clip_cntl;
1014 uint32_t spi_interp_control;
1015 uint32_t pa_su_point_size;
1016 uint32_t pa_su_point_minmax;
1017 uint32_t pa_su_line_cntl;
1018 uint32_t pa_su_vtx_cntl;
1019 uint32_t pa_su_sc_mode_cntl;
1020 };
1021
1022 struct radv_multisample_state {
1023 uint32_t db_eqaa;
1024 uint32_t pa_sc_line_cntl;
1025 uint32_t pa_sc_mode_cntl_0;
1026 uint32_t pa_sc_mode_cntl_1;
1027 uint32_t pa_sc_aa_config;
1028 uint32_t pa_sc_aa_mask[2];
1029 unsigned num_samples;
1030 };
1031
1032 struct radv_prim_vertex_count {
1033 uint8_t min;
1034 uint8_t incr;
1035 };
1036
1037 struct radv_tessellation_state {
1038 uint32_t ls_hs_config;
1039 uint32_t tcs_in_layout;
1040 uint32_t tcs_out_layout;
1041 uint32_t tcs_out_offsets;
1042 uint32_t offchip_layout;
1043 unsigned num_patches;
1044 unsigned lds_size;
1045 unsigned num_tcs_input_cp;
1046 uint32_t tf_param;
1047 };
1048
1049 struct radv_vertex_elements_info {
1050 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1051 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1052 uint32_t binding[MAX_VERTEX_ATTRIBS];
1053 uint32_t offset[MAX_VERTEX_ATTRIBS];
1054 uint32_t count;
1055 };
1056
1057 #define SI_GS_PER_ES 128
1058
1059 struct radv_pipeline {
1060 struct radv_device * device;
1061 uint32_t dynamic_state_mask;
1062 struct radv_dynamic_state dynamic_state;
1063
1064 struct radv_pipeline_layout * layout;
1065
1066 bool needs_data_cache;
1067 bool need_indirect_descriptor_sets;
1068 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1069 struct radv_shader_variant *gs_copy_shader;
1070 VkShaderStageFlags active_stages;
1071
1072 struct radv_vertex_elements_info vertex_elements;
1073
1074 uint32_t binding_stride[MAX_VBS];
1075
1076 union {
1077 struct {
1078 struct radv_blend_state blend;
1079 struct radv_depth_stencil_state ds;
1080 struct radv_raster_state raster;
1081 struct radv_multisample_state ms;
1082 struct radv_tessellation_state tess;
1083 uint32_t db_shader_control;
1084 uint32_t shader_z_format;
1085 unsigned prim;
1086 unsigned gs_out;
1087 uint32_t vgt_gs_mode;
1088 bool vgt_primitiveid_en;
1089 bool prim_restart_enable;
1090 bool partial_es_wave;
1091 uint8_t primgroup_size;
1092 unsigned esgs_ring_size;
1093 unsigned gsvs_ring_size;
1094 uint32_t ps_input_cntl[32];
1095 uint32_t ps_input_cntl_num;
1096 uint32_t pa_cl_vs_out_cntl;
1097 uint32_t vgt_shader_stages_en;
1098 uint32_t vtx_base_sgpr;
1099 uint32_t base_ia_multi_vgt_param;
1100 bool wd_switch_on_eop;
1101 bool ia_switch_on_eoi;
1102 bool partial_vs_wave;
1103 uint8_t vtx_emit_num;
1104 struct radv_prim_vertex_count prim_vertex_count;
1105 bool can_use_guardband;
1106 } graphics;
1107 };
1108
1109 unsigned max_waves;
1110 unsigned scratch_bytes_per_wave;
1111 };
1112
1113 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1114 {
1115 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1116 }
1117
1118 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1119 {
1120 return pipeline->shaders[MESA_SHADER_TESS_EVAL] ? true : false;
1121 }
1122
1123 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1124 gl_shader_stage stage,
1125 int idx);
1126
1127 struct radv_graphics_pipeline_create_info {
1128 bool use_rectlist;
1129 bool db_depth_clear;
1130 bool db_stencil_clear;
1131 bool db_depth_disable_expclear;
1132 bool db_stencil_disable_expclear;
1133 bool db_flush_depth_inplace;
1134 bool db_flush_stencil_inplace;
1135 bool db_resummarize;
1136 uint32_t custom_blend_mode;
1137 };
1138
1139 VkResult
1140 radv_graphics_pipeline_create(VkDevice device,
1141 VkPipelineCache cache,
1142 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1143 const struct radv_graphics_pipeline_create_info *extra,
1144 const VkAllocationCallbacks *alloc,
1145 VkPipeline *pPipeline);
1146
1147 struct vk_format_description;
1148 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1149 int first_non_void);
1150 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1151 int first_non_void);
1152 uint32_t radv_translate_colorformat(VkFormat format);
1153 uint32_t radv_translate_color_numformat(VkFormat format,
1154 const struct vk_format_description *desc,
1155 int first_non_void);
1156 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1157 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1158 uint32_t radv_translate_dbformat(VkFormat format);
1159 uint32_t radv_translate_tex_dataformat(VkFormat format,
1160 const struct vk_format_description *desc,
1161 int first_non_void);
1162 uint32_t radv_translate_tex_numformat(VkFormat format,
1163 const struct vk_format_description *desc,
1164 int first_non_void);
1165 bool radv_format_pack_clear_color(VkFormat format,
1166 uint32_t clear_vals[2],
1167 VkClearColorValue *value);
1168 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1169 bool radv_dcc_formats_compatible(VkFormat format1,
1170 VkFormat format2);
1171
1172 struct radv_fmask_info {
1173 uint64_t offset;
1174 uint64_t size;
1175 unsigned alignment;
1176 unsigned pitch_in_pixels;
1177 unsigned bank_height;
1178 unsigned slice_tile_max;
1179 unsigned tile_mode_index;
1180 unsigned tile_swizzle;
1181 };
1182
1183 struct radv_cmask_info {
1184 uint64_t offset;
1185 uint64_t size;
1186 unsigned alignment;
1187 unsigned slice_tile_max;
1188 unsigned base_address_reg;
1189 };
1190
1191 struct r600_htile_info {
1192 uint64_t offset;
1193 uint64_t size;
1194 unsigned pitch;
1195 unsigned height;
1196 unsigned xalign;
1197 unsigned yalign;
1198 };
1199
1200 struct radv_image {
1201 VkImageType type;
1202 /* The original VkFormat provided by the client. This may not match any
1203 * of the actual surface formats.
1204 */
1205 VkFormat vk_format;
1206 VkImageAspectFlags aspects;
1207 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1208 struct ac_surf_info info;
1209 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1210 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1211
1212 VkDeviceSize size;
1213 uint32_t alignment;
1214
1215 unsigned queue_family_mask;
1216 bool exclusive;
1217 bool shareable;
1218
1219 /* Set when bound */
1220 struct radeon_winsys_bo *bo;
1221 VkDeviceSize offset;
1222 uint32_t dcc_offset;
1223 uint32_t htile_offset;
1224 struct radeon_surf surface;
1225
1226 struct radv_fmask_info fmask;
1227 struct radv_cmask_info cmask;
1228 uint32_t clear_value_offset;
1229 uint32_t dcc_pred_offset;
1230 };
1231
1232 /* Whether the image has a htile that is known consistent with the contents of
1233 * the image. */
1234 bool radv_layout_has_htile(const struct radv_image *image,
1235 VkImageLayout layout,
1236 unsigned queue_mask);
1237
1238 /* Whether the image has a htile that is known consistent with the contents of
1239 * the image and is allowed to be in compressed form.
1240 *
1241 * If this is false reads that don't use the htile should be able to return
1242 * correct results.
1243 */
1244 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1245 VkImageLayout layout,
1246 unsigned queue_mask);
1247
1248 bool radv_layout_can_fast_clear(const struct radv_image *image,
1249 VkImageLayout layout,
1250 unsigned queue_mask);
1251
1252
1253 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1254
1255 static inline uint32_t
1256 radv_get_layerCount(const struct radv_image *image,
1257 const VkImageSubresourceRange *range)
1258 {
1259 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1260 image->info.array_size - range->baseArrayLayer : range->layerCount;
1261 }
1262
1263 static inline uint32_t
1264 radv_get_levelCount(const struct radv_image *image,
1265 const VkImageSubresourceRange *range)
1266 {
1267 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1268 image->info.levels - range->baseMipLevel : range->levelCount;
1269 }
1270
1271 struct radeon_bo_metadata;
1272 void
1273 radv_init_metadata(struct radv_device *device,
1274 struct radv_image *image,
1275 struct radeon_bo_metadata *metadata);
1276
1277 struct radv_image_view {
1278 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1279 struct radeon_winsys_bo *bo;
1280
1281 VkImageViewType type;
1282 VkImageAspectFlags aspect_mask;
1283 VkFormat vk_format;
1284 uint32_t base_layer;
1285 uint32_t layer_count;
1286 uint32_t base_mip;
1287 uint32_t level_count;
1288 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1289
1290 uint32_t descriptor[8];
1291 uint32_t fmask_descriptor[8];
1292
1293 /* Descriptor for use as a storage image as opposed to a sampled image.
1294 * This has a few differences for cube maps (e.g. type).
1295 */
1296 uint32_t storage_descriptor[8];
1297 uint32_t storage_fmask_descriptor[8];
1298 };
1299
1300 struct radv_image_create_info {
1301 const VkImageCreateInfo *vk_info;
1302 bool scanout;
1303 };
1304
1305 VkResult radv_image_create(VkDevice _device,
1306 const struct radv_image_create_info *info,
1307 const VkAllocationCallbacks* alloc,
1308 VkImage *pImage);
1309
1310 void radv_image_view_init(struct radv_image_view *view,
1311 struct radv_device *device,
1312 const VkImageViewCreateInfo* pCreateInfo);
1313
1314 struct radv_buffer_view {
1315 struct radeon_winsys_bo *bo;
1316 VkFormat vk_format;
1317 uint64_t range; /**< VkBufferViewCreateInfo::range */
1318 uint32_t state[4];
1319 };
1320 void radv_buffer_view_init(struct radv_buffer_view *view,
1321 struct radv_device *device,
1322 const VkBufferViewCreateInfo* pCreateInfo);
1323
1324 static inline struct VkExtent3D
1325 radv_sanitize_image_extent(const VkImageType imageType,
1326 const struct VkExtent3D imageExtent)
1327 {
1328 switch (imageType) {
1329 case VK_IMAGE_TYPE_1D:
1330 return (VkExtent3D) { imageExtent.width, 1, 1 };
1331 case VK_IMAGE_TYPE_2D:
1332 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1333 case VK_IMAGE_TYPE_3D:
1334 return imageExtent;
1335 default:
1336 unreachable("invalid image type");
1337 }
1338 }
1339
1340 static inline struct VkOffset3D
1341 radv_sanitize_image_offset(const VkImageType imageType,
1342 const struct VkOffset3D imageOffset)
1343 {
1344 switch (imageType) {
1345 case VK_IMAGE_TYPE_1D:
1346 return (VkOffset3D) { imageOffset.x, 0, 0 };
1347 case VK_IMAGE_TYPE_2D:
1348 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1349 case VK_IMAGE_TYPE_3D:
1350 return imageOffset;
1351 default:
1352 unreachable("invalid image type");
1353 }
1354 }
1355
1356 static inline bool
1357 radv_image_extent_compare(const struct radv_image *image,
1358 const VkExtent3D *extent)
1359 {
1360 if (extent->width != image->info.width ||
1361 extent->height != image->info.height ||
1362 extent->depth != image->info.depth)
1363 return false;
1364 return true;
1365 }
1366
1367 struct radv_sampler {
1368 uint32_t state[4];
1369 };
1370
1371 struct radv_color_buffer_info {
1372 uint64_t cb_color_base;
1373 uint64_t cb_color_cmask;
1374 uint64_t cb_color_fmask;
1375 uint64_t cb_dcc_base;
1376 uint32_t cb_color_pitch;
1377 uint32_t cb_color_slice;
1378 uint32_t cb_color_view;
1379 uint32_t cb_color_info;
1380 uint32_t cb_color_attrib;
1381 uint32_t cb_color_attrib2;
1382 uint32_t cb_dcc_control;
1383 uint32_t cb_color_cmask_slice;
1384 uint32_t cb_color_fmask_slice;
1385 uint32_t cb_clear_value0;
1386 uint32_t cb_clear_value1;
1387 uint32_t micro_tile_mode;
1388 uint32_t gfx9_epitch;
1389 };
1390
1391 struct radv_ds_buffer_info {
1392 uint64_t db_z_read_base;
1393 uint64_t db_stencil_read_base;
1394 uint64_t db_z_write_base;
1395 uint64_t db_stencil_write_base;
1396 uint64_t db_htile_data_base;
1397 uint32_t db_depth_info;
1398 uint32_t db_z_info;
1399 uint32_t db_stencil_info;
1400 uint32_t db_depth_view;
1401 uint32_t db_depth_size;
1402 uint32_t db_depth_slice;
1403 uint32_t db_htile_surface;
1404 uint32_t pa_su_poly_offset_db_fmt_cntl;
1405 uint32_t db_z_info2;
1406 uint32_t db_stencil_info2;
1407 float offset_scale;
1408 };
1409
1410 struct radv_attachment_info {
1411 union {
1412 struct radv_color_buffer_info cb;
1413 struct radv_ds_buffer_info ds;
1414 };
1415 struct radv_image_view *attachment;
1416 };
1417
1418 struct radv_framebuffer {
1419 uint32_t width;
1420 uint32_t height;
1421 uint32_t layers;
1422
1423 uint32_t attachment_count;
1424 struct radv_attachment_info attachments[0];
1425 };
1426
1427 struct radv_subpass_barrier {
1428 VkPipelineStageFlags src_stage_mask;
1429 VkAccessFlags src_access_mask;
1430 VkAccessFlags dst_access_mask;
1431 };
1432
1433 struct radv_subpass {
1434 uint32_t input_count;
1435 uint32_t color_count;
1436 VkAttachmentReference * input_attachments;
1437 VkAttachmentReference * color_attachments;
1438 VkAttachmentReference * resolve_attachments;
1439 VkAttachmentReference depth_stencil_attachment;
1440
1441 /** Subpass has at least one resolve attachment */
1442 bool has_resolve;
1443
1444 struct radv_subpass_barrier start_barrier;
1445
1446 uint32_t view_mask;
1447 };
1448
1449 struct radv_render_pass_attachment {
1450 VkFormat format;
1451 uint32_t samples;
1452 VkAttachmentLoadOp load_op;
1453 VkAttachmentLoadOp stencil_load_op;
1454 VkImageLayout initial_layout;
1455 VkImageLayout final_layout;
1456 uint32_t view_mask;
1457 };
1458
1459 struct radv_render_pass {
1460 uint32_t attachment_count;
1461 uint32_t subpass_count;
1462 VkAttachmentReference * subpass_attachments;
1463 struct radv_render_pass_attachment * attachments;
1464 struct radv_subpass_barrier end_barrier;
1465 struct radv_subpass subpasses[0];
1466 };
1467
1468 VkResult radv_device_init_meta(struct radv_device *device);
1469 void radv_device_finish_meta(struct radv_device *device);
1470
1471 struct radv_query_pool {
1472 struct radeon_winsys_bo *bo;
1473 uint32_t stride;
1474 uint32_t availability_offset;
1475 char *ptr;
1476 VkQueryType type;
1477 uint32_t pipeline_stats_mask;
1478 };
1479
1480 struct radv_semaphore {
1481 /* use a winsys sem for non-exportable */
1482 struct radeon_winsys_sem *sem;
1483 uint32_t syncobj;
1484 uint32_t temp_syncobj;
1485 };
1486
1487 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1488 int num_wait_sems,
1489 const VkSemaphore *wait_sems,
1490 int num_signal_sems,
1491 const VkSemaphore *signal_sems);
1492 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1493
1494 void
1495 radv_update_descriptor_sets(struct radv_device *device,
1496 struct radv_cmd_buffer *cmd_buffer,
1497 VkDescriptorSet overrideSet,
1498 uint32_t descriptorWriteCount,
1499 const VkWriteDescriptorSet *pDescriptorWrites,
1500 uint32_t descriptorCopyCount,
1501 const VkCopyDescriptorSet *pDescriptorCopies);
1502
1503 void
1504 radv_update_descriptor_set_with_template(struct radv_device *device,
1505 struct radv_cmd_buffer *cmd_buffer,
1506 struct radv_descriptor_set *set,
1507 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1508 const void *pData);
1509
1510 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1511 VkPipelineBindPoint pipelineBindPoint,
1512 VkPipelineLayout _layout,
1513 uint32_t set,
1514 uint32_t descriptorWriteCount,
1515 const VkWriteDescriptorSet *pDescriptorWrites);
1516
1517 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1518 struct radv_image *image, uint32_t value);
1519 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1520 struct radv_image *image, uint32_t value);
1521
1522 struct radv_fence {
1523 struct radeon_winsys_fence *fence;
1524 bool submitted;
1525 bool signalled;
1526 };
1527
1528 struct radeon_winsys_sem;
1529
1530 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1531 \
1532 static inline struct __radv_type * \
1533 __radv_type ## _from_handle(__VkType _handle) \
1534 { \
1535 return (struct __radv_type *) _handle; \
1536 } \
1537 \
1538 static inline __VkType \
1539 __radv_type ## _to_handle(struct __radv_type *_obj) \
1540 { \
1541 return (__VkType) _obj; \
1542 }
1543
1544 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1545 \
1546 static inline struct __radv_type * \
1547 __radv_type ## _from_handle(__VkType _handle) \
1548 { \
1549 return (struct __radv_type *)(uintptr_t) _handle; \
1550 } \
1551 \
1552 static inline __VkType \
1553 __radv_type ## _to_handle(struct __radv_type *_obj) \
1554 { \
1555 return (__VkType)(uintptr_t) _obj; \
1556 }
1557
1558 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1559 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1560
1561 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1562 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1563 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1564 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1565 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1566
1567 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1568 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1569 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1570 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1571 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1572 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1573 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1574 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1575 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1576 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1577 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1578 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1579 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1580 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1581 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1582 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1583 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1584 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1585 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1586 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1587 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1588
1589 #endif /* RADV_PRIVATE_H */