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radv: start fixing up queue allocate for multiple queues
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/vk_alloc.h"
51 #include "main/macros.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "radv_descriptor_set.h"
57
58 #include <llvm-c/TargetMachine.h>
59
60 /* Pre-declarations needed for WSI entrypoints */
61 struct wl_surface;
62 struct wl_display;
63 typedef struct xcb_connection_t xcb_connection_t;
64 typedef uint32_t xcb_visualid_t;
65 typedef uint32_t xcb_window_t;
66
67 #include <vulkan/vulkan.h>
68 #include <vulkan/vulkan_intel.h>
69 #include <vulkan/vk_icd.h>
70
71 #include "radv_entrypoints.h"
72
73 #include "wsi_common.h"
74
75 #define MAX_VBS 32
76 #define MAX_VERTEX_ATTRIBS 32
77 #define MAX_RTS 8
78 #define MAX_VIEWPORTS 16
79 #define MAX_SCISSORS 16
80 #define MAX_PUSH_CONSTANTS_SIZE 128
81 #define MAX_DYNAMIC_BUFFERS 16
82 #define MAX_IMAGES 8
83 #define MAX_SAMPLES_LOG2 4 /* SKL supports 16 samples */
84 #define NUM_META_FS_KEYS 11
85
86 #define NUM_DEPTH_CLEAR_PIPELINES 3
87
88 enum radv_mem_heap {
89 RADV_MEM_HEAP_VRAM,
90 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
91 RADV_MEM_HEAP_GTT,
92 RADV_MEM_HEAP_COUNT
93 };
94
95 enum radv_mem_type {
96 RADV_MEM_TYPE_VRAM,
97 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
98 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
99 RADV_MEM_TYPE_GTT_CACHED,
100 RADV_MEM_TYPE_COUNT
101 };
102
103 #define radv_noreturn __attribute__((__noreturn__))
104 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
105
106 static inline uint32_t
107 align_u32(uint32_t v, uint32_t a)
108 {
109 assert(a != 0 && a == (a & -a));
110 return (v + a - 1) & ~(a - 1);
111 }
112
113 static inline uint32_t
114 align_u32_npot(uint32_t v, uint32_t a)
115 {
116 return (v + a - 1) / a * a;
117 }
118
119 static inline uint64_t
120 align_u64(uint64_t v, uint64_t a)
121 {
122 assert(a != 0 && a == (a & -a));
123 return (v + a - 1) & ~(a - 1);
124 }
125
126 static inline int32_t
127 align_i32(int32_t v, int32_t a)
128 {
129 assert(a != 0 && a == (a & -a));
130 return (v + a - 1) & ~(a - 1);
131 }
132
133 /** Alignment must be a power of 2. */
134 static inline bool
135 radv_is_aligned(uintmax_t n, uintmax_t a)
136 {
137 assert(a == (a & -a));
138 return (n & (a - 1)) == 0;
139 }
140
141 static inline uint32_t
142 round_up_u32(uint32_t v, uint32_t a)
143 {
144 return (v + a - 1) / a;
145 }
146
147 static inline uint64_t
148 round_up_u64(uint64_t v, uint64_t a)
149 {
150 return (v + a - 1) / a;
151 }
152
153 static inline uint32_t
154 radv_minify(uint32_t n, uint32_t levels)
155 {
156 if (unlikely(n == 0))
157 return 0;
158 else
159 return MAX2(n >> levels, 1);
160 }
161 static inline float
162 radv_clamp_f(float f, float min, float max)
163 {
164 assert(min < max);
165
166 if (f > max)
167 return max;
168 else if (f < min)
169 return min;
170 else
171 return f;
172 }
173
174 static inline bool
175 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
176 {
177 if (*inout_mask & clear_mask) {
178 *inout_mask &= ~clear_mask;
179 return true;
180 } else {
181 return false;
182 }
183 }
184
185 #define for_each_bit(b, dword) \
186 for (uint32_t __dword = (dword); \
187 (b) = __builtin_ffs(__dword) - 1, __dword; \
188 __dword &= ~(1 << (b)))
189
190 #define typed_memcpy(dest, src, count) ({ \
191 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
192 memcpy((dest), (src), (count) * sizeof(*(src))); \
193 })
194
195 #define zero(x) (memset(&(x), 0, sizeof(x)))
196
197 /* Whenever we generate an error, pass it through this function. Useful for
198 * debugging, where we can break on it. Only call at error site, not when
199 * propagating errors. Might be useful to plug in a stack trace here.
200 */
201
202 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
203
204 #ifdef DEBUG
205 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
206 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
207 #else
208 #define vk_error(error) error
209 #define vk_errorf(error, format, ...) error
210 #endif
211
212 void __radv_finishme(const char *file, int line, const char *format, ...)
213 radv_printflike(3, 4);
214 void radv_loge(const char *format, ...) radv_printflike(1, 2);
215 void radv_loge_v(const char *format, va_list va);
216
217 /**
218 * Print a FINISHME message, including its source location.
219 */
220 #define radv_finishme(format, ...) \
221 do { \
222 static bool reported = false; \
223 if (!reported) { \
224 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
225 reported = true; \
226 } \
227 } while (0)
228
229 /* A non-fatal assert. Useful for debugging. */
230 #ifdef DEBUG
231 #define radv_assert(x) ({ \
232 if (unlikely(!(x))) \
233 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
234 })
235 #else
236 #define radv_assert(x)
237 #endif
238
239 void radv_abortf(const char *format, ...) radv_noreturn radv_printflike(1, 2);
240 void radv_abortfv(const char *format, va_list va) radv_noreturn;
241
242 #define stub_return(v) \
243 do { \
244 radv_finishme("stub %s", __func__); \
245 return (v); \
246 } while (0)
247
248 #define stub() \
249 do { \
250 radv_finishme("stub %s", __func__); \
251 return; \
252 } while (0)
253
254 void *radv_resolve_entrypoint(uint32_t index);
255 void *radv_lookup_entrypoint(const char *name);
256
257 extern struct radv_dispatch_table dtable;
258
259 struct radv_physical_device {
260 VK_LOADER_DATA _loader_data;
261
262 struct radv_instance * instance;
263
264 struct radeon_winsys *ws;
265 struct radeon_info rad_info;
266 uint32_t chipset_id;
267 char path[20];
268 const char * name;
269 uint64_t aperture_size;
270 int cmd_parser_version;
271 uint32_t pci_vendor_id;
272 uint32_t pci_device_id;
273
274 uint8_t uuid[VK_UUID_SIZE];
275
276 struct wsi_device wsi_device;
277 };
278
279 struct radv_instance {
280 VK_LOADER_DATA _loader_data;
281
282 VkAllocationCallbacks alloc;
283
284 uint32_t apiVersion;
285 int physicalDeviceCount;
286 struct radv_physical_device physicalDevice;
287 };
288
289 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
290 void radv_finish_wsi(struct radv_physical_device *physical_device);
291
292 struct cache_entry;
293
294 struct radv_pipeline_cache {
295 struct radv_device * device;
296 pthread_mutex_t mutex;
297
298 uint32_t total_size;
299 uint32_t table_size;
300 uint32_t kernel_count;
301 struct cache_entry ** hash_table;
302 bool modified;
303
304 VkAllocationCallbacks alloc;
305 };
306
307 void
308 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
309 struct radv_device *device);
310 void
311 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
312 void
313 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
314 const void *data, size_t size);
315
316 struct radv_shader_variant *
317 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
318 struct radv_pipeline_cache *cache,
319 const unsigned char *sha1);
320
321 struct radv_shader_variant *
322 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
323 const unsigned char *sha1,
324 struct radv_shader_variant *variant,
325 const void *code, unsigned code_size);
326
327 void radv_shader_variant_destroy(struct radv_device *device,
328 struct radv_shader_variant *variant);
329
330 struct radv_meta_state {
331 VkAllocationCallbacks alloc;
332
333 struct radv_pipeline_cache cache;
334
335 /**
336 * Use array element `i` for images with `2^i` samples.
337 */
338 struct {
339 VkRenderPass render_pass[NUM_META_FS_KEYS];
340 struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
341
342 VkRenderPass depth_only_rp[NUM_DEPTH_CLEAR_PIPELINES];
343 struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
344 VkRenderPass stencil_only_rp[NUM_DEPTH_CLEAR_PIPELINES];
345 struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
346 VkRenderPass depthstencil_rp[NUM_DEPTH_CLEAR_PIPELINES];
347 struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
348 } clear[1 + MAX_SAMPLES_LOG2];
349
350 struct {
351 VkRenderPass render_pass[NUM_META_FS_KEYS];
352
353 /** Pipeline that blits from a 1D image. */
354 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
355
356 /** Pipeline that blits from a 2D image. */
357 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
358
359 /** Pipeline that blits from a 3D image. */
360 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
361
362 VkRenderPass depth_only_rp;
363 VkPipeline depth_only_1d_pipeline;
364 VkPipeline depth_only_2d_pipeline;
365 VkPipeline depth_only_3d_pipeline;
366
367 VkRenderPass stencil_only_rp;
368 VkPipeline stencil_only_1d_pipeline;
369 VkPipeline stencil_only_2d_pipeline;
370 VkPipeline stencil_only_3d_pipeline;
371 VkPipelineLayout pipeline_layout;
372 VkDescriptorSetLayout ds_layout;
373 } blit;
374
375 struct {
376 VkRenderPass render_passes[NUM_META_FS_KEYS];
377
378 VkPipelineLayout p_layouts[2];
379 VkDescriptorSetLayout ds_layouts[2];
380 VkPipeline pipelines[2][NUM_META_FS_KEYS];
381
382 VkRenderPass depth_only_rp;
383 VkPipeline depth_only_pipeline[2];
384
385 VkRenderPass stencil_only_rp;
386 VkPipeline stencil_only_pipeline[2];
387 } blit2d;
388
389 struct {
390 VkPipelineLayout img_p_layout;
391 VkDescriptorSetLayout img_ds_layout;
392 VkPipeline pipeline;
393 } itob;
394 struct {
395 VkRenderPass render_pass;
396 VkPipelineLayout img_p_layout;
397 VkDescriptorSetLayout img_ds_layout;
398 VkPipeline pipeline;
399 } btoi;
400
401 struct {
402 VkPipeline pipeline;
403 VkRenderPass pass;
404 } resolve;
405
406 struct {
407 VkDescriptorSetLayout ds_layout;
408 VkPipelineLayout p_layout;
409 struct {
410 VkPipeline pipeline;
411 VkPipeline i_pipeline;
412 } rc[MAX_SAMPLES_LOG2];
413 } resolve_compute;
414
415 struct {
416 VkPipeline decompress_pipeline;
417 VkPipeline resummarize_pipeline;
418 VkRenderPass pass;
419 } depth_decomp;
420
421 struct {
422 VkPipeline cmask_eliminate_pipeline;
423 VkPipeline fmask_decompress_pipeline;
424 VkRenderPass pass;
425 } fast_clear_flush;
426
427 struct {
428 VkPipelineLayout fill_p_layout;
429 VkPipelineLayout copy_p_layout;
430 VkDescriptorSetLayout fill_ds_layout;
431 VkDescriptorSetLayout copy_ds_layout;
432 VkPipeline fill_pipeline;
433 VkPipeline copy_pipeline;
434 } buffer;
435 };
436
437 /* queue types */
438 #define RADV_QUEUE_GENERAL 0
439 #define RADV_QUEUE_COMPUTE 1
440 #define RADV_QUEUE_TRANSFER 2
441
442 #define RADV_MAX_QUEUE_FAMILIES 3
443
444 struct radv_queue {
445 VK_LOADER_DATA _loader_data;
446 struct radv_device * device;
447 int queue_family_index;
448 int queue_idx;
449 };
450
451 struct radv_device {
452 VK_LOADER_DATA _loader_data;
453
454 VkAllocationCallbacks alloc;
455
456 struct radv_instance * instance;
457 struct radeon_winsys *ws;
458 struct radeon_winsys_ctx *hw_ctx;
459
460 struct radv_meta_state meta_state;
461
462 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
463 int queue_count[RADV_MAX_QUEUE_FAMILIES];
464 struct radeon_winsys_cs *empty_cs;
465
466 bool allow_fast_clears;
467 bool allow_dcc;
468 bool shader_stats_dump;
469
470 /* MSAA sample locations.
471 * The first index is the sample index.
472 * The second index is the coordinate: X, Y. */
473 float sample_locations_1x[1][2];
474 float sample_locations_2x[2][2];
475 float sample_locations_4x[4][2];
476 float sample_locations_8x[8][2];
477 float sample_locations_16x[16][2];
478 };
479
480 struct radv_device_memory {
481 struct radeon_winsys_bo *bo;
482 uint32_t type_index;
483 VkDeviceSize map_size;
484 void * map;
485 };
486
487
488 struct radv_descriptor_range {
489 uint64_t va;
490 uint32_t size;
491 };
492
493 struct radv_descriptor_set {
494 const struct radv_descriptor_set_layout *layout;
495 struct list_head descriptor_pool;
496 uint32_t size;
497
498 struct radv_buffer_view *buffer_views;
499 struct radeon_winsys_bo *bo;
500 uint64_t va;
501 uint32_t *mapped_ptr;
502 struct radv_descriptor_range *dynamic_descriptors;
503 struct radeon_winsys_bo *descriptors[0];
504 };
505
506 struct radv_descriptor_pool_free_node {
507 int next;
508 uint32_t offset;
509 uint32_t size;
510 };
511
512 struct radv_descriptor_pool {
513 struct list_head descriptor_sets;
514
515 struct radeon_winsys_bo *bo;
516 uint8_t *mapped_ptr;
517 uint64_t current_offset;
518 uint64_t size;
519
520 int free_list;
521 int full_list;
522 uint32_t max_sets;
523 struct radv_descriptor_pool_free_node free_nodes[];
524 };
525
526 struct radv_buffer {
527 struct radv_device * device;
528 VkDeviceSize size;
529
530 VkBufferUsageFlags usage;
531
532 /* Set when bound */
533 struct radeon_winsys_bo * bo;
534 VkDeviceSize offset;
535 };
536
537
538 enum radv_cmd_dirty_bits {
539 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
540 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
541 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
542 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
543 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
544 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
545 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
546 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
547 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
548 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
549 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
550 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
551 RADV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
552 };
553 typedef uint32_t radv_cmd_dirty_mask_t;
554
555 enum radv_cmd_flush_bits {
556 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
557 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
558 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
559 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
560 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
561 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
562 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
563 /* Framebuffer caches */
564 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 4,
565 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 5,
566 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 6,
567 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 7,
568 /* Engine synchronization. */
569 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 8,
570 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 9,
571 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 10,
572 RADV_CMD_FLAG_VGT_FLUSH = 1 << 11,
573
574 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
575 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
576 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
577 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
578 };
579
580 struct radv_vertex_binding {
581 struct radv_buffer * buffer;
582 VkDeviceSize offset;
583 };
584
585 struct radv_dynamic_state {
586 struct {
587 uint32_t count;
588 VkViewport viewports[MAX_VIEWPORTS];
589 } viewport;
590
591 struct {
592 uint32_t count;
593 VkRect2D scissors[MAX_SCISSORS];
594 } scissor;
595
596 float line_width;
597
598 struct {
599 float bias;
600 float clamp;
601 float slope;
602 } depth_bias;
603
604 float blend_constants[4];
605
606 struct {
607 float min;
608 float max;
609 } depth_bounds;
610
611 struct {
612 uint32_t front;
613 uint32_t back;
614 } stencil_compare_mask;
615
616 struct {
617 uint32_t front;
618 uint32_t back;
619 } stencil_write_mask;
620
621 struct {
622 uint32_t front;
623 uint32_t back;
624 } stencil_reference;
625 };
626
627 extern const struct radv_dynamic_state default_dynamic_state;
628
629 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
630 const struct radv_dynamic_state *src,
631 uint32_t copy_mask);
632 /**
633 * Attachment state when recording a renderpass instance.
634 *
635 * The clear value is valid only if there exists a pending clear.
636 */
637 struct radv_attachment_state {
638 VkImageAspectFlags pending_clear_aspects;
639 VkClearValue clear_value;
640 VkImageLayout current_layout;
641 };
642
643 struct radv_cmd_state {
644 uint32_t vb_dirty;
645 bool vertex_descriptors_dirty;
646 radv_cmd_dirty_mask_t dirty;
647
648 struct radv_pipeline * pipeline;
649 struct radv_pipeline * emitted_pipeline;
650 struct radv_pipeline * compute_pipeline;
651 struct radv_pipeline * emitted_compute_pipeline;
652 struct radv_framebuffer * framebuffer;
653 struct radv_render_pass * pass;
654 const struct radv_subpass * subpass;
655 struct radv_dynamic_state dynamic;
656 struct radv_vertex_binding vertex_bindings[MAX_VBS];
657 struct radv_descriptor_set * descriptors[MAX_SETS];
658 struct radv_attachment_state * attachments;
659 VkRect2D render_area;
660 struct radv_buffer * index_buffer;
661 uint32_t index_type;
662 uint32_t index_offset;
663 uint32_t last_primitive_reset_index;
664 enum radv_cmd_flush_bits flush_bits;
665 unsigned active_occlusion_queries;
666 float offset_scale;
667 uint32_t descriptors_dirty;
668 };
669 struct radv_cmd_pool {
670 VkAllocationCallbacks alloc;
671 struct list_head cmd_buffers;
672 };
673
674 struct radv_cmd_buffer_upload {
675 uint8_t *map;
676 unsigned offset;
677 uint64_t size;
678 struct radeon_winsys_bo *upload_bo;
679 struct list_head list;
680 };
681
682 struct radv_cmd_buffer {
683 VK_LOADER_DATA _loader_data;
684
685 struct radv_device * device;
686
687 struct radv_cmd_pool * pool;
688 struct list_head pool_link;
689
690 VkCommandBufferUsageFlags usage_flags;
691 VkCommandBufferLevel level;
692 struct radeon_winsys_cs *cs;
693 struct radv_cmd_state state;
694
695 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
696 uint32_t dynamic_buffers[16 * MAX_DYNAMIC_BUFFERS];
697 VkShaderStageFlags push_constant_stages;
698
699 struct radv_cmd_buffer_upload upload;
700
701 bool record_fail;
702 };
703
704 struct radv_image;
705
706 void si_init_config(struct radv_physical_device *physical_device,
707 struct radv_cmd_buffer *cmd_buffer);
708 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
709 int count, const VkViewport *viewports);
710 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
711 int count, const VkRect2D *scissors);
712 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer);
713 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
714 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
715 uint64_t src_va, uint64_t dest_va,
716 uint64_t size);
717 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
718 uint64_t size, unsigned value);
719 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
720 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
721 struct radv_descriptor_set *set,
722 unsigned idx);
723 bool
724 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
725 unsigned size,
726 unsigned alignment,
727 unsigned *out_offset,
728 void **ptr);
729 void
730 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
731 const struct radv_subpass *subpass,
732 bool transitions);
733 bool
734 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
735 unsigned size, unsigned alignmnet,
736 const void *data, unsigned *out_offset);
737 void
738 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
739 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
740 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
741 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
742 unsigned radv_cayman_get_maxdist(int log_samples);
743 void radv_device_init_msaa(struct radv_device *device);
744 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
745 struct radv_image *image,
746 VkClearDepthStencilValue ds_clear_value,
747 VkImageAspectFlags aspects);
748 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
749 struct radv_image *image,
750 int idx,
751 uint32_t color_values[2]);
752 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
753 struct radeon_winsys_bo *bo,
754 uint64_t offset, uint64_t size, uint32_t value);
755
756 /*
757 * Takes x,y,z as exact numbers of invocations, instead of blocks.
758 *
759 * Limitations: Can't call normal dispatch functions without binding or rebinding
760 * the compute pipeline.
761 */
762 void radv_unaligned_dispatch(
763 struct radv_cmd_buffer *cmd_buffer,
764 uint32_t x,
765 uint32_t y,
766 uint32_t z);
767
768 struct radv_event {
769 struct radeon_winsys_bo *bo;
770 uint64_t *map;
771 };
772
773 struct nir_shader;
774
775 struct radv_shader_module {
776 struct nir_shader * nir;
777 unsigned char sha1[20];
778 uint32_t size;
779 char data[0];
780 };
781
782 union ac_shader_variant_key;
783
784 void
785 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
786 const char *entrypoint,
787 const VkSpecializationInfo *spec_info,
788 const struct radv_pipeline_layout *layout,
789 const union ac_shader_variant_key *key);
790
791 static inline gl_shader_stage
792 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
793 {
794 assert(__builtin_popcount(vk_stage) == 1);
795 return ffs(vk_stage) - 1;
796 }
797
798 static inline VkShaderStageFlagBits
799 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
800 {
801 return (1 << mesa_stage);
802 }
803
804 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
805
806 #define radv_foreach_stage(stage, stage_bits) \
807 for (gl_shader_stage stage, \
808 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
809 stage = __builtin_ffs(__tmp) - 1, __tmp; \
810 __tmp &= ~(1 << (stage)))
811
812 struct radv_shader_variant {
813 uint32_t ref_count;
814
815 struct radeon_winsys_bo *bo;
816 struct ac_shader_config config;
817 struct ac_shader_variant_info info;
818 unsigned rsrc1;
819 unsigned rsrc2;
820 uint32_t code_size;
821 };
822
823 struct radv_depth_stencil_state {
824 uint32_t db_depth_control;
825 uint32_t db_stencil_control;
826 uint32_t db_render_control;
827 uint32_t db_render_override2;
828 };
829
830 struct radv_blend_state {
831 uint32_t cb_color_control;
832 uint32_t cb_target_mask;
833 uint32_t sx_mrt0_blend_opt[8];
834 uint32_t cb_blend_control[8];
835
836 uint32_t spi_shader_col_format;
837 uint32_t cb_shader_mask;
838 uint32_t db_alpha_to_mask;
839 };
840
841 unsigned radv_format_meta_fs_key(VkFormat format);
842
843 struct radv_raster_state {
844 uint32_t pa_cl_clip_cntl;
845 uint32_t pa_cl_vs_out_cntl;
846 uint32_t spi_interp_control;
847 uint32_t pa_su_point_size;
848 uint32_t pa_su_point_minmax;
849 uint32_t pa_su_line_cntl;
850 uint32_t pa_su_vtx_cntl;
851 uint32_t pa_su_sc_mode_cntl;
852 };
853
854 struct radv_multisample_state {
855 uint32_t db_eqaa;
856 uint32_t pa_sc_line_cntl;
857 uint32_t pa_sc_mode_cntl_0;
858 uint32_t pa_sc_mode_cntl_1;
859 uint32_t pa_sc_aa_config;
860 uint32_t pa_sc_aa_mask[2];
861 unsigned num_samples;
862 };
863
864 struct radv_pipeline {
865 struct radv_device * device;
866 uint32_t dynamic_state_mask;
867 struct radv_dynamic_state dynamic_state;
868
869 struct radv_pipeline_layout * layout;
870
871 bool needs_data_cache;
872
873 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
874 VkShaderStageFlags active_stages;
875
876 uint32_t va_rsrc_word3[MAX_VERTEX_ATTRIBS];
877 uint32_t va_format_size[MAX_VERTEX_ATTRIBS];
878 uint32_t va_binding[MAX_VERTEX_ATTRIBS];
879 uint32_t va_offset[MAX_VERTEX_ATTRIBS];
880 uint32_t num_vertex_attribs;
881 uint32_t binding_stride[MAX_VBS];
882
883 union {
884 struct {
885 struct radv_blend_state blend;
886 struct radv_depth_stencil_state ds;
887 struct radv_raster_state raster;
888 struct radv_multisample_state ms;
889 unsigned prim;
890 unsigned gs_out;
891 bool prim_restart_enable;
892 } graphics;
893 };
894 };
895
896 struct radv_graphics_pipeline_create_info {
897 bool use_rectlist;
898 bool db_depth_clear;
899 bool db_stencil_clear;
900 bool db_depth_disable_expclear;
901 bool db_stencil_disable_expclear;
902 bool db_flush_depth_inplace;
903 bool db_flush_stencil_inplace;
904 bool db_resummarize;
905 uint32_t custom_blend_mode;
906 };
907
908 VkResult
909 radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
910 struct radv_pipeline_cache *cache,
911 const VkGraphicsPipelineCreateInfo *pCreateInfo,
912 const struct radv_graphics_pipeline_create_info *extra,
913 const VkAllocationCallbacks *alloc);
914
915 VkResult
916 radv_graphics_pipeline_create(VkDevice device,
917 VkPipelineCache cache,
918 const VkGraphicsPipelineCreateInfo *pCreateInfo,
919 const struct radv_graphics_pipeline_create_info *extra,
920 const VkAllocationCallbacks *alloc,
921 VkPipeline *pPipeline);
922
923 struct vk_format_description;
924 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
925 int first_non_void);
926 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
927 int first_non_void);
928 uint32_t radv_translate_colorformat(VkFormat format);
929 uint32_t radv_translate_color_numformat(VkFormat format,
930 const struct vk_format_description *desc,
931 int first_non_void);
932 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
933 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
934 uint32_t radv_translate_dbformat(VkFormat format);
935 uint32_t radv_translate_tex_dataformat(VkFormat format,
936 const struct vk_format_description *desc,
937 int first_non_void);
938 uint32_t radv_translate_tex_numformat(VkFormat format,
939 const struct vk_format_description *desc,
940 int first_non_void);
941 bool radv_format_pack_clear_color(VkFormat format,
942 uint32_t clear_vals[2],
943 VkClearColorValue *value);
944 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
945
946 struct radv_fmask_info {
947 uint64_t offset;
948 uint64_t size;
949 unsigned alignment;
950 unsigned pitch_in_pixels;
951 unsigned bank_height;
952 unsigned slice_tile_max;
953 unsigned tile_mode_index;
954 };
955
956 struct radv_cmask_info {
957 uint64_t offset;
958 uint64_t size;
959 unsigned alignment;
960 unsigned slice_tile_max;
961 unsigned base_address_reg;
962 };
963
964 struct r600_htile_info {
965 uint64_t offset;
966 uint64_t size;
967 unsigned pitch;
968 unsigned height;
969 unsigned xalign;
970 unsigned yalign;
971 };
972
973 struct radv_image {
974 VkImageType type;
975 /* The original VkFormat provided by the client. This may not match any
976 * of the actual surface formats.
977 */
978 VkFormat vk_format;
979 VkImageAspectFlags aspects;
980 VkExtent3D extent;
981 uint32_t levels;
982 uint32_t array_size;
983 uint32_t samples; /**< VkImageCreateInfo::samples */
984 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
985 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
986
987 VkDeviceSize size;
988 uint32_t alignment;
989
990 /* Set when bound */
991 struct radeon_winsys_bo *bo;
992 VkDeviceSize offset;
993 uint32_t dcc_offset;
994 struct radeon_surf surface;
995
996 struct radv_fmask_info fmask;
997 struct radv_cmask_info cmask;
998 uint32_t clear_value_offset;
999
1000 /* Depth buffer compression and fast clear. */
1001 struct r600_htile_info htile;
1002 };
1003
1004 bool radv_layout_has_htile(const struct radv_image *image,
1005 VkImageLayout layout);
1006 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1007 VkImageLayout layout);
1008 bool radv_layout_can_expclear(const struct radv_image *image,
1009 VkImageLayout layout);
1010 bool radv_layout_has_cmask(const struct radv_image *image,
1011 VkImageLayout layout);
1012 static inline uint32_t
1013 radv_get_layerCount(const struct radv_image *image,
1014 const VkImageSubresourceRange *range)
1015 {
1016 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1017 image->array_size - range->baseArrayLayer : range->layerCount;
1018 }
1019
1020 static inline uint32_t
1021 radv_get_levelCount(const struct radv_image *image,
1022 const VkImageSubresourceRange *range)
1023 {
1024 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1025 image->levels - range->baseMipLevel : range->levelCount;
1026 }
1027
1028 struct radeon_bo_metadata;
1029 void
1030 radv_init_metadata(struct radv_device *device,
1031 struct radv_image *image,
1032 struct radeon_bo_metadata *metadata);
1033
1034 struct radv_image_view {
1035 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1036 struct radeon_winsys_bo *bo;
1037
1038 VkImageViewType type;
1039 VkImageAspectFlags aspect_mask;
1040 VkFormat vk_format;
1041 uint32_t base_layer;
1042 uint32_t layer_count;
1043 uint32_t base_mip;
1044 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1045
1046 uint32_t descriptor[8];
1047 uint32_t fmask_descriptor[8];
1048 };
1049
1050 struct radv_image_create_info {
1051 const VkImageCreateInfo *vk_info;
1052 uint32_t stride;
1053 bool scanout;
1054 };
1055
1056 VkResult radv_image_create(VkDevice _device,
1057 const struct radv_image_create_info *info,
1058 const VkAllocationCallbacks* alloc,
1059 VkImage *pImage);
1060
1061 void radv_image_view_init(struct radv_image_view *view,
1062 struct radv_device *device,
1063 const VkImageViewCreateInfo* pCreateInfo,
1064 struct radv_cmd_buffer *cmd_buffer,
1065 VkImageUsageFlags usage_mask);
1066 void radv_image_set_optimal_micro_tile_mode(struct radv_device *device,
1067 struct radv_image *image, uint32_t micro_tile_mode);
1068 struct radv_buffer_view {
1069 struct radeon_winsys_bo *bo;
1070 VkFormat vk_format;
1071 uint64_t range; /**< VkBufferViewCreateInfo::range */
1072 uint32_t state[4];
1073 };
1074 void radv_buffer_view_init(struct radv_buffer_view *view,
1075 struct radv_device *device,
1076 const VkBufferViewCreateInfo* pCreateInfo,
1077 struct radv_cmd_buffer *cmd_buffer);
1078
1079 static inline struct VkExtent3D
1080 radv_sanitize_image_extent(const VkImageType imageType,
1081 const struct VkExtent3D imageExtent)
1082 {
1083 switch (imageType) {
1084 case VK_IMAGE_TYPE_1D:
1085 return (VkExtent3D) { imageExtent.width, 1, 1 };
1086 case VK_IMAGE_TYPE_2D:
1087 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1088 case VK_IMAGE_TYPE_3D:
1089 return imageExtent;
1090 default:
1091 unreachable("invalid image type");
1092 }
1093 }
1094
1095 static inline struct VkOffset3D
1096 radv_sanitize_image_offset(const VkImageType imageType,
1097 const struct VkOffset3D imageOffset)
1098 {
1099 switch (imageType) {
1100 case VK_IMAGE_TYPE_1D:
1101 return (VkOffset3D) { imageOffset.x, 0, 0 };
1102 case VK_IMAGE_TYPE_2D:
1103 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1104 case VK_IMAGE_TYPE_3D:
1105 return imageOffset;
1106 default:
1107 unreachable("invalid image type");
1108 }
1109 }
1110
1111 struct radv_sampler {
1112 uint32_t state[4];
1113 };
1114
1115 struct radv_color_buffer_info {
1116 uint32_t cb_color_base;
1117 uint32_t cb_color_pitch;
1118 uint32_t cb_color_slice;
1119 uint32_t cb_color_view;
1120 uint32_t cb_color_info;
1121 uint32_t cb_color_attrib;
1122 uint32_t cb_dcc_control;
1123 uint32_t cb_color_cmask;
1124 uint32_t cb_color_cmask_slice;
1125 uint32_t cb_color_fmask;
1126 uint32_t cb_color_fmask_slice;
1127 uint32_t cb_clear_value0;
1128 uint32_t cb_clear_value1;
1129 uint32_t cb_dcc_base;
1130 uint32_t micro_tile_mode;
1131 };
1132
1133 struct radv_ds_buffer_info {
1134 uint32_t db_depth_info;
1135 uint32_t db_z_info;
1136 uint32_t db_stencil_info;
1137 uint32_t db_z_read_base;
1138 uint32_t db_stencil_read_base;
1139 uint32_t db_z_write_base;
1140 uint32_t db_stencil_write_base;
1141 uint32_t db_depth_view;
1142 uint32_t db_depth_size;
1143 uint32_t db_depth_slice;
1144 uint32_t db_htile_surface;
1145 uint32_t db_htile_data_base;
1146 uint32_t pa_su_poly_offset_db_fmt_cntl;
1147 float offset_scale;
1148 };
1149
1150 struct radv_attachment_info {
1151 union {
1152 struct radv_color_buffer_info cb;
1153 struct radv_ds_buffer_info ds;
1154 };
1155 struct radv_image_view *attachment;
1156 };
1157
1158 struct radv_framebuffer {
1159 uint32_t width;
1160 uint32_t height;
1161 uint32_t layers;
1162
1163 uint32_t attachment_count;
1164 struct radv_attachment_info attachments[0];
1165 };
1166
1167 struct radv_subpass_barrier {
1168 VkPipelineStageFlags src_stage_mask;
1169 VkAccessFlags src_access_mask;
1170 VkAccessFlags dst_access_mask;
1171 };
1172
1173 struct radv_subpass {
1174 uint32_t input_count;
1175 VkAttachmentReference * input_attachments;
1176 uint32_t color_count;
1177 VkAttachmentReference * color_attachments;
1178 VkAttachmentReference * resolve_attachments;
1179 VkAttachmentReference depth_stencil_attachment;
1180
1181 /** Subpass has at least one resolve attachment */
1182 bool has_resolve;
1183
1184 struct radv_subpass_barrier start_barrier;
1185 };
1186
1187 struct radv_render_pass_attachment {
1188 VkFormat format;
1189 uint32_t samples;
1190 VkAttachmentLoadOp load_op;
1191 VkAttachmentLoadOp stencil_load_op;
1192 VkImageLayout initial_layout;
1193 VkImageLayout final_layout;
1194 };
1195
1196 struct radv_render_pass {
1197 uint32_t attachment_count;
1198 uint32_t subpass_count;
1199 VkAttachmentReference * subpass_attachments;
1200 struct radv_render_pass_attachment * attachments;
1201 struct radv_subpass_barrier end_barrier;
1202 struct radv_subpass subpasses[0];
1203 };
1204
1205 VkResult radv_device_init_meta(struct radv_device *device);
1206 void radv_device_finish_meta(struct radv_device *device);
1207
1208 struct radv_query_pool {
1209 struct radeon_winsys_bo *bo;
1210 uint32_t stride;
1211 uint32_t availability_offset;
1212 char *ptr;
1213 VkQueryType type;
1214 };
1215
1216 VkResult
1217 radv_temp_descriptor_set_create(struct radv_device *device,
1218 struct radv_cmd_buffer *cmd_buffer,
1219 VkDescriptorSetLayout _layout,
1220 VkDescriptorSet *_set);
1221
1222 void
1223 radv_temp_descriptor_set_destroy(struct radv_device *device,
1224 VkDescriptorSet _set);
1225 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1226 struct radv_image *image, uint32_t value);
1227 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1228 struct radv_image *image, uint32_t value);
1229
1230 struct radv_fence {
1231 struct radeon_winsys_fence *fence;
1232 bool submitted;
1233 bool signalled;
1234 };
1235
1236 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1237 \
1238 static inline struct __radv_type * \
1239 __radv_type ## _from_handle(__VkType _handle) \
1240 { \
1241 return (struct __radv_type *) _handle; \
1242 } \
1243 \
1244 static inline __VkType \
1245 __radv_type ## _to_handle(struct __radv_type *_obj) \
1246 { \
1247 return (__VkType) _obj; \
1248 }
1249
1250 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1251 \
1252 static inline struct __radv_type * \
1253 __radv_type ## _from_handle(__VkType _handle) \
1254 { \
1255 return (struct __radv_type *)(uintptr_t) _handle; \
1256 } \
1257 \
1258 static inline __VkType \
1259 __radv_type ## _to_handle(struct __radv_type *_obj) \
1260 { \
1261 return (__VkType)(uintptr_t) _obj; \
1262 }
1263
1264 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1265 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1266
1267 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1268 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1269 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1270 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1271 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1272
1273 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1274 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1275 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1276 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1277 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1278 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1279 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1280 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1281 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1282 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1283 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1284 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1285 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1286 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1287 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1288 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1289 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1290 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1291 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1292
1293 #define RADV_DEFINE_STRUCT_CASTS(__radv_type, __VkType) \
1294 \
1295 static inline const __VkType * \
1296 __radv_type ## _to_ ## __VkType(const struct __radv_type *__radv_obj) \
1297 { \
1298 return (const __VkType *) __radv_obj; \
1299 }
1300
1301 #endif /* RADV_PRIVATE_H */