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radv: only emit cache flushes when the pool size is large enough
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52 #include "vk_debug_report.h"
53
54 #include "radv_radeon_winsys.h"
55 #include "ac_binary.h"
56 #include "ac_nir_to_llvm.h"
57 #include "ac_gpu_info.h"
58 #include "ac_surface.h"
59 #include "radv_descriptor_set.h"
60 #include "radv_extensions.h"
61
62 #include <llvm-c/TargetMachine.h>
63
64 /* Pre-declarations needed for WSI entrypoints */
65 struct wl_surface;
66 struct wl_display;
67 typedef struct xcb_connection_t xcb_connection_t;
68 typedef uint32_t xcb_visualid_t;
69 typedef uint32_t xcb_window_t;
70
71 #include <vulkan/vulkan.h>
72 #include <vulkan/vulkan_intel.h>
73 #include <vulkan/vk_icd.h>
74 #include <vulkan/vk_android_native_buffer.h>
75
76 #include "radv_entrypoints.h"
77
78 #include "wsi_common.h"
79
80 #define ATI_VENDOR_ID 0x1002
81
82 #define MAX_VBS 32
83 #define MAX_VERTEX_ATTRIBS 32
84 #define MAX_RTS 8
85 #define MAX_VIEWPORTS 16
86 #define MAX_SCISSORS 16
87 #define MAX_DISCARD_RECTANGLES 4
88 #define MAX_PUSH_CONSTANTS_SIZE 128
89 #define MAX_PUSH_DESCRIPTORS 32
90 #define MAX_DYNAMIC_BUFFERS 16
91 #define MAX_SAMPLES_LOG2 4
92 #define NUM_META_FS_KEYS 13
93 #define RADV_MAX_DRM_DEVICES 8
94 #define MAX_VIEWS 8
95
96 #define NUM_DEPTH_CLEAR_PIPELINES 3
97
98 /*
99 * This is the point we switch from using CP to compute shader
100 * for certain buffer operations.
101 */
102 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
103
104 enum radv_mem_heap {
105 RADV_MEM_HEAP_VRAM,
106 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
107 RADV_MEM_HEAP_GTT,
108 RADV_MEM_HEAP_COUNT
109 };
110
111 enum radv_mem_type {
112 RADV_MEM_TYPE_VRAM,
113 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
114 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
115 RADV_MEM_TYPE_GTT_CACHED,
116 RADV_MEM_TYPE_COUNT
117 };
118
119 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
120
121 static inline uint32_t
122 align_u32(uint32_t v, uint32_t a)
123 {
124 assert(a != 0 && a == (a & -a));
125 return (v + a - 1) & ~(a - 1);
126 }
127
128 static inline uint32_t
129 align_u32_npot(uint32_t v, uint32_t a)
130 {
131 return (v + a - 1) / a * a;
132 }
133
134 static inline uint64_t
135 align_u64(uint64_t v, uint64_t a)
136 {
137 assert(a != 0 && a == (a & -a));
138 return (v + a - 1) & ~(a - 1);
139 }
140
141 static inline int32_t
142 align_i32(int32_t v, int32_t a)
143 {
144 assert(a != 0 && a == (a & -a));
145 return (v + a - 1) & ~(a - 1);
146 }
147
148 /** Alignment must be a power of 2. */
149 static inline bool
150 radv_is_aligned(uintmax_t n, uintmax_t a)
151 {
152 assert(a == (a & -a));
153 return (n & (a - 1)) == 0;
154 }
155
156 static inline uint32_t
157 round_up_u32(uint32_t v, uint32_t a)
158 {
159 return (v + a - 1) / a;
160 }
161
162 static inline uint64_t
163 round_up_u64(uint64_t v, uint64_t a)
164 {
165 return (v + a - 1) / a;
166 }
167
168 static inline uint32_t
169 radv_minify(uint32_t n, uint32_t levels)
170 {
171 if (unlikely(n == 0))
172 return 0;
173 else
174 return MAX2(n >> levels, 1);
175 }
176 static inline float
177 radv_clamp_f(float f, float min, float max)
178 {
179 assert(min < max);
180
181 if (f > max)
182 return max;
183 else if (f < min)
184 return min;
185 else
186 return f;
187 }
188
189 static inline bool
190 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
191 {
192 if (*inout_mask & clear_mask) {
193 *inout_mask &= ~clear_mask;
194 return true;
195 } else {
196 return false;
197 }
198 }
199
200 #define for_each_bit(b, dword) \
201 for (uint32_t __dword = (dword); \
202 (b) = __builtin_ffs(__dword) - 1, __dword; \
203 __dword &= ~(1 << (b)))
204
205 #define typed_memcpy(dest, src, count) ({ \
206 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
207 memcpy((dest), (src), (count) * sizeof(*(src))); \
208 })
209
210 /* Whenever we generate an error, pass it through this function. Useful for
211 * debugging, where we can break on it. Only call at error site, not when
212 * propagating errors. Might be useful to plug in a stack trace here.
213 */
214
215 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
216
217 #ifdef DEBUG
218 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
219 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
220 #else
221 #define vk_error(error) error
222 #define vk_errorf(error, format, ...) error
223 #endif
224
225 void __radv_finishme(const char *file, int line, const char *format, ...)
226 radv_printflike(3, 4);
227 void radv_loge(const char *format, ...) radv_printflike(1, 2);
228 void radv_loge_v(const char *format, va_list va);
229
230 /**
231 * Print a FINISHME message, including its source location.
232 */
233 #define radv_finishme(format, ...) \
234 do { \
235 static bool reported = false; \
236 if (!reported) { \
237 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
238 reported = true; \
239 } \
240 } while (0)
241
242 /* A non-fatal assert. Useful for debugging. */
243 #ifdef DEBUG
244 #define radv_assert(x) ({ \
245 if (unlikely(!(x))) \
246 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
247 })
248 #else
249 #define radv_assert(x)
250 #endif
251
252 #define stub_return(v) \
253 do { \
254 radv_finishme("stub %s", __func__); \
255 return (v); \
256 } while (0)
257
258 #define stub() \
259 do { \
260 radv_finishme("stub %s", __func__); \
261 return; \
262 } while (0)
263
264 void *radv_lookup_entrypoint_unchecked(const char *name);
265 void *radv_lookup_entrypoint_checked(const char *name,
266 uint32_t core_version,
267 const struct radv_instance_extension_table *instance,
268 const struct radv_device_extension_table *device);
269
270 struct radv_physical_device {
271 VK_LOADER_DATA _loader_data;
272
273 struct radv_instance * instance;
274
275 struct radeon_winsys *ws;
276 struct radeon_info rad_info;
277 char path[20];
278 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
279 uint8_t driver_uuid[VK_UUID_SIZE];
280 uint8_t device_uuid[VK_UUID_SIZE];
281 uint8_t cache_uuid[VK_UUID_SIZE];
282
283 int local_fd;
284 struct wsi_device wsi_device;
285
286 bool has_rbplus; /* if RB+ register exist */
287 bool rbplus_allowed; /* if RB+ is allowed */
288 bool has_clear_state;
289 bool cpdma_prefetch_writes_memory;
290 bool has_scissor_bug;
291
292 /* This is the drivers on-disk cache used as a fallback as opposed to
293 * the pipeline cache defined by apps.
294 */
295 struct disk_cache * disk_cache;
296
297 VkPhysicalDeviceMemoryProperties memory_properties;
298 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
299
300 struct radv_device_extension_table supported_extensions;
301 };
302
303 struct radv_instance {
304 VK_LOADER_DATA _loader_data;
305
306 VkAllocationCallbacks alloc;
307
308 uint32_t apiVersion;
309 int physicalDeviceCount;
310 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
311
312 uint64_t debug_flags;
313 uint64_t perftest_flags;
314
315 struct vk_debug_report_instance debug_report_callbacks;
316
317 struct radv_instance_extension_table enabled_extensions;
318 };
319
320 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
321 void radv_finish_wsi(struct radv_physical_device *physical_device);
322
323 bool radv_instance_extension_supported(const char *name);
324 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
325 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
326 const char *name);
327
328 struct cache_entry;
329
330 struct radv_pipeline_cache {
331 struct radv_device * device;
332 pthread_mutex_t mutex;
333
334 uint32_t total_size;
335 uint32_t table_size;
336 uint32_t kernel_count;
337 struct cache_entry ** hash_table;
338 bool modified;
339
340 VkAllocationCallbacks alloc;
341 };
342
343 struct radv_pipeline_key {
344 uint32_t instance_rate_inputs;
345 unsigned tess_input_vertices;
346 uint32_t col_format;
347 uint32_t is_int8;
348 uint32_t is_int10;
349 uint8_t log2_ps_iter_samples;
350 uint8_t log2_num_samples;
351 uint32_t multisample : 1;
352 uint32_t has_multiview_view_index : 1;
353 };
354
355 void
356 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
357 struct radv_device *device);
358 void
359 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
360 void
361 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
362 const void *data, size_t size);
363
364 struct radv_shader_variant;
365
366 bool
367 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
368 struct radv_pipeline_cache *cache,
369 const unsigned char *sha1,
370 struct radv_shader_variant **variants);
371
372 void
373 radv_pipeline_cache_insert_shaders(struct radv_device *device,
374 struct radv_pipeline_cache *cache,
375 const unsigned char *sha1,
376 struct radv_shader_variant **variants,
377 const void *const *codes,
378 const unsigned *code_sizes);
379
380 enum radv_blit_ds_layout {
381 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
382 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
383 RADV_BLIT_DS_LAYOUT_COUNT,
384 };
385
386 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
387 {
388 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
389 }
390
391 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
392 {
393 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
394 }
395
396 enum radv_meta_dst_layout {
397 RADV_META_DST_LAYOUT_GENERAL,
398 RADV_META_DST_LAYOUT_OPTIMAL,
399 RADV_META_DST_LAYOUT_COUNT,
400 };
401
402 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
403 {
404 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
405 }
406
407 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
408 {
409 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
410 }
411
412 struct radv_meta_state {
413 VkAllocationCallbacks alloc;
414
415 struct radv_pipeline_cache cache;
416
417 /**
418 * Use array element `i` for images with `2^i` samples.
419 */
420 struct {
421 VkRenderPass render_pass[NUM_META_FS_KEYS];
422 VkPipeline color_pipelines[NUM_META_FS_KEYS];
423
424 VkRenderPass depthstencil_rp;
425 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
426 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
427 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
428 } clear[1 + MAX_SAMPLES_LOG2];
429
430 VkPipelineLayout clear_color_p_layout;
431 VkPipelineLayout clear_depth_p_layout;
432 struct {
433 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
434
435 /** Pipeline that blits from a 1D image. */
436 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
437
438 /** Pipeline that blits from a 2D image. */
439 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
440
441 /** Pipeline that blits from a 3D image. */
442 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
443
444 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
445 VkPipeline depth_only_1d_pipeline;
446 VkPipeline depth_only_2d_pipeline;
447 VkPipeline depth_only_3d_pipeline;
448
449 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
450 VkPipeline stencil_only_1d_pipeline;
451 VkPipeline stencil_only_2d_pipeline;
452 VkPipeline stencil_only_3d_pipeline;
453 VkPipelineLayout pipeline_layout;
454 VkDescriptorSetLayout ds_layout;
455 } blit;
456
457 struct {
458 VkRenderPass render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
459
460 VkPipelineLayout p_layouts[3];
461 VkDescriptorSetLayout ds_layouts[3];
462 VkPipeline pipelines[3][NUM_META_FS_KEYS];
463
464 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
465 VkPipeline depth_only_pipeline[3];
466
467 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
468 VkPipeline stencil_only_pipeline[3];
469 } blit2d;
470
471 struct {
472 VkPipelineLayout img_p_layout;
473 VkDescriptorSetLayout img_ds_layout;
474 VkPipeline pipeline;
475 VkPipeline pipeline_3d;
476 } itob;
477 struct {
478 VkPipelineLayout img_p_layout;
479 VkDescriptorSetLayout img_ds_layout;
480 VkPipeline pipeline;
481 VkPipeline pipeline_3d;
482 } btoi;
483 struct {
484 VkPipelineLayout img_p_layout;
485 VkDescriptorSetLayout img_ds_layout;
486 VkPipeline pipeline;
487 VkPipeline pipeline_3d;
488 } itoi;
489 struct {
490 VkPipelineLayout img_p_layout;
491 VkDescriptorSetLayout img_ds_layout;
492 VkPipeline pipeline;
493 VkPipeline pipeline_3d;
494 } cleari;
495
496 struct {
497 VkPipelineLayout p_layout;
498 VkPipeline pipeline[NUM_META_FS_KEYS];
499 VkRenderPass pass[NUM_META_FS_KEYS];
500 } resolve;
501
502 struct {
503 VkDescriptorSetLayout ds_layout;
504 VkPipelineLayout p_layout;
505 struct {
506 VkPipeline pipeline;
507 VkPipeline i_pipeline;
508 VkPipeline srgb_pipeline;
509 } rc[MAX_SAMPLES_LOG2];
510 } resolve_compute;
511
512 struct {
513 VkDescriptorSetLayout ds_layout;
514 VkPipelineLayout p_layout;
515
516 struct {
517 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
518 VkPipeline pipeline[NUM_META_FS_KEYS];
519 } rc[MAX_SAMPLES_LOG2];
520 } resolve_fragment;
521
522 struct {
523 VkPipelineLayout p_layout;
524 VkPipeline decompress_pipeline;
525 VkPipeline resummarize_pipeline;
526 VkRenderPass pass;
527 } depth_decomp[1 + MAX_SAMPLES_LOG2];
528
529 struct {
530 VkPipelineLayout p_layout;
531 VkPipeline cmask_eliminate_pipeline;
532 VkPipeline fmask_decompress_pipeline;
533 VkPipeline dcc_decompress_pipeline;
534 VkRenderPass pass;
535
536 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
537 VkPipelineLayout dcc_decompress_compute_p_layout;
538 VkPipeline dcc_decompress_compute_pipeline;
539 } fast_clear_flush;
540
541 struct {
542 VkPipelineLayout fill_p_layout;
543 VkPipelineLayout copy_p_layout;
544 VkDescriptorSetLayout fill_ds_layout;
545 VkDescriptorSetLayout copy_ds_layout;
546 VkPipeline fill_pipeline;
547 VkPipeline copy_pipeline;
548 } buffer;
549
550 struct {
551 VkDescriptorSetLayout ds_layout;
552 VkPipelineLayout p_layout;
553 VkPipeline occlusion_query_pipeline;
554 VkPipeline pipeline_statistics_query_pipeline;
555 } query;
556 };
557
558 /* queue types */
559 #define RADV_QUEUE_GENERAL 0
560 #define RADV_QUEUE_COMPUTE 1
561 #define RADV_QUEUE_TRANSFER 2
562
563 #define RADV_MAX_QUEUE_FAMILIES 3
564
565 enum ring_type radv_queue_family_to_ring(int f);
566
567 struct radv_queue {
568 VK_LOADER_DATA _loader_data;
569 struct radv_device * device;
570 struct radeon_winsys_ctx *hw_ctx;
571 enum radeon_ctx_priority priority;
572 uint32_t queue_family_index;
573 int queue_idx;
574
575 uint32_t scratch_size;
576 uint32_t compute_scratch_size;
577 uint32_t esgs_ring_size;
578 uint32_t gsvs_ring_size;
579 bool has_tess_rings;
580 bool has_sample_positions;
581
582 struct radeon_winsys_bo *scratch_bo;
583 struct radeon_winsys_bo *descriptor_bo;
584 struct radeon_winsys_bo *compute_scratch_bo;
585 struct radeon_winsys_bo *esgs_ring_bo;
586 struct radeon_winsys_bo *gsvs_ring_bo;
587 struct radeon_winsys_bo *tess_rings_bo;
588 struct radeon_winsys_cs *initial_preamble_cs;
589 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
590 struct radeon_winsys_cs *continue_preamble_cs;
591 };
592
593 struct radv_device {
594 VK_LOADER_DATA _loader_data;
595
596 VkAllocationCallbacks alloc;
597
598 struct radv_instance * instance;
599 struct radeon_winsys *ws;
600
601 struct radv_meta_state meta_state;
602
603 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
604 int queue_count[RADV_MAX_QUEUE_FAMILIES];
605 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
606
607 bool always_use_syncobj;
608 bool llvm_supports_spill;
609 bool has_distributed_tess;
610 bool pbb_allowed;
611 bool dfsm_allowed;
612 uint32_t tess_offchip_block_dw_size;
613 uint32_t scratch_waves;
614 uint32_t dispatch_initiator;
615
616 uint32_t gs_table_depth;
617
618 /* MSAA sample locations.
619 * The first index is the sample index.
620 * The second index is the coordinate: X, Y. */
621 float sample_locations_1x[1][2];
622 float sample_locations_2x[2][2];
623 float sample_locations_4x[4][2];
624 float sample_locations_8x[8][2];
625 float sample_locations_16x[16][2];
626
627 /* CIK and later */
628 uint32_t gfx_init_size_dw;
629 struct radeon_winsys_bo *gfx_init;
630
631 struct radeon_winsys_bo *trace_bo;
632 uint32_t *trace_id_ptr;
633
634 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
635 bool keep_shader_info;
636
637 struct radv_physical_device *physical_device;
638
639 /* Backup in-memory cache to be used if the app doesn't provide one */
640 struct radv_pipeline_cache * mem_cache;
641
642 /*
643 * use different counters so MSAA MRTs get consecutive surface indices,
644 * even if MASK is allocated in between.
645 */
646 uint32_t image_mrt_offset_counter;
647 uint32_t fmask_mrt_offset_counter;
648 struct list_head shader_slabs;
649 mtx_t shader_slab_mutex;
650
651 /* For detecting VM faults reported by dmesg. */
652 uint64_t dmesg_timestamp;
653
654 struct radv_device_extension_table enabled_extensions;
655 };
656
657 struct radv_device_memory {
658 struct radeon_winsys_bo *bo;
659 /* for dedicated allocations */
660 struct radv_image *image;
661 struct radv_buffer *buffer;
662 uint32_t type_index;
663 VkDeviceSize map_size;
664 void * map;
665 void * user_ptr;
666 };
667
668
669 struct radv_descriptor_range {
670 uint64_t va;
671 uint32_t size;
672 };
673
674 struct radv_descriptor_set {
675 const struct radv_descriptor_set_layout *layout;
676 uint32_t size;
677
678 struct radeon_winsys_bo *bo;
679 uint64_t va;
680 uint32_t *mapped_ptr;
681 struct radv_descriptor_range *dynamic_descriptors;
682
683 struct radeon_winsys_bo *descriptors[0];
684 };
685
686 struct radv_push_descriptor_set
687 {
688 struct radv_descriptor_set set;
689 uint32_t capacity;
690 };
691
692 struct radv_descriptor_pool_entry {
693 uint32_t offset;
694 uint32_t size;
695 struct radv_descriptor_set *set;
696 };
697
698 struct radv_descriptor_pool {
699 struct radeon_winsys_bo *bo;
700 uint8_t *mapped_ptr;
701 uint64_t current_offset;
702 uint64_t size;
703
704 uint8_t *host_memory_base;
705 uint8_t *host_memory_ptr;
706 uint8_t *host_memory_end;
707
708 uint32_t entry_count;
709 uint32_t max_entry_count;
710 struct radv_descriptor_pool_entry entries[0];
711 };
712
713 struct radv_descriptor_update_template_entry {
714 VkDescriptorType descriptor_type;
715
716 /* The number of descriptors to update */
717 uint32_t descriptor_count;
718
719 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
720 uint32_t dst_offset;
721
722 /* In dwords. Not valid/used for dynamic descriptors */
723 uint32_t dst_stride;
724
725 uint32_t buffer_offset;
726
727 /* Only valid for combined image samplers and samplers */
728 uint16_t has_sampler;
729
730 /* In bytes */
731 size_t src_offset;
732 size_t src_stride;
733
734 /* For push descriptors */
735 const uint32_t *immutable_samplers;
736 };
737
738 struct radv_descriptor_update_template {
739 uint32_t entry_count;
740 VkPipelineBindPoint bind_point;
741 struct radv_descriptor_update_template_entry entry[0];
742 };
743
744 struct radv_buffer {
745 VkDeviceSize size;
746
747 VkBufferUsageFlags usage;
748 VkBufferCreateFlags flags;
749
750 /* Set when bound */
751 struct radeon_winsys_bo * bo;
752 VkDeviceSize offset;
753
754 bool shareable;
755 };
756
757 enum radv_dynamic_state_bits {
758 RADV_DYNAMIC_VIEWPORT = 1 << 0,
759 RADV_DYNAMIC_SCISSOR = 1 << 1,
760 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
761 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
762 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
763 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
764 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
765 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
766 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
767 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
768 RADV_DYNAMIC_ALL = (1 << 10) - 1,
769 };
770
771 enum radv_cmd_dirty_bits {
772 /* Keep the dynamic state dirty bits in sync with
773 * enum radv_dynamic_state_bits */
774 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
775 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
776 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
777 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
778 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
779 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
780 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
781 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
782 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
783 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
784 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
785 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
786 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
787 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
788 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
789 };
790
791 enum radv_cmd_flush_bits {
792 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
793 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
794 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
795 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
796 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
797 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
798 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
799 /* Same as above, but only writes back and doesn't invalidate */
800 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
801 /* Framebuffer caches */
802 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
803 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
804 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
805 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
806 /* Engine synchronization. */
807 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
808 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
809 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
810 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
811
812 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
813 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
814 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
815 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
816 };
817
818 struct radv_vertex_binding {
819 struct radv_buffer * buffer;
820 VkDeviceSize offset;
821 };
822
823 struct radv_viewport_state {
824 uint32_t count;
825 VkViewport viewports[MAX_VIEWPORTS];
826 };
827
828 struct radv_scissor_state {
829 uint32_t count;
830 VkRect2D scissors[MAX_SCISSORS];
831 };
832
833 struct radv_discard_rectangle_state {
834 uint32_t count;
835 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
836 };
837
838 struct radv_dynamic_state {
839 /**
840 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
841 * Defines the set of saved dynamic state.
842 */
843 uint32_t mask;
844
845 struct radv_viewport_state viewport;
846
847 struct radv_scissor_state scissor;
848
849 float line_width;
850
851 struct {
852 float bias;
853 float clamp;
854 float slope;
855 } depth_bias;
856
857 float blend_constants[4];
858
859 struct {
860 float min;
861 float max;
862 } depth_bounds;
863
864 struct {
865 uint32_t front;
866 uint32_t back;
867 } stencil_compare_mask;
868
869 struct {
870 uint32_t front;
871 uint32_t back;
872 } stencil_write_mask;
873
874 struct {
875 uint32_t front;
876 uint32_t back;
877 } stencil_reference;
878
879 struct radv_discard_rectangle_state discard_rectangle;
880 };
881
882 extern const struct radv_dynamic_state default_dynamic_state;
883
884 const char *
885 radv_get_debug_option_name(int id);
886
887 const char *
888 radv_get_perftest_option_name(int id);
889
890 /**
891 * Attachment state when recording a renderpass instance.
892 *
893 * The clear value is valid only if there exists a pending clear.
894 */
895 struct radv_attachment_state {
896 VkImageAspectFlags pending_clear_aspects;
897 uint32_t cleared_views;
898 VkClearValue clear_value;
899 VkImageLayout current_layout;
900 };
901
902 struct radv_descriptor_state {
903 struct radv_descriptor_set *sets[MAX_SETS];
904 uint32_t dirty;
905 uint32_t valid;
906 struct radv_push_descriptor_set push_set;
907 bool push_dirty;
908 };
909
910 struct radv_cmd_state {
911 /* Vertex descriptors */
912 bool vb_prefetch_dirty;
913 uint64_t vb_va;
914 unsigned vb_size;
915
916 bool predicating;
917 uint32_t dirty;
918
919 struct radv_pipeline * pipeline;
920 struct radv_pipeline * emitted_pipeline;
921 struct radv_pipeline * compute_pipeline;
922 struct radv_pipeline * emitted_compute_pipeline;
923 struct radv_framebuffer * framebuffer;
924 struct radv_render_pass * pass;
925 const struct radv_subpass * subpass;
926 struct radv_dynamic_state dynamic;
927 struct radv_attachment_state * attachments;
928 VkRect2D render_area;
929
930 /* Index buffer */
931 struct radv_buffer *index_buffer;
932 uint64_t index_offset;
933 uint32_t index_type;
934 uint32_t max_index_count;
935 uint64_t index_va;
936 int32_t last_index_type;
937
938 int32_t last_primitive_reset_en;
939 uint32_t last_primitive_reset_index;
940 enum radv_cmd_flush_bits flush_bits;
941 unsigned active_occlusion_queries;
942 float offset_scale;
943 uint32_t trace_id;
944 uint32_t last_ia_multi_vgt_param;
945
946 uint32_t last_num_instances;
947 uint32_t last_first_instance;
948 uint32_t last_vertex_offset;
949 };
950
951 struct radv_cmd_pool {
952 VkAllocationCallbacks alloc;
953 struct list_head cmd_buffers;
954 struct list_head free_cmd_buffers;
955 uint32_t queue_family_index;
956 };
957
958 struct radv_cmd_buffer_upload {
959 uint8_t *map;
960 unsigned offset;
961 uint64_t size;
962 struct radeon_winsys_bo *upload_bo;
963 struct list_head list;
964 };
965
966 enum radv_cmd_buffer_status {
967 RADV_CMD_BUFFER_STATUS_INVALID,
968 RADV_CMD_BUFFER_STATUS_INITIAL,
969 RADV_CMD_BUFFER_STATUS_RECORDING,
970 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
971 RADV_CMD_BUFFER_STATUS_PENDING,
972 };
973
974 struct radv_cmd_buffer {
975 VK_LOADER_DATA _loader_data;
976
977 struct radv_device * device;
978
979 struct radv_cmd_pool * pool;
980 struct list_head pool_link;
981
982 VkCommandBufferUsageFlags usage_flags;
983 VkCommandBufferLevel level;
984 enum radv_cmd_buffer_status status;
985 struct radeon_winsys_cs *cs;
986 struct radv_cmd_state state;
987 struct radv_vertex_binding vertex_bindings[MAX_VBS];
988 uint32_t queue_family_index;
989
990 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
991 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
992 VkShaderStageFlags push_constant_stages;
993 struct radv_descriptor_set meta_push_descriptors;
994
995 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
996
997 struct radv_cmd_buffer_upload upload;
998
999 uint32_t scratch_size_needed;
1000 uint32_t compute_scratch_size_needed;
1001 uint32_t esgs_ring_size_needed;
1002 uint32_t gsvs_ring_size_needed;
1003 bool tess_rings_needed;
1004 bool sample_positions_needed;
1005
1006 VkResult record_result;
1007
1008 int ring_offsets_idx; /* just used for verification */
1009 uint32_t gfx9_fence_offset;
1010 struct radeon_winsys_bo *gfx9_fence_bo;
1011 uint32_t gfx9_fence_idx;
1012
1013 /**
1014 * Whether a query pool has been resetted and we have to flush caches.
1015 */
1016 bool pending_reset_query;
1017 };
1018
1019 struct radv_image;
1020
1021 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1022
1023 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
1024 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
1025
1026 void cik_create_gfx_config(struct radv_device *device);
1027
1028 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
1029 int count, const VkViewport *viewports);
1030 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
1031 int count, const VkRect2D *scissors,
1032 const VkViewport *viewports, bool can_use_guardband);
1033 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1034 bool instanced_draw, bool indirect_draw,
1035 uint32_t draw_vertex_count);
1036 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
1037 bool predicated,
1038 enum chip_class chip_class,
1039 bool is_mec,
1040 unsigned event, unsigned event_flags,
1041 unsigned data_sel,
1042 uint64_t va,
1043 uint32_t old_fence,
1044 uint32_t new_fence);
1045
1046 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
1047 bool predicated,
1048 uint64_t va, uint32_t ref,
1049 uint32_t mask);
1050 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
1051 enum chip_class chip_class,
1052 uint32_t *fence_ptr, uint64_t va,
1053 bool is_mec,
1054 enum radv_cmd_flush_bits flush_bits);
1055 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1056 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1057 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1058 uint64_t src_va, uint64_t dest_va,
1059 uint64_t size);
1060 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1061 unsigned size);
1062 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1063 uint64_t size, unsigned value);
1064 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1065 bool
1066 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1067 unsigned size,
1068 unsigned alignment,
1069 unsigned *out_offset,
1070 void **ptr);
1071 void
1072 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1073 const struct radv_subpass *subpass,
1074 bool transitions);
1075 bool
1076 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1077 unsigned size, unsigned alignmnet,
1078 const void *data, unsigned *out_offset);
1079
1080 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1081 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1082 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1083 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1084 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1085 unsigned radv_cayman_get_maxdist(int log_samples);
1086 void radv_device_init_msaa(struct radv_device *device);
1087 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1088 struct radv_image *image,
1089 VkClearDepthStencilValue ds_clear_value,
1090 VkImageAspectFlags aspects);
1091 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1092 struct radv_image *image,
1093 int idx,
1094 uint32_t color_values[2]);
1095 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1096 struct radv_image *image,
1097 bool value);
1098 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1099 struct radeon_winsys_bo *bo,
1100 uint64_t offset, uint64_t size, uint32_t value);
1101 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1102 bool radv_get_memory_fd(struct radv_device *device,
1103 struct radv_device_memory *memory,
1104 int *pFD);
1105
1106 static inline struct radv_descriptor_state *
1107 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1108 VkPipelineBindPoint bind_point)
1109 {
1110 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1111 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1112 return &cmd_buffer->descriptors[bind_point];
1113 }
1114
1115 /*
1116 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1117 *
1118 * Limitations: Can't call normal dispatch functions without binding or rebinding
1119 * the compute pipeline.
1120 */
1121 void radv_unaligned_dispatch(
1122 struct radv_cmd_buffer *cmd_buffer,
1123 uint32_t x,
1124 uint32_t y,
1125 uint32_t z);
1126
1127 struct radv_event {
1128 struct radeon_winsys_bo *bo;
1129 uint64_t *map;
1130 };
1131
1132 struct radv_shader_module;
1133
1134 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1135 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1136 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1137 void
1138 radv_hash_shaders(unsigned char *hash,
1139 const VkPipelineShaderStageCreateInfo **stages,
1140 const struct radv_pipeline_layout *layout,
1141 const struct radv_pipeline_key *key,
1142 uint32_t flags);
1143
1144 static inline gl_shader_stage
1145 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1146 {
1147 assert(__builtin_popcount(vk_stage) == 1);
1148 return ffs(vk_stage) - 1;
1149 }
1150
1151 static inline VkShaderStageFlagBits
1152 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1153 {
1154 return (1 << mesa_stage);
1155 }
1156
1157 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1158
1159 #define radv_foreach_stage(stage, stage_bits) \
1160 for (gl_shader_stage stage, \
1161 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1162 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1163 __tmp &= ~(1 << (stage)))
1164
1165 unsigned radv_format_meta_fs_key(VkFormat format);
1166
1167 struct radv_multisample_state {
1168 uint32_t db_eqaa;
1169 uint32_t pa_sc_line_cntl;
1170 uint32_t pa_sc_mode_cntl_0;
1171 uint32_t pa_sc_mode_cntl_1;
1172 uint32_t pa_sc_aa_config;
1173 uint32_t pa_sc_aa_mask[2];
1174 unsigned num_samples;
1175 };
1176
1177 struct radv_prim_vertex_count {
1178 uint8_t min;
1179 uint8_t incr;
1180 };
1181
1182 struct radv_vertex_elements_info {
1183 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1184 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1185 uint32_t binding[MAX_VERTEX_ATTRIBS];
1186 uint32_t offset[MAX_VERTEX_ATTRIBS];
1187 uint32_t count;
1188 };
1189
1190 struct radv_ia_multi_vgt_param_helpers {
1191 uint32_t base;
1192 bool partial_es_wave;
1193 uint8_t primgroup_size;
1194 bool wd_switch_on_eop;
1195 bool ia_switch_on_eoi;
1196 bool partial_vs_wave;
1197 };
1198
1199 #define SI_GS_PER_ES 128
1200
1201 struct radv_pipeline {
1202 struct radv_device * device;
1203 struct radv_dynamic_state dynamic_state;
1204
1205 struct radv_pipeline_layout * layout;
1206
1207 bool needs_data_cache;
1208 bool need_indirect_descriptor_sets;
1209 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1210 struct radv_shader_variant *gs_copy_shader;
1211 VkShaderStageFlags active_stages;
1212
1213 struct radeon_winsys_cs cs;
1214
1215 struct radv_vertex_elements_info vertex_elements;
1216
1217 uint32_t binding_stride[MAX_VBS];
1218
1219 uint32_t user_data_0[MESA_SHADER_STAGES];
1220 union {
1221 struct {
1222 struct radv_multisample_state ms;
1223 uint32_t spi_baryc_cntl;
1224 bool prim_restart_enable;
1225 unsigned esgs_ring_size;
1226 unsigned gsvs_ring_size;
1227 uint32_t vtx_base_sgpr;
1228 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1229 uint8_t vtx_emit_num;
1230 struct radv_prim_vertex_count prim_vertex_count;
1231 bool can_use_guardband;
1232 uint32_t needed_dynamic_state;
1233 } graphics;
1234 };
1235
1236 unsigned max_waves;
1237 unsigned scratch_bytes_per_wave;
1238 };
1239
1240 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1241 {
1242 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1243 }
1244
1245 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1246 {
1247 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1248 }
1249
1250 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1251 gl_shader_stage stage,
1252 int idx);
1253
1254 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1255
1256 struct radv_graphics_pipeline_create_info {
1257 bool use_rectlist;
1258 bool db_depth_clear;
1259 bool db_stencil_clear;
1260 bool db_depth_disable_expclear;
1261 bool db_stencil_disable_expclear;
1262 bool db_flush_depth_inplace;
1263 bool db_flush_stencil_inplace;
1264 bool db_resummarize;
1265 uint32_t custom_blend_mode;
1266 };
1267
1268 VkResult
1269 radv_graphics_pipeline_create(VkDevice device,
1270 VkPipelineCache cache,
1271 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1272 const struct radv_graphics_pipeline_create_info *extra,
1273 const VkAllocationCallbacks *alloc,
1274 VkPipeline *pPipeline);
1275
1276 struct vk_format_description;
1277 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1278 int first_non_void);
1279 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1280 int first_non_void);
1281 uint32_t radv_translate_colorformat(VkFormat format);
1282 uint32_t radv_translate_color_numformat(VkFormat format,
1283 const struct vk_format_description *desc,
1284 int first_non_void);
1285 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1286 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1287 uint32_t radv_translate_dbformat(VkFormat format);
1288 uint32_t radv_translate_tex_dataformat(VkFormat format,
1289 const struct vk_format_description *desc,
1290 int first_non_void);
1291 uint32_t radv_translate_tex_numformat(VkFormat format,
1292 const struct vk_format_description *desc,
1293 int first_non_void);
1294 bool radv_format_pack_clear_color(VkFormat format,
1295 uint32_t clear_vals[2],
1296 VkClearColorValue *value);
1297 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1298 bool radv_dcc_formats_compatible(VkFormat format1,
1299 VkFormat format2);
1300
1301 struct radv_fmask_info {
1302 uint64_t offset;
1303 uint64_t size;
1304 unsigned alignment;
1305 unsigned pitch_in_pixels;
1306 unsigned bank_height;
1307 unsigned slice_tile_max;
1308 unsigned tile_mode_index;
1309 unsigned tile_swizzle;
1310 };
1311
1312 struct radv_cmask_info {
1313 uint64_t offset;
1314 uint64_t size;
1315 unsigned alignment;
1316 unsigned slice_tile_max;
1317 };
1318
1319 struct radv_image {
1320 VkImageType type;
1321 /* The original VkFormat provided by the client. This may not match any
1322 * of the actual surface formats.
1323 */
1324 VkFormat vk_format;
1325 VkImageAspectFlags aspects;
1326 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1327 struct ac_surf_info info;
1328 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1329 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1330
1331 VkDeviceSize size;
1332 uint32_t alignment;
1333
1334 unsigned queue_family_mask;
1335 bool exclusive;
1336 bool shareable;
1337
1338 /* Set when bound */
1339 struct radeon_winsys_bo *bo;
1340 VkDeviceSize offset;
1341 uint64_t dcc_offset;
1342 uint64_t htile_offset;
1343 bool tc_compatible_htile;
1344 struct radeon_surf surface;
1345
1346 struct radv_fmask_info fmask;
1347 struct radv_cmask_info cmask;
1348 uint64_t clear_value_offset;
1349 uint64_t dcc_pred_offset;
1350
1351 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1352 VkDeviceMemory owned_memory;
1353 };
1354
1355 /* Whether the image has a htile that is known consistent with the contents of
1356 * the image. */
1357 bool radv_layout_has_htile(const struct radv_image *image,
1358 VkImageLayout layout,
1359 unsigned queue_mask);
1360
1361 /* Whether the image has a htile that is known consistent with the contents of
1362 * the image and is allowed to be in compressed form.
1363 *
1364 * If this is false reads that don't use the htile should be able to return
1365 * correct results.
1366 */
1367 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1368 VkImageLayout layout,
1369 unsigned queue_mask);
1370
1371 bool radv_layout_can_fast_clear(const struct radv_image *image,
1372 VkImageLayout layout,
1373 unsigned queue_mask);
1374
1375 bool radv_layout_dcc_compressed(const struct radv_image *image,
1376 VkImageLayout layout,
1377 unsigned queue_mask);
1378
1379 static inline bool
1380 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1381 {
1382 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1383 }
1384
1385 static inline bool
1386 radv_htile_enabled(const struct radv_image *image, unsigned level)
1387 {
1388 return image->surface.htile_size && level == 0;
1389 }
1390
1391 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1392
1393 static inline uint32_t
1394 radv_get_layerCount(const struct radv_image *image,
1395 const VkImageSubresourceRange *range)
1396 {
1397 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1398 image->info.array_size - range->baseArrayLayer : range->layerCount;
1399 }
1400
1401 static inline uint32_t
1402 radv_get_levelCount(const struct radv_image *image,
1403 const VkImageSubresourceRange *range)
1404 {
1405 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1406 image->info.levels - range->baseMipLevel : range->levelCount;
1407 }
1408
1409 struct radeon_bo_metadata;
1410 void
1411 radv_init_metadata(struct radv_device *device,
1412 struct radv_image *image,
1413 struct radeon_bo_metadata *metadata);
1414
1415 struct radv_image_view {
1416 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1417 struct radeon_winsys_bo *bo;
1418
1419 VkImageViewType type;
1420 VkImageAspectFlags aspect_mask;
1421 VkFormat vk_format;
1422 uint32_t base_layer;
1423 uint32_t layer_count;
1424 uint32_t base_mip;
1425 uint32_t level_count;
1426 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1427
1428 uint32_t descriptor[16];
1429
1430 /* Descriptor for use as a storage image as opposed to a sampled image.
1431 * This has a few differences for cube maps (e.g. type).
1432 */
1433 uint32_t storage_descriptor[16];
1434 };
1435
1436 struct radv_image_create_info {
1437 const VkImageCreateInfo *vk_info;
1438 bool scanout;
1439 bool no_metadata_planes;
1440 };
1441
1442 VkResult radv_image_create(VkDevice _device,
1443 const struct radv_image_create_info *info,
1444 const VkAllocationCallbacks* alloc,
1445 VkImage *pImage);
1446
1447 VkResult
1448 radv_image_from_gralloc(VkDevice device_h,
1449 const VkImageCreateInfo *base_info,
1450 const VkNativeBufferANDROID *gralloc_info,
1451 const VkAllocationCallbacks *alloc,
1452 VkImage *out_image_h);
1453
1454 void radv_image_view_init(struct radv_image_view *view,
1455 struct radv_device *device,
1456 const VkImageViewCreateInfo* pCreateInfo);
1457
1458 struct radv_buffer_view {
1459 struct radeon_winsys_bo *bo;
1460 VkFormat vk_format;
1461 uint64_t range; /**< VkBufferViewCreateInfo::range */
1462 uint32_t state[4];
1463 };
1464 void radv_buffer_view_init(struct radv_buffer_view *view,
1465 struct radv_device *device,
1466 const VkBufferViewCreateInfo* pCreateInfo);
1467
1468 static inline struct VkExtent3D
1469 radv_sanitize_image_extent(const VkImageType imageType,
1470 const struct VkExtent3D imageExtent)
1471 {
1472 switch (imageType) {
1473 case VK_IMAGE_TYPE_1D:
1474 return (VkExtent3D) { imageExtent.width, 1, 1 };
1475 case VK_IMAGE_TYPE_2D:
1476 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1477 case VK_IMAGE_TYPE_3D:
1478 return imageExtent;
1479 default:
1480 unreachable("invalid image type");
1481 }
1482 }
1483
1484 static inline struct VkOffset3D
1485 radv_sanitize_image_offset(const VkImageType imageType,
1486 const struct VkOffset3D imageOffset)
1487 {
1488 switch (imageType) {
1489 case VK_IMAGE_TYPE_1D:
1490 return (VkOffset3D) { imageOffset.x, 0, 0 };
1491 case VK_IMAGE_TYPE_2D:
1492 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1493 case VK_IMAGE_TYPE_3D:
1494 return imageOffset;
1495 default:
1496 unreachable("invalid image type");
1497 }
1498 }
1499
1500 static inline bool
1501 radv_image_extent_compare(const struct radv_image *image,
1502 const VkExtent3D *extent)
1503 {
1504 if (extent->width != image->info.width ||
1505 extent->height != image->info.height ||
1506 extent->depth != image->info.depth)
1507 return false;
1508 return true;
1509 }
1510
1511 struct radv_sampler {
1512 uint32_t state[4];
1513 };
1514
1515 struct radv_color_buffer_info {
1516 uint64_t cb_color_base;
1517 uint64_t cb_color_cmask;
1518 uint64_t cb_color_fmask;
1519 uint64_t cb_dcc_base;
1520 uint32_t cb_color_pitch;
1521 uint32_t cb_color_slice;
1522 uint32_t cb_color_view;
1523 uint32_t cb_color_info;
1524 uint32_t cb_color_attrib;
1525 uint32_t cb_color_attrib2;
1526 uint32_t cb_dcc_control;
1527 uint32_t cb_color_cmask_slice;
1528 uint32_t cb_color_fmask_slice;
1529 };
1530
1531 struct radv_ds_buffer_info {
1532 uint64_t db_z_read_base;
1533 uint64_t db_stencil_read_base;
1534 uint64_t db_z_write_base;
1535 uint64_t db_stencil_write_base;
1536 uint64_t db_htile_data_base;
1537 uint32_t db_depth_info;
1538 uint32_t db_z_info;
1539 uint32_t db_stencil_info;
1540 uint32_t db_depth_view;
1541 uint32_t db_depth_size;
1542 uint32_t db_depth_slice;
1543 uint32_t db_htile_surface;
1544 uint32_t pa_su_poly_offset_db_fmt_cntl;
1545 uint32_t db_z_info2;
1546 uint32_t db_stencil_info2;
1547 float offset_scale;
1548 };
1549
1550 struct radv_attachment_info {
1551 union {
1552 struct radv_color_buffer_info cb;
1553 struct radv_ds_buffer_info ds;
1554 };
1555 struct radv_image_view *attachment;
1556 };
1557
1558 struct radv_framebuffer {
1559 uint32_t width;
1560 uint32_t height;
1561 uint32_t layers;
1562
1563 uint32_t attachment_count;
1564 struct radv_attachment_info attachments[0];
1565 };
1566
1567 struct radv_subpass_barrier {
1568 VkPipelineStageFlags src_stage_mask;
1569 VkAccessFlags src_access_mask;
1570 VkAccessFlags dst_access_mask;
1571 };
1572
1573 struct radv_subpass {
1574 uint32_t input_count;
1575 uint32_t color_count;
1576 VkAttachmentReference * input_attachments;
1577 VkAttachmentReference * color_attachments;
1578 VkAttachmentReference * resolve_attachments;
1579 VkAttachmentReference depth_stencil_attachment;
1580
1581 /** Subpass has at least one resolve attachment */
1582 bool has_resolve;
1583
1584 struct radv_subpass_barrier start_barrier;
1585
1586 uint32_t view_mask;
1587 };
1588
1589 struct radv_render_pass_attachment {
1590 VkFormat format;
1591 uint32_t samples;
1592 VkAttachmentLoadOp load_op;
1593 VkAttachmentLoadOp stencil_load_op;
1594 VkImageLayout initial_layout;
1595 VkImageLayout final_layout;
1596 uint32_t view_mask;
1597 };
1598
1599 struct radv_render_pass {
1600 uint32_t attachment_count;
1601 uint32_t subpass_count;
1602 VkAttachmentReference * subpass_attachments;
1603 struct radv_render_pass_attachment * attachments;
1604 struct radv_subpass_barrier end_barrier;
1605 struct radv_subpass subpasses[0];
1606 };
1607
1608 VkResult radv_device_init_meta(struct radv_device *device);
1609 void radv_device_finish_meta(struct radv_device *device);
1610
1611 struct radv_query_pool {
1612 struct radeon_winsys_bo *bo;
1613 uint32_t stride;
1614 uint32_t availability_offset;
1615 uint64_t size;
1616 char *ptr;
1617 VkQueryType type;
1618 uint32_t pipeline_stats_mask;
1619 };
1620
1621 struct radv_semaphore {
1622 /* use a winsys sem for non-exportable */
1623 struct radeon_winsys_sem *sem;
1624 uint32_t syncobj;
1625 uint32_t temp_syncobj;
1626 };
1627
1628 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1629 int num_wait_sems,
1630 const VkSemaphore *wait_sems,
1631 int num_signal_sems,
1632 const VkSemaphore *signal_sems,
1633 VkFence fence);
1634 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1635
1636 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1637 VkPipelineBindPoint bind_point,
1638 struct radv_descriptor_set *set,
1639 unsigned idx);
1640
1641 void
1642 radv_update_descriptor_sets(struct radv_device *device,
1643 struct radv_cmd_buffer *cmd_buffer,
1644 VkDescriptorSet overrideSet,
1645 uint32_t descriptorWriteCount,
1646 const VkWriteDescriptorSet *pDescriptorWrites,
1647 uint32_t descriptorCopyCount,
1648 const VkCopyDescriptorSet *pDescriptorCopies);
1649
1650 void
1651 radv_update_descriptor_set_with_template(struct radv_device *device,
1652 struct radv_cmd_buffer *cmd_buffer,
1653 struct radv_descriptor_set *set,
1654 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1655 const void *pData);
1656
1657 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1658 VkPipelineBindPoint pipelineBindPoint,
1659 VkPipelineLayout _layout,
1660 uint32_t set,
1661 uint32_t descriptorWriteCount,
1662 const VkWriteDescriptorSet *pDescriptorWrites);
1663
1664 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1665 struct radv_image *image, uint32_t value);
1666 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1667 struct radv_image *image, uint32_t value);
1668
1669 struct radv_fence {
1670 struct radeon_winsys_fence *fence;
1671 bool submitted;
1672 bool signalled;
1673
1674 uint32_t syncobj;
1675 uint32_t temp_syncobj;
1676 };
1677
1678 struct radeon_winsys_sem;
1679
1680 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1681 \
1682 static inline struct __radv_type * \
1683 __radv_type ## _from_handle(__VkType _handle) \
1684 { \
1685 return (struct __radv_type *) _handle; \
1686 } \
1687 \
1688 static inline __VkType \
1689 __radv_type ## _to_handle(struct __radv_type *_obj) \
1690 { \
1691 return (__VkType) _obj; \
1692 }
1693
1694 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1695 \
1696 static inline struct __radv_type * \
1697 __radv_type ## _from_handle(__VkType _handle) \
1698 { \
1699 return (struct __radv_type *)(uintptr_t) _handle; \
1700 } \
1701 \
1702 static inline __VkType \
1703 __radv_type ## _to_handle(struct __radv_type *_obj) \
1704 { \
1705 return (__VkType)(uintptr_t) _obj; \
1706 }
1707
1708 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1709 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1710
1711 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1712 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1713 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1714 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1715 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1716
1717 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1718 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1719 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1720 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1721 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1722 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1723 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1724 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1725 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1726 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1727 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1728 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1729 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1730 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1731 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1732 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1733 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1734 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1735 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1736 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1737 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1738
1739 #endif /* RADV_PRIVATE_H */