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radv: add GFX9 cache flushing support.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/vk_alloc.h"
51 #include "main/macros.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_debug.h"
59 #include "radv_descriptor_set.h"
60
61 #include <llvm-c/TargetMachine.h>
62
63 /* Pre-declarations needed for WSI entrypoints */
64 struct wl_surface;
65 struct wl_display;
66 typedef struct xcb_connection_t xcb_connection_t;
67 typedef uint32_t xcb_visualid_t;
68 typedef uint32_t xcb_window_t;
69
70 #include <vulkan/vulkan.h>
71 #include <vulkan/vulkan_intel.h>
72 #include <vulkan/vk_icd.h>
73
74 #include "radv_entrypoints.h"
75
76 #include "wsi_common.h"
77
78 #define MAX_VBS 32
79 #define MAX_VERTEX_ATTRIBS 32
80 #define MAX_RTS 8
81 #define MAX_VIEWPORTS 16
82 #define MAX_SCISSORS 16
83 #define MAX_PUSH_CONSTANTS_SIZE 128
84 #define MAX_PUSH_DESCRIPTORS 32
85 #define MAX_DYNAMIC_BUFFERS 16
86 #define MAX_SAMPLES_LOG2 4
87 #define NUM_META_FS_KEYS 11
88 #define RADV_MAX_DRM_DEVICES 8
89
90 #define NUM_DEPTH_CLEAR_PIPELINES 3
91
92 enum radv_mem_heap {
93 RADV_MEM_HEAP_VRAM,
94 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
95 RADV_MEM_HEAP_GTT,
96 RADV_MEM_HEAP_COUNT
97 };
98
99 enum radv_mem_type {
100 RADV_MEM_TYPE_VRAM,
101 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
102 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
103 RADV_MEM_TYPE_GTT_CACHED,
104 RADV_MEM_TYPE_COUNT
105 };
106
107 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
108
109 static inline uint32_t
110 align_u32(uint32_t v, uint32_t a)
111 {
112 assert(a != 0 && a == (a & -a));
113 return (v + a - 1) & ~(a - 1);
114 }
115
116 static inline uint32_t
117 align_u32_npot(uint32_t v, uint32_t a)
118 {
119 return (v + a - 1) / a * a;
120 }
121
122 static inline uint64_t
123 align_u64(uint64_t v, uint64_t a)
124 {
125 assert(a != 0 && a == (a & -a));
126 return (v + a - 1) & ~(a - 1);
127 }
128
129 static inline int32_t
130 align_i32(int32_t v, int32_t a)
131 {
132 assert(a != 0 && a == (a & -a));
133 return (v + a - 1) & ~(a - 1);
134 }
135
136 /** Alignment must be a power of 2. */
137 static inline bool
138 radv_is_aligned(uintmax_t n, uintmax_t a)
139 {
140 assert(a == (a & -a));
141 return (n & (a - 1)) == 0;
142 }
143
144 static inline uint32_t
145 round_up_u32(uint32_t v, uint32_t a)
146 {
147 return (v + a - 1) / a;
148 }
149
150 static inline uint64_t
151 round_up_u64(uint64_t v, uint64_t a)
152 {
153 return (v + a - 1) / a;
154 }
155
156 static inline uint32_t
157 radv_minify(uint32_t n, uint32_t levels)
158 {
159 if (unlikely(n == 0))
160 return 0;
161 else
162 return MAX2(n >> levels, 1);
163 }
164 static inline float
165 radv_clamp_f(float f, float min, float max)
166 {
167 assert(min < max);
168
169 if (f > max)
170 return max;
171 else if (f < min)
172 return min;
173 else
174 return f;
175 }
176
177 static inline bool
178 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
179 {
180 if (*inout_mask & clear_mask) {
181 *inout_mask &= ~clear_mask;
182 return true;
183 } else {
184 return false;
185 }
186 }
187
188 #define for_each_bit(b, dword) \
189 for (uint32_t __dword = (dword); \
190 (b) = __builtin_ffs(__dword) - 1, __dword; \
191 __dword &= ~(1 << (b)))
192
193 #define typed_memcpy(dest, src, count) ({ \
194 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
195 memcpy((dest), (src), (count) * sizeof(*(src))); \
196 })
197
198 #define zero(x) (memset(&(x), 0, sizeof(x)))
199
200 /* Whenever we generate an error, pass it through this function. Useful for
201 * debugging, where we can break on it. Only call at error site, not when
202 * propagating errors. Might be useful to plug in a stack trace here.
203 */
204
205 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
206
207 #ifdef DEBUG
208 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
209 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
210 #else
211 #define vk_error(error) error
212 #define vk_errorf(error, format, ...) error
213 #endif
214
215 void __radv_finishme(const char *file, int line, const char *format, ...)
216 radv_printflike(3, 4);
217 void radv_loge(const char *format, ...) radv_printflike(1, 2);
218 void radv_loge_v(const char *format, va_list va);
219
220 /**
221 * Print a FINISHME message, including its source location.
222 */
223 #define radv_finishme(format, ...) \
224 do { \
225 static bool reported = false; \
226 if (!reported) { \
227 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
228 reported = true; \
229 } \
230 } while (0)
231
232 /* A non-fatal assert. Useful for debugging. */
233 #ifdef DEBUG
234 #define radv_assert(x) ({ \
235 if (unlikely(!(x))) \
236 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
237 })
238 #else
239 #define radv_assert(x)
240 #endif
241
242 #define stub_return(v) \
243 do { \
244 radv_finishme("stub %s", __func__); \
245 return (v); \
246 } while (0)
247
248 #define stub() \
249 do { \
250 radv_finishme("stub %s", __func__); \
251 return; \
252 } while (0)
253
254 void *radv_lookup_entrypoint(const char *name);
255
256 struct radv_extensions {
257 VkExtensionProperties *ext_array;
258 uint32_t num_ext;
259 };
260
261 struct radv_physical_device {
262 VK_LOADER_DATA _loader_data;
263
264 struct radv_instance * instance;
265
266 struct radeon_winsys *ws;
267 struct radeon_info rad_info;
268 char path[20];
269 const char * name;
270 uint8_t uuid[VK_UUID_SIZE];
271 uint8_t device_uuid[VK_UUID_SIZE];
272
273 int local_fd;
274 struct wsi_device wsi_device;
275 struct radv_extensions extensions;
276 };
277
278 struct radv_instance {
279 VK_LOADER_DATA _loader_data;
280
281 VkAllocationCallbacks alloc;
282
283 uint32_t apiVersion;
284 int physicalDeviceCount;
285 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
286
287 uint64_t debug_flags;
288 };
289
290 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
291 void radv_finish_wsi(struct radv_physical_device *physical_device);
292
293 struct cache_entry;
294
295 struct radv_pipeline_cache {
296 struct radv_device * device;
297 pthread_mutex_t mutex;
298
299 uint32_t total_size;
300 uint32_t table_size;
301 uint32_t kernel_count;
302 struct cache_entry ** hash_table;
303 bool modified;
304
305 VkAllocationCallbacks alloc;
306 };
307
308 void
309 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
310 struct radv_device *device);
311 void
312 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
313 void
314 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
315 const void *data, size_t size);
316
317 struct radv_shader_variant *
318 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
319 struct radv_pipeline_cache *cache,
320 const unsigned char *sha1);
321
322 struct radv_shader_variant *
323 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
324 const unsigned char *sha1,
325 struct radv_shader_variant *variant,
326 const void *code, unsigned code_size);
327
328 void radv_shader_variant_destroy(struct radv_device *device,
329 struct radv_shader_variant *variant);
330
331 struct radv_meta_state {
332 VkAllocationCallbacks alloc;
333
334 struct radv_pipeline_cache cache;
335
336 /**
337 * Use array element `i` for images with `2^i` samples.
338 */
339 struct {
340 VkRenderPass render_pass[NUM_META_FS_KEYS];
341 struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
342
343 VkRenderPass depthstencil_rp;
344 struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
345 struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
346 struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
347 } clear[1 + MAX_SAMPLES_LOG2];
348
349 VkPipelineLayout clear_color_p_layout;
350 VkPipelineLayout clear_depth_p_layout;
351 struct {
352 VkRenderPass render_pass[NUM_META_FS_KEYS];
353
354 /** Pipeline that blits from a 1D image. */
355 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
356
357 /** Pipeline that blits from a 2D image. */
358 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
359
360 /** Pipeline that blits from a 3D image. */
361 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
362
363 VkRenderPass depth_only_rp;
364 VkPipeline depth_only_1d_pipeline;
365 VkPipeline depth_only_2d_pipeline;
366 VkPipeline depth_only_3d_pipeline;
367
368 VkRenderPass stencil_only_rp;
369 VkPipeline stencil_only_1d_pipeline;
370 VkPipeline stencil_only_2d_pipeline;
371 VkPipeline stencil_only_3d_pipeline;
372 VkPipelineLayout pipeline_layout;
373 VkDescriptorSetLayout ds_layout;
374 } blit;
375
376 struct {
377 VkRenderPass render_passes[NUM_META_FS_KEYS];
378
379 VkPipelineLayout p_layouts[2];
380 VkDescriptorSetLayout ds_layouts[2];
381 VkPipeline pipelines[2][NUM_META_FS_KEYS];
382
383 VkRenderPass depth_only_rp;
384 VkPipeline depth_only_pipeline[2];
385
386 VkRenderPass stencil_only_rp;
387 VkPipeline stencil_only_pipeline[2];
388 } blit2d;
389
390 struct {
391 VkPipelineLayout img_p_layout;
392 VkDescriptorSetLayout img_ds_layout;
393 VkPipeline pipeline;
394 } itob;
395 struct {
396 VkRenderPass render_pass;
397 VkPipelineLayout img_p_layout;
398 VkDescriptorSetLayout img_ds_layout;
399 VkPipeline pipeline;
400 } btoi;
401 struct {
402 VkPipelineLayout img_p_layout;
403 VkDescriptorSetLayout img_ds_layout;
404 VkPipeline pipeline;
405 } itoi;
406 struct {
407 VkPipelineLayout img_p_layout;
408 VkDescriptorSetLayout img_ds_layout;
409 VkPipeline pipeline;
410 } cleari;
411
412 struct {
413 VkPipeline pipeline;
414 VkRenderPass pass;
415 } resolve;
416
417 struct {
418 VkDescriptorSetLayout ds_layout;
419 VkPipelineLayout p_layout;
420 struct {
421 VkPipeline pipeline;
422 VkPipeline i_pipeline;
423 VkPipeline srgb_pipeline;
424 } rc[MAX_SAMPLES_LOG2];
425 } resolve_compute;
426
427 struct {
428 VkDescriptorSetLayout ds_layout;
429 VkPipelineLayout p_layout;
430
431 struct {
432 VkRenderPass srgb_render_pass;
433 VkPipeline srgb_pipeline;
434 VkRenderPass render_pass[NUM_META_FS_KEYS];
435 VkPipeline pipeline[NUM_META_FS_KEYS];
436 } rc[MAX_SAMPLES_LOG2];
437 } resolve_fragment;
438
439 struct {
440 VkPipeline decompress_pipeline;
441 VkPipeline resummarize_pipeline;
442 VkRenderPass pass;
443 } depth_decomp;
444
445 struct {
446 VkPipeline cmask_eliminate_pipeline;
447 VkPipeline fmask_decompress_pipeline;
448 VkRenderPass pass;
449 } fast_clear_flush;
450
451 struct {
452 VkPipelineLayout fill_p_layout;
453 VkPipelineLayout copy_p_layout;
454 VkDescriptorSetLayout fill_ds_layout;
455 VkDescriptorSetLayout copy_ds_layout;
456 VkPipeline fill_pipeline;
457 VkPipeline copy_pipeline;
458 } buffer;
459
460 struct {
461 VkDescriptorSetLayout ds_layout;
462 VkPipelineLayout p_layout;
463 VkPipeline occlusion_query_pipeline;
464 VkPipeline pipeline_statistics_query_pipeline;
465 } query;
466 };
467
468 /* queue types */
469 #define RADV_QUEUE_GENERAL 0
470 #define RADV_QUEUE_COMPUTE 1
471 #define RADV_QUEUE_TRANSFER 2
472
473 #define RADV_MAX_QUEUE_FAMILIES 3
474
475 enum ring_type radv_queue_family_to_ring(int f);
476
477 struct radv_queue {
478 VK_LOADER_DATA _loader_data;
479 struct radv_device * device;
480 struct radeon_winsys_ctx *hw_ctx;
481 int queue_family_index;
482 int queue_idx;
483
484 uint32_t scratch_size;
485 uint32_t compute_scratch_size;
486 uint32_t esgs_ring_size;
487 uint32_t gsvs_ring_size;
488 bool has_tess_rings;
489 bool has_sample_positions;
490
491 struct radeon_winsys_bo *scratch_bo;
492 struct radeon_winsys_bo *descriptor_bo;
493 struct radeon_winsys_bo *compute_scratch_bo;
494 struct radeon_winsys_bo *esgs_ring_bo;
495 struct radeon_winsys_bo *gsvs_ring_bo;
496 struct radeon_winsys_bo *tess_factor_ring_bo;
497 struct radeon_winsys_bo *tess_offchip_ring_bo;
498 struct radeon_winsys_cs *initial_preamble_cs;
499 struct radeon_winsys_cs *continue_preamble_cs;
500 };
501
502 struct radv_device {
503 VK_LOADER_DATA _loader_data;
504
505 VkAllocationCallbacks alloc;
506
507 struct radv_instance * instance;
508 struct radeon_winsys *ws;
509
510 struct radv_meta_state meta_state;
511
512 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
513 int queue_count[RADV_MAX_QUEUE_FAMILIES];
514 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
515 struct radeon_winsys_cs *flush_cs[RADV_MAX_QUEUE_FAMILIES];
516 struct radeon_winsys_cs *flush_shader_cs[RADV_MAX_QUEUE_FAMILIES];
517 uint64_t debug_flags;
518
519 bool llvm_supports_spill;
520 bool has_distributed_tess;
521 uint32_t tess_offchip_block_dw_size;
522 uint32_t scratch_waves;
523
524 uint32_t gs_table_depth;
525
526 /* MSAA sample locations.
527 * The first index is the sample index.
528 * The second index is the coordinate: X, Y. */
529 float sample_locations_1x[1][2];
530 float sample_locations_2x[2][2];
531 float sample_locations_4x[4][2];
532 float sample_locations_8x[8][2];
533 float sample_locations_16x[16][2];
534
535 /* CIK and later */
536 uint32_t gfx_init_size_dw;
537 struct radeon_winsys_bo *gfx_init;
538
539 struct radeon_winsys_bo *trace_bo;
540 uint32_t *trace_id_ptr;
541
542 struct radv_physical_device *physical_device;
543
544 /* Backup in-memory cache to be used if the app doesn't provide one */
545 struct radv_pipeline_cache * mem_cache;
546 };
547
548 struct radv_device_memory {
549 struct radeon_winsys_bo *bo;
550 /* for dedicated allocations */
551 struct radv_image *image;
552 struct radv_buffer *buffer;
553 uint32_t type_index;
554 VkDeviceSize map_size;
555 void * map;
556 };
557
558
559 struct radv_descriptor_range {
560 uint64_t va;
561 uint32_t size;
562 };
563
564 struct radv_descriptor_set {
565 const struct radv_descriptor_set_layout *layout;
566 uint32_t size;
567
568 struct radeon_winsys_bo *bo;
569 uint64_t va;
570 uint32_t *mapped_ptr;
571 struct radv_descriptor_range *dynamic_descriptors;
572
573 struct list_head vram_list;
574
575 struct radeon_winsys_bo *descriptors[0];
576 };
577
578 struct radv_push_descriptor_set
579 {
580 struct radv_descriptor_set set;
581 uint32_t capacity;
582 };
583
584 struct radv_descriptor_pool {
585 struct radeon_winsys_bo *bo;
586 uint8_t *mapped_ptr;
587 uint64_t current_offset;
588 uint64_t size;
589
590 struct list_head vram_list;
591
592 uint8_t *host_memory_base;
593 uint8_t *host_memory_ptr;
594 uint8_t *host_memory_end;
595 };
596
597 struct radv_descriptor_update_template_entry {
598 VkDescriptorType descriptor_type;
599
600 /* The number of descriptors to update */
601 uint32_t descriptor_count;
602
603 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
604 uint32_t dst_offset;
605
606 /* In dwords. Not valid/used for dynamic descriptors */
607 uint32_t dst_stride;
608
609 uint32_t buffer_offset;
610
611 /* Only valid for combined image samplers and samplers */
612 uint16_t has_sampler;
613
614 /* In bytes */
615 size_t src_offset;
616 size_t src_stride;
617
618 /* For push descriptors */
619 const uint32_t *immutable_samplers;
620 };
621
622 struct radv_descriptor_update_template {
623 uint32_t entry_count;
624 struct radv_descriptor_update_template_entry entry[0];
625 };
626
627 struct radv_buffer {
628 struct radv_device * device;
629 VkDeviceSize size;
630
631 VkBufferUsageFlags usage;
632 VkBufferCreateFlags flags;
633
634 /* Set when bound */
635 struct radeon_winsys_bo * bo;
636 VkDeviceSize offset;
637 };
638
639
640 enum radv_cmd_dirty_bits {
641 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
642 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
643 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
644 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
645 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
646 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
647 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
648 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
649 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
650 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
651 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
652 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
653 RADV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
654 };
655 typedef uint32_t radv_cmd_dirty_mask_t;
656
657 enum radv_cmd_flush_bits {
658 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
659 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
660 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
661 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
662 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
663 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
664 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
665 /* Same as above, but only writes back and doesn't invalidate */
666 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
667 /* Framebuffer caches */
668 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
669 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
670 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
671 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
672 /* Engine synchronization. */
673 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
674 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
675 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
676 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
677
678 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
679 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
680 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
681 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
682 };
683
684 struct radv_vertex_binding {
685 struct radv_buffer * buffer;
686 VkDeviceSize offset;
687 };
688
689 struct radv_dynamic_state {
690 struct {
691 uint32_t count;
692 VkViewport viewports[MAX_VIEWPORTS];
693 } viewport;
694
695 struct {
696 uint32_t count;
697 VkRect2D scissors[MAX_SCISSORS];
698 } scissor;
699
700 float line_width;
701
702 struct {
703 float bias;
704 float clamp;
705 float slope;
706 } depth_bias;
707
708 float blend_constants[4];
709
710 struct {
711 float min;
712 float max;
713 } depth_bounds;
714
715 struct {
716 uint32_t front;
717 uint32_t back;
718 } stencil_compare_mask;
719
720 struct {
721 uint32_t front;
722 uint32_t back;
723 } stencil_write_mask;
724
725 struct {
726 uint32_t front;
727 uint32_t back;
728 } stencil_reference;
729 };
730
731 extern const struct radv_dynamic_state default_dynamic_state;
732
733 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
734 const struct radv_dynamic_state *src,
735 uint32_t copy_mask);
736 /**
737 * Attachment state when recording a renderpass instance.
738 *
739 * The clear value is valid only if there exists a pending clear.
740 */
741 struct radv_attachment_state {
742 VkImageAspectFlags pending_clear_aspects;
743 VkClearValue clear_value;
744 VkImageLayout current_layout;
745 };
746
747 struct radv_cmd_state {
748 uint32_t vb_dirty;
749 radv_cmd_dirty_mask_t dirty;
750 bool vertex_descriptors_dirty;
751 bool push_descriptors_dirty;
752
753 struct radv_pipeline * pipeline;
754 struct radv_pipeline * emitted_pipeline;
755 struct radv_pipeline * compute_pipeline;
756 struct radv_pipeline * emitted_compute_pipeline;
757 struct radv_framebuffer * framebuffer;
758 struct radv_render_pass * pass;
759 const struct radv_subpass * subpass;
760 struct radv_dynamic_state dynamic;
761 struct radv_vertex_binding vertex_bindings[MAX_VBS];
762 struct radv_descriptor_set * descriptors[MAX_SETS];
763 struct radv_attachment_state * attachments;
764 VkRect2D render_area;
765 struct radv_buffer * index_buffer;
766 uint32_t index_type;
767 uint32_t index_offset;
768 int32_t last_primitive_reset_en;
769 uint32_t last_primitive_reset_index;
770 enum radv_cmd_flush_bits flush_bits;
771 unsigned active_occlusion_queries;
772 float offset_scale;
773 uint32_t descriptors_dirty;
774 uint32_t trace_id;
775 uint32_t last_ia_multi_vgt_param;
776 };
777
778 struct radv_cmd_pool {
779 VkAllocationCallbacks alloc;
780 struct list_head cmd_buffers;
781 struct list_head free_cmd_buffers;
782 uint32_t queue_family_index;
783 };
784
785 struct radv_cmd_buffer_upload {
786 uint8_t *map;
787 unsigned offset;
788 uint64_t size;
789 struct radeon_winsys_bo *upload_bo;
790 struct list_head list;
791 };
792
793 struct radv_cmd_buffer {
794 VK_LOADER_DATA _loader_data;
795
796 struct radv_device * device;
797
798 struct radv_cmd_pool * pool;
799 struct list_head pool_link;
800
801 VkCommandBufferUsageFlags usage_flags;
802 VkCommandBufferLevel level;
803 struct radeon_winsys_cs *cs;
804 struct radv_cmd_state state;
805 uint32_t queue_family_index;
806
807 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
808 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
809 VkShaderStageFlags push_constant_stages;
810 struct radv_push_descriptor_set push_descriptors;
811 struct radv_descriptor_set meta_push_descriptors;
812
813 struct radv_cmd_buffer_upload upload;
814
815 uint32_t scratch_size_needed;
816 uint32_t compute_scratch_size_needed;
817 uint32_t esgs_ring_size_needed;
818 uint32_t gsvs_ring_size_needed;
819 bool tess_rings_needed;
820 bool sample_positions_needed;
821
822 bool record_fail;
823
824 int ring_offsets_idx; /* just used for verification */
825 uint32_t gfx9_fence_offset;
826 struct radeon_winsys_bo *gfx9_fence_bo;
827 uint32_t gfx9_fence_idx;
828 };
829
830 struct radv_image;
831
832 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
833
834 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
835 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
836
837 void cik_create_gfx_config(struct radv_device *device);
838
839 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
840 int count, const VkViewport *viewports);
841 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
842 int count, const VkRect2D *scissors,
843 const VkViewport *viewports, bool can_use_guardband);
844 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
845 bool instanced_draw, bool indirect_draw,
846 uint32_t draw_vertex_count);
847 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
848 enum chip_class chip_class,
849 bool is_mec,
850 unsigned event, unsigned event_flags,
851 unsigned data_sel,
852 uint64_t va,
853 uint32_t old_fence,
854 uint32_t new_fence);
855
856 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
857 uint64_t va, uint32_t ref,
858 uint32_t mask);
859 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
860 enum chip_class chip_class,
861 uint32_t *fence_ptr, uint64_t va,
862 bool is_mec,
863 enum radv_cmd_flush_bits flush_bits);
864 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
865 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
866 uint64_t src_va, uint64_t dest_va,
867 uint64_t size);
868 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
869 unsigned size);
870 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
871 uint64_t size, unsigned value);
872 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
873 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
874 struct radv_descriptor_set *set,
875 unsigned idx);
876 bool
877 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
878 unsigned size,
879 unsigned alignment,
880 unsigned *out_offset,
881 void **ptr);
882 void
883 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
884 const struct radv_subpass *subpass,
885 bool transitions);
886 bool
887 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
888 unsigned size, unsigned alignmnet,
889 const void *data, unsigned *out_offset);
890 void
891 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
892 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
893 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
894 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
895 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
896 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
897 unsigned radv_cayman_get_maxdist(int log_samples);
898 void radv_device_init_msaa(struct radv_device *device);
899 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
900 struct radv_image *image,
901 VkClearDepthStencilValue ds_clear_value,
902 VkImageAspectFlags aspects);
903 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
904 struct radv_image *image,
905 int idx,
906 uint32_t color_values[2]);
907 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
908 struct radeon_winsys_bo *bo,
909 uint64_t offset, uint64_t size, uint32_t value);
910 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
911 bool radv_get_memory_fd(struct radv_device *device,
912 struct radv_device_memory *memory,
913 int *pFD);
914 /*
915 * Takes x,y,z as exact numbers of invocations, instead of blocks.
916 *
917 * Limitations: Can't call normal dispatch functions without binding or rebinding
918 * the compute pipeline.
919 */
920 void radv_unaligned_dispatch(
921 struct radv_cmd_buffer *cmd_buffer,
922 uint32_t x,
923 uint32_t y,
924 uint32_t z);
925
926 struct radv_event {
927 struct radeon_winsys_bo *bo;
928 uint64_t *map;
929 };
930
931 struct nir_shader;
932
933 struct radv_shader_module {
934 struct nir_shader * nir;
935 unsigned char sha1[20];
936 uint32_t size;
937 char data[0];
938 };
939
940 union ac_shader_variant_key;
941
942 void
943 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
944 const char *entrypoint,
945 const VkSpecializationInfo *spec_info,
946 const struct radv_pipeline_layout *layout,
947 const union ac_shader_variant_key *key,
948 uint32_t is_geom_copy_shader);
949
950 static inline gl_shader_stage
951 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
952 {
953 assert(__builtin_popcount(vk_stage) == 1);
954 return ffs(vk_stage) - 1;
955 }
956
957 static inline VkShaderStageFlagBits
958 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
959 {
960 return (1 << mesa_stage);
961 }
962
963 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
964
965 #define radv_foreach_stage(stage, stage_bits) \
966 for (gl_shader_stage stage, \
967 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
968 stage = __builtin_ffs(__tmp) - 1, __tmp; \
969 __tmp &= ~(1 << (stage)))
970
971 struct radv_shader_variant {
972 uint32_t ref_count;
973
974 struct radeon_winsys_bo *bo;
975 struct ac_shader_config config;
976 struct ac_shader_variant_info info;
977 unsigned rsrc1;
978 unsigned rsrc2;
979 uint32_t code_size;
980 };
981
982 struct radv_depth_stencil_state {
983 uint32_t db_depth_control;
984 uint32_t db_stencil_control;
985 uint32_t db_render_control;
986 uint32_t db_render_override2;
987 };
988
989 struct radv_blend_state {
990 uint32_t cb_color_control;
991 uint32_t cb_target_mask;
992 uint32_t sx_mrt0_blend_opt[8];
993 uint32_t cb_blend_control[8];
994
995 uint32_t spi_shader_col_format;
996 uint32_t cb_shader_mask;
997 uint32_t db_alpha_to_mask;
998 };
999
1000 unsigned radv_format_meta_fs_key(VkFormat format);
1001
1002 struct radv_raster_state {
1003 uint32_t pa_cl_clip_cntl;
1004 uint32_t spi_interp_control;
1005 uint32_t pa_su_point_size;
1006 uint32_t pa_su_point_minmax;
1007 uint32_t pa_su_line_cntl;
1008 uint32_t pa_su_vtx_cntl;
1009 uint32_t pa_su_sc_mode_cntl;
1010 };
1011
1012 struct radv_multisample_state {
1013 uint32_t db_eqaa;
1014 uint32_t pa_sc_line_cntl;
1015 uint32_t pa_sc_mode_cntl_0;
1016 uint32_t pa_sc_mode_cntl_1;
1017 uint32_t pa_sc_aa_config;
1018 uint32_t pa_sc_aa_mask[2];
1019 unsigned num_samples;
1020 };
1021
1022 struct radv_prim_vertex_count {
1023 uint8_t min;
1024 uint8_t incr;
1025 };
1026
1027 struct radv_tessellation_state {
1028 uint32_t ls_hs_config;
1029 uint32_t tcs_in_layout;
1030 uint32_t tcs_out_layout;
1031 uint32_t tcs_out_offsets;
1032 uint32_t offchip_layout;
1033 unsigned num_patches;
1034 unsigned lds_size;
1035 unsigned num_tcs_input_cp;
1036 uint32_t tf_param;
1037 };
1038
1039 struct radv_pipeline {
1040 struct radv_device * device;
1041 uint32_t dynamic_state_mask;
1042 struct radv_dynamic_state dynamic_state;
1043
1044 struct radv_pipeline_layout * layout;
1045
1046 bool needs_data_cache;
1047 bool need_indirect_descriptor_sets;
1048 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1049 struct radv_shader_variant *gs_copy_shader;
1050 VkShaderStageFlags active_stages;
1051
1052 uint32_t va_rsrc_word3[MAX_VERTEX_ATTRIBS];
1053 uint32_t va_format_size[MAX_VERTEX_ATTRIBS];
1054 uint32_t va_binding[MAX_VERTEX_ATTRIBS];
1055 uint32_t va_offset[MAX_VERTEX_ATTRIBS];
1056 uint32_t num_vertex_attribs;
1057 uint32_t binding_stride[MAX_VBS];
1058
1059 union {
1060 struct {
1061 struct radv_blend_state blend;
1062 struct radv_depth_stencil_state ds;
1063 struct radv_raster_state raster;
1064 struct radv_multisample_state ms;
1065 struct radv_tessellation_state tess;
1066 uint32_t db_shader_control;
1067 uint32_t shader_z_format;
1068 unsigned prim;
1069 unsigned gs_out;
1070 uint32_t vgt_gs_mode;
1071 bool prim_restart_enable;
1072 unsigned esgs_ring_size;
1073 unsigned gsvs_ring_size;
1074 uint32_t ps_input_cntl[32];
1075 uint32_t ps_input_cntl_num;
1076 uint32_t pa_cl_vs_out_cntl;
1077 uint32_t vgt_shader_stages_en;
1078 struct radv_prim_vertex_count prim_vertex_count;
1079 bool can_use_guardband;
1080 } graphics;
1081 };
1082
1083 unsigned max_waves;
1084 unsigned scratch_bytes_per_wave;
1085 };
1086
1087 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1088 {
1089 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1090 }
1091
1092 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1093 {
1094 return pipeline->shaders[MESA_SHADER_TESS_EVAL] ? true : false;
1095 }
1096
1097 struct radv_graphics_pipeline_create_info {
1098 bool use_rectlist;
1099 bool db_depth_clear;
1100 bool db_stencil_clear;
1101 bool db_depth_disable_expclear;
1102 bool db_stencil_disable_expclear;
1103 bool db_flush_depth_inplace;
1104 bool db_flush_stencil_inplace;
1105 bool db_resummarize;
1106 uint32_t custom_blend_mode;
1107 };
1108
1109 VkResult
1110 radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
1111 struct radv_pipeline_cache *cache,
1112 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1113 const struct radv_graphics_pipeline_create_info *extra,
1114 const VkAllocationCallbacks *alloc);
1115
1116 VkResult
1117 radv_graphics_pipeline_create(VkDevice device,
1118 VkPipelineCache cache,
1119 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1120 const struct radv_graphics_pipeline_create_info *extra,
1121 const VkAllocationCallbacks *alloc,
1122 VkPipeline *pPipeline);
1123
1124 struct vk_format_description;
1125 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1126 int first_non_void);
1127 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1128 int first_non_void);
1129 uint32_t radv_translate_colorformat(VkFormat format);
1130 uint32_t radv_translate_color_numformat(VkFormat format,
1131 const struct vk_format_description *desc,
1132 int first_non_void);
1133 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1134 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1135 uint32_t radv_translate_dbformat(VkFormat format);
1136 uint32_t radv_translate_tex_dataformat(VkFormat format,
1137 const struct vk_format_description *desc,
1138 int first_non_void);
1139 uint32_t radv_translate_tex_numformat(VkFormat format,
1140 const struct vk_format_description *desc,
1141 int first_non_void);
1142 bool radv_format_pack_clear_color(VkFormat format,
1143 uint32_t clear_vals[2],
1144 VkClearColorValue *value);
1145 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1146
1147 struct radv_fmask_info {
1148 uint64_t offset;
1149 uint64_t size;
1150 unsigned alignment;
1151 unsigned pitch_in_pixels;
1152 unsigned bank_height;
1153 unsigned slice_tile_max;
1154 unsigned tile_mode_index;
1155 };
1156
1157 struct radv_cmask_info {
1158 uint64_t offset;
1159 uint64_t size;
1160 unsigned alignment;
1161 unsigned slice_tile_max;
1162 unsigned base_address_reg;
1163 };
1164
1165 struct r600_htile_info {
1166 uint64_t offset;
1167 uint64_t size;
1168 unsigned pitch;
1169 unsigned height;
1170 unsigned xalign;
1171 unsigned yalign;
1172 };
1173
1174 struct radv_image {
1175 VkImageType type;
1176 /* The original VkFormat provided by the client. This may not match any
1177 * of the actual surface formats.
1178 */
1179 VkFormat vk_format;
1180 VkImageAspectFlags aspects;
1181 struct ac_surf_info info;
1182 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1183 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1184 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1185
1186 VkDeviceSize size;
1187 uint32_t alignment;
1188
1189 bool exclusive;
1190 unsigned queue_family_mask;
1191
1192 /* Set when bound */
1193 struct radeon_winsys_bo *bo;
1194 VkDeviceSize offset;
1195 uint32_t dcc_offset;
1196 uint32_t htile_offset;
1197 struct radeon_surf surface;
1198
1199 struct radv_fmask_info fmask;
1200 struct radv_cmask_info cmask;
1201 uint32_t clear_value_offset;
1202 };
1203
1204 /* Whether the image has a htile that is known consistent with the contents of
1205 * the image. */
1206 bool radv_layout_has_htile(const struct radv_image *image,
1207 VkImageLayout layout,
1208 unsigned queue_mask);
1209
1210 /* Whether the image has a htile that is known consistent with the contents of
1211 * the image and is allowed to be in compressed form.
1212 *
1213 * If this is false reads that don't use the htile should be able to return
1214 * correct results.
1215 */
1216 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1217 VkImageLayout layout,
1218 unsigned queue_mask);
1219
1220 bool radv_layout_can_fast_clear(const struct radv_image *image,
1221 VkImageLayout layout,
1222 unsigned queue_mask);
1223
1224
1225 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1226
1227 static inline uint32_t
1228 radv_get_layerCount(const struct radv_image *image,
1229 const VkImageSubresourceRange *range)
1230 {
1231 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1232 image->info.array_size - range->baseArrayLayer : range->layerCount;
1233 }
1234
1235 static inline uint32_t
1236 radv_get_levelCount(const struct radv_image *image,
1237 const VkImageSubresourceRange *range)
1238 {
1239 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1240 image->info.levels - range->baseMipLevel : range->levelCount;
1241 }
1242
1243 struct radeon_bo_metadata;
1244 void
1245 radv_init_metadata(struct radv_device *device,
1246 struct radv_image *image,
1247 struct radeon_bo_metadata *metadata);
1248
1249 struct radv_image_view {
1250 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1251 struct radeon_winsys_bo *bo;
1252
1253 VkImageViewType type;
1254 VkImageAspectFlags aspect_mask;
1255 VkFormat vk_format;
1256 uint32_t base_layer;
1257 uint32_t layer_count;
1258 uint32_t base_mip;
1259 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1260
1261 uint32_t descriptor[8];
1262 uint32_t fmask_descriptor[8];
1263 };
1264
1265 struct radv_image_create_info {
1266 const VkImageCreateInfo *vk_info;
1267 bool scanout;
1268 };
1269
1270 VkResult radv_image_create(VkDevice _device,
1271 const struct radv_image_create_info *info,
1272 const VkAllocationCallbacks* alloc,
1273 VkImage *pImage);
1274
1275 void radv_image_view_init(struct radv_image_view *view,
1276 struct radv_device *device,
1277 const VkImageViewCreateInfo* pCreateInfo,
1278 struct radv_cmd_buffer *cmd_buffer,
1279 VkImageUsageFlags usage_mask);
1280
1281 struct radv_buffer_view {
1282 struct radeon_winsys_bo *bo;
1283 VkFormat vk_format;
1284 uint64_t range; /**< VkBufferViewCreateInfo::range */
1285 uint32_t state[4];
1286 };
1287 void radv_buffer_view_init(struct radv_buffer_view *view,
1288 struct radv_device *device,
1289 const VkBufferViewCreateInfo* pCreateInfo,
1290 struct radv_cmd_buffer *cmd_buffer);
1291
1292 static inline struct VkExtent3D
1293 radv_sanitize_image_extent(const VkImageType imageType,
1294 const struct VkExtent3D imageExtent)
1295 {
1296 switch (imageType) {
1297 case VK_IMAGE_TYPE_1D:
1298 return (VkExtent3D) { imageExtent.width, 1, 1 };
1299 case VK_IMAGE_TYPE_2D:
1300 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1301 case VK_IMAGE_TYPE_3D:
1302 return imageExtent;
1303 default:
1304 unreachable("invalid image type");
1305 }
1306 }
1307
1308 static inline struct VkOffset3D
1309 radv_sanitize_image_offset(const VkImageType imageType,
1310 const struct VkOffset3D imageOffset)
1311 {
1312 switch (imageType) {
1313 case VK_IMAGE_TYPE_1D:
1314 return (VkOffset3D) { imageOffset.x, 0, 0 };
1315 case VK_IMAGE_TYPE_2D:
1316 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1317 case VK_IMAGE_TYPE_3D:
1318 return imageOffset;
1319 default:
1320 unreachable("invalid image type");
1321 }
1322 }
1323
1324 static inline bool
1325 radv_image_extent_compare(const struct radv_image *image,
1326 const VkExtent3D *extent)
1327 {
1328 if (extent->width != image->info.width ||
1329 extent->height != image->info.height ||
1330 extent->depth != image->info.depth)
1331 return false;
1332 return true;
1333 }
1334
1335 struct radv_sampler {
1336 uint32_t state[4];
1337 };
1338
1339 struct radv_color_buffer_info {
1340 uint64_t cb_color_base;
1341 uint64_t cb_color_cmask;
1342 uint64_t cb_color_fmask;
1343 uint64_t cb_dcc_base;
1344 uint32_t cb_color_pitch;
1345 uint32_t cb_color_slice;
1346 uint32_t cb_color_view;
1347 uint32_t cb_color_info;
1348 uint32_t cb_color_attrib;
1349 uint32_t cb_color_attrib2;
1350 uint32_t cb_dcc_control;
1351 uint32_t cb_color_cmask_slice;
1352 uint32_t cb_color_fmask_slice;
1353 uint32_t cb_clear_value0;
1354 uint32_t cb_clear_value1;
1355 uint32_t micro_tile_mode;
1356 uint32_t gfx9_epitch;
1357 };
1358
1359 struct radv_ds_buffer_info {
1360 uint64_t db_z_read_base;
1361 uint64_t db_stencil_read_base;
1362 uint64_t db_z_write_base;
1363 uint64_t db_stencil_write_base;
1364 uint64_t db_htile_data_base;
1365 uint32_t db_depth_info;
1366 uint32_t db_z_info;
1367 uint32_t db_stencil_info;
1368 uint32_t db_depth_view;
1369 uint32_t db_depth_size;
1370 uint32_t db_depth_slice;
1371 uint32_t db_htile_surface;
1372 uint32_t pa_su_poly_offset_db_fmt_cntl;
1373 uint32_t db_z_info2;
1374 uint32_t db_stencil_info2;
1375 float offset_scale;
1376 };
1377
1378 struct radv_attachment_info {
1379 union {
1380 struct radv_color_buffer_info cb;
1381 struct radv_ds_buffer_info ds;
1382 };
1383 struct radv_image_view *attachment;
1384 };
1385
1386 struct radv_framebuffer {
1387 uint32_t width;
1388 uint32_t height;
1389 uint32_t layers;
1390
1391 uint32_t attachment_count;
1392 struct radv_attachment_info attachments[0];
1393 };
1394
1395 struct radv_subpass_barrier {
1396 VkPipelineStageFlags src_stage_mask;
1397 VkAccessFlags src_access_mask;
1398 VkAccessFlags dst_access_mask;
1399 };
1400
1401 struct radv_subpass {
1402 uint32_t input_count;
1403 uint32_t color_count;
1404 VkAttachmentReference * input_attachments;
1405 VkAttachmentReference * color_attachments;
1406 VkAttachmentReference * resolve_attachments;
1407 VkAttachmentReference depth_stencil_attachment;
1408
1409 /** Subpass has at least one resolve attachment */
1410 bool has_resolve;
1411
1412 struct radv_subpass_barrier start_barrier;
1413 };
1414
1415 struct radv_render_pass_attachment {
1416 VkFormat format;
1417 uint32_t samples;
1418 VkAttachmentLoadOp load_op;
1419 VkAttachmentLoadOp stencil_load_op;
1420 VkImageLayout initial_layout;
1421 VkImageLayout final_layout;
1422 };
1423
1424 struct radv_render_pass {
1425 uint32_t attachment_count;
1426 uint32_t subpass_count;
1427 VkAttachmentReference * subpass_attachments;
1428 struct radv_render_pass_attachment * attachments;
1429 struct radv_subpass_barrier end_barrier;
1430 struct radv_subpass subpasses[0];
1431 };
1432
1433 VkResult radv_device_init_meta(struct radv_device *device);
1434 void radv_device_finish_meta(struct radv_device *device);
1435
1436 struct radv_query_pool {
1437 struct radeon_winsys_bo *bo;
1438 uint32_t stride;
1439 uint32_t availability_offset;
1440 char *ptr;
1441 VkQueryType type;
1442 uint32_t pipeline_stats_mask;
1443 };
1444
1445 void
1446 radv_update_descriptor_sets(struct radv_device *device,
1447 struct radv_cmd_buffer *cmd_buffer,
1448 VkDescriptorSet overrideSet,
1449 uint32_t descriptorWriteCount,
1450 const VkWriteDescriptorSet *pDescriptorWrites,
1451 uint32_t descriptorCopyCount,
1452 const VkCopyDescriptorSet *pDescriptorCopies);
1453
1454 void
1455 radv_update_descriptor_set_with_template(struct radv_device *device,
1456 struct radv_cmd_buffer *cmd_buffer,
1457 struct radv_descriptor_set *set,
1458 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1459 const void *pData);
1460
1461 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1462 VkPipelineBindPoint pipelineBindPoint,
1463 VkPipelineLayout _layout,
1464 uint32_t set,
1465 uint32_t descriptorWriteCount,
1466 const VkWriteDescriptorSet *pDescriptorWrites);
1467
1468 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1469 struct radv_image *image, uint32_t value);
1470 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1471 struct radv_image *image, uint32_t value);
1472
1473 struct radv_fence {
1474 struct radeon_winsys_fence *fence;
1475 bool submitted;
1476 bool signalled;
1477 };
1478
1479 struct radeon_winsys_sem;
1480
1481 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1482 \
1483 static inline struct __radv_type * \
1484 __radv_type ## _from_handle(__VkType _handle) \
1485 { \
1486 return (struct __radv_type *) _handle; \
1487 } \
1488 \
1489 static inline __VkType \
1490 __radv_type ## _to_handle(struct __radv_type *_obj) \
1491 { \
1492 return (__VkType) _obj; \
1493 }
1494
1495 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1496 \
1497 static inline struct __radv_type * \
1498 __radv_type ## _from_handle(__VkType _handle) \
1499 { \
1500 return (struct __radv_type *)(uintptr_t) _handle; \
1501 } \
1502 \
1503 static inline __VkType \
1504 __radv_type ## _to_handle(struct __radv_type *_obj) \
1505 { \
1506 return (__VkType)(uintptr_t) _obj; \
1507 }
1508
1509 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1510 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1511
1512 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1513 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1514 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1515 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1516 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1517
1518 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1519 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1520 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1521 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1522 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1523 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1524 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1525 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1526 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1527 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1528 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1529 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1530 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1531 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1532 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1533 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1534 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1535 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1536 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1537 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1538 RADV_DEFINE_NONDISP_HANDLE_CASTS(radeon_winsys_sem, VkSemaphore)
1539
1540 #endif /* RADV_PRIVATE_H */