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radv: enable AMD_shader_ballot with RADV_PERFTEST_SHADER_BALLOT ('shader_ballot')
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
53 #include "vk_alloc.h"
54 #include "vk_debug_report.h"
55
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_descriptor_set.h"
64 #include "radv_extensions.h"
65 #include "radv_cs.h"
66
67 #include <llvm-c/TargetMachine.h>
68
69 /* Pre-declarations needed for WSI entrypoints */
70 struct wl_surface;
71 struct wl_display;
72 typedef struct xcb_connection_t xcb_connection_t;
73 typedef uint32_t xcb_visualid_t;
74 typedef uint32_t xcb_window_t;
75
76 #include <vulkan/vulkan.h>
77 #include <vulkan/vulkan_intel.h>
78 #include <vulkan/vk_icd.h>
79 #include <vulkan/vk_android_native_buffer.h>
80
81 #include "radv_entrypoints.h"
82
83 #include "wsi_common.h"
84 #include "wsi_common_display.h"
85
86 #define ATI_VENDOR_ID 0x1002
87
88 #define MAX_VBS 32
89 #define MAX_VERTEX_ATTRIBS 32
90 #define MAX_RTS 8
91 #define MAX_VIEWPORTS 16
92 #define MAX_SCISSORS 16
93 #define MAX_DISCARD_RECTANGLES 4
94 #define MAX_SAMPLE_LOCATIONS 32
95 #define MAX_PUSH_CONSTANTS_SIZE 128
96 #define MAX_PUSH_DESCRIPTORS 32
97 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
98 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
99 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
100 #define MAX_SAMPLES_LOG2 4
101 #define NUM_META_FS_KEYS 12
102 #define RADV_MAX_DRM_DEVICES 8
103 #define MAX_VIEWS 8
104 #define MAX_SO_STREAMS 4
105 #define MAX_SO_BUFFERS 4
106 #define MAX_SO_OUTPUTS 64
107 #define MAX_INLINE_UNIFORM_BLOCK_SIZE (4ull * 1024 * 1024)
108 #define MAX_INLINE_UNIFORM_BLOCK_COUNT 64
109
110 #define NUM_DEPTH_CLEAR_PIPELINES 3
111
112 /*
113 * This is the point we switch from using CP to compute shader
114 * for certain buffer operations.
115 */
116 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
117
118 #define RADV_BUFFER_UPDATE_THRESHOLD 1024
119
120 enum radv_mem_heap {
121 RADV_MEM_HEAP_VRAM,
122 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
123 RADV_MEM_HEAP_GTT,
124 RADV_MEM_HEAP_COUNT
125 };
126
127 enum radv_mem_type {
128 RADV_MEM_TYPE_VRAM,
129 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
130 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
131 RADV_MEM_TYPE_GTT_CACHED,
132 RADV_MEM_TYPE_COUNT
133 };
134
135 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
136
137 static inline uint32_t
138 align_u32(uint32_t v, uint32_t a)
139 {
140 assert(a != 0 && a == (a & -a));
141 return (v + a - 1) & ~(a - 1);
142 }
143
144 static inline uint32_t
145 align_u32_npot(uint32_t v, uint32_t a)
146 {
147 return (v + a - 1) / a * a;
148 }
149
150 static inline uint64_t
151 align_u64(uint64_t v, uint64_t a)
152 {
153 assert(a != 0 && a == (a & -a));
154 return (v + a - 1) & ~(a - 1);
155 }
156
157 static inline int32_t
158 align_i32(int32_t v, int32_t a)
159 {
160 assert(a != 0 && a == (a & -a));
161 return (v + a - 1) & ~(a - 1);
162 }
163
164 /** Alignment must be a power of 2. */
165 static inline bool
166 radv_is_aligned(uintmax_t n, uintmax_t a)
167 {
168 assert(a == (a & -a));
169 return (n & (a - 1)) == 0;
170 }
171
172 static inline uint32_t
173 round_up_u32(uint32_t v, uint32_t a)
174 {
175 return (v + a - 1) / a;
176 }
177
178 static inline uint64_t
179 round_up_u64(uint64_t v, uint64_t a)
180 {
181 return (v + a - 1) / a;
182 }
183
184 static inline uint32_t
185 radv_minify(uint32_t n, uint32_t levels)
186 {
187 if (unlikely(n == 0))
188 return 0;
189 else
190 return MAX2(n >> levels, 1);
191 }
192 static inline float
193 radv_clamp_f(float f, float min, float max)
194 {
195 assert(min < max);
196
197 if (f > max)
198 return max;
199 else if (f < min)
200 return min;
201 else
202 return f;
203 }
204
205 static inline bool
206 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
207 {
208 if (*inout_mask & clear_mask) {
209 *inout_mask &= ~clear_mask;
210 return true;
211 } else {
212 return false;
213 }
214 }
215
216 #define for_each_bit(b, dword) \
217 for (uint32_t __dword = (dword); \
218 (b) = __builtin_ffs(__dword) - 1, __dword; \
219 __dword &= ~(1 << (b)))
220
221 #define typed_memcpy(dest, src, count) ({ \
222 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
223 memcpy((dest), (src), (count) * sizeof(*(src))); \
224 })
225
226 /* Whenever we generate an error, pass it through this function. Useful for
227 * debugging, where we can break on it. Only call at error site, not when
228 * propagating errors. Might be useful to plug in a stack trace here.
229 */
230
231 struct radv_instance;
232
233 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
234
235 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
236 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
237
238 void __radv_finishme(const char *file, int line, const char *format, ...)
239 radv_printflike(3, 4);
240 void radv_loge(const char *format, ...) radv_printflike(1, 2);
241 void radv_loge_v(const char *format, va_list va);
242 void radv_logi(const char *format, ...) radv_printflike(1, 2);
243 void radv_logi_v(const char *format, va_list va);
244
245 /**
246 * Print a FINISHME message, including its source location.
247 */
248 #define radv_finishme(format, ...) \
249 do { \
250 static bool reported = false; \
251 if (!reported) { \
252 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
253 reported = true; \
254 } \
255 } while (0)
256
257 /* A non-fatal assert. Useful for debugging. */
258 #ifdef DEBUG
259 #define radv_assert(x) ({ \
260 if (unlikely(!(x))) \
261 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
262 })
263 #else
264 #define radv_assert(x)
265 #endif
266
267 #define stub_return(v) \
268 do { \
269 radv_finishme("stub %s", __func__); \
270 return (v); \
271 } while (0)
272
273 #define stub() \
274 do { \
275 radv_finishme("stub %s", __func__); \
276 return; \
277 } while (0)
278
279 void *radv_lookup_entrypoint_unchecked(const char *name);
280 void *radv_lookup_entrypoint_checked(const char *name,
281 uint32_t core_version,
282 const struct radv_instance_extension_table *instance,
283 const struct radv_device_extension_table *device);
284 void *radv_lookup_physical_device_entrypoint_checked(const char *name,
285 uint32_t core_version,
286 const struct radv_instance_extension_table *instance);
287
288 struct radv_physical_device {
289 VK_LOADER_DATA _loader_data;
290
291 struct radv_instance * instance;
292
293 struct radeon_winsys *ws;
294 struct radeon_info rad_info;
295 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
296 uint8_t driver_uuid[VK_UUID_SIZE];
297 uint8_t device_uuid[VK_UUID_SIZE];
298 uint8_t cache_uuid[VK_UUID_SIZE];
299
300 int local_fd;
301 int master_fd;
302 struct wsi_device wsi_device;
303
304 bool has_rbplus; /* if RB+ register exist */
305 bool rbplus_allowed; /* if RB+ is allowed */
306 bool has_clear_state;
307 bool cpdma_prefetch_writes_memory;
308 bool has_scissor_bug;
309
310 bool has_out_of_order_rast;
311 bool out_of_order_rast_allowed;
312
313 /* Whether DCC should be enabled for MSAA textures. */
314 bool dcc_msaa_allowed;
315
316 /* Whether LOAD_CONTEXT_REG packets are supported. */
317 bool has_load_ctx_reg_pkt;
318
319 /* Whether to enable the AMD_shader_ballot extension */
320 bool use_shader_ballot;
321
322 /* This is the drivers on-disk cache used as a fallback as opposed to
323 * the pipeline cache defined by apps.
324 */
325 struct disk_cache * disk_cache;
326
327 VkPhysicalDeviceMemoryProperties memory_properties;
328 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
329
330 drmPciBusInfo bus_info;
331
332 struct radv_device_extension_table supported_extensions;
333 };
334
335 struct radv_instance {
336 VK_LOADER_DATA _loader_data;
337
338 VkAllocationCallbacks alloc;
339
340 uint32_t apiVersion;
341 int physicalDeviceCount;
342 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
343
344 uint64_t debug_flags;
345 uint64_t perftest_flags;
346
347 struct vk_debug_report_instance debug_report_callbacks;
348
349 struct radv_instance_extension_table enabled_extensions;
350
351 struct driOptionCache dri_options;
352 struct driOptionCache available_dri_options;
353 };
354
355 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
356 void radv_finish_wsi(struct radv_physical_device *physical_device);
357
358 bool radv_instance_extension_supported(const char *name);
359 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
360 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
361 const char *name);
362
363 struct cache_entry;
364
365 struct radv_pipeline_cache {
366 struct radv_device * device;
367 pthread_mutex_t mutex;
368
369 uint32_t total_size;
370 uint32_t table_size;
371 uint32_t kernel_count;
372 struct cache_entry ** hash_table;
373 bool modified;
374
375 VkAllocationCallbacks alloc;
376 };
377
378 struct radv_pipeline_key {
379 uint32_t instance_rate_inputs;
380 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
381 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
382 uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
383 uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
384 uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
385 uint64_t vertex_alpha_adjust;
386 uint32_t vertex_post_shuffle;
387 unsigned tess_input_vertices;
388 uint32_t col_format;
389 uint32_t is_int8;
390 uint32_t is_int10;
391 uint8_t log2_ps_iter_samples;
392 uint8_t num_samples;
393 uint32_t has_multiview_view_index : 1;
394 uint32_t optimisations_disabled : 1;
395 };
396
397 void
398 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
399 struct radv_device *device);
400 void
401 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
402 bool
403 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
404 const void *data, size_t size);
405
406 struct radv_shader_variant;
407
408 bool
409 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
410 struct radv_pipeline_cache *cache,
411 const unsigned char *sha1,
412 struct radv_shader_variant **variants,
413 bool *found_in_application_cache);
414
415 void
416 radv_pipeline_cache_insert_shaders(struct radv_device *device,
417 struct radv_pipeline_cache *cache,
418 const unsigned char *sha1,
419 struct radv_shader_variant **variants,
420 const void *const *codes,
421 const unsigned *code_sizes);
422
423 enum radv_blit_ds_layout {
424 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
425 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
426 RADV_BLIT_DS_LAYOUT_COUNT,
427 };
428
429 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
430 {
431 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
432 }
433
434 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
435 {
436 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
437 }
438
439 enum radv_meta_dst_layout {
440 RADV_META_DST_LAYOUT_GENERAL,
441 RADV_META_DST_LAYOUT_OPTIMAL,
442 RADV_META_DST_LAYOUT_COUNT,
443 };
444
445 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
446 {
447 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
448 }
449
450 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
451 {
452 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
453 }
454
455 struct radv_meta_state {
456 VkAllocationCallbacks alloc;
457
458 struct radv_pipeline_cache cache;
459
460 /*
461 * For on-demand pipeline creation, makes sure that
462 * only one thread tries to build a pipeline at the same time.
463 */
464 mtx_t mtx;
465
466 /**
467 * Use array element `i` for images with `2^i` samples.
468 */
469 struct {
470 VkRenderPass render_pass[NUM_META_FS_KEYS];
471 VkPipeline color_pipelines[NUM_META_FS_KEYS];
472
473 VkRenderPass depthstencil_rp;
474 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
475 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
476 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
477 } clear[1 + MAX_SAMPLES_LOG2];
478
479 VkPipelineLayout clear_color_p_layout;
480 VkPipelineLayout clear_depth_p_layout;
481
482 /* Optimized compute fast HTILE clear for stencil or depth only. */
483 VkPipeline clear_htile_mask_pipeline;
484 VkPipelineLayout clear_htile_mask_p_layout;
485 VkDescriptorSetLayout clear_htile_mask_ds_layout;
486
487 struct {
488 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
489
490 /** Pipeline that blits from a 1D image. */
491 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
492
493 /** Pipeline that blits from a 2D image. */
494 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
495
496 /** Pipeline that blits from a 3D image. */
497 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
498
499 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
500 VkPipeline depth_only_1d_pipeline;
501 VkPipeline depth_only_2d_pipeline;
502 VkPipeline depth_only_3d_pipeline;
503
504 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
505 VkPipeline stencil_only_1d_pipeline;
506 VkPipeline stencil_only_2d_pipeline;
507 VkPipeline stencil_only_3d_pipeline;
508 VkPipelineLayout pipeline_layout;
509 VkDescriptorSetLayout ds_layout;
510 } blit;
511
512 struct {
513 VkPipelineLayout p_layouts[5];
514 VkDescriptorSetLayout ds_layouts[5];
515 VkPipeline pipelines[5][NUM_META_FS_KEYS];
516
517 VkPipeline depth_only_pipeline[5];
518
519 VkPipeline stencil_only_pipeline[5];
520 } blit2d[1 + MAX_SAMPLES_LOG2];
521
522 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
523 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
524 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
525
526 struct {
527 VkPipelineLayout img_p_layout;
528 VkDescriptorSetLayout img_ds_layout;
529 VkPipeline pipeline;
530 VkPipeline pipeline_3d;
531 } itob;
532 struct {
533 VkPipelineLayout img_p_layout;
534 VkDescriptorSetLayout img_ds_layout;
535 VkPipeline pipeline;
536 VkPipeline pipeline_3d;
537 } btoi;
538 struct {
539 VkPipelineLayout img_p_layout;
540 VkDescriptorSetLayout img_ds_layout;
541 VkPipeline pipeline;
542 } btoi_r32g32b32;
543 struct {
544 VkPipelineLayout img_p_layout;
545 VkDescriptorSetLayout img_ds_layout;
546 VkPipeline pipeline;
547 VkPipeline pipeline_3d;
548 } itoi;
549 struct {
550 VkPipelineLayout img_p_layout;
551 VkDescriptorSetLayout img_ds_layout;
552 VkPipeline pipeline;
553 } itoi_r32g32b32;
554 struct {
555 VkPipelineLayout img_p_layout;
556 VkDescriptorSetLayout img_ds_layout;
557 VkPipeline pipeline;
558 VkPipeline pipeline_3d;
559 } cleari;
560 struct {
561 VkPipelineLayout img_p_layout;
562 VkDescriptorSetLayout img_ds_layout;
563 VkPipeline pipeline;
564 } cleari_r32g32b32;
565
566 struct {
567 VkPipelineLayout p_layout;
568 VkPipeline pipeline[NUM_META_FS_KEYS];
569 VkRenderPass pass[NUM_META_FS_KEYS];
570 } resolve;
571
572 struct {
573 VkDescriptorSetLayout ds_layout;
574 VkPipelineLayout p_layout;
575 struct {
576 VkPipeline pipeline;
577 VkPipeline i_pipeline;
578 VkPipeline srgb_pipeline;
579 } rc[MAX_SAMPLES_LOG2];
580 } resolve_compute;
581
582 struct {
583 VkDescriptorSetLayout ds_layout;
584 VkPipelineLayout p_layout;
585
586 struct {
587 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
588 VkPipeline pipeline[NUM_META_FS_KEYS];
589 } rc[MAX_SAMPLES_LOG2];
590 } resolve_fragment;
591
592 struct {
593 VkPipelineLayout p_layout;
594 VkPipeline decompress_pipeline;
595 VkPipeline resummarize_pipeline;
596 VkRenderPass pass;
597 } depth_decomp[1 + MAX_SAMPLES_LOG2];
598
599 struct {
600 VkPipelineLayout p_layout;
601 VkPipeline cmask_eliminate_pipeline;
602 VkPipeline fmask_decompress_pipeline;
603 VkPipeline dcc_decompress_pipeline;
604 VkRenderPass pass;
605
606 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
607 VkPipelineLayout dcc_decompress_compute_p_layout;
608 VkPipeline dcc_decompress_compute_pipeline;
609 } fast_clear_flush;
610
611 struct {
612 VkPipelineLayout fill_p_layout;
613 VkPipelineLayout copy_p_layout;
614 VkDescriptorSetLayout fill_ds_layout;
615 VkDescriptorSetLayout copy_ds_layout;
616 VkPipeline fill_pipeline;
617 VkPipeline copy_pipeline;
618 } buffer;
619
620 struct {
621 VkDescriptorSetLayout ds_layout;
622 VkPipelineLayout p_layout;
623 VkPipeline occlusion_query_pipeline;
624 VkPipeline pipeline_statistics_query_pipeline;
625 VkPipeline tfb_query_pipeline;
626 } query;
627
628 struct {
629 VkDescriptorSetLayout ds_layout;
630 VkPipelineLayout p_layout;
631 VkPipeline pipeline[MAX_SAMPLES_LOG2];
632 } fmask_expand;
633 };
634
635 /* queue types */
636 #define RADV_QUEUE_GENERAL 0
637 #define RADV_QUEUE_COMPUTE 1
638 #define RADV_QUEUE_TRANSFER 2
639
640 #define RADV_MAX_QUEUE_FAMILIES 3
641
642 enum ring_type radv_queue_family_to_ring(int f);
643
644 struct radv_queue {
645 VK_LOADER_DATA _loader_data;
646 struct radv_device * device;
647 struct radeon_winsys_ctx *hw_ctx;
648 enum radeon_ctx_priority priority;
649 uint32_t queue_family_index;
650 int queue_idx;
651 VkDeviceQueueCreateFlags flags;
652
653 uint32_t scratch_size;
654 uint32_t compute_scratch_size;
655 uint32_t esgs_ring_size;
656 uint32_t gsvs_ring_size;
657 bool has_tess_rings;
658 bool has_sample_positions;
659
660 struct radeon_winsys_bo *scratch_bo;
661 struct radeon_winsys_bo *descriptor_bo;
662 struct radeon_winsys_bo *compute_scratch_bo;
663 struct radeon_winsys_bo *esgs_ring_bo;
664 struct radeon_winsys_bo *gsvs_ring_bo;
665 struct radeon_winsys_bo *tess_rings_bo;
666 struct radeon_cmdbuf *initial_preamble_cs;
667 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
668 struct radeon_cmdbuf *continue_preamble_cs;
669 };
670
671 struct radv_bo_list {
672 struct radv_winsys_bo_list list;
673 unsigned capacity;
674 pthread_mutex_t mutex;
675 };
676
677 struct radv_device {
678 VK_LOADER_DATA _loader_data;
679
680 VkAllocationCallbacks alloc;
681
682 struct radv_instance * instance;
683 struct radeon_winsys *ws;
684
685 struct radv_meta_state meta_state;
686
687 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
688 int queue_count[RADV_MAX_QUEUE_FAMILIES];
689 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
690
691 bool always_use_syncobj;
692 bool has_distributed_tess;
693 bool pbb_allowed;
694 bool dfsm_allowed;
695 uint32_t tess_offchip_block_dw_size;
696 uint32_t scratch_waves;
697 uint32_t dispatch_initiator;
698
699 uint32_t gs_table_depth;
700
701 /* MSAA sample locations.
702 * The first index is the sample index.
703 * The second index is the coordinate: X, Y. */
704 float sample_locations_1x[1][2];
705 float sample_locations_2x[2][2];
706 float sample_locations_4x[4][2];
707 float sample_locations_8x[8][2];
708
709 /* GFX7 and later */
710 uint32_t gfx_init_size_dw;
711 struct radeon_winsys_bo *gfx_init;
712
713 struct radeon_winsys_bo *trace_bo;
714 uint32_t *trace_id_ptr;
715
716 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
717 bool keep_shader_info;
718
719 struct radv_physical_device *physical_device;
720
721 /* Backup in-memory cache to be used if the app doesn't provide one */
722 struct radv_pipeline_cache * mem_cache;
723
724 /*
725 * use different counters so MSAA MRTs get consecutive surface indices,
726 * even if MASK is allocated in between.
727 */
728 uint32_t image_mrt_offset_counter;
729 uint32_t fmask_mrt_offset_counter;
730 struct list_head shader_slabs;
731 mtx_t shader_slab_mutex;
732
733 /* For detecting VM faults reported by dmesg. */
734 uint64_t dmesg_timestamp;
735
736 struct radv_device_extension_table enabled_extensions;
737
738 /* Whether the driver uses a global BO list. */
739 bool use_global_bo_list;
740
741 struct radv_bo_list bo_list;
742
743 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
744 int force_aniso;
745 };
746
747 struct radv_device_memory {
748 struct radeon_winsys_bo *bo;
749 /* for dedicated allocations */
750 struct radv_image *image;
751 struct radv_buffer *buffer;
752 uint32_t type_index;
753 VkDeviceSize map_size;
754 void * map;
755 void * user_ptr;
756 };
757
758
759 struct radv_descriptor_range {
760 uint64_t va;
761 uint32_t size;
762 };
763
764 struct radv_descriptor_set {
765 const struct radv_descriptor_set_layout *layout;
766 uint32_t size;
767
768 struct radeon_winsys_bo *bo;
769 uint64_t va;
770 uint32_t *mapped_ptr;
771 struct radv_descriptor_range *dynamic_descriptors;
772
773 struct radeon_winsys_bo *descriptors[0];
774 };
775
776 struct radv_push_descriptor_set
777 {
778 struct radv_descriptor_set set;
779 uint32_t capacity;
780 };
781
782 struct radv_descriptor_pool_entry {
783 uint32_t offset;
784 uint32_t size;
785 struct radv_descriptor_set *set;
786 };
787
788 struct radv_descriptor_pool {
789 struct radeon_winsys_bo *bo;
790 uint8_t *mapped_ptr;
791 uint64_t current_offset;
792 uint64_t size;
793
794 uint8_t *host_memory_base;
795 uint8_t *host_memory_ptr;
796 uint8_t *host_memory_end;
797
798 uint32_t entry_count;
799 uint32_t max_entry_count;
800 struct radv_descriptor_pool_entry entries[0];
801 };
802
803 struct radv_descriptor_update_template_entry {
804 VkDescriptorType descriptor_type;
805
806 /* The number of descriptors to update */
807 uint32_t descriptor_count;
808
809 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
810 uint32_t dst_offset;
811
812 /* In dwords. Not valid/used for dynamic descriptors */
813 uint32_t dst_stride;
814
815 uint32_t buffer_offset;
816
817 /* Only valid for combined image samplers and samplers */
818 uint8_t has_sampler;
819 uint8_t sampler_offset;
820
821 /* In bytes */
822 size_t src_offset;
823 size_t src_stride;
824
825 /* For push descriptors */
826 const uint32_t *immutable_samplers;
827 };
828
829 struct radv_descriptor_update_template {
830 uint32_t entry_count;
831 VkPipelineBindPoint bind_point;
832 struct radv_descriptor_update_template_entry entry[0];
833 };
834
835 struct radv_buffer {
836 VkDeviceSize size;
837
838 VkBufferUsageFlags usage;
839 VkBufferCreateFlags flags;
840
841 /* Set when bound */
842 struct radeon_winsys_bo * bo;
843 VkDeviceSize offset;
844
845 bool shareable;
846 };
847
848 enum radv_dynamic_state_bits {
849 RADV_DYNAMIC_VIEWPORT = 1 << 0,
850 RADV_DYNAMIC_SCISSOR = 1 << 1,
851 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
852 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
853 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
854 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
855 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
856 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
857 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
858 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
859 RADV_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
860 RADV_DYNAMIC_ALL = (1 << 11) - 1,
861 };
862
863 enum radv_cmd_dirty_bits {
864 /* Keep the dynamic state dirty bits in sync with
865 * enum radv_dynamic_state_bits */
866 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
867 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
868 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
869 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
870 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
871 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
872 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
873 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
874 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
875 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
876 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
877 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 11) - 1,
878 RADV_CMD_DIRTY_PIPELINE = 1 << 11,
879 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 12,
880 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 13,
881 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 14,
882 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 15,
883 };
884
885 enum radv_cmd_flush_bits {
886 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
887 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
888 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
889 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
890 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
891 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
892 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
893 /* Same as above, but only writes back and doesn't invalidate */
894 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
895 /* Framebuffer caches */
896 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
897 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
898 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
899 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
900 /* Engine synchronization. */
901 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
902 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
903 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
904 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
905 /* Pipeline query controls. */
906 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
907 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
908 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
909
910 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
911 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
912 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
913 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
914 };
915
916 struct radv_vertex_binding {
917 struct radv_buffer * buffer;
918 VkDeviceSize offset;
919 };
920
921 struct radv_streamout_binding {
922 struct radv_buffer *buffer;
923 VkDeviceSize offset;
924 VkDeviceSize size;
925 };
926
927 struct radv_streamout_state {
928 /* Mask of bound streamout buffers. */
929 uint8_t enabled_mask;
930
931 /* External state that comes from the last vertex stage, it must be
932 * set explicitely when binding a new graphics pipeline.
933 */
934 uint16_t stride_in_dw[MAX_SO_BUFFERS];
935 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
936
937 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
938 uint32_t hw_enabled_mask;
939
940 /* State of VGT_STRMOUT_(CONFIG|EN) */
941 bool streamout_enabled;
942 };
943
944 struct radv_viewport_state {
945 uint32_t count;
946 VkViewport viewports[MAX_VIEWPORTS];
947 };
948
949 struct radv_scissor_state {
950 uint32_t count;
951 VkRect2D scissors[MAX_SCISSORS];
952 };
953
954 struct radv_discard_rectangle_state {
955 uint32_t count;
956 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
957 };
958
959 struct radv_sample_locations_state {
960 VkSampleCountFlagBits per_pixel;
961 VkExtent2D grid_size;
962 uint32_t count;
963 VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
964 };
965
966 struct radv_dynamic_state {
967 /**
968 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
969 * Defines the set of saved dynamic state.
970 */
971 uint32_t mask;
972
973 struct radv_viewport_state viewport;
974
975 struct radv_scissor_state scissor;
976
977 float line_width;
978
979 struct {
980 float bias;
981 float clamp;
982 float slope;
983 } depth_bias;
984
985 float blend_constants[4];
986
987 struct {
988 float min;
989 float max;
990 } depth_bounds;
991
992 struct {
993 uint32_t front;
994 uint32_t back;
995 } stencil_compare_mask;
996
997 struct {
998 uint32_t front;
999 uint32_t back;
1000 } stencil_write_mask;
1001
1002 struct {
1003 uint32_t front;
1004 uint32_t back;
1005 } stencil_reference;
1006
1007 struct radv_discard_rectangle_state discard_rectangle;
1008
1009 struct radv_sample_locations_state sample_location;
1010 };
1011
1012 extern const struct radv_dynamic_state default_dynamic_state;
1013
1014 const char *
1015 radv_get_debug_option_name(int id);
1016
1017 const char *
1018 radv_get_perftest_option_name(int id);
1019
1020 /**
1021 * Attachment state when recording a renderpass instance.
1022 *
1023 * The clear value is valid only if there exists a pending clear.
1024 */
1025 struct radv_attachment_state {
1026 VkImageAspectFlags pending_clear_aspects;
1027 uint32_t cleared_views;
1028 VkClearValue clear_value;
1029 VkImageLayout current_layout;
1030 struct radv_sample_locations_state sample_location;
1031 };
1032
1033 struct radv_descriptor_state {
1034 struct radv_descriptor_set *sets[MAX_SETS];
1035 uint32_t dirty;
1036 uint32_t valid;
1037 struct radv_push_descriptor_set push_set;
1038 bool push_dirty;
1039 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1040 };
1041
1042 struct radv_subpass_sample_locs_state {
1043 uint32_t subpass_idx;
1044 struct radv_sample_locations_state sample_location;
1045 };
1046
1047 struct radv_cmd_state {
1048 /* Vertex descriptors */
1049 uint64_t vb_va;
1050 unsigned vb_size;
1051
1052 bool predicating;
1053 uint32_t dirty;
1054
1055 uint32_t prefetch_L2_mask;
1056
1057 struct radv_pipeline * pipeline;
1058 struct radv_pipeline * emitted_pipeline;
1059 struct radv_pipeline * compute_pipeline;
1060 struct radv_pipeline * emitted_compute_pipeline;
1061 struct radv_framebuffer * framebuffer;
1062 struct radv_render_pass * pass;
1063 const struct radv_subpass * subpass;
1064 struct radv_dynamic_state dynamic;
1065 struct radv_attachment_state * attachments;
1066 struct radv_streamout_state streamout;
1067 VkRect2D render_area;
1068
1069 uint32_t num_subpass_sample_locs;
1070 struct radv_subpass_sample_locs_state * subpass_sample_locs;
1071
1072 /* Index buffer */
1073 struct radv_buffer *index_buffer;
1074 uint64_t index_offset;
1075 uint32_t index_type;
1076 uint32_t max_index_count;
1077 uint64_t index_va;
1078 int32_t last_index_type;
1079
1080 int32_t last_primitive_reset_en;
1081 uint32_t last_primitive_reset_index;
1082 enum radv_cmd_flush_bits flush_bits;
1083 unsigned active_occlusion_queries;
1084 bool perfect_occlusion_queries_enabled;
1085 unsigned active_pipeline_queries;
1086 float offset_scale;
1087 uint32_t trace_id;
1088 uint32_t last_ia_multi_vgt_param;
1089
1090 uint32_t last_num_instances;
1091 uint32_t last_first_instance;
1092 uint32_t last_vertex_offset;
1093
1094 /* Whether CP DMA is busy/idle. */
1095 bool dma_is_busy;
1096
1097 /* Conditional rendering info. */
1098 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1099 uint64_t predication_va;
1100
1101 bool context_roll_without_scissor_emitted;
1102 };
1103
1104 struct radv_cmd_pool {
1105 VkAllocationCallbacks alloc;
1106 struct list_head cmd_buffers;
1107 struct list_head free_cmd_buffers;
1108 uint32_t queue_family_index;
1109 };
1110
1111 struct radv_cmd_buffer_upload {
1112 uint8_t *map;
1113 unsigned offset;
1114 uint64_t size;
1115 struct radeon_winsys_bo *upload_bo;
1116 struct list_head list;
1117 };
1118
1119 enum radv_cmd_buffer_status {
1120 RADV_CMD_BUFFER_STATUS_INVALID,
1121 RADV_CMD_BUFFER_STATUS_INITIAL,
1122 RADV_CMD_BUFFER_STATUS_RECORDING,
1123 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1124 RADV_CMD_BUFFER_STATUS_PENDING,
1125 };
1126
1127 struct radv_cmd_buffer {
1128 VK_LOADER_DATA _loader_data;
1129
1130 struct radv_device * device;
1131
1132 struct radv_cmd_pool * pool;
1133 struct list_head pool_link;
1134
1135 VkCommandBufferUsageFlags usage_flags;
1136 VkCommandBufferLevel level;
1137 enum radv_cmd_buffer_status status;
1138 struct radeon_cmdbuf *cs;
1139 struct radv_cmd_state state;
1140 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1141 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1142 uint32_t queue_family_index;
1143
1144 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1145 VkShaderStageFlags push_constant_stages;
1146 struct radv_descriptor_set meta_push_descriptors;
1147
1148 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1149
1150 struct radv_cmd_buffer_upload upload;
1151
1152 uint32_t scratch_size_needed;
1153 uint32_t compute_scratch_size_needed;
1154 uint32_t esgs_ring_size_needed;
1155 uint32_t gsvs_ring_size_needed;
1156 bool tess_rings_needed;
1157 bool sample_positions_needed;
1158
1159 VkResult record_result;
1160
1161 uint64_t gfx9_fence_va;
1162 uint32_t gfx9_fence_idx;
1163 uint64_t gfx9_eop_bug_va;
1164
1165 /**
1166 * Whether a query pool has been resetted and we have to flush caches.
1167 */
1168 bool pending_reset_query;
1169
1170 /**
1171 * Bitmask of pending active query flushes.
1172 */
1173 enum radv_cmd_flush_bits active_query_flush_bits;
1174 };
1175
1176 struct radv_image;
1177
1178 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1179
1180 void si_emit_graphics(struct radv_physical_device *physical_device,
1181 struct radeon_cmdbuf *cs);
1182 void si_emit_compute(struct radv_physical_device *physical_device,
1183 struct radeon_cmdbuf *cs);
1184
1185 void cik_create_gfx_config(struct radv_device *device);
1186
1187 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1188 int count, const VkViewport *viewports);
1189 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1190 int count, const VkRect2D *scissors,
1191 const VkViewport *viewports, bool can_use_guardband);
1192 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1193 bool instanced_draw, bool indirect_draw,
1194 bool count_from_stream_output,
1195 uint32_t draw_vertex_count);
1196 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1197 enum chip_class chip_class,
1198 bool is_mec,
1199 unsigned event, unsigned event_flags,
1200 unsigned data_sel,
1201 uint64_t va,
1202 uint32_t new_fence,
1203 uint64_t gfx9_eop_bug_va);
1204
1205 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1206 uint32_t ref, uint32_t mask);
1207 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1208 enum chip_class chip_class,
1209 uint32_t *fence_ptr, uint64_t va,
1210 bool is_mec,
1211 enum radv_cmd_flush_bits flush_bits,
1212 uint64_t gfx9_eop_bug_va);
1213 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1214 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1215 bool inverted, uint64_t va);
1216 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1217 uint64_t src_va, uint64_t dest_va,
1218 uint64_t size);
1219 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1220 unsigned size);
1221 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1222 uint64_t size, unsigned value);
1223 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1224
1225 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1226 bool
1227 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1228 unsigned size,
1229 unsigned alignment,
1230 unsigned *out_offset,
1231 void **ptr);
1232 void
1233 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1234 const struct radv_subpass *subpass);
1235 bool
1236 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1237 unsigned size, unsigned alignmnet,
1238 const void *data, unsigned *out_offset);
1239
1240 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1241 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1242 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1243 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1244 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
1245 unsigned radv_get_default_max_sample_dist(int log_samples);
1246 void radv_device_init_msaa(struct radv_device *device);
1247
1248 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1249 struct radv_image *image,
1250 VkClearDepthStencilValue ds_clear_value,
1251 VkImageAspectFlags aspects);
1252
1253 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1254 struct radv_image *image,
1255 int cb_idx,
1256 uint32_t color_values[2]);
1257
1258 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1259 struct radv_image *image, bool value);
1260
1261 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1262 struct radv_image *image, bool value);
1263
1264 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1265 struct radeon_winsys_bo *bo,
1266 uint64_t offset, uint64_t size, uint32_t value);
1267 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1268 bool radv_get_memory_fd(struct radv_device *device,
1269 struct radv_device_memory *memory,
1270 int *pFD);
1271
1272 static inline void
1273 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1274 unsigned sh_offset, unsigned pointer_count,
1275 bool use_32bit_pointers)
1276 {
1277 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1278 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1279 }
1280
1281 static inline void
1282 radv_emit_shader_pointer_body(struct radv_device *device,
1283 struct radeon_cmdbuf *cs,
1284 uint64_t va, bool use_32bit_pointers)
1285 {
1286 radeon_emit(cs, va);
1287
1288 if (use_32bit_pointers) {
1289 assert(va == 0 ||
1290 (va >> 32) == device->physical_device->rad_info.address32_hi);
1291 } else {
1292 radeon_emit(cs, va >> 32);
1293 }
1294 }
1295
1296 static inline void
1297 radv_emit_shader_pointer(struct radv_device *device,
1298 struct radeon_cmdbuf *cs,
1299 uint32_t sh_offset, uint64_t va, bool global)
1300 {
1301 bool use_32bit_pointers = !global;
1302
1303 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1304 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1305 }
1306
1307 static inline struct radv_descriptor_state *
1308 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1309 VkPipelineBindPoint bind_point)
1310 {
1311 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1312 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1313 return &cmd_buffer->descriptors[bind_point];
1314 }
1315
1316 /*
1317 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1318 *
1319 * Limitations: Can't call normal dispatch functions without binding or rebinding
1320 * the compute pipeline.
1321 */
1322 void radv_unaligned_dispatch(
1323 struct radv_cmd_buffer *cmd_buffer,
1324 uint32_t x,
1325 uint32_t y,
1326 uint32_t z);
1327
1328 struct radv_event {
1329 struct radeon_winsys_bo *bo;
1330 uint64_t *map;
1331 };
1332
1333 struct radv_shader_module;
1334
1335 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1336 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1337 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1338 void
1339 radv_hash_shaders(unsigned char *hash,
1340 const VkPipelineShaderStageCreateInfo **stages,
1341 const struct radv_pipeline_layout *layout,
1342 const struct radv_pipeline_key *key,
1343 uint32_t flags);
1344
1345 static inline gl_shader_stage
1346 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1347 {
1348 assert(__builtin_popcount(vk_stage) == 1);
1349 return ffs(vk_stage) - 1;
1350 }
1351
1352 static inline VkShaderStageFlagBits
1353 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1354 {
1355 return (1 << mesa_stage);
1356 }
1357
1358 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1359
1360 #define radv_foreach_stage(stage, stage_bits) \
1361 for (gl_shader_stage stage, \
1362 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1363 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1364 __tmp &= ~(1 << (stage)))
1365
1366 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1367 unsigned radv_format_meta_fs_key(VkFormat format);
1368
1369 struct radv_multisample_state {
1370 uint32_t db_eqaa;
1371 uint32_t pa_sc_line_cntl;
1372 uint32_t pa_sc_mode_cntl_0;
1373 uint32_t pa_sc_mode_cntl_1;
1374 uint32_t pa_sc_aa_config;
1375 uint32_t pa_sc_aa_mask[2];
1376 unsigned num_samples;
1377 };
1378
1379 struct radv_prim_vertex_count {
1380 uint8_t min;
1381 uint8_t incr;
1382 };
1383
1384 struct radv_vertex_elements_info {
1385 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1386 };
1387
1388 struct radv_ia_multi_vgt_param_helpers {
1389 uint32_t base;
1390 bool partial_es_wave;
1391 uint8_t primgroup_size;
1392 bool wd_switch_on_eop;
1393 bool ia_switch_on_eoi;
1394 bool partial_vs_wave;
1395 };
1396
1397 #define SI_GS_PER_ES 128
1398
1399 struct radv_pipeline {
1400 struct radv_device * device;
1401 struct radv_dynamic_state dynamic_state;
1402
1403 struct radv_pipeline_layout * layout;
1404
1405 bool need_indirect_descriptor_sets;
1406 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1407 struct radv_shader_variant *gs_copy_shader;
1408 VkShaderStageFlags active_stages;
1409
1410 struct radeon_cmdbuf cs;
1411 uint32_t ctx_cs_hash;
1412 struct radeon_cmdbuf ctx_cs;
1413
1414 struct radv_vertex_elements_info vertex_elements;
1415
1416 uint32_t binding_stride[MAX_VBS];
1417 uint8_t num_vertex_bindings;
1418
1419 uint32_t user_data_0[MESA_SHADER_STAGES];
1420 union {
1421 struct {
1422 struct radv_multisample_state ms;
1423 uint32_t spi_baryc_cntl;
1424 bool prim_restart_enable;
1425 unsigned esgs_ring_size;
1426 unsigned gsvs_ring_size;
1427 uint32_t vtx_base_sgpr;
1428 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1429 uint8_t vtx_emit_num;
1430 struct radv_prim_vertex_count prim_vertex_count;
1431 bool can_use_guardband;
1432 uint32_t needed_dynamic_state;
1433 bool disable_out_of_order_rast_for_occlusion;
1434
1435 /* Used for rbplus */
1436 uint32_t col_format;
1437 uint32_t cb_target_mask;
1438 } graphics;
1439 };
1440
1441 unsigned max_waves;
1442 unsigned scratch_bytes_per_wave;
1443
1444 /* Not NULL if graphics pipeline uses streamout. */
1445 struct radv_shader_variant *streamout_shader;
1446 };
1447
1448 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1449 {
1450 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1451 }
1452
1453 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1454 {
1455 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1456 }
1457
1458 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1459 gl_shader_stage stage,
1460 int idx);
1461
1462 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1463 gl_shader_stage stage);
1464
1465 struct radv_graphics_pipeline_create_info {
1466 bool use_rectlist;
1467 bool db_depth_clear;
1468 bool db_stencil_clear;
1469 bool db_depth_disable_expclear;
1470 bool db_stencil_disable_expclear;
1471 bool db_flush_depth_inplace;
1472 bool db_flush_stencil_inplace;
1473 bool db_resummarize;
1474 uint32_t custom_blend_mode;
1475 };
1476
1477 VkResult
1478 radv_graphics_pipeline_create(VkDevice device,
1479 VkPipelineCache cache,
1480 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1481 const struct radv_graphics_pipeline_create_info *extra,
1482 const VkAllocationCallbacks *alloc,
1483 VkPipeline *pPipeline);
1484
1485 struct vk_format_description;
1486 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1487 int first_non_void);
1488 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1489 int first_non_void);
1490 uint32_t radv_translate_colorformat(VkFormat format);
1491 uint32_t radv_translate_color_numformat(VkFormat format,
1492 const struct vk_format_description *desc,
1493 int first_non_void);
1494 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1495 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1496 uint32_t radv_translate_dbformat(VkFormat format);
1497 uint32_t radv_translate_tex_dataformat(VkFormat format,
1498 const struct vk_format_description *desc,
1499 int first_non_void);
1500 uint32_t radv_translate_tex_numformat(VkFormat format,
1501 const struct vk_format_description *desc,
1502 int first_non_void);
1503 bool radv_format_pack_clear_color(VkFormat format,
1504 uint32_t clear_vals[2],
1505 VkClearColorValue *value);
1506 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1507 bool radv_dcc_formats_compatible(VkFormat format1,
1508 VkFormat format2);
1509 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
1510
1511 struct radv_fmask_info {
1512 uint64_t offset;
1513 uint64_t size;
1514 unsigned alignment;
1515 unsigned pitch_in_pixels;
1516 unsigned bank_height;
1517 unsigned slice_tile_max;
1518 unsigned tile_mode_index;
1519 unsigned tile_swizzle;
1520 };
1521
1522 struct radv_cmask_info {
1523 uint64_t offset;
1524 uint64_t size;
1525 unsigned alignment;
1526 unsigned slice_tile_max;
1527 };
1528
1529
1530 struct radv_image_plane {
1531 VkFormat format;
1532 struct radeon_surf surface;
1533 uint64_t offset;
1534 };
1535
1536 struct radv_image {
1537 VkImageType type;
1538 /* The original VkFormat provided by the client. This may not match any
1539 * of the actual surface formats.
1540 */
1541 VkFormat vk_format;
1542 VkImageAspectFlags aspects;
1543 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1544 struct ac_surf_info info;
1545 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1546 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1547
1548 VkDeviceSize size;
1549 uint32_t alignment;
1550
1551 unsigned queue_family_mask;
1552 bool exclusive;
1553 bool shareable;
1554
1555 /* Set when bound */
1556 struct radeon_winsys_bo *bo;
1557 VkDeviceSize offset;
1558 uint64_t dcc_offset;
1559 uint64_t htile_offset;
1560 bool tc_compatible_htile;
1561
1562 struct radv_fmask_info fmask;
1563 struct radv_cmask_info cmask;
1564 uint64_t clear_value_offset;
1565 uint64_t fce_pred_offset;
1566 uint64_t dcc_pred_offset;
1567
1568 /*
1569 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1570 * stored at this offset is UINT_MAX, the driver will emit
1571 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1572 * SET_CONTEXT_REG packet.
1573 */
1574 uint64_t tc_compat_zrange_offset;
1575
1576 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1577 VkDeviceMemory owned_memory;
1578
1579 unsigned plane_count;
1580 struct radv_image_plane planes[0];
1581 };
1582
1583 /* Whether the image has a htile that is known consistent with the contents of
1584 * the image. */
1585 bool radv_layout_has_htile(const struct radv_image *image,
1586 VkImageLayout layout,
1587 unsigned queue_mask);
1588
1589 /* Whether the image has a htile that is known consistent with the contents of
1590 * the image and is allowed to be in compressed form.
1591 *
1592 * If this is false reads that don't use the htile should be able to return
1593 * correct results.
1594 */
1595 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1596 VkImageLayout layout,
1597 unsigned queue_mask);
1598
1599 bool radv_layout_can_fast_clear(const struct radv_image *image,
1600 VkImageLayout layout,
1601 unsigned queue_mask);
1602
1603 bool radv_layout_dcc_compressed(const struct radv_image *image,
1604 VkImageLayout layout,
1605 unsigned queue_mask);
1606
1607 /**
1608 * Return whether the image has CMASK metadata for color surfaces.
1609 */
1610 static inline bool
1611 radv_image_has_cmask(const struct radv_image *image)
1612 {
1613 return image->cmask.size;
1614 }
1615
1616 /**
1617 * Return whether the image has FMASK metadata for color surfaces.
1618 */
1619 static inline bool
1620 radv_image_has_fmask(const struct radv_image *image)
1621 {
1622 return image->fmask.size;
1623 }
1624
1625 /**
1626 * Return whether the image has DCC metadata for color surfaces.
1627 */
1628 static inline bool
1629 radv_image_has_dcc(const struct radv_image *image)
1630 {
1631 return image->planes[0].surface.dcc_size;
1632 }
1633
1634 /**
1635 * Return whether DCC metadata is enabled for a level.
1636 */
1637 static inline bool
1638 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1639 {
1640 return radv_image_has_dcc(image) &&
1641 level < image->planes[0].surface.num_dcc_levels;
1642 }
1643
1644 /**
1645 * Return whether the image has CB metadata.
1646 */
1647 static inline bool
1648 radv_image_has_CB_metadata(const struct radv_image *image)
1649 {
1650 return radv_image_has_cmask(image) ||
1651 radv_image_has_fmask(image) ||
1652 radv_image_has_dcc(image);
1653 }
1654
1655 /**
1656 * Return whether the image has HTILE metadata for depth surfaces.
1657 */
1658 static inline bool
1659 radv_image_has_htile(const struct radv_image *image)
1660 {
1661 return image->planes[0].surface.htile_size;
1662 }
1663
1664 /**
1665 * Return whether HTILE metadata is enabled for a level.
1666 */
1667 static inline bool
1668 radv_htile_enabled(const struct radv_image *image, unsigned level)
1669 {
1670 return radv_image_has_htile(image) && level == 0;
1671 }
1672
1673 /**
1674 * Return whether the image is TC-compatible HTILE.
1675 */
1676 static inline bool
1677 radv_image_is_tc_compat_htile(const struct radv_image *image)
1678 {
1679 return radv_image_has_htile(image) && image->tc_compatible_htile;
1680 }
1681
1682 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1683
1684 static inline uint32_t
1685 radv_get_layerCount(const struct radv_image *image,
1686 const VkImageSubresourceRange *range)
1687 {
1688 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1689 image->info.array_size - range->baseArrayLayer : range->layerCount;
1690 }
1691
1692 static inline uint32_t
1693 radv_get_levelCount(const struct radv_image *image,
1694 const VkImageSubresourceRange *range)
1695 {
1696 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1697 image->info.levels - range->baseMipLevel : range->levelCount;
1698 }
1699
1700 struct radeon_bo_metadata;
1701 void
1702 radv_init_metadata(struct radv_device *device,
1703 struct radv_image *image,
1704 struct radeon_bo_metadata *metadata);
1705
1706 void
1707 radv_image_override_offset_stride(struct radv_device *device,
1708 struct radv_image *image,
1709 uint64_t offset, uint32_t stride);
1710
1711 union radv_descriptor {
1712 struct {
1713 uint32_t plane0_descriptor[8];
1714 uint32_t fmask_descriptor[8];
1715 };
1716 struct {
1717 uint32_t plane_descriptors[3][8];
1718 };
1719 };
1720
1721 struct radv_image_view {
1722 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1723 struct radeon_winsys_bo *bo;
1724
1725 VkImageViewType type;
1726 VkImageAspectFlags aspect_mask;
1727 VkFormat vk_format;
1728 unsigned plane_id;
1729 bool multiple_planes;
1730 uint32_t base_layer;
1731 uint32_t layer_count;
1732 uint32_t base_mip;
1733 uint32_t level_count;
1734 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1735
1736 union radv_descriptor descriptor;
1737
1738 /* Descriptor for use as a storage image as opposed to a sampled image.
1739 * This has a few differences for cube maps (e.g. type).
1740 */
1741 union radv_descriptor storage_descriptor;
1742 };
1743
1744 struct radv_image_create_info {
1745 const VkImageCreateInfo *vk_info;
1746 bool scanout;
1747 bool no_metadata_planes;
1748 const struct radeon_bo_metadata *bo_metadata;
1749 };
1750
1751 VkResult radv_image_create(VkDevice _device,
1752 const struct radv_image_create_info *info,
1753 const VkAllocationCallbacks* alloc,
1754 VkImage *pImage);
1755
1756 VkResult
1757 radv_image_from_gralloc(VkDevice device_h,
1758 const VkImageCreateInfo *base_info,
1759 const VkNativeBufferANDROID *gralloc_info,
1760 const VkAllocationCallbacks *alloc,
1761 VkImage *out_image_h);
1762
1763 void radv_image_view_init(struct radv_image_view *view,
1764 struct radv_device *device,
1765 const VkImageViewCreateInfo* pCreateInfo);
1766
1767 VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
1768
1769 struct radv_sampler_ycbcr_conversion {
1770 VkFormat format;
1771 VkSamplerYcbcrModelConversion ycbcr_model;
1772 VkSamplerYcbcrRange ycbcr_range;
1773 VkComponentMapping components;
1774 VkChromaLocation chroma_offsets[2];
1775 VkFilter chroma_filter;
1776 };
1777
1778 struct radv_buffer_view {
1779 struct radeon_winsys_bo *bo;
1780 VkFormat vk_format;
1781 uint64_t range; /**< VkBufferViewCreateInfo::range */
1782 uint32_t state[4];
1783 };
1784 void radv_buffer_view_init(struct radv_buffer_view *view,
1785 struct radv_device *device,
1786 const VkBufferViewCreateInfo* pCreateInfo);
1787
1788 static inline struct VkExtent3D
1789 radv_sanitize_image_extent(const VkImageType imageType,
1790 const struct VkExtent3D imageExtent)
1791 {
1792 switch (imageType) {
1793 case VK_IMAGE_TYPE_1D:
1794 return (VkExtent3D) { imageExtent.width, 1, 1 };
1795 case VK_IMAGE_TYPE_2D:
1796 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1797 case VK_IMAGE_TYPE_3D:
1798 return imageExtent;
1799 default:
1800 unreachable("invalid image type");
1801 }
1802 }
1803
1804 static inline struct VkOffset3D
1805 radv_sanitize_image_offset(const VkImageType imageType,
1806 const struct VkOffset3D imageOffset)
1807 {
1808 switch (imageType) {
1809 case VK_IMAGE_TYPE_1D:
1810 return (VkOffset3D) { imageOffset.x, 0, 0 };
1811 case VK_IMAGE_TYPE_2D:
1812 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1813 case VK_IMAGE_TYPE_3D:
1814 return imageOffset;
1815 default:
1816 unreachable("invalid image type");
1817 }
1818 }
1819
1820 static inline bool
1821 radv_image_extent_compare(const struct radv_image *image,
1822 const VkExtent3D *extent)
1823 {
1824 if (extent->width != image->info.width ||
1825 extent->height != image->info.height ||
1826 extent->depth != image->info.depth)
1827 return false;
1828 return true;
1829 }
1830
1831 struct radv_sampler {
1832 uint32_t state[4];
1833 struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
1834 };
1835
1836 struct radv_color_buffer_info {
1837 uint64_t cb_color_base;
1838 uint64_t cb_color_cmask;
1839 uint64_t cb_color_fmask;
1840 uint64_t cb_dcc_base;
1841 uint32_t cb_color_slice;
1842 uint32_t cb_color_view;
1843 uint32_t cb_color_info;
1844 uint32_t cb_color_attrib;
1845 uint32_t cb_color_attrib2;
1846 uint32_t cb_dcc_control;
1847 uint32_t cb_color_cmask_slice;
1848 uint32_t cb_color_fmask_slice;
1849 union {
1850 uint32_t cb_color_pitch; // GFX6-GFX8
1851 uint32_t cb_mrt_epitch; // GFX9+
1852 };
1853 };
1854
1855 struct radv_ds_buffer_info {
1856 uint64_t db_z_read_base;
1857 uint64_t db_stencil_read_base;
1858 uint64_t db_z_write_base;
1859 uint64_t db_stencil_write_base;
1860 uint64_t db_htile_data_base;
1861 uint32_t db_depth_info;
1862 uint32_t db_z_info;
1863 uint32_t db_stencil_info;
1864 uint32_t db_depth_view;
1865 uint32_t db_depth_size;
1866 uint32_t db_depth_slice;
1867 uint32_t db_htile_surface;
1868 uint32_t pa_su_poly_offset_db_fmt_cntl;
1869 uint32_t db_z_info2;
1870 uint32_t db_stencil_info2;
1871 float offset_scale;
1872 };
1873
1874 struct radv_attachment_info {
1875 union {
1876 struct radv_color_buffer_info cb;
1877 struct radv_ds_buffer_info ds;
1878 };
1879 struct radv_image_view *attachment;
1880 };
1881
1882 struct radv_framebuffer {
1883 uint32_t width;
1884 uint32_t height;
1885 uint32_t layers;
1886
1887 uint32_t attachment_count;
1888 struct radv_attachment_info attachments[0];
1889 };
1890
1891 struct radv_subpass_barrier {
1892 VkPipelineStageFlags src_stage_mask;
1893 VkAccessFlags src_access_mask;
1894 VkAccessFlags dst_access_mask;
1895 };
1896
1897 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1898 const struct radv_subpass_barrier *barrier);
1899
1900 struct radv_subpass_attachment {
1901 uint32_t attachment;
1902 VkImageLayout layout;
1903 };
1904
1905 struct radv_subpass {
1906 uint32_t attachment_count;
1907 struct radv_subpass_attachment * attachments;
1908
1909 uint32_t input_count;
1910 uint32_t color_count;
1911 struct radv_subpass_attachment * input_attachments;
1912 struct radv_subpass_attachment * color_attachments;
1913 struct radv_subpass_attachment * resolve_attachments;
1914 struct radv_subpass_attachment * depth_stencil_attachment;
1915
1916 /** Subpass has at least one resolve attachment */
1917 bool has_resolve;
1918
1919 /** Subpass has at least one color attachment */
1920 bool has_color_att;
1921
1922 struct radv_subpass_barrier start_barrier;
1923
1924 uint32_t view_mask;
1925 VkSampleCountFlagBits max_sample_count;
1926 };
1927
1928 struct radv_render_pass_attachment {
1929 VkFormat format;
1930 uint32_t samples;
1931 VkAttachmentLoadOp load_op;
1932 VkAttachmentLoadOp stencil_load_op;
1933 VkImageLayout initial_layout;
1934 VkImageLayout final_layout;
1935
1936 /* The subpass id in which the attachment will be used first/last. */
1937 uint32_t first_subpass_idx;
1938 uint32_t last_subpass_idx;
1939 };
1940
1941 struct radv_render_pass {
1942 uint32_t attachment_count;
1943 uint32_t subpass_count;
1944 struct radv_subpass_attachment * subpass_attachments;
1945 struct radv_render_pass_attachment * attachments;
1946 struct radv_subpass_barrier end_barrier;
1947 struct radv_subpass subpasses[0];
1948 };
1949
1950 VkResult radv_device_init_meta(struct radv_device *device);
1951 void radv_device_finish_meta(struct radv_device *device);
1952
1953 struct radv_query_pool {
1954 struct radeon_winsys_bo *bo;
1955 uint32_t stride;
1956 uint32_t availability_offset;
1957 uint64_t size;
1958 char *ptr;
1959 VkQueryType type;
1960 uint32_t pipeline_stats_mask;
1961 };
1962
1963 struct radv_semaphore {
1964 /* use a winsys sem for non-exportable */
1965 struct radeon_winsys_sem *sem;
1966 uint32_t syncobj;
1967 uint32_t temp_syncobj;
1968 };
1969
1970 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1971 VkPipelineBindPoint bind_point,
1972 struct radv_descriptor_set *set,
1973 unsigned idx);
1974
1975 void
1976 radv_update_descriptor_sets(struct radv_device *device,
1977 struct radv_cmd_buffer *cmd_buffer,
1978 VkDescriptorSet overrideSet,
1979 uint32_t descriptorWriteCount,
1980 const VkWriteDescriptorSet *pDescriptorWrites,
1981 uint32_t descriptorCopyCount,
1982 const VkCopyDescriptorSet *pDescriptorCopies);
1983
1984 void
1985 radv_update_descriptor_set_with_template(struct radv_device *device,
1986 struct radv_cmd_buffer *cmd_buffer,
1987 struct radv_descriptor_set *set,
1988 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1989 const void *pData);
1990
1991 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1992 VkPipelineBindPoint pipelineBindPoint,
1993 VkPipelineLayout _layout,
1994 uint32_t set,
1995 uint32_t descriptorWriteCount,
1996 const VkWriteDescriptorSet *pDescriptorWrites);
1997
1998 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1999 struct radv_image *image, uint32_t value);
2000
2001 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
2002 struct radv_image *image);
2003
2004 struct radv_fence {
2005 struct radeon_winsys_fence *fence;
2006 struct wsi_fence *fence_wsi;
2007
2008 uint32_t syncobj;
2009 uint32_t temp_syncobj;
2010 };
2011
2012 /* radv_nir_to_llvm.c */
2013 struct radv_shader_variant_info;
2014 struct radv_nir_compiler_options;
2015
2016 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
2017 struct nir_shader *geom_shader,
2018 struct ac_shader_binary *binary,
2019 struct ac_shader_config *config,
2020 struct radv_shader_variant_info *shader_info,
2021 const struct radv_nir_compiler_options *option);
2022
2023 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
2024 struct ac_shader_binary *binary,
2025 struct ac_shader_config *config,
2026 struct radv_shader_variant_info *shader_info,
2027 struct nir_shader *const *nir,
2028 int nir_count,
2029 const struct radv_nir_compiler_options *options);
2030
2031 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
2032 const struct nir_shader *nir);
2033
2034 /* radv_shader_info.h */
2035 struct radv_shader_info;
2036
2037 void radv_nir_shader_info_pass(const struct nir_shader *nir,
2038 const struct radv_nir_compiler_options *options,
2039 struct radv_shader_info *info);
2040
2041 void radv_nir_shader_info_init(struct radv_shader_info *info);
2042
2043 struct radeon_winsys_sem;
2044
2045 uint64_t radv_get_current_time(void);
2046
2047 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2048 \
2049 static inline struct __radv_type * \
2050 __radv_type ## _from_handle(__VkType _handle) \
2051 { \
2052 return (struct __radv_type *) _handle; \
2053 } \
2054 \
2055 static inline __VkType \
2056 __radv_type ## _to_handle(struct __radv_type *_obj) \
2057 { \
2058 return (__VkType) _obj; \
2059 }
2060
2061 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2062 \
2063 static inline struct __radv_type * \
2064 __radv_type ## _from_handle(__VkType _handle) \
2065 { \
2066 return (struct __radv_type *)(uintptr_t) _handle; \
2067 } \
2068 \
2069 static inline __VkType \
2070 __radv_type ## _to_handle(struct __radv_type *_obj) \
2071 { \
2072 return (__VkType)(uintptr_t) _obj; \
2073 }
2074
2075 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2076 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2077
2078 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
2079 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
2080 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
2081 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
2082 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
2083
2084 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
2085 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
2086 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
2087 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
2088 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
2089 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
2090 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
2091 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
2092 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
2093 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
2094 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
2095 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
2096 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
2097 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
2098 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
2099 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2100 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2101 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2102 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2103 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
2104 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2105 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2106
2107 #endif /* RADV_PRIVATE_H */