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radv: replace vb_dirty with RADV_CMD_DIRTY_VERTEX_BUFFER
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
59
60 #include <llvm-c/TargetMachine.h>
61
62 /* Pre-declarations needed for WSI entrypoints */
63 struct wl_surface;
64 struct wl_display;
65 typedef struct xcb_connection_t xcb_connection_t;
66 typedef uint32_t xcb_visualid_t;
67 typedef uint32_t xcb_window_t;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "radv_entrypoints.h"
74
75 #include "wsi_common.h"
76
77 #define ATI_VENDOR_ID 0x1002
78
79 #define MAX_VBS 32
80 #define MAX_VERTEX_ATTRIBS 32
81 #define MAX_RTS 8
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
90 #define MAX_VIEWS 8
91
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
93
94 enum radv_mem_heap {
95 RADV_MEM_HEAP_VRAM,
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
97 RADV_MEM_HEAP_GTT,
98 RADV_MEM_HEAP_COUNT
99 };
100
101 enum radv_mem_type {
102 RADV_MEM_TYPE_VRAM,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
105 RADV_MEM_TYPE_GTT_CACHED,
106 RADV_MEM_TYPE_COUNT
107 };
108
109 enum radv_mem_flags_bits {
110 /* enable implicit synchronization when accessing the underlying bo */
111 RADV_MEM_IMPLICIT_SYNC = 1 << 0,
112 };
113
114 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
115
116 static inline uint32_t
117 align_u32(uint32_t v, uint32_t a)
118 {
119 assert(a != 0 && a == (a & -a));
120 return (v + a - 1) & ~(a - 1);
121 }
122
123 static inline uint32_t
124 align_u32_npot(uint32_t v, uint32_t a)
125 {
126 return (v + a - 1) / a * a;
127 }
128
129 static inline uint64_t
130 align_u64(uint64_t v, uint64_t a)
131 {
132 assert(a != 0 && a == (a & -a));
133 return (v + a - 1) & ~(a - 1);
134 }
135
136 static inline int32_t
137 align_i32(int32_t v, int32_t a)
138 {
139 assert(a != 0 && a == (a & -a));
140 return (v + a - 1) & ~(a - 1);
141 }
142
143 /** Alignment must be a power of 2. */
144 static inline bool
145 radv_is_aligned(uintmax_t n, uintmax_t a)
146 {
147 assert(a == (a & -a));
148 return (n & (a - 1)) == 0;
149 }
150
151 static inline uint32_t
152 round_up_u32(uint32_t v, uint32_t a)
153 {
154 return (v + a - 1) / a;
155 }
156
157 static inline uint64_t
158 round_up_u64(uint64_t v, uint64_t a)
159 {
160 return (v + a - 1) / a;
161 }
162
163 static inline uint32_t
164 radv_minify(uint32_t n, uint32_t levels)
165 {
166 if (unlikely(n == 0))
167 return 0;
168 else
169 return MAX2(n >> levels, 1);
170 }
171 static inline float
172 radv_clamp_f(float f, float min, float max)
173 {
174 assert(min < max);
175
176 if (f > max)
177 return max;
178 else if (f < min)
179 return min;
180 else
181 return f;
182 }
183
184 static inline bool
185 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
186 {
187 if (*inout_mask & clear_mask) {
188 *inout_mask &= ~clear_mask;
189 return true;
190 } else {
191 return false;
192 }
193 }
194
195 #define for_each_bit(b, dword) \
196 for (uint32_t __dword = (dword); \
197 (b) = __builtin_ffs(__dword) - 1, __dword; \
198 __dword &= ~(1 << (b)))
199
200 #define typed_memcpy(dest, src, count) ({ \
201 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
202 memcpy((dest), (src), (count) * sizeof(*(src))); \
203 })
204
205 /* Whenever we generate an error, pass it through this function. Useful for
206 * debugging, where we can break on it. Only call at error site, not when
207 * propagating errors. Might be useful to plug in a stack trace here.
208 */
209
210 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
211
212 #ifdef DEBUG
213 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
214 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
215 #else
216 #define vk_error(error) error
217 #define vk_errorf(error, format, ...) error
218 #endif
219
220 void __radv_finishme(const char *file, int line, const char *format, ...)
221 radv_printflike(3, 4);
222 void radv_loge(const char *format, ...) radv_printflike(1, 2);
223 void radv_loge_v(const char *format, va_list va);
224
225 /**
226 * Print a FINISHME message, including its source location.
227 */
228 #define radv_finishme(format, ...) \
229 do { \
230 static bool reported = false; \
231 if (!reported) { \
232 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
233 reported = true; \
234 } \
235 } while (0)
236
237 /* A non-fatal assert. Useful for debugging. */
238 #ifdef DEBUG
239 #define radv_assert(x) ({ \
240 if (unlikely(!(x))) \
241 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
242 })
243 #else
244 #define radv_assert(x)
245 #endif
246
247 #define stub_return(v) \
248 do { \
249 radv_finishme("stub %s", __func__); \
250 return (v); \
251 } while (0)
252
253 #define stub() \
254 do { \
255 radv_finishme("stub %s", __func__); \
256 return; \
257 } while (0)
258
259 void *radv_lookup_entrypoint(const char *name);
260
261 struct radv_physical_device {
262 VK_LOADER_DATA _loader_data;
263
264 struct radv_instance * instance;
265
266 struct radeon_winsys *ws;
267 struct radeon_info rad_info;
268 char path[20];
269 const char * name;
270 uint8_t driver_uuid[VK_UUID_SIZE];
271 uint8_t device_uuid[VK_UUID_SIZE];
272 uint8_t cache_uuid[VK_UUID_SIZE];
273
274 int local_fd;
275 struct wsi_device wsi_device;
276
277 bool has_rbplus; /* if RB+ register exist */
278 bool rbplus_allowed; /* if RB+ is allowed */
279 bool has_clear_state;
280
281 /* This is the drivers on-disk cache used as a fallback as opposed to
282 * the pipeline cache defined by apps.
283 */
284 struct disk_cache * disk_cache;
285
286 VkPhysicalDeviceMemoryProperties memory_properties;
287 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
288 };
289
290 struct radv_instance {
291 VK_LOADER_DATA _loader_data;
292
293 VkAllocationCallbacks alloc;
294
295 uint32_t apiVersion;
296 int physicalDeviceCount;
297 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
298
299 uint64_t debug_flags;
300 uint64_t perftest_flags;
301 };
302
303 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
304 void radv_finish_wsi(struct radv_physical_device *physical_device);
305
306 bool radv_instance_extension_supported(const char *name);
307 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
308 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
309 const char *name);
310
311 struct cache_entry;
312
313 struct radv_pipeline_cache {
314 struct radv_device * device;
315 pthread_mutex_t mutex;
316
317 uint32_t total_size;
318 uint32_t table_size;
319 uint32_t kernel_count;
320 struct cache_entry ** hash_table;
321 bool modified;
322
323 VkAllocationCallbacks alloc;
324 };
325
326 struct radv_pipeline_key {
327 uint32_t instance_rate_inputs;
328 unsigned tess_input_vertices;
329 uint32_t col_format;
330 uint32_t is_int8;
331 uint32_t is_int10;
332 uint32_t multisample : 1;
333 uint32_t has_multiview_view_index : 1;
334 };
335
336 void
337 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
338 struct radv_device *device);
339 void
340 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
341 void
342 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
343 const void *data, size_t size);
344
345 struct radv_shader_variant;
346
347 bool
348 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
349 struct radv_pipeline_cache *cache,
350 const unsigned char *sha1,
351 struct radv_shader_variant **variants);
352
353 void
354 radv_pipeline_cache_insert_shaders(struct radv_device *device,
355 struct radv_pipeline_cache *cache,
356 const unsigned char *sha1,
357 struct radv_shader_variant **variants,
358 const void *const *codes,
359 const unsigned *code_sizes);
360
361 struct radv_meta_state {
362 VkAllocationCallbacks alloc;
363
364 struct radv_pipeline_cache cache;
365
366 /**
367 * Use array element `i` for images with `2^i` samples.
368 */
369 struct {
370 VkRenderPass render_pass[NUM_META_FS_KEYS];
371 VkPipeline color_pipelines[NUM_META_FS_KEYS];
372
373 VkRenderPass depthstencil_rp;
374 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
375 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
376 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
377 } clear[1 + MAX_SAMPLES_LOG2];
378
379 VkPipelineLayout clear_color_p_layout;
380 VkPipelineLayout clear_depth_p_layout;
381 struct {
382 VkRenderPass render_pass[NUM_META_FS_KEYS];
383
384 /** Pipeline that blits from a 1D image. */
385 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
386
387 /** Pipeline that blits from a 2D image. */
388 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
389
390 /** Pipeline that blits from a 3D image. */
391 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
392
393 VkRenderPass depth_only_rp;
394 VkPipeline depth_only_1d_pipeline;
395 VkPipeline depth_only_2d_pipeline;
396 VkPipeline depth_only_3d_pipeline;
397
398 VkRenderPass stencil_only_rp;
399 VkPipeline stencil_only_1d_pipeline;
400 VkPipeline stencil_only_2d_pipeline;
401 VkPipeline stencil_only_3d_pipeline;
402 VkPipelineLayout pipeline_layout;
403 VkDescriptorSetLayout ds_layout;
404 } blit;
405
406 struct {
407 VkRenderPass render_passes[NUM_META_FS_KEYS];
408
409 VkPipelineLayout p_layouts[2];
410 VkDescriptorSetLayout ds_layouts[2];
411 VkPipeline pipelines[2][NUM_META_FS_KEYS];
412
413 VkRenderPass depth_only_rp;
414 VkPipeline depth_only_pipeline[2];
415
416 VkRenderPass stencil_only_rp;
417 VkPipeline stencil_only_pipeline[2];
418 } blit2d;
419
420 struct {
421 VkPipelineLayout img_p_layout;
422 VkDescriptorSetLayout img_ds_layout;
423 VkPipeline pipeline;
424 } itob;
425 struct {
426 VkPipelineLayout img_p_layout;
427 VkDescriptorSetLayout img_ds_layout;
428 VkPipeline pipeline;
429 } btoi;
430 struct {
431 VkPipelineLayout img_p_layout;
432 VkDescriptorSetLayout img_ds_layout;
433 VkPipeline pipeline;
434 } itoi;
435 struct {
436 VkPipelineLayout img_p_layout;
437 VkDescriptorSetLayout img_ds_layout;
438 VkPipeline pipeline;
439 } cleari;
440
441 struct {
442 VkPipeline pipeline;
443 VkRenderPass pass;
444 } resolve;
445
446 struct {
447 VkDescriptorSetLayout ds_layout;
448 VkPipelineLayout p_layout;
449 struct {
450 VkPipeline pipeline;
451 VkPipeline i_pipeline;
452 VkPipeline srgb_pipeline;
453 } rc[MAX_SAMPLES_LOG2];
454 } resolve_compute;
455
456 struct {
457 VkDescriptorSetLayout ds_layout;
458 VkPipelineLayout p_layout;
459
460 struct {
461 VkRenderPass render_pass[NUM_META_FS_KEYS];
462 VkPipeline pipeline[NUM_META_FS_KEYS];
463 } rc[MAX_SAMPLES_LOG2];
464 } resolve_fragment;
465
466 struct {
467 VkPipeline decompress_pipeline;
468 VkPipeline resummarize_pipeline;
469 VkRenderPass pass;
470 } depth_decomp[1 + MAX_SAMPLES_LOG2];
471
472 struct {
473 VkPipeline cmask_eliminate_pipeline;
474 VkPipeline fmask_decompress_pipeline;
475 VkRenderPass pass;
476 } fast_clear_flush;
477
478 struct {
479 VkPipelineLayout fill_p_layout;
480 VkPipelineLayout copy_p_layout;
481 VkDescriptorSetLayout fill_ds_layout;
482 VkDescriptorSetLayout copy_ds_layout;
483 VkPipeline fill_pipeline;
484 VkPipeline copy_pipeline;
485 } buffer;
486
487 struct {
488 VkDescriptorSetLayout ds_layout;
489 VkPipelineLayout p_layout;
490 VkPipeline occlusion_query_pipeline;
491 VkPipeline pipeline_statistics_query_pipeline;
492 } query;
493 };
494
495 /* queue types */
496 #define RADV_QUEUE_GENERAL 0
497 #define RADV_QUEUE_COMPUTE 1
498 #define RADV_QUEUE_TRANSFER 2
499
500 #define RADV_MAX_QUEUE_FAMILIES 3
501
502 enum ring_type radv_queue_family_to_ring(int f);
503
504 struct radv_queue {
505 VK_LOADER_DATA _loader_data;
506 struct radv_device * device;
507 struct radeon_winsys_ctx *hw_ctx;
508 enum radeon_ctx_priority priority;
509 uint32_t queue_family_index;
510 int queue_idx;
511
512 uint32_t scratch_size;
513 uint32_t compute_scratch_size;
514 uint32_t esgs_ring_size;
515 uint32_t gsvs_ring_size;
516 bool has_tess_rings;
517 bool has_sample_positions;
518
519 struct radeon_winsys_bo *scratch_bo;
520 struct radeon_winsys_bo *descriptor_bo;
521 struct radeon_winsys_bo *compute_scratch_bo;
522 struct radeon_winsys_bo *esgs_ring_bo;
523 struct radeon_winsys_bo *gsvs_ring_bo;
524 struct radeon_winsys_bo *tess_factor_ring_bo;
525 struct radeon_winsys_bo *tess_offchip_ring_bo;
526 struct radeon_winsys_cs *initial_preamble_cs;
527 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
528 struct radeon_winsys_cs *continue_preamble_cs;
529 };
530
531 struct radv_device {
532 VK_LOADER_DATA _loader_data;
533
534 VkAllocationCallbacks alloc;
535
536 struct radv_instance * instance;
537 struct radeon_winsys *ws;
538
539 struct radv_meta_state meta_state;
540
541 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
542 int queue_count[RADV_MAX_QUEUE_FAMILIES];
543 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
544
545 bool llvm_supports_spill;
546 bool has_distributed_tess;
547 bool dfsm_allowed;
548 uint32_t tess_offchip_block_dw_size;
549 uint32_t scratch_waves;
550
551 uint32_t gs_table_depth;
552
553 /* MSAA sample locations.
554 * The first index is the sample index.
555 * The second index is the coordinate: X, Y. */
556 float sample_locations_1x[1][2];
557 float sample_locations_2x[2][2];
558 float sample_locations_4x[4][2];
559 float sample_locations_8x[8][2];
560 float sample_locations_16x[16][2];
561
562 /* CIK and later */
563 uint32_t gfx_init_size_dw;
564 struct radeon_winsys_bo *gfx_init;
565
566 struct radeon_winsys_bo *trace_bo;
567 uint32_t *trace_id_ptr;
568
569 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
570 bool keep_shader_info;
571
572 struct radv_physical_device *physical_device;
573
574 /* Backup in-memory cache to be used if the app doesn't provide one */
575 struct radv_pipeline_cache * mem_cache;
576
577 /*
578 * use different counters so MSAA MRTs get consecutive surface indices,
579 * even if MASK is allocated in between.
580 */
581 uint32_t image_mrt_offset_counter;
582 uint32_t fmask_mrt_offset_counter;
583 struct list_head shader_slabs;
584 mtx_t shader_slab_mutex;
585
586 /* For detecting VM faults reported by dmesg. */
587 uint64_t dmesg_timestamp;
588 };
589
590 struct radv_device_memory {
591 struct radeon_winsys_bo *bo;
592 /* for dedicated allocations */
593 struct radv_image *image;
594 struct radv_buffer *buffer;
595 uint32_t type_index;
596 VkDeviceSize map_size;
597 void * map;
598 };
599
600
601 struct radv_descriptor_range {
602 uint64_t va;
603 uint32_t size;
604 };
605
606 struct radv_descriptor_set {
607 const struct radv_descriptor_set_layout *layout;
608 uint32_t size;
609
610 struct radeon_winsys_bo *bo;
611 uint64_t va;
612 uint32_t *mapped_ptr;
613 struct radv_descriptor_range *dynamic_descriptors;
614
615 struct radeon_winsys_bo *descriptors[0];
616 };
617
618 struct radv_push_descriptor_set
619 {
620 struct radv_descriptor_set set;
621 uint32_t capacity;
622 };
623
624 struct radv_descriptor_pool_entry {
625 uint32_t offset;
626 uint32_t size;
627 struct radv_descriptor_set *set;
628 };
629
630 struct radv_descriptor_pool {
631 struct radeon_winsys_bo *bo;
632 uint8_t *mapped_ptr;
633 uint64_t current_offset;
634 uint64_t size;
635
636 uint8_t *host_memory_base;
637 uint8_t *host_memory_ptr;
638 uint8_t *host_memory_end;
639
640 uint32_t entry_count;
641 uint32_t max_entry_count;
642 struct radv_descriptor_pool_entry entries[0];
643 };
644
645 struct radv_descriptor_update_template_entry {
646 VkDescriptorType descriptor_type;
647
648 /* The number of descriptors to update */
649 uint32_t descriptor_count;
650
651 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
652 uint32_t dst_offset;
653
654 /* In dwords. Not valid/used for dynamic descriptors */
655 uint32_t dst_stride;
656
657 uint32_t buffer_offset;
658
659 /* Only valid for combined image samplers and samplers */
660 uint16_t has_sampler;
661
662 /* In bytes */
663 size_t src_offset;
664 size_t src_stride;
665
666 /* For push descriptors */
667 const uint32_t *immutable_samplers;
668 };
669
670 struct radv_descriptor_update_template {
671 uint32_t entry_count;
672 struct radv_descriptor_update_template_entry entry[0];
673 };
674
675 struct radv_buffer {
676 struct radv_device * device;
677 VkDeviceSize size;
678
679 VkBufferUsageFlags usage;
680 VkBufferCreateFlags flags;
681
682 /* Set when bound */
683 struct radeon_winsys_bo * bo;
684 VkDeviceSize offset;
685
686 bool shareable;
687 };
688
689
690 enum radv_cmd_dirty_bits {
691 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
692 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
693 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
694 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
695 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
696 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
697 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
698 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
699 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
700 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
701 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
702 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
703 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 11,
704 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 12,
705 };
706
707 enum radv_cmd_flush_bits {
708 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
709 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
710 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
711 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
712 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
713 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
714 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
715 /* Same as above, but only writes back and doesn't invalidate */
716 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
717 /* Framebuffer caches */
718 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
719 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
720 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
721 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
722 /* Engine synchronization. */
723 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
724 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
725 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
726 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
727
728 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
729 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
730 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
731 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
732 };
733
734 struct radv_vertex_binding {
735 struct radv_buffer * buffer;
736 VkDeviceSize offset;
737 };
738
739 struct radv_viewport_state {
740 uint32_t count;
741 VkViewport viewports[MAX_VIEWPORTS];
742 };
743
744 struct radv_scissor_state {
745 uint32_t count;
746 VkRect2D scissors[MAX_SCISSORS];
747 };
748
749 struct radv_dynamic_state {
750 /**
751 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
752 * Defines the set of saved dynamic state.
753 */
754 uint32_t mask;
755
756 struct radv_viewport_state viewport;
757
758 struct radv_scissor_state scissor;
759
760 float line_width;
761
762 struct {
763 float bias;
764 float clamp;
765 float slope;
766 } depth_bias;
767
768 float blend_constants[4];
769
770 struct {
771 float min;
772 float max;
773 } depth_bounds;
774
775 struct {
776 uint32_t front;
777 uint32_t back;
778 } stencil_compare_mask;
779
780 struct {
781 uint32_t front;
782 uint32_t back;
783 } stencil_write_mask;
784
785 struct {
786 uint32_t front;
787 uint32_t back;
788 } stencil_reference;
789 };
790
791 extern const struct radv_dynamic_state default_dynamic_state;
792
793 const char *
794 radv_get_debug_option_name(int id);
795
796 const char *
797 radv_get_perftest_option_name(int id);
798
799 /**
800 * Attachment state when recording a renderpass instance.
801 *
802 * The clear value is valid only if there exists a pending clear.
803 */
804 struct radv_attachment_state {
805 VkImageAspectFlags pending_clear_aspects;
806 uint32_t cleared_views;
807 VkClearValue clear_value;
808 VkImageLayout current_layout;
809 };
810
811 struct radv_cmd_state {
812 /* Vertex descriptors */
813 bool vb_prefetch_dirty;
814 uint64_t vb_va;
815 unsigned vb_size;
816
817 bool push_descriptors_dirty;
818 bool predicating;
819 uint32_t dirty;
820
821 struct radv_pipeline * pipeline;
822 struct radv_pipeline * emitted_pipeline;
823 struct radv_pipeline * compute_pipeline;
824 struct radv_pipeline * emitted_compute_pipeline;
825 struct radv_framebuffer * framebuffer;
826 struct radv_render_pass * pass;
827 const struct radv_subpass * subpass;
828 struct radv_dynamic_state dynamic;
829 struct radv_attachment_state * attachments;
830 VkRect2D render_area;
831
832 /* Index buffer */
833 struct radv_buffer *index_buffer;
834 uint64_t index_offset;
835 uint32_t index_type;
836 uint32_t max_index_count;
837 uint64_t index_va;
838
839 int32_t last_primitive_reset_en;
840 uint32_t last_primitive_reset_index;
841 enum radv_cmd_flush_bits flush_bits;
842 unsigned active_occlusion_queries;
843 float offset_scale;
844 uint32_t descriptors_dirty;
845 uint32_t valid_descriptors;
846 uint32_t trace_id;
847 uint32_t last_ia_multi_vgt_param;
848 };
849
850 struct radv_cmd_pool {
851 VkAllocationCallbacks alloc;
852 struct list_head cmd_buffers;
853 struct list_head free_cmd_buffers;
854 uint32_t queue_family_index;
855 };
856
857 struct radv_cmd_buffer_upload {
858 uint8_t *map;
859 unsigned offset;
860 uint64_t size;
861 struct radeon_winsys_bo *upload_bo;
862 struct list_head list;
863 };
864
865 struct radv_cmd_buffer {
866 VK_LOADER_DATA _loader_data;
867
868 struct radv_device * device;
869
870 struct radv_cmd_pool * pool;
871 struct list_head pool_link;
872
873 VkCommandBufferUsageFlags usage_flags;
874 VkCommandBufferLevel level;
875 struct radeon_winsys_cs *cs;
876 struct radv_cmd_state state;
877 struct radv_vertex_binding vertex_bindings[MAX_VBS];
878 uint32_t queue_family_index;
879
880 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
881 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
882 VkShaderStageFlags push_constant_stages;
883 struct radv_push_descriptor_set push_descriptors;
884 struct radv_descriptor_set meta_push_descriptors;
885 struct radv_descriptor_set *descriptors[MAX_SETS];
886
887 struct radv_cmd_buffer_upload upload;
888
889 uint32_t scratch_size_needed;
890 uint32_t compute_scratch_size_needed;
891 uint32_t esgs_ring_size_needed;
892 uint32_t gsvs_ring_size_needed;
893 bool tess_rings_needed;
894 bool sample_positions_needed;
895
896 VkResult record_result;
897
898 int ring_offsets_idx; /* just used for verification */
899 uint32_t gfx9_fence_offset;
900 struct radeon_winsys_bo *gfx9_fence_bo;
901 uint32_t gfx9_fence_idx;
902 };
903
904 struct radv_image;
905
906 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
907
908 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
909 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
910
911 void cik_create_gfx_config(struct radv_device *device);
912
913 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
914 int count, const VkViewport *viewports);
915 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
916 int count, const VkRect2D *scissors,
917 const VkViewport *viewports, bool can_use_guardband);
918 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
919 bool instanced_draw, bool indirect_draw,
920 uint32_t draw_vertex_count);
921 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
922 bool predicated,
923 enum chip_class chip_class,
924 bool is_mec,
925 unsigned event, unsigned event_flags,
926 unsigned data_sel,
927 uint64_t va,
928 uint32_t old_fence,
929 uint32_t new_fence);
930
931 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
932 bool predicated,
933 uint64_t va, uint32_t ref,
934 uint32_t mask);
935 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
936 bool predicated,
937 enum chip_class chip_class,
938 uint32_t *fence_ptr, uint64_t va,
939 bool is_mec,
940 enum radv_cmd_flush_bits flush_bits);
941 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
942 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
943 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
944 uint64_t src_va, uint64_t dest_va,
945 uint64_t size);
946 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
947 unsigned size);
948 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
949 uint64_t size, unsigned value);
950 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
951 bool
952 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
953 unsigned size,
954 unsigned alignment,
955 unsigned *out_offset,
956 void **ptr);
957 void
958 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
959 const struct radv_subpass *subpass,
960 bool transitions);
961 bool
962 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
963 unsigned size, unsigned alignmnet,
964 const void *data, unsigned *out_offset);
965
966 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
967 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
968 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
969 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
970 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
971 unsigned radv_cayman_get_maxdist(int log_samples);
972 void radv_device_init_msaa(struct radv_device *device);
973 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
974 struct radv_image *image,
975 VkClearDepthStencilValue ds_clear_value,
976 VkImageAspectFlags aspects);
977 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
978 struct radv_image *image,
979 int idx,
980 uint32_t color_values[2]);
981 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
982 struct radv_image *image,
983 bool value);
984 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
985 struct radeon_winsys_bo *bo,
986 uint64_t offset, uint64_t size, uint32_t value);
987 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
988 bool radv_get_memory_fd(struct radv_device *device,
989 struct radv_device_memory *memory,
990 int *pFD);
991 VkResult radv_alloc_memory(VkDevice _device,
992 const VkMemoryAllocateInfo* pAllocateInfo,
993 const VkAllocationCallbacks* pAllocator,
994 enum radv_mem_flags_bits flags,
995 VkDeviceMemory* pMem);
996
997 /*
998 * Takes x,y,z as exact numbers of invocations, instead of blocks.
999 *
1000 * Limitations: Can't call normal dispatch functions without binding or rebinding
1001 * the compute pipeline.
1002 */
1003 void radv_unaligned_dispatch(
1004 struct radv_cmd_buffer *cmd_buffer,
1005 uint32_t x,
1006 uint32_t y,
1007 uint32_t z);
1008
1009 struct radv_event {
1010 struct radeon_winsys_bo *bo;
1011 uint64_t *map;
1012 };
1013
1014 struct radv_shader_module;
1015
1016 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1017 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1018 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1019 void
1020 radv_hash_shaders(unsigned char *hash,
1021 const VkPipelineShaderStageCreateInfo **stages,
1022 const struct radv_pipeline_layout *layout,
1023 const struct radv_pipeline_key *key,
1024 uint32_t flags);
1025
1026 static inline gl_shader_stage
1027 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1028 {
1029 assert(__builtin_popcount(vk_stage) == 1);
1030 return ffs(vk_stage) - 1;
1031 }
1032
1033 static inline VkShaderStageFlagBits
1034 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1035 {
1036 return (1 << mesa_stage);
1037 }
1038
1039 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1040
1041 #define radv_foreach_stage(stage, stage_bits) \
1042 for (gl_shader_stage stage, \
1043 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1044 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1045 __tmp &= ~(1 << (stage)))
1046
1047 struct radv_depth_stencil_state {
1048 uint32_t db_depth_control;
1049 uint32_t db_stencil_control;
1050 uint32_t db_render_control;
1051 uint32_t db_render_override2;
1052 };
1053
1054 struct radv_blend_state {
1055 uint32_t cb_color_control;
1056 uint32_t cb_target_mask;
1057 uint32_t sx_mrt_blend_opt[8];
1058 uint32_t cb_blend_control[8];
1059
1060 uint32_t spi_shader_col_format;
1061 uint32_t cb_shader_mask;
1062 uint32_t db_alpha_to_mask;
1063 };
1064
1065 unsigned radv_format_meta_fs_key(VkFormat format);
1066
1067 struct radv_raster_state {
1068 uint32_t pa_cl_clip_cntl;
1069 uint32_t spi_interp_control;
1070 uint32_t pa_su_vtx_cntl;
1071 uint32_t pa_su_sc_mode_cntl;
1072 };
1073
1074 struct radv_multisample_state {
1075 uint32_t db_eqaa;
1076 uint32_t pa_sc_line_cntl;
1077 uint32_t pa_sc_mode_cntl_0;
1078 uint32_t pa_sc_mode_cntl_1;
1079 uint32_t pa_sc_aa_config;
1080 uint32_t pa_sc_aa_mask[2];
1081 unsigned num_samples;
1082 };
1083
1084 struct radv_prim_vertex_count {
1085 uint8_t min;
1086 uint8_t incr;
1087 };
1088
1089 struct radv_tessellation_state {
1090 uint32_t ls_hs_config;
1091 uint32_t tcs_in_layout;
1092 uint32_t tcs_out_layout;
1093 uint32_t tcs_out_offsets;
1094 uint32_t offchip_layout;
1095 unsigned num_patches;
1096 unsigned lds_size;
1097 unsigned num_tcs_input_cp;
1098 uint32_t tf_param;
1099 };
1100
1101 struct radv_gs_state {
1102 uint32_t vgt_gs_onchip_cntl;
1103 uint32_t vgt_gs_max_prims_per_subgroup;
1104 uint32_t vgt_esgs_ring_itemsize;
1105 uint32_t lds_size;
1106 };
1107
1108 struct radv_vertex_elements_info {
1109 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1110 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1111 uint32_t binding[MAX_VERTEX_ATTRIBS];
1112 uint32_t offset[MAX_VERTEX_ATTRIBS];
1113 uint32_t count;
1114 };
1115
1116 struct radv_vs_state {
1117 uint32_t pa_cl_vs_out_cntl;
1118 uint32_t spi_shader_pos_format;
1119 uint32_t spi_vs_out_config;
1120 uint32_t vgt_reuse_off;
1121 };
1122
1123 #define SI_GS_PER_ES 128
1124
1125 struct radv_pipeline {
1126 struct radv_device * device;
1127 struct radv_dynamic_state dynamic_state;
1128
1129 struct radv_pipeline_layout * layout;
1130
1131 bool needs_data_cache;
1132 bool need_indirect_descriptor_sets;
1133 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1134 struct radv_shader_variant *gs_copy_shader;
1135 VkShaderStageFlags active_stages;
1136
1137 struct radv_vertex_elements_info vertex_elements;
1138
1139 uint32_t binding_stride[MAX_VBS];
1140
1141 uint32_t user_data_0[MESA_SHADER_STAGES];
1142 union {
1143 struct {
1144 struct radv_blend_state blend;
1145 struct radv_depth_stencil_state ds;
1146 struct radv_raster_state raster;
1147 struct radv_multisample_state ms;
1148 struct radv_tessellation_state tess;
1149 struct radv_gs_state gs;
1150 struct radv_vs_state vs;
1151 uint32_t db_shader_control;
1152 uint32_t shader_z_format;
1153 unsigned prim;
1154 unsigned gs_out;
1155 uint32_t vgt_gs_mode;
1156 bool vgt_primitiveid_en;
1157 bool prim_restart_enable;
1158 bool partial_es_wave;
1159 uint8_t primgroup_size;
1160 unsigned esgs_ring_size;
1161 unsigned gsvs_ring_size;
1162 uint32_t ps_input_cntl[32];
1163 uint32_t ps_input_cntl_num;
1164 uint32_t vgt_shader_stages_en;
1165 uint32_t vtx_base_sgpr;
1166 uint32_t base_ia_multi_vgt_param;
1167 bool wd_switch_on_eop;
1168 bool ia_switch_on_eoi;
1169 bool partial_vs_wave;
1170 uint8_t vtx_emit_num;
1171 uint32_t vtx_reuse_depth;
1172 struct radv_prim_vertex_count prim_vertex_count;
1173 bool can_use_guardband;
1174 } graphics;
1175 };
1176
1177 unsigned max_waves;
1178 unsigned scratch_bytes_per_wave;
1179 };
1180
1181 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1182 {
1183 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1184 }
1185
1186 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1187 {
1188 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1189 }
1190
1191 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1192 gl_shader_stage stage,
1193 int idx);
1194
1195 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1196
1197 struct radv_graphics_pipeline_create_info {
1198 bool use_rectlist;
1199 bool db_depth_clear;
1200 bool db_stencil_clear;
1201 bool db_depth_disable_expclear;
1202 bool db_stencil_disable_expclear;
1203 bool db_flush_depth_inplace;
1204 bool db_flush_stencil_inplace;
1205 bool db_resummarize;
1206 uint32_t custom_blend_mode;
1207 };
1208
1209 VkResult
1210 radv_graphics_pipeline_create(VkDevice device,
1211 VkPipelineCache cache,
1212 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1213 const struct radv_graphics_pipeline_create_info *extra,
1214 const VkAllocationCallbacks *alloc,
1215 VkPipeline *pPipeline);
1216
1217 struct vk_format_description;
1218 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1219 int first_non_void);
1220 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1221 int first_non_void);
1222 uint32_t radv_translate_colorformat(VkFormat format);
1223 uint32_t radv_translate_color_numformat(VkFormat format,
1224 const struct vk_format_description *desc,
1225 int first_non_void);
1226 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1227 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1228 uint32_t radv_translate_dbformat(VkFormat format);
1229 uint32_t radv_translate_tex_dataformat(VkFormat format,
1230 const struct vk_format_description *desc,
1231 int first_non_void);
1232 uint32_t radv_translate_tex_numformat(VkFormat format,
1233 const struct vk_format_description *desc,
1234 int first_non_void);
1235 bool radv_format_pack_clear_color(VkFormat format,
1236 uint32_t clear_vals[2],
1237 VkClearColorValue *value);
1238 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1239 bool radv_dcc_formats_compatible(VkFormat format1,
1240 VkFormat format2);
1241
1242 struct radv_fmask_info {
1243 uint64_t offset;
1244 uint64_t size;
1245 unsigned alignment;
1246 unsigned pitch_in_pixels;
1247 unsigned bank_height;
1248 unsigned slice_tile_max;
1249 unsigned tile_mode_index;
1250 unsigned tile_swizzle;
1251 };
1252
1253 struct radv_cmask_info {
1254 uint64_t offset;
1255 uint64_t size;
1256 unsigned alignment;
1257 unsigned slice_tile_max;
1258 unsigned base_address_reg;
1259 };
1260
1261 struct radv_image {
1262 VkImageType type;
1263 /* The original VkFormat provided by the client. This may not match any
1264 * of the actual surface formats.
1265 */
1266 VkFormat vk_format;
1267 VkImageAspectFlags aspects;
1268 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1269 struct ac_surf_info info;
1270 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1271 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1272
1273 VkDeviceSize size;
1274 uint32_t alignment;
1275
1276 unsigned queue_family_mask;
1277 bool exclusive;
1278 bool shareable;
1279
1280 /* Set when bound */
1281 struct radeon_winsys_bo *bo;
1282 VkDeviceSize offset;
1283 uint64_t dcc_offset;
1284 uint64_t htile_offset;
1285 bool tc_compatible_htile;
1286 struct radeon_surf surface;
1287
1288 struct radv_fmask_info fmask;
1289 struct radv_cmask_info cmask;
1290 uint64_t clear_value_offset;
1291 uint64_t dcc_pred_offset;
1292 };
1293
1294 /* Whether the image has a htile that is known consistent with the contents of
1295 * the image. */
1296 bool radv_layout_has_htile(const struct radv_image *image,
1297 VkImageLayout layout,
1298 unsigned queue_mask);
1299
1300 /* Whether the image has a htile that is known consistent with the contents of
1301 * the image and is allowed to be in compressed form.
1302 *
1303 * If this is false reads that don't use the htile should be able to return
1304 * correct results.
1305 */
1306 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1307 VkImageLayout layout,
1308 unsigned queue_mask);
1309
1310 bool radv_layout_can_fast_clear(const struct radv_image *image,
1311 VkImageLayout layout,
1312 unsigned queue_mask);
1313
1314 static inline bool
1315 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1316 {
1317 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1318 }
1319
1320 static inline bool
1321 radv_htile_enabled(const struct radv_image *image, unsigned level)
1322 {
1323 return image->surface.htile_size && level == 0;
1324 }
1325
1326 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1327
1328 static inline uint32_t
1329 radv_get_layerCount(const struct radv_image *image,
1330 const VkImageSubresourceRange *range)
1331 {
1332 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1333 image->info.array_size - range->baseArrayLayer : range->layerCount;
1334 }
1335
1336 static inline uint32_t
1337 radv_get_levelCount(const struct radv_image *image,
1338 const VkImageSubresourceRange *range)
1339 {
1340 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1341 image->info.levels - range->baseMipLevel : range->levelCount;
1342 }
1343
1344 struct radeon_bo_metadata;
1345 void
1346 radv_init_metadata(struct radv_device *device,
1347 struct radv_image *image,
1348 struct radeon_bo_metadata *metadata);
1349
1350 struct radv_image_view {
1351 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1352 struct radeon_winsys_bo *bo;
1353
1354 VkImageViewType type;
1355 VkImageAspectFlags aspect_mask;
1356 VkFormat vk_format;
1357 uint32_t base_layer;
1358 uint32_t layer_count;
1359 uint32_t base_mip;
1360 uint32_t level_count;
1361 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1362
1363 uint32_t descriptor[8];
1364 uint32_t fmask_descriptor[8];
1365
1366 /* Descriptor for use as a storage image as opposed to a sampled image.
1367 * This has a few differences for cube maps (e.g. type).
1368 */
1369 uint32_t storage_descriptor[8];
1370 uint32_t storage_fmask_descriptor[8];
1371 };
1372
1373 struct radv_image_create_info {
1374 const VkImageCreateInfo *vk_info;
1375 bool scanout;
1376 };
1377
1378 VkResult radv_image_create(VkDevice _device,
1379 const struct radv_image_create_info *info,
1380 const VkAllocationCallbacks* alloc,
1381 VkImage *pImage);
1382
1383 void radv_image_view_init(struct radv_image_view *view,
1384 struct radv_device *device,
1385 const VkImageViewCreateInfo* pCreateInfo);
1386
1387 struct radv_buffer_view {
1388 struct radeon_winsys_bo *bo;
1389 VkFormat vk_format;
1390 uint64_t range; /**< VkBufferViewCreateInfo::range */
1391 uint32_t state[4];
1392 };
1393 void radv_buffer_view_init(struct radv_buffer_view *view,
1394 struct radv_device *device,
1395 const VkBufferViewCreateInfo* pCreateInfo);
1396
1397 static inline struct VkExtent3D
1398 radv_sanitize_image_extent(const VkImageType imageType,
1399 const struct VkExtent3D imageExtent)
1400 {
1401 switch (imageType) {
1402 case VK_IMAGE_TYPE_1D:
1403 return (VkExtent3D) { imageExtent.width, 1, 1 };
1404 case VK_IMAGE_TYPE_2D:
1405 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1406 case VK_IMAGE_TYPE_3D:
1407 return imageExtent;
1408 default:
1409 unreachable("invalid image type");
1410 }
1411 }
1412
1413 static inline struct VkOffset3D
1414 radv_sanitize_image_offset(const VkImageType imageType,
1415 const struct VkOffset3D imageOffset)
1416 {
1417 switch (imageType) {
1418 case VK_IMAGE_TYPE_1D:
1419 return (VkOffset3D) { imageOffset.x, 0, 0 };
1420 case VK_IMAGE_TYPE_2D:
1421 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1422 case VK_IMAGE_TYPE_3D:
1423 return imageOffset;
1424 default:
1425 unreachable("invalid image type");
1426 }
1427 }
1428
1429 static inline bool
1430 radv_image_extent_compare(const struct radv_image *image,
1431 const VkExtent3D *extent)
1432 {
1433 if (extent->width != image->info.width ||
1434 extent->height != image->info.height ||
1435 extent->depth != image->info.depth)
1436 return false;
1437 return true;
1438 }
1439
1440 struct radv_sampler {
1441 uint32_t state[4];
1442 };
1443
1444 struct radv_color_buffer_info {
1445 uint64_t cb_color_base;
1446 uint64_t cb_color_cmask;
1447 uint64_t cb_color_fmask;
1448 uint64_t cb_dcc_base;
1449 uint32_t cb_color_pitch;
1450 uint32_t cb_color_slice;
1451 uint32_t cb_color_view;
1452 uint32_t cb_color_info;
1453 uint32_t cb_color_attrib;
1454 uint32_t cb_color_attrib2;
1455 uint32_t cb_dcc_control;
1456 uint32_t cb_color_cmask_slice;
1457 uint32_t cb_color_fmask_slice;
1458 uint32_t cb_clear_value0;
1459 uint32_t cb_clear_value1;
1460 uint32_t micro_tile_mode;
1461 uint32_t gfx9_epitch;
1462 };
1463
1464 struct radv_ds_buffer_info {
1465 uint64_t db_z_read_base;
1466 uint64_t db_stencil_read_base;
1467 uint64_t db_z_write_base;
1468 uint64_t db_stencil_write_base;
1469 uint64_t db_htile_data_base;
1470 uint32_t db_depth_info;
1471 uint32_t db_z_info;
1472 uint32_t db_stencil_info;
1473 uint32_t db_depth_view;
1474 uint32_t db_depth_size;
1475 uint32_t db_depth_slice;
1476 uint32_t db_htile_surface;
1477 uint32_t pa_su_poly_offset_db_fmt_cntl;
1478 uint32_t db_z_info2;
1479 uint32_t db_stencil_info2;
1480 float offset_scale;
1481 };
1482
1483 struct radv_attachment_info {
1484 union {
1485 struct radv_color_buffer_info cb;
1486 struct radv_ds_buffer_info ds;
1487 };
1488 struct radv_image_view *attachment;
1489 };
1490
1491 struct radv_framebuffer {
1492 uint32_t width;
1493 uint32_t height;
1494 uint32_t layers;
1495
1496 uint32_t attachment_count;
1497 struct radv_attachment_info attachments[0];
1498 };
1499
1500 struct radv_subpass_barrier {
1501 VkPipelineStageFlags src_stage_mask;
1502 VkAccessFlags src_access_mask;
1503 VkAccessFlags dst_access_mask;
1504 };
1505
1506 struct radv_subpass {
1507 uint32_t input_count;
1508 uint32_t color_count;
1509 VkAttachmentReference * input_attachments;
1510 VkAttachmentReference * color_attachments;
1511 VkAttachmentReference * resolve_attachments;
1512 VkAttachmentReference depth_stencil_attachment;
1513
1514 /** Subpass has at least one resolve attachment */
1515 bool has_resolve;
1516
1517 struct radv_subpass_barrier start_barrier;
1518
1519 uint32_t view_mask;
1520 };
1521
1522 struct radv_render_pass_attachment {
1523 VkFormat format;
1524 uint32_t samples;
1525 VkAttachmentLoadOp load_op;
1526 VkAttachmentLoadOp stencil_load_op;
1527 VkImageLayout initial_layout;
1528 VkImageLayout final_layout;
1529 uint32_t view_mask;
1530 };
1531
1532 struct radv_render_pass {
1533 uint32_t attachment_count;
1534 uint32_t subpass_count;
1535 VkAttachmentReference * subpass_attachments;
1536 struct radv_render_pass_attachment * attachments;
1537 struct radv_subpass_barrier end_barrier;
1538 struct radv_subpass subpasses[0];
1539 };
1540
1541 VkResult radv_device_init_meta(struct radv_device *device);
1542 void radv_device_finish_meta(struct radv_device *device);
1543
1544 struct radv_query_pool {
1545 struct radeon_winsys_bo *bo;
1546 uint32_t stride;
1547 uint32_t availability_offset;
1548 char *ptr;
1549 VkQueryType type;
1550 uint32_t pipeline_stats_mask;
1551 };
1552
1553 struct radv_semaphore {
1554 /* use a winsys sem for non-exportable */
1555 struct radeon_winsys_sem *sem;
1556 uint32_t syncobj;
1557 uint32_t temp_syncobj;
1558 };
1559
1560 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1561 int num_wait_sems,
1562 const VkSemaphore *wait_sems,
1563 int num_signal_sems,
1564 const VkSemaphore *signal_sems);
1565 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1566
1567 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1568 struct radv_descriptor_set *set,
1569 unsigned idx);
1570
1571 void
1572 radv_update_descriptor_sets(struct radv_device *device,
1573 struct radv_cmd_buffer *cmd_buffer,
1574 VkDescriptorSet overrideSet,
1575 uint32_t descriptorWriteCount,
1576 const VkWriteDescriptorSet *pDescriptorWrites,
1577 uint32_t descriptorCopyCount,
1578 const VkCopyDescriptorSet *pDescriptorCopies);
1579
1580 void
1581 radv_update_descriptor_set_with_template(struct radv_device *device,
1582 struct radv_cmd_buffer *cmd_buffer,
1583 struct radv_descriptor_set *set,
1584 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1585 const void *pData);
1586
1587 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1588 VkPipelineBindPoint pipelineBindPoint,
1589 VkPipelineLayout _layout,
1590 uint32_t set,
1591 uint32_t descriptorWriteCount,
1592 const VkWriteDescriptorSet *pDescriptorWrites);
1593
1594 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1595 struct radv_image *image, uint32_t value);
1596 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1597 struct radv_image *image, uint32_t value);
1598
1599 struct radv_fence {
1600 struct radeon_winsys_fence *fence;
1601 bool submitted;
1602 bool signalled;
1603 };
1604
1605 struct radeon_winsys_sem;
1606
1607 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1608 \
1609 static inline struct __radv_type * \
1610 __radv_type ## _from_handle(__VkType _handle) \
1611 { \
1612 return (struct __radv_type *) _handle; \
1613 } \
1614 \
1615 static inline __VkType \
1616 __radv_type ## _to_handle(struct __radv_type *_obj) \
1617 { \
1618 return (__VkType) _obj; \
1619 }
1620
1621 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1622 \
1623 static inline struct __radv_type * \
1624 __radv_type ## _from_handle(__VkType _handle) \
1625 { \
1626 return (struct __radv_type *)(uintptr_t) _handle; \
1627 } \
1628 \
1629 static inline __VkType \
1630 __radv_type ## _to_handle(struct __radv_type *_obj) \
1631 { \
1632 return (__VkType)(uintptr_t) _obj; \
1633 }
1634
1635 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1636 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1637
1638 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1639 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1640 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1641 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1642 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1643
1644 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1645 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1646 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1647 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1648 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1649 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1650 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1651 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1652 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1653 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1654 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1655 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1656 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1657 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1658 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1659 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1660 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1661 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1662 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1663 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1664 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1665
1666 #endif /* RADV_PRIVATE_H */