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radv: emit the initial config only once in the preambles
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "ac_llvm_util.h"
62 #include "radv_descriptor_set.h"
63 #include "radv_extensions.h"
64 #include "radv_cs.h"
65
66 #include <llvm-c/TargetMachine.h>
67
68 /* Pre-declarations needed for WSI entrypoints */
69 struct wl_surface;
70 struct wl_display;
71 typedef struct xcb_connection_t xcb_connection_t;
72 typedef uint32_t xcb_visualid_t;
73 typedef uint32_t xcb_window_t;
74
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vk_icd.h>
78 #include <vulkan/vk_android_native_buffer.h>
79
80 #include "radv_entrypoints.h"
81
82 #include "wsi_common.h"
83 #include "wsi_common_display.h"
84
85 #define ATI_VENDOR_ID 0x1002
86
87 #define MAX_VBS 32
88 #define MAX_VERTEX_ATTRIBS 32
89 #define MAX_RTS 8
90 #define MAX_VIEWPORTS 16
91 #define MAX_SCISSORS 16
92 #define MAX_DISCARD_RECTANGLES 4
93 #define MAX_PUSH_CONSTANTS_SIZE 128
94 #define MAX_PUSH_DESCRIPTORS 32
95 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
96 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
97 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
98 #define MAX_SAMPLES_LOG2 4
99 #define NUM_META_FS_KEYS 12
100 #define RADV_MAX_DRM_DEVICES 8
101 #define MAX_VIEWS 8
102
103 #define NUM_DEPTH_CLEAR_PIPELINES 3
104
105 /*
106 * This is the point we switch from using CP to compute shader
107 * for certain buffer operations.
108 */
109 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
110
111 enum radv_mem_heap {
112 RADV_MEM_HEAP_VRAM,
113 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
114 RADV_MEM_HEAP_GTT,
115 RADV_MEM_HEAP_COUNT
116 };
117
118 enum radv_mem_type {
119 RADV_MEM_TYPE_VRAM,
120 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
121 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
122 RADV_MEM_TYPE_GTT_CACHED,
123 RADV_MEM_TYPE_COUNT
124 };
125
126 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
127
128 static inline uint32_t
129 align_u32(uint32_t v, uint32_t a)
130 {
131 assert(a != 0 && a == (a & -a));
132 return (v + a - 1) & ~(a - 1);
133 }
134
135 static inline uint32_t
136 align_u32_npot(uint32_t v, uint32_t a)
137 {
138 return (v + a - 1) / a * a;
139 }
140
141 static inline uint64_t
142 align_u64(uint64_t v, uint64_t a)
143 {
144 assert(a != 0 && a == (a & -a));
145 return (v + a - 1) & ~(a - 1);
146 }
147
148 static inline int32_t
149 align_i32(int32_t v, int32_t a)
150 {
151 assert(a != 0 && a == (a & -a));
152 return (v + a - 1) & ~(a - 1);
153 }
154
155 /** Alignment must be a power of 2. */
156 static inline bool
157 radv_is_aligned(uintmax_t n, uintmax_t a)
158 {
159 assert(a == (a & -a));
160 return (n & (a - 1)) == 0;
161 }
162
163 static inline uint32_t
164 round_up_u32(uint32_t v, uint32_t a)
165 {
166 return (v + a - 1) / a;
167 }
168
169 static inline uint64_t
170 round_up_u64(uint64_t v, uint64_t a)
171 {
172 return (v + a - 1) / a;
173 }
174
175 static inline uint32_t
176 radv_minify(uint32_t n, uint32_t levels)
177 {
178 if (unlikely(n == 0))
179 return 0;
180 else
181 return MAX2(n >> levels, 1);
182 }
183 static inline float
184 radv_clamp_f(float f, float min, float max)
185 {
186 assert(min < max);
187
188 if (f > max)
189 return max;
190 else if (f < min)
191 return min;
192 else
193 return f;
194 }
195
196 static inline bool
197 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
198 {
199 if (*inout_mask & clear_mask) {
200 *inout_mask &= ~clear_mask;
201 return true;
202 } else {
203 return false;
204 }
205 }
206
207 #define for_each_bit(b, dword) \
208 for (uint32_t __dword = (dword); \
209 (b) = __builtin_ffs(__dword) - 1, __dword; \
210 __dword &= ~(1 << (b)))
211
212 #define typed_memcpy(dest, src, count) ({ \
213 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
214 memcpy((dest), (src), (count) * sizeof(*(src))); \
215 })
216
217 /* Whenever we generate an error, pass it through this function. Useful for
218 * debugging, where we can break on it. Only call at error site, not when
219 * propagating errors. Might be useful to plug in a stack trace here.
220 */
221
222 struct radv_instance;
223
224 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
225
226 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
227 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
228
229 void __radv_finishme(const char *file, int line, const char *format, ...)
230 radv_printflike(3, 4);
231 void radv_loge(const char *format, ...) radv_printflike(1, 2);
232 void radv_loge_v(const char *format, va_list va);
233 void radv_logi(const char *format, ...) radv_printflike(1, 2);
234 void radv_logi_v(const char *format, va_list va);
235
236 /**
237 * Print a FINISHME message, including its source location.
238 */
239 #define radv_finishme(format, ...) \
240 do { \
241 static bool reported = false; \
242 if (!reported) { \
243 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
244 reported = true; \
245 } \
246 } while (0)
247
248 /* A non-fatal assert. Useful for debugging. */
249 #ifdef DEBUG
250 #define radv_assert(x) ({ \
251 if (unlikely(!(x))) \
252 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
253 })
254 #else
255 #define radv_assert(x)
256 #endif
257
258 #define stub_return(v) \
259 do { \
260 radv_finishme("stub %s", __func__); \
261 return (v); \
262 } while (0)
263
264 #define stub() \
265 do { \
266 radv_finishme("stub %s", __func__); \
267 return; \
268 } while (0)
269
270 void *radv_lookup_entrypoint_unchecked(const char *name);
271 void *radv_lookup_entrypoint_checked(const char *name,
272 uint32_t core_version,
273 const struct radv_instance_extension_table *instance,
274 const struct radv_device_extension_table *device);
275
276 struct radv_physical_device {
277 VK_LOADER_DATA _loader_data;
278
279 struct radv_instance * instance;
280
281 struct radeon_winsys *ws;
282 struct radeon_info rad_info;
283 char path[20];
284 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
285 uint8_t driver_uuid[VK_UUID_SIZE];
286 uint8_t device_uuid[VK_UUID_SIZE];
287 uint8_t cache_uuid[VK_UUID_SIZE];
288
289 int local_fd;
290 int master_fd;
291 struct wsi_device wsi_device;
292
293 bool has_rbplus; /* if RB+ register exist */
294 bool rbplus_allowed; /* if RB+ is allowed */
295 bool has_clear_state;
296 bool cpdma_prefetch_writes_memory;
297 bool has_scissor_bug;
298
299 bool has_out_of_order_rast;
300 bool out_of_order_rast_allowed;
301
302 /* Whether DCC should be enabled for MSAA textures. */
303 bool dcc_msaa_allowed;
304
305 /* This is the drivers on-disk cache used as a fallback as opposed to
306 * the pipeline cache defined by apps.
307 */
308 struct disk_cache * disk_cache;
309
310 VkPhysicalDeviceMemoryProperties memory_properties;
311 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
312
313 struct radv_device_extension_table supported_extensions;
314 };
315
316 struct radv_instance {
317 VK_LOADER_DATA _loader_data;
318
319 VkAllocationCallbacks alloc;
320
321 uint32_t apiVersion;
322 int physicalDeviceCount;
323 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
324
325 uint64_t debug_flags;
326 uint64_t perftest_flags;
327
328 struct vk_debug_report_instance debug_report_callbacks;
329
330 struct radv_instance_extension_table enabled_extensions;
331 };
332
333 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
334 void radv_finish_wsi(struct radv_physical_device *physical_device);
335
336 bool radv_instance_extension_supported(const char *name);
337 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
338 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
339 const char *name);
340
341 struct cache_entry;
342
343 struct radv_pipeline_cache {
344 struct radv_device * device;
345 pthread_mutex_t mutex;
346
347 uint32_t total_size;
348 uint32_t table_size;
349 uint32_t kernel_count;
350 struct cache_entry ** hash_table;
351 bool modified;
352
353 VkAllocationCallbacks alloc;
354 };
355
356 struct radv_pipeline_key {
357 uint32_t instance_rate_inputs;
358 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
359 uint64_t vertex_alpha_adjust;
360 unsigned tess_input_vertices;
361 uint32_t col_format;
362 uint32_t is_int8;
363 uint32_t is_int10;
364 uint8_t log2_ps_iter_samples;
365 uint8_t num_samples;
366 uint32_t has_multiview_view_index : 1;
367 uint32_t optimisations_disabled : 1;
368 };
369
370 void
371 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
372 struct radv_device *device);
373 void
374 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
375 bool
376 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
377 const void *data, size_t size);
378
379 struct radv_shader_variant;
380
381 bool
382 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
383 struct radv_pipeline_cache *cache,
384 const unsigned char *sha1,
385 struct radv_shader_variant **variants);
386
387 void
388 radv_pipeline_cache_insert_shaders(struct radv_device *device,
389 struct radv_pipeline_cache *cache,
390 const unsigned char *sha1,
391 struct radv_shader_variant **variants,
392 const void *const *codes,
393 const unsigned *code_sizes);
394
395 enum radv_blit_ds_layout {
396 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
397 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
398 RADV_BLIT_DS_LAYOUT_COUNT,
399 };
400
401 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
402 {
403 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
404 }
405
406 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
407 {
408 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
409 }
410
411 enum radv_meta_dst_layout {
412 RADV_META_DST_LAYOUT_GENERAL,
413 RADV_META_DST_LAYOUT_OPTIMAL,
414 RADV_META_DST_LAYOUT_COUNT,
415 };
416
417 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
418 {
419 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
420 }
421
422 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
423 {
424 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
425 }
426
427 struct radv_meta_state {
428 VkAllocationCallbacks alloc;
429
430 struct radv_pipeline_cache cache;
431
432 /*
433 * For on-demand pipeline creation, makes sure that
434 * only one thread tries to build a pipeline at the same time.
435 */
436 mtx_t mtx;
437
438 /**
439 * Use array element `i` for images with `2^i` samples.
440 */
441 struct {
442 VkRenderPass render_pass[NUM_META_FS_KEYS];
443 VkPipeline color_pipelines[NUM_META_FS_KEYS];
444
445 VkRenderPass depthstencil_rp;
446 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
447 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
448 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
449 } clear[1 + MAX_SAMPLES_LOG2];
450
451 VkPipelineLayout clear_color_p_layout;
452 VkPipelineLayout clear_depth_p_layout;
453 struct {
454 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
455
456 /** Pipeline that blits from a 1D image. */
457 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
458
459 /** Pipeline that blits from a 2D image. */
460 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
461
462 /** Pipeline that blits from a 3D image. */
463 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
464
465 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
466 VkPipeline depth_only_1d_pipeline;
467 VkPipeline depth_only_2d_pipeline;
468 VkPipeline depth_only_3d_pipeline;
469
470 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
471 VkPipeline stencil_only_1d_pipeline;
472 VkPipeline stencil_only_2d_pipeline;
473 VkPipeline stencil_only_3d_pipeline;
474 VkPipelineLayout pipeline_layout;
475 VkDescriptorSetLayout ds_layout;
476 } blit;
477
478 struct {
479 VkPipelineLayout p_layouts[5];
480 VkDescriptorSetLayout ds_layouts[5];
481 VkPipeline pipelines[5][NUM_META_FS_KEYS];
482
483 VkPipeline depth_only_pipeline[5];
484
485 VkPipeline stencil_only_pipeline[5];
486 } blit2d[1 + MAX_SAMPLES_LOG2];
487
488 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
489 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
490 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
491
492 struct {
493 VkPipelineLayout img_p_layout;
494 VkDescriptorSetLayout img_ds_layout;
495 VkPipeline pipeline;
496 VkPipeline pipeline_3d;
497 } itob;
498 struct {
499 VkPipelineLayout img_p_layout;
500 VkDescriptorSetLayout img_ds_layout;
501 VkPipeline pipeline;
502 VkPipeline pipeline_3d;
503 } btoi;
504 struct {
505 VkPipelineLayout img_p_layout;
506 VkDescriptorSetLayout img_ds_layout;
507 VkPipeline pipeline;
508 VkPipeline pipeline_3d;
509 } itoi;
510 struct {
511 VkPipelineLayout img_p_layout;
512 VkDescriptorSetLayout img_ds_layout;
513 VkPipeline pipeline;
514 VkPipeline pipeline_3d;
515 } cleari;
516
517 struct {
518 VkPipelineLayout p_layout;
519 VkPipeline pipeline[NUM_META_FS_KEYS];
520 VkRenderPass pass[NUM_META_FS_KEYS];
521 } resolve;
522
523 struct {
524 VkDescriptorSetLayout ds_layout;
525 VkPipelineLayout p_layout;
526 struct {
527 VkPipeline pipeline;
528 VkPipeline i_pipeline;
529 VkPipeline srgb_pipeline;
530 } rc[MAX_SAMPLES_LOG2];
531 } resolve_compute;
532
533 struct {
534 VkDescriptorSetLayout ds_layout;
535 VkPipelineLayout p_layout;
536
537 struct {
538 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
539 VkPipeline pipeline[NUM_META_FS_KEYS];
540 } rc[MAX_SAMPLES_LOG2];
541 } resolve_fragment;
542
543 struct {
544 VkPipelineLayout p_layout;
545 VkPipeline decompress_pipeline;
546 VkPipeline resummarize_pipeline;
547 VkRenderPass pass;
548 } depth_decomp[1 + MAX_SAMPLES_LOG2];
549
550 struct {
551 VkPipelineLayout p_layout;
552 VkPipeline cmask_eliminate_pipeline;
553 VkPipeline fmask_decompress_pipeline;
554 VkPipeline dcc_decompress_pipeline;
555 VkRenderPass pass;
556
557 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
558 VkPipelineLayout dcc_decompress_compute_p_layout;
559 VkPipeline dcc_decompress_compute_pipeline;
560 } fast_clear_flush;
561
562 struct {
563 VkPipelineLayout fill_p_layout;
564 VkPipelineLayout copy_p_layout;
565 VkDescriptorSetLayout fill_ds_layout;
566 VkDescriptorSetLayout copy_ds_layout;
567 VkPipeline fill_pipeline;
568 VkPipeline copy_pipeline;
569 } buffer;
570
571 struct {
572 VkDescriptorSetLayout ds_layout;
573 VkPipelineLayout p_layout;
574 VkPipeline occlusion_query_pipeline;
575 VkPipeline pipeline_statistics_query_pipeline;
576 } query;
577 };
578
579 /* queue types */
580 #define RADV_QUEUE_GENERAL 0
581 #define RADV_QUEUE_COMPUTE 1
582 #define RADV_QUEUE_TRANSFER 2
583
584 #define RADV_MAX_QUEUE_FAMILIES 3
585
586 enum ring_type radv_queue_family_to_ring(int f);
587
588 struct radv_queue {
589 VK_LOADER_DATA _loader_data;
590 struct radv_device * device;
591 struct radeon_winsys_ctx *hw_ctx;
592 enum radeon_ctx_priority priority;
593 uint32_t queue_family_index;
594 int queue_idx;
595 VkDeviceQueueCreateFlags flags;
596
597 uint32_t scratch_size;
598 uint32_t compute_scratch_size;
599 uint32_t esgs_ring_size;
600 uint32_t gsvs_ring_size;
601 bool has_tess_rings;
602 bool has_sample_positions;
603
604 struct radeon_winsys_bo *scratch_bo;
605 struct radeon_winsys_bo *descriptor_bo;
606 struct radeon_winsys_bo *compute_scratch_bo;
607 struct radeon_winsys_bo *esgs_ring_bo;
608 struct radeon_winsys_bo *gsvs_ring_bo;
609 struct radeon_winsys_bo *tess_rings_bo;
610 struct radeon_cmdbuf *initial_preamble_cs;
611 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
612 struct radeon_cmdbuf *continue_preamble_cs;
613 };
614
615 struct radv_bo_list {
616 struct radv_winsys_bo_list list;
617 unsigned capacity;
618 pthread_mutex_t mutex;
619 };
620
621 struct radv_device {
622 VK_LOADER_DATA _loader_data;
623
624 VkAllocationCallbacks alloc;
625
626 struct radv_instance * instance;
627 struct radeon_winsys *ws;
628
629 struct radv_meta_state meta_state;
630
631 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
632 int queue_count[RADV_MAX_QUEUE_FAMILIES];
633 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
634
635 bool always_use_syncobj;
636 bool has_distributed_tess;
637 bool pbb_allowed;
638 bool dfsm_allowed;
639 uint32_t tess_offchip_block_dw_size;
640 uint32_t scratch_waves;
641 uint32_t dispatch_initiator;
642
643 uint32_t gs_table_depth;
644
645 /* MSAA sample locations.
646 * The first index is the sample index.
647 * The second index is the coordinate: X, Y. */
648 float sample_locations_1x[1][2];
649 float sample_locations_2x[2][2];
650 float sample_locations_4x[4][2];
651 float sample_locations_8x[8][2];
652 float sample_locations_16x[16][2];
653
654 /* CIK and later */
655 uint32_t gfx_init_size_dw;
656 struct radeon_winsys_bo *gfx_init;
657
658 struct radeon_winsys_bo *trace_bo;
659 uint32_t *trace_id_ptr;
660
661 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
662 bool keep_shader_info;
663
664 struct radv_physical_device *physical_device;
665
666 /* Backup in-memory cache to be used if the app doesn't provide one */
667 struct radv_pipeline_cache * mem_cache;
668
669 /*
670 * use different counters so MSAA MRTs get consecutive surface indices,
671 * even if MASK is allocated in between.
672 */
673 uint32_t image_mrt_offset_counter;
674 uint32_t fmask_mrt_offset_counter;
675 struct list_head shader_slabs;
676 mtx_t shader_slab_mutex;
677
678 /* For detecting VM faults reported by dmesg. */
679 uint64_t dmesg_timestamp;
680
681 struct radv_device_extension_table enabled_extensions;
682
683 /* Whether the driver uses a global BO list. */
684 bool use_global_bo_list;
685
686 struct radv_bo_list bo_list;
687 };
688
689 struct radv_device_memory {
690 struct radeon_winsys_bo *bo;
691 /* for dedicated allocations */
692 struct radv_image *image;
693 struct radv_buffer *buffer;
694 uint32_t type_index;
695 VkDeviceSize map_size;
696 void * map;
697 void * user_ptr;
698 };
699
700
701 struct radv_descriptor_range {
702 uint64_t va;
703 uint32_t size;
704 };
705
706 struct radv_descriptor_set {
707 const struct radv_descriptor_set_layout *layout;
708 uint32_t size;
709
710 struct radeon_winsys_bo *bo;
711 uint64_t va;
712 uint32_t *mapped_ptr;
713 struct radv_descriptor_range *dynamic_descriptors;
714
715 struct radeon_winsys_bo *descriptors[0];
716 };
717
718 struct radv_push_descriptor_set
719 {
720 struct radv_descriptor_set set;
721 uint32_t capacity;
722 };
723
724 struct radv_descriptor_pool_entry {
725 uint32_t offset;
726 uint32_t size;
727 struct radv_descriptor_set *set;
728 };
729
730 struct radv_descriptor_pool {
731 struct radeon_winsys_bo *bo;
732 uint8_t *mapped_ptr;
733 uint64_t current_offset;
734 uint64_t size;
735
736 uint8_t *host_memory_base;
737 uint8_t *host_memory_ptr;
738 uint8_t *host_memory_end;
739
740 uint32_t entry_count;
741 uint32_t max_entry_count;
742 struct radv_descriptor_pool_entry entries[0];
743 };
744
745 struct radv_descriptor_update_template_entry {
746 VkDescriptorType descriptor_type;
747
748 /* The number of descriptors to update */
749 uint32_t descriptor_count;
750
751 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
752 uint32_t dst_offset;
753
754 /* In dwords. Not valid/used for dynamic descriptors */
755 uint32_t dst_stride;
756
757 uint32_t buffer_offset;
758
759 /* Only valid for combined image samplers and samplers */
760 uint16_t has_sampler;
761
762 /* In bytes */
763 size_t src_offset;
764 size_t src_stride;
765
766 /* For push descriptors */
767 const uint32_t *immutable_samplers;
768 };
769
770 struct radv_descriptor_update_template {
771 uint32_t entry_count;
772 VkPipelineBindPoint bind_point;
773 struct radv_descriptor_update_template_entry entry[0];
774 };
775
776 struct radv_buffer {
777 VkDeviceSize size;
778
779 VkBufferUsageFlags usage;
780 VkBufferCreateFlags flags;
781
782 /* Set when bound */
783 struct radeon_winsys_bo * bo;
784 VkDeviceSize offset;
785
786 bool shareable;
787 };
788
789 enum radv_dynamic_state_bits {
790 RADV_DYNAMIC_VIEWPORT = 1 << 0,
791 RADV_DYNAMIC_SCISSOR = 1 << 1,
792 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
793 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
794 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
795 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
796 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
797 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
798 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
799 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
800 RADV_DYNAMIC_ALL = (1 << 10) - 1,
801 };
802
803 enum radv_cmd_dirty_bits {
804 /* Keep the dynamic state dirty bits in sync with
805 * enum radv_dynamic_state_bits */
806 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
807 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
808 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
809 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
810 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
811 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
812 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
813 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
814 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
815 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
816 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
817 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
818 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
819 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
820 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
821 };
822
823 enum radv_cmd_flush_bits {
824 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
825 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
826 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
827 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
828 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
829 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
830 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
831 /* Same as above, but only writes back and doesn't invalidate */
832 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
833 /* Framebuffer caches */
834 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
835 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
836 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
837 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
838 /* Engine synchronization. */
839 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
840 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
841 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
842 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
843 /* Pipeline query controls. */
844 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
845 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
846
847 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
848 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
849 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
850 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
851 };
852
853 struct radv_vertex_binding {
854 struct radv_buffer * buffer;
855 VkDeviceSize offset;
856 };
857
858 struct radv_viewport_state {
859 uint32_t count;
860 VkViewport viewports[MAX_VIEWPORTS];
861 };
862
863 struct radv_scissor_state {
864 uint32_t count;
865 VkRect2D scissors[MAX_SCISSORS];
866 };
867
868 struct radv_discard_rectangle_state {
869 uint32_t count;
870 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
871 };
872
873 struct radv_dynamic_state {
874 /**
875 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
876 * Defines the set of saved dynamic state.
877 */
878 uint32_t mask;
879
880 struct radv_viewport_state viewport;
881
882 struct radv_scissor_state scissor;
883
884 float line_width;
885
886 struct {
887 float bias;
888 float clamp;
889 float slope;
890 } depth_bias;
891
892 float blend_constants[4];
893
894 struct {
895 float min;
896 float max;
897 } depth_bounds;
898
899 struct {
900 uint32_t front;
901 uint32_t back;
902 } stencil_compare_mask;
903
904 struct {
905 uint32_t front;
906 uint32_t back;
907 } stencil_write_mask;
908
909 struct {
910 uint32_t front;
911 uint32_t back;
912 } stencil_reference;
913
914 struct radv_discard_rectangle_state discard_rectangle;
915 };
916
917 extern const struct radv_dynamic_state default_dynamic_state;
918
919 const char *
920 radv_get_debug_option_name(int id);
921
922 const char *
923 radv_get_perftest_option_name(int id);
924
925 /**
926 * Attachment state when recording a renderpass instance.
927 *
928 * The clear value is valid only if there exists a pending clear.
929 */
930 struct radv_attachment_state {
931 VkImageAspectFlags pending_clear_aspects;
932 uint32_t cleared_views;
933 VkClearValue clear_value;
934 VkImageLayout current_layout;
935 };
936
937 struct radv_descriptor_state {
938 struct radv_descriptor_set *sets[MAX_SETS];
939 uint32_t dirty;
940 uint32_t valid;
941 struct radv_push_descriptor_set push_set;
942 bool push_dirty;
943 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
944 };
945
946 struct radv_cmd_state {
947 /* Vertex descriptors */
948 uint64_t vb_va;
949 unsigned vb_size;
950
951 bool predicating;
952 uint32_t dirty;
953
954 uint32_t prefetch_L2_mask;
955
956 struct radv_pipeline * pipeline;
957 struct radv_pipeline * emitted_pipeline;
958 struct radv_pipeline * compute_pipeline;
959 struct radv_pipeline * emitted_compute_pipeline;
960 struct radv_framebuffer * framebuffer;
961 struct radv_render_pass * pass;
962 const struct radv_subpass * subpass;
963 struct radv_dynamic_state dynamic;
964 struct radv_attachment_state * attachments;
965 VkRect2D render_area;
966
967 /* Index buffer */
968 struct radv_buffer *index_buffer;
969 uint64_t index_offset;
970 uint32_t index_type;
971 uint32_t max_index_count;
972 uint64_t index_va;
973 int32_t last_index_type;
974
975 int32_t last_primitive_reset_en;
976 uint32_t last_primitive_reset_index;
977 enum radv_cmd_flush_bits flush_bits;
978 unsigned active_occlusion_queries;
979 bool perfect_occlusion_queries_enabled;
980 unsigned active_pipeline_queries;
981 float offset_scale;
982 uint32_t trace_id;
983 uint32_t last_ia_multi_vgt_param;
984
985 uint32_t last_num_instances;
986 uint32_t last_first_instance;
987 uint32_t last_vertex_offset;
988
989 /* Whether CP DMA is busy/idle. */
990 bool dma_is_busy;
991
992 /* Conditional rendering info. */
993 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
994 uint64_t predication_va;
995 };
996
997 struct radv_cmd_pool {
998 VkAllocationCallbacks alloc;
999 struct list_head cmd_buffers;
1000 struct list_head free_cmd_buffers;
1001 uint32_t queue_family_index;
1002 };
1003
1004 struct radv_cmd_buffer_upload {
1005 uint8_t *map;
1006 unsigned offset;
1007 uint64_t size;
1008 struct radeon_winsys_bo *upload_bo;
1009 struct list_head list;
1010 };
1011
1012 enum radv_cmd_buffer_status {
1013 RADV_CMD_BUFFER_STATUS_INVALID,
1014 RADV_CMD_BUFFER_STATUS_INITIAL,
1015 RADV_CMD_BUFFER_STATUS_RECORDING,
1016 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1017 RADV_CMD_BUFFER_STATUS_PENDING,
1018 };
1019
1020 struct radv_cmd_buffer {
1021 VK_LOADER_DATA _loader_data;
1022
1023 struct radv_device * device;
1024
1025 struct radv_cmd_pool * pool;
1026 struct list_head pool_link;
1027
1028 VkCommandBufferUsageFlags usage_flags;
1029 VkCommandBufferLevel level;
1030 enum radv_cmd_buffer_status status;
1031 struct radeon_cmdbuf *cs;
1032 struct radv_cmd_state state;
1033 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1034 uint32_t queue_family_index;
1035
1036 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1037 VkShaderStageFlags push_constant_stages;
1038 struct radv_descriptor_set meta_push_descriptors;
1039
1040 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1041
1042 struct radv_cmd_buffer_upload upload;
1043
1044 uint32_t scratch_size_needed;
1045 uint32_t compute_scratch_size_needed;
1046 uint32_t esgs_ring_size_needed;
1047 uint32_t gsvs_ring_size_needed;
1048 bool tess_rings_needed;
1049 bool sample_positions_needed;
1050
1051 VkResult record_result;
1052
1053 uint32_t gfx9_fence_offset;
1054 struct radeon_winsys_bo *gfx9_fence_bo;
1055 uint32_t gfx9_fence_idx;
1056 uint64_t gfx9_eop_bug_va;
1057
1058 /**
1059 * Whether a query pool has been resetted and we have to flush caches.
1060 */
1061 bool pending_reset_query;
1062 };
1063
1064 struct radv_image;
1065
1066 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1067
1068 void si_emit_graphics(struct radv_physical_device *physical_device,
1069 struct radeon_cmdbuf *cs);
1070 void si_emit_compute(struct radv_physical_device *physical_device,
1071 struct radeon_cmdbuf *cs);
1072
1073 void cik_create_gfx_config(struct radv_device *device);
1074
1075 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1076 int count, const VkViewport *viewports);
1077 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1078 int count, const VkRect2D *scissors,
1079 const VkViewport *viewports, bool can_use_guardband);
1080 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1081 bool instanced_draw, bool indirect_draw,
1082 uint32_t draw_vertex_count);
1083 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1084 enum chip_class chip_class,
1085 bool is_mec,
1086 unsigned event, unsigned event_flags,
1087 unsigned data_sel,
1088 uint64_t va,
1089 uint32_t old_fence,
1090 uint32_t new_fence,
1091 uint64_t gfx9_eop_bug_va);
1092
1093 void si_emit_wait_fence(struct radeon_cmdbuf *cs,
1094 uint64_t va, uint32_t ref,
1095 uint32_t mask);
1096 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1097 enum chip_class chip_class,
1098 uint32_t *fence_ptr, uint64_t va,
1099 bool is_mec,
1100 enum radv_cmd_flush_bits flush_bits,
1101 uint64_t gfx9_eop_bug_va);
1102 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1103 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1104 bool inverted, uint64_t va);
1105 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1106 uint64_t src_va, uint64_t dest_va,
1107 uint64_t size);
1108 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1109 unsigned size);
1110 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1111 uint64_t size, unsigned value);
1112 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1113
1114 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1115 bool
1116 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1117 unsigned size,
1118 unsigned alignment,
1119 unsigned *out_offset,
1120 void **ptr);
1121 void
1122 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1123 const struct radv_subpass *subpass,
1124 bool transitions);
1125 bool
1126 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1127 unsigned size, unsigned alignmnet,
1128 const void *data, unsigned *out_offset);
1129
1130 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1131 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1132 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1133 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1134 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
1135 unsigned radv_cayman_get_maxdist(int log_samples);
1136 void radv_device_init_msaa(struct radv_device *device);
1137
1138 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1139 struct radv_image *image,
1140 VkClearDepthStencilValue ds_clear_value,
1141 VkImageAspectFlags aspects);
1142
1143 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1144 struct radv_image *image,
1145 int cb_idx,
1146 uint32_t color_values[2]);
1147
1148 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1149 struct radv_image *image,
1150 bool value);
1151 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1152 struct radeon_winsys_bo *bo,
1153 uint64_t offset, uint64_t size, uint32_t value);
1154 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1155 bool radv_get_memory_fd(struct radv_device *device,
1156 struct radv_device_memory *memory,
1157 int *pFD);
1158
1159 static inline void
1160 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1161 unsigned sh_offset, unsigned pointer_count,
1162 bool use_32bit_pointers)
1163 {
1164 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1165 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1166 }
1167
1168 static inline void
1169 radv_emit_shader_pointer_body(struct radv_device *device,
1170 struct radeon_cmdbuf *cs,
1171 uint64_t va, bool use_32bit_pointers)
1172 {
1173 radeon_emit(cs, va);
1174
1175 if (use_32bit_pointers) {
1176 assert(va == 0 ||
1177 (va >> 32) == device->physical_device->rad_info.address32_hi);
1178 } else {
1179 radeon_emit(cs, va >> 32);
1180 }
1181 }
1182
1183 static inline void
1184 radv_emit_shader_pointer(struct radv_device *device,
1185 struct radeon_cmdbuf *cs,
1186 uint32_t sh_offset, uint64_t va, bool global)
1187 {
1188 bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
1189
1190 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1191 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1192 }
1193
1194 static inline struct radv_descriptor_state *
1195 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1196 VkPipelineBindPoint bind_point)
1197 {
1198 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1199 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1200 return &cmd_buffer->descriptors[bind_point];
1201 }
1202
1203 /*
1204 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1205 *
1206 * Limitations: Can't call normal dispatch functions without binding or rebinding
1207 * the compute pipeline.
1208 */
1209 void radv_unaligned_dispatch(
1210 struct radv_cmd_buffer *cmd_buffer,
1211 uint32_t x,
1212 uint32_t y,
1213 uint32_t z);
1214
1215 struct radv_event {
1216 struct radeon_winsys_bo *bo;
1217 uint64_t *map;
1218 };
1219
1220 struct radv_shader_module;
1221
1222 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1223 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1224 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1225 void
1226 radv_hash_shaders(unsigned char *hash,
1227 const VkPipelineShaderStageCreateInfo **stages,
1228 const struct radv_pipeline_layout *layout,
1229 const struct radv_pipeline_key *key,
1230 uint32_t flags);
1231
1232 static inline gl_shader_stage
1233 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1234 {
1235 assert(__builtin_popcount(vk_stage) == 1);
1236 return ffs(vk_stage) - 1;
1237 }
1238
1239 static inline VkShaderStageFlagBits
1240 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1241 {
1242 return (1 << mesa_stage);
1243 }
1244
1245 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1246
1247 #define radv_foreach_stage(stage, stage_bits) \
1248 for (gl_shader_stage stage, \
1249 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1250 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1251 __tmp &= ~(1 << (stage)))
1252
1253 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1254 unsigned radv_format_meta_fs_key(VkFormat format);
1255
1256 struct radv_multisample_state {
1257 uint32_t db_eqaa;
1258 uint32_t pa_sc_line_cntl;
1259 uint32_t pa_sc_mode_cntl_0;
1260 uint32_t pa_sc_mode_cntl_1;
1261 uint32_t pa_sc_aa_config;
1262 uint32_t pa_sc_aa_mask[2];
1263 unsigned num_samples;
1264 };
1265
1266 struct radv_prim_vertex_count {
1267 uint8_t min;
1268 uint8_t incr;
1269 };
1270
1271 struct radv_vertex_elements_info {
1272 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1273 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1274 uint32_t binding[MAX_VERTEX_ATTRIBS];
1275 uint32_t offset[MAX_VERTEX_ATTRIBS];
1276 uint32_t count;
1277 };
1278
1279 struct radv_ia_multi_vgt_param_helpers {
1280 uint32_t base;
1281 bool partial_es_wave;
1282 uint8_t primgroup_size;
1283 bool wd_switch_on_eop;
1284 bool ia_switch_on_eoi;
1285 bool partial_vs_wave;
1286 };
1287
1288 #define SI_GS_PER_ES 128
1289
1290 struct radv_pipeline {
1291 struct radv_device * device;
1292 struct radv_dynamic_state dynamic_state;
1293
1294 struct radv_pipeline_layout * layout;
1295
1296 bool need_indirect_descriptor_sets;
1297 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1298 struct radv_shader_variant *gs_copy_shader;
1299 VkShaderStageFlags active_stages;
1300
1301 struct radeon_cmdbuf cs;
1302
1303 struct radv_vertex_elements_info vertex_elements;
1304
1305 uint32_t binding_stride[MAX_VBS];
1306
1307 uint32_t user_data_0[MESA_SHADER_STAGES];
1308 union {
1309 struct {
1310 struct radv_multisample_state ms;
1311 uint32_t spi_baryc_cntl;
1312 bool prim_restart_enable;
1313 unsigned esgs_ring_size;
1314 unsigned gsvs_ring_size;
1315 uint32_t vtx_base_sgpr;
1316 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1317 uint8_t vtx_emit_num;
1318 struct radv_prim_vertex_count prim_vertex_count;
1319 bool can_use_guardband;
1320 uint32_t needed_dynamic_state;
1321 bool disable_out_of_order_rast_for_occlusion;
1322
1323 /* Used for rbplus */
1324 uint32_t col_format;
1325 uint32_t cb_target_mask;
1326 } graphics;
1327 };
1328
1329 unsigned max_waves;
1330 unsigned scratch_bytes_per_wave;
1331 };
1332
1333 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1334 {
1335 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1336 }
1337
1338 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1339 {
1340 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1341 }
1342
1343 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1344 gl_shader_stage stage,
1345 int idx);
1346
1347 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1348 gl_shader_stage stage);
1349
1350 struct radv_graphics_pipeline_create_info {
1351 bool use_rectlist;
1352 bool db_depth_clear;
1353 bool db_stencil_clear;
1354 bool db_depth_disable_expclear;
1355 bool db_stencil_disable_expclear;
1356 bool db_flush_depth_inplace;
1357 bool db_flush_stencil_inplace;
1358 bool db_resummarize;
1359 uint32_t custom_blend_mode;
1360 };
1361
1362 VkResult
1363 radv_graphics_pipeline_create(VkDevice device,
1364 VkPipelineCache cache,
1365 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1366 const struct radv_graphics_pipeline_create_info *extra,
1367 const VkAllocationCallbacks *alloc,
1368 VkPipeline *pPipeline);
1369
1370 struct vk_format_description;
1371 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1372 int first_non_void);
1373 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1374 int first_non_void);
1375 uint32_t radv_translate_colorformat(VkFormat format);
1376 uint32_t radv_translate_color_numformat(VkFormat format,
1377 const struct vk_format_description *desc,
1378 int first_non_void);
1379 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1380 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1381 uint32_t radv_translate_dbformat(VkFormat format);
1382 uint32_t radv_translate_tex_dataformat(VkFormat format,
1383 const struct vk_format_description *desc,
1384 int first_non_void);
1385 uint32_t radv_translate_tex_numformat(VkFormat format,
1386 const struct vk_format_description *desc,
1387 int first_non_void);
1388 bool radv_format_pack_clear_color(VkFormat format,
1389 uint32_t clear_vals[2],
1390 VkClearColorValue *value);
1391 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1392 bool radv_dcc_formats_compatible(VkFormat format1,
1393 VkFormat format2);
1394
1395 struct radv_fmask_info {
1396 uint64_t offset;
1397 uint64_t size;
1398 unsigned alignment;
1399 unsigned pitch_in_pixels;
1400 unsigned bank_height;
1401 unsigned slice_tile_max;
1402 unsigned tile_mode_index;
1403 unsigned tile_swizzle;
1404 };
1405
1406 struct radv_cmask_info {
1407 uint64_t offset;
1408 uint64_t size;
1409 unsigned alignment;
1410 unsigned slice_tile_max;
1411 };
1412
1413 struct radv_image {
1414 VkImageType type;
1415 /* The original VkFormat provided by the client. This may not match any
1416 * of the actual surface formats.
1417 */
1418 VkFormat vk_format;
1419 VkImageAspectFlags aspects;
1420 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1421 struct ac_surf_info info;
1422 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1423 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1424
1425 VkDeviceSize size;
1426 uint32_t alignment;
1427
1428 unsigned queue_family_mask;
1429 bool exclusive;
1430 bool shareable;
1431
1432 /* Set when bound */
1433 struct radeon_winsys_bo *bo;
1434 VkDeviceSize offset;
1435 uint64_t dcc_offset;
1436 uint64_t htile_offset;
1437 bool tc_compatible_htile;
1438 struct radeon_surf surface;
1439
1440 struct radv_fmask_info fmask;
1441 struct radv_cmask_info cmask;
1442 uint64_t clear_value_offset;
1443 uint64_t dcc_pred_offset;
1444
1445 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1446 VkDeviceMemory owned_memory;
1447 };
1448
1449 /* Whether the image has a htile that is known consistent with the contents of
1450 * the image. */
1451 bool radv_layout_has_htile(const struct radv_image *image,
1452 VkImageLayout layout,
1453 unsigned queue_mask);
1454
1455 /* Whether the image has a htile that is known consistent with the contents of
1456 * the image and is allowed to be in compressed form.
1457 *
1458 * If this is false reads that don't use the htile should be able to return
1459 * correct results.
1460 */
1461 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1462 VkImageLayout layout,
1463 unsigned queue_mask);
1464
1465 bool radv_layout_can_fast_clear(const struct radv_image *image,
1466 VkImageLayout layout,
1467 unsigned queue_mask);
1468
1469 bool radv_layout_dcc_compressed(const struct radv_image *image,
1470 VkImageLayout layout,
1471 unsigned queue_mask);
1472
1473 /**
1474 * Return whether the image has CMASK metadata for color surfaces.
1475 */
1476 static inline bool
1477 radv_image_has_cmask(const struct radv_image *image)
1478 {
1479 return image->cmask.size;
1480 }
1481
1482 /**
1483 * Return whether the image has FMASK metadata for color surfaces.
1484 */
1485 static inline bool
1486 radv_image_has_fmask(const struct radv_image *image)
1487 {
1488 return image->fmask.size;
1489 }
1490
1491 /**
1492 * Return whether the image has DCC metadata for color surfaces.
1493 */
1494 static inline bool
1495 radv_image_has_dcc(const struct radv_image *image)
1496 {
1497 return image->surface.dcc_size;
1498 }
1499
1500 /**
1501 * Return whether DCC metadata is enabled for a level.
1502 */
1503 static inline bool
1504 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1505 {
1506 return radv_image_has_dcc(image) &&
1507 level < image->surface.num_dcc_levels;
1508 }
1509
1510 /**
1511 * Return whether the image has CB metadata.
1512 */
1513 static inline bool
1514 radv_image_has_CB_metadata(const struct radv_image *image)
1515 {
1516 return radv_image_has_cmask(image) ||
1517 radv_image_has_fmask(image) ||
1518 radv_image_has_dcc(image);
1519 }
1520
1521 /**
1522 * Return whether the image has HTILE metadata for depth surfaces.
1523 */
1524 static inline bool
1525 radv_image_has_htile(const struct radv_image *image)
1526 {
1527 return image->surface.htile_size;
1528 }
1529
1530 /**
1531 * Return whether HTILE metadata is enabled for a level.
1532 */
1533 static inline bool
1534 radv_htile_enabled(const struct radv_image *image, unsigned level)
1535 {
1536 return radv_image_has_htile(image) && level == 0;
1537 }
1538
1539 /**
1540 * Return whether the image is TC-compatible HTILE.
1541 */
1542 static inline bool
1543 radv_image_is_tc_compat_htile(const struct radv_image *image)
1544 {
1545 return radv_image_has_htile(image) && image->tc_compatible_htile;
1546 }
1547
1548 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1549
1550 static inline uint32_t
1551 radv_get_layerCount(const struct radv_image *image,
1552 const VkImageSubresourceRange *range)
1553 {
1554 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1555 image->info.array_size - range->baseArrayLayer : range->layerCount;
1556 }
1557
1558 static inline uint32_t
1559 radv_get_levelCount(const struct radv_image *image,
1560 const VkImageSubresourceRange *range)
1561 {
1562 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1563 image->info.levels - range->baseMipLevel : range->levelCount;
1564 }
1565
1566 struct radeon_bo_metadata;
1567 void
1568 radv_init_metadata(struct radv_device *device,
1569 struct radv_image *image,
1570 struct radeon_bo_metadata *metadata);
1571
1572 struct radv_image_view {
1573 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1574 struct radeon_winsys_bo *bo;
1575
1576 VkImageViewType type;
1577 VkImageAspectFlags aspect_mask;
1578 VkFormat vk_format;
1579 uint32_t base_layer;
1580 uint32_t layer_count;
1581 uint32_t base_mip;
1582 uint32_t level_count;
1583 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1584
1585 uint32_t descriptor[16];
1586
1587 /* Descriptor for use as a storage image as opposed to a sampled image.
1588 * This has a few differences for cube maps (e.g. type).
1589 */
1590 uint32_t storage_descriptor[16];
1591 };
1592
1593 struct radv_image_create_info {
1594 const VkImageCreateInfo *vk_info;
1595 bool scanout;
1596 bool no_metadata_planes;
1597 };
1598
1599 VkResult radv_image_create(VkDevice _device,
1600 const struct radv_image_create_info *info,
1601 const VkAllocationCallbacks* alloc,
1602 VkImage *pImage);
1603
1604 VkResult
1605 radv_image_from_gralloc(VkDevice device_h,
1606 const VkImageCreateInfo *base_info,
1607 const VkNativeBufferANDROID *gralloc_info,
1608 const VkAllocationCallbacks *alloc,
1609 VkImage *out_image_h);
1610
1611 void radv_image_view_init(struct radv_image_view *view,
1612 struct radv_device *device,
1613 const VkImageViewCreateInfo* pCreateInfo);
1614
1615 struct radv_buffer_view {
1616 struct radeon_winsys_bo *bo;
1617 VkFormat vk_format;
1618 uint64_t range; /**< VkBufferViewCreateInfo::range */
1619 uint32_t state[4];
1620 };
1621 void radv_buffer_view_init(struct radv_buffer_view *view,
1622 struct radv_device *device,
1623 const VkBufferViewCreateInfo* pCreateInfo);
1624
1625 static inline struct VkExtent3D
1626 radv_sanitize_image_extent(const VkImageType imageType,
1627 const struct VkExtent3D imageExtent)
1628 {
1629 switch (imageType) {
1630 case VK_IMAGE_TYPE_1D:
1631 return (VkExtent3D) { imageExtent.width, 1, 1 };
1632 case VK_IMAGE_TYPE_2D:
1633 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1634 case VK_IMAGE_TYPE_3D:
1635 return imageExtent;
1636 default:
1637 unreachable("invalid image type");
1638 }
1639 }
1640
1641 static inline struct VkOffset3D
1642 radv_sanitize_image_offset(const VkImageType imageType,
1643 const struct VkOffset3D imageOffset)
1644 {
1645 switch (imageType) {
1646 case VK_IMAGE_TYPE_1D:
1647 return (VkOffset3D) { imageOffset.x, 0, 0 };
1648 case VK_IMAGE_TYPE_2D:
1649 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1650 case VK_IMAGE_TYPE_3D:
1651 return imageOffset;
1652 default:
1653 unreachable("invalid image type");
1654 }
1655 }
1656
1657 static inline bool
1658 radv_image_extent_compare(const struct radv_image *image,
1659 const VkExtent3D *extent)
1660 {
1661 if (extent->width != image->info.width ||
1662 extent->height != image->info.height ||
1663 extent->depth != image->info.depth)
1664 return false;
1665 return true;
1666 }
1667
1668 struct radv_sampler {
1669 uint32_t state[4];
1670 };
1671
1672 struct radv_color_buffer_info {
1673 uint64_t cb_color_base;
1674 uint64_t cb_color_cmask;
1675 uint64_t cb_color_fmask;
1676 uint64_t cb_dcc_base;
1677 uint32_t cb_color_pitch;
1678 uint32_t cb_color_slice;
1679 uint32_t cb_color_view;
1680 uint32_t cb_color_info;
1681 uint32_t cb_color_attrib;
1682 uint32_t cb_color_attrib2;
1683 uint32_t cb_dcc_control;
1684 uint32_t cb_color_cmask_slice;
1685 uint32_t cb_color_fmask_slice;
1686 };
1687
1688 struct radv_ds_buffer_info {
1689 uint64_t db_z_read_base;
1690 uint64_t db_stencil_read_base;
1691 uint64_t db_z_write_base;
1692 uint64_t db_stencil_write_base;
1693 uint64_t db_htile_data_base;
1694 uint32_t db_depth_info;
1695 uint32_t db_z_info;
1696 uint32_t db_stencil_info;
1697 uint32_t db_depth_view;
1698 uint32_t db_depth_size;
1699 uint32_t db_depth_slice;
1700 uint32_t db_htile_surface;
1701 uint32_t pa_su_poly_offset_db_fmt_cntl;
1702 uint32_t db_z_info2;
1703 uint32_t db_stencil_info2;
1704 float offset_scale;
1705 };
1706
1707 struct radv_attachment_info {
1708 union {
1709 struct radv_color_buffer_info cb;
1710 struct radv_ds_buffer_info ds;
1711 };
1712 struct radv_image_view *attachment;
1713 };
1714
1715 struct radv_framebuffer {
1716 uint32_t width;
1717 uint32_t height;
1718 uint32_t layers;
1719
1720 uint32_t attachment_count;
1721 struct radv_attachment_info attachments[0];
1722 };
1723
1724 struct radv_subpass_barrier {
1725 VkPipelineStageFlags src_stage_mask;
1726 VkAccessFlags src_access_mask;
1727 VkAccessFlags dst_access_mask;
1728 };
1729
1730 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1731 const struct radv_subpass_barrier *barrier);
1732
1733 struct radv_subpass_attachment {
1734 uint32_t attachment;
1735 VkImageLayout layout;
1736 };
1737
1738 struct radv_subpass {
1739 uint32_t input_count;
1740 uint32_t color_count;
1741 struct radv_subpass_attachment * input_attachments;
1742 struct radv_subpass_attachment * color_attachments;
1743 struct radv_subpass_attachment * resolve_attachments;
1744 struct radv_subpass_attachment depth_stencil_attachment;
1745
1746 /** Subpass has at least one resolve attachment */
1747 bool has_resolve;
1748
1749 struct radv_subpass_barrier start_barrier;
1750
1751 uint32_t view_mask;
1752 VkSampleCountFlagBits max_sample_count;
1753 };
1754
1755 struct radv_render_pass_attachment {
1756 VkFormat format;
1757 uint32_t samples;
1758 VkAttachmentLoadOp load_op;
1759 VkAttachmentLoadOp stencil_load_op;
1760 VkImageLayout initial_layout;
1761 VkImageLayout final_layout;
1762 uint32_t view_mask;
1763 };
1764
1765 struct radv_render_pass {
1766 uint32_t attachment_count;
1767 uint32_t subpass_count;
1768 struct radv_subpass_attachment * subpass_attachments;
1769 struct radv_render_pass_attachment * attachments;
1770 struct radv_subpass_barrier end_barrier;
1771 struct radv_subpass subpasses[0];
1772 };
1773
1774 VkResult radv_device_init_meta(struct radv_device *device);
1775 void radv_device_finish_meta(struct radv_device *device);
1776
1777 struct radv_query_pool {
1778 struct radeon_winsys_bo *bo;
1779 uint32_t stride;
1780 uint32_t availability_offset;
1781 uint64_t size;
1782 char *ptr;
1783 VkQueryType type;
1784 uint32_t pipeline_stats_mask;
1785 };
1786
1787 struct radv_semaphore {
1788 /* use a winsys sem for non-exportable */
1789 struct radeon_winsys_sem *sem;
1790 uint32_t syncobj;
1791 uint32_t temp_syncobj;
1792 };
1793
1794 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1795 VkPipelineBindPoint bind_point,
1796 struct radv_descriptor_set *set,
1797 unsigned idx);
1798
1799 void
1800 radv_update_descriptor_sets(struct radv_device *device,
1801 struct radv_cmd_buffer *cmd_buffer,
1802 VkDescriptorSet overrideSet,
1803 uint32_t descriptorWriteCount,
1804 const VkWriteDescriptorSet *pDescriptorWrites,
1805 uint32_t descriptorCopyCount,
1806 const VkCopyDescriptorSet *pDescriptorCopies);
1807
1808 void
1809 radv_update_descriptor_set_with_template(struct radv_device *device,
1810 struct radv_cmd_buffer *cmd_buffer,
1811 struct radv_descriptor_set *set,
1812 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1813 const void *pData);
1814
1815 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1816 VkPipelineBindPoint pipelineBindPoint,
1817 VkPipelineLayout _layout,
1818 uint32_t set,
1819 uint32_t descriptorWriteCount,
1820 const VkWriteDescriptorSet *pDescriptorWrites);
1821
1822 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1823 struct radv_image *image, uint32_t value);
1824
1825 struct radv_fence {
1826 struct radeon_winsys_fence *fence;
1827 struct wsi_fence *fence_wsi;
1828 bool submitted;
1829 bool signalled;
1830
1831 uint32_t syncobj;
1832 uint32_t temp_syncobj;
1833 };
1834
1835 /* radv_nir_to_llvm.c */
1836 struct radv_shader_variant_info;
1837 struct radv_nir_compiler_options;
1838
1839 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
1840 struct nir_shader *geom_shader,
1841 struct ac_shader_binary *binary,
1842 struct ac_shader_config *config,
1843 struct radv_shader_variant_info *shader_info,
1844 const struct radv_nir_compiler_options *option);
1845
1846 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
1847 struct ac_shader_binary *binary,
1848 struct ac_shader_config *config,
1849 struct radv_shader_variant_info *shader_info,
1850 struct nir_shader *const *nir,
1851 int nir_count,
1852 const struct radv_nir_compiler_options *options);
1853
1854 /* radv_shader_info.h */
1855 struct radv_shader_info;
1856
1857 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1858 const struct radv_nir_compiler_options *options,
1859 struct radv_shader_info *info);
1860
1861 struct radeon_winsys_sem;
1862
1863 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1864 \
1865 static inline struct __radv_type * \
1866 __radv_type ## _from_handle(__VkType _handle) \
1867 { \
1868 return (struct __radv_type *) _handle; \
1869 } \
1870 \
1871 static inline __VkType \
1872 __radv_type ## _to_handle(struct __radv_type *_obj) \
1873 { \
1874 return (__VkType) _obj; \
1875 }
1876
1877 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1878 \
1879 static inline struct __radv_type * \
1880 __radv_type ## _from_handle(__VkType _handle) \
1881 { \
1882 return (struct __radv_type *)(uintptr_t) _handle; \
1883 } \
1884 \
1885 static inline __VkType \
1886 __radv_type ## _to_handle(struct __radv_type *_obj) \
1887 { \
1888 return (__VkType)(uintptr_t) _obj; \
1889 }
1890
1891 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1892 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1893
1894 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1895 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1896 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1897 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1898 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1899
1900 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1901 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1902 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1903 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1904 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1905 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1906 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1907 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1908 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1909 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1910 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1911 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1912 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1913 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1914 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1915 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1916 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1917 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1918 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1919 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1920 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1921
1922 #endif /* RADV_PRIVATE_H */