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ac: rename SI-CIK-VI to GFX6-GFX7-GFX8
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
53 #include "vk_alloc.h"
54 #include "vk_debug_report.h"
55
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_descriptor_set.h"
64 #include "radv_extensions.h"
65 #include "radv_cs.h"
66
67 #include <llvm-c/TargetMachine.h>
68
69 /* Pre-declarations needed for WSI entrypoints */
70 struct wl_surface;
71 struct wl_display;
72 typedef struct xcb_connection_t xcb_connection_t;
73 typedef uint32_t xcb_visualid_t;
74 typedef uint32_t xcb_window_t;
75
76 #include <vulkan/vulkan.h>
77 #include <vulkan/vulkan_intel.h>
78 #include <vulkan/vk_icd.h>
79 #include <vulkan/vk_android_native_buffer.h>
80
81 #include "radv_entrypoints.h"
82
83 #include "wsi_common.h"
84 #include "wsi_common_display.h"
85
86 #define ATI_VENDOR_ID 0x1002
87
88 #define MAX_VBS 32
89 #define MAX_VERTEX_ATTRIBS 32
90 #define MAX_RTS 8
91 #define MAX_VIEWPORTS 16
92 #define MAX_SCISSORS 16
93 #define MAX_DISCARD_RECTANGLES 4
94 #define MAX_PUSH_CONSTANTS_SIZE 128
95 #define MAX_PUSH_DESCRIPTORS 32
96 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
97 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
98 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
99 #define MAX_SAMPLES_LOG2 4
100 #define NUM_META_FS_KEYS 12
101 #define RADV_MAX_DRM_DEVICES 8
102 #define MAX_VIEWS 8
103 #define MAX_SO_STREAMS 4
104 #define MAX_SO_BUFFERS 4
105 #define MAX_SO_OUTPUTS 64
106 #define MAX_INLINE_UNIFORM_BLOCK_SIZE (4ull * 1024 * 1024)
107 #define MAX_INLINE_UNIFORM_BLOCK_COUNT 64
108
109 #define NUM_DEPTH_CLEAR_PIPELINES 3
110
111 /*
112 * This is the point we switch from using CP to compute shader
113 * for certain buffer operations.
114 */
115 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
116
117 #define RADV_BUFFER_UPDATE_THRESHOLD 1024
118
119 enum radv_mem_heap {
120 RADV_MEM_HEAP_VRAM,
121 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
122 RADV_MEM_HEAP_GTT,
123 RADV_MEM_HEAP_COUNT
124 };
125
126 enum radv_mem_type {
127 RADV_MEM_TYPE_VRAM,
128 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
129 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
130 RADV_MEM_TYPE_GTT_CACHED,
131 RADV_MEM_TYPE_COUNT
132 };
133
134 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
135
136 static inline uint32_t
137 align_u32(uint32_t v, uint32_t a)
138 {
139 assert(a != 0 && a == (a & -a));
140 return (v + a - 1) & ~(a - 1);
141 }
142
143 static inline uint32_t
144 align_u32_npot(uint32_t v, uint32_t a)
145 {
146 return (v + a - 1) / a * a;
147 }
148
149 static inline uint64_t
150 align_u64(uint64_t v, uint64_t a)
151 {
152 assert(a != 0 && a == (a & -a));
153 return (v + a - 1) & ~(a - 1);
154 }
155
156 static inline int32_t
157 align_i32(int32_t v, int32_t a)
158 {
159 assert(a != 0 && a == (a & -a));
160 return (v + a - 1) & ~(a - 1);
161 }
162
163 /** Alignment must be a power of 2. */
164 static inline bool
165 radv_is_aligned(uintmax_t n, uintmax_t a)
166 {
167 assert(a == (a & -a));
168 return (n & (a - 1)) == 0;
169 }
170
171 static inline uint32_t
172 round_up_u32(uint32_t v, uint32_t a)
173 {
174 return (v + a - 1) / a;
175 }
176
177 static inline uint64_t
178 round_up_u64(uint64_t v, uint64_t a)
179 {
180 return (v + a - 1) / a;
181 }
182
183 static inline uint32_t
184 radv_minify(uint32_t n, uint32_t levels)
185 {
186 if (unlikely(n == 0))
187 return 0;
188 else
189 return MAX2(n >> levels, 1);
190 }
191 static inline float
192 radv_clamp_f(float f, float min, float max)
193 {
194 assert(min < max);
195
196 if (f > max)
197 return max;
198 else if (f < min)
199 return min;
200 else
201 return f;
202 }
203
204 static inline bool
205 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
206 {
207 if (*inout_mask & clear_mask) {
208 *inout_mask &= ~clear_mask;
209 return true;
210 } else {
211 return false;
212 }
213 }
214
215 #define for_each_bit(b, dword) \
216 for (uint32_t __dword = (dword); \
217 (b) = __builtin_ffs(__dword) - 1, __dword; \
218 __dword &= ~(1 << (b)))
219
220 #define typed_memcpy(dest, src, count) ({ \
221 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
222 memcpy((dest), (src), (count) * sizeof(*(src))); \
223 })
224
225 /* Whenever we generate an error, pass it through this function. Useful for
226 * debugging, where we can break on it. Only call at error site, not when
227 * propagating errors. Might be useful to plug in a stack trace here.
228 */
229
230 struct radv_instance;
231
232 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
233
234 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
235 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
236
237 void __radv_finishme(const char *file, int line, const char *format, ...)
238 radv_printflike(3, 4);
239 void radv_loge(const char *format, ...) radv_printflike(1, 2);
240 void radv_loge_v(const char *format, va_list va);
241 void radv_logi(const char *format, ...) radv_printflike(1, 2);
242 void radv_logi_v(const char *format, va_list va);
243
244 /**
245 * Print a FINISHME message, including its source location.
246 */
247 #define radv_finishme(format, ...) \
248 do { \
249 static bool reported = false; \
250 if (!reported) { \
251 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
252 reported = true; \
253 } \
254 } while (0)
255
256 /* A non-fatal assert. Useful for debugging. */
257 #ifdef DEBUG
258 #define radv_assert(x) ({ \
259 if (unlikely(!(x))) \
260 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
261 })
262 #else
263 #define radv_assert(x)
264 #endif
265
266 #define stub_return(v) \
267 do { \
268 radv_finishme("stub %s", __func__); \
269 return (v); \
270 } while (0)
271
272 #define stub() \
273 do { \
274 radv_finishme("stub %s", __func__); \
275 return; \
276 } while (0)
277
278 void *radv_lookup_entrypoint_unchecked(const char *name);
279 void *radv_lookup_entrypoint_checked(const char *name,
280 uint32_t core_version,
281 const struct radv_instance_extension_table *instance,
282 const struct radv_device_extension_table *device);
283 void *radv_lookup_physical_device_entrypoint_checked(const char *name,
284 uint32_t core_version,
285 const struct radv_instance_extension_table *instance);
286
287 struct radv_physical_device {
288 VK_LOADER_DATA _loader_data;
289
290 struct radv_instance * instance;
291
292 struct radeon_winsys *ws;
293 struct radeon_info rad_info;
294 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
295 uint8_t driver_uuid[VK_UUID_SIZE];
296 uint8_t device_uuid[VK_UUID_SIZE];
297 uint8_t cache_uuid[VK_UUID_SIZE];
298
299 int local_fd;
300 int master_fd;
301 struct wsi_device wsi_device;
302
303 bool has_rbplus; /* if RB+ register exist */
304 bool rbplus_allowed; /* if RB+ is allowed */
305 bool has_clear_state;
306 bool cpdma_prefetch_writes_memory;
307 bool has_scissor_bug;
308
309 bool has_out_of_order_rast;
310 bool out_of_order_rast_allowed;
311
312 /* Whether DCC should be enabled for MSAA textures. */
313 bool dcc_msaa_allowed;
314
315 /* Whether LOAD_CONTEXT_REG packets are supported. */
316 bool has_load_ctx_reg_pkt;
317
318 /* This is the drivers on-disk cache used as a fallback as opposed to
319 * the pipeline cache defined by apps.
320 */
321 struct disk_cache * disk_cache;
322
323 VkPhysicalDeviceMemoryProperties memory_properties;
324 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
325
326 drmPciBusInfo bus_info;
327
328 struct radv_device_extension_table supported_extensions;
329 };
330
331 struct radv_instance {
332 VK_LOADER_DATA _loader_data;
333
334 VkAllocationCallbacks alloc;
335
336 uint32_t apiVersion;
337 int physicalDeviceCount;
338 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
339
340 uint64_t debug_flags;
341 uint64_t perftest_flags;
342
343 struct vk_debug_report_instance debug_report_callbacks;
344
345 struct radv_instance_extension_table enabled_extensions;
346
347 struct driOptionCache dri_options;
348 struct driOptionCache available_dri_options;
349 };
350
351 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
352 void radv_finish_wsi(struct radv_physical_device *physical_device);
353
354 bool radv_instance_extension_supported(const char *name);
355 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
356 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
357 const char *name);
358
359 struct cache_entry;
360
361 struct radv_pipeline_cache {
362 struct radv_device * device;
363 pthread_mutex_t mutex;
364
365 uint32_t total_size;
366 uint32_t table_size;
367 uint32_t kernel_count;
368 struct cache_entry ** hash_table;
369 bool modified;
370
371 VkAllocationCallbacks alloc;
372 };
373
374 struct radv_pipeline_key {
375 uint32_t instance_rate_inputs;
376 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
377 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
378 uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
379 uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
380 uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
381 uint64_t vertex_alpha_adjust;
382 uint32_t vertex_post_shuffle;
383 unsigned tess_input_vertices;
384 uint32_t col_format;
385 uint32_t is_int8;
386 uint32_t is_int10;
387 uint8_t log2_ps_iter_samples;
388 uint8_t num_samples;
389 uint32_t has_multiview_view_index : 1;
390 uint32_t optimisations_disabled : 1;
391 };
392
393 void
394 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
395 struct radv_device *device);
396 void
397 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
398 bool
399 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
400 const void *data, size_t size);
401
402 struct radv_shader_variant;
403
404 bool
405 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
406 struct radv_pipeline_cache *cache,
407 const unsigned char *sha1,
408 struct radv_shader_variant **variants,
409 bool *found_in_application_cache);
410
411 void
412 radv_pipeline_cache_insert_shaders(struct radv_device *device,
413 struct radv_pipeline_cache *cache,
414 const unsigned char *sha1,
415 struct radv_shader_variant **variants,
416 const void *const *codes,
417 const unsigned *code_sizes);
418
419 enum radv_blit_ds_layout {
420 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
421 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
422 RADV_BLIT_DS_LAYOUT_COUNT,
423 };
424
425 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
426 {
427 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
428 }
429
430 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
431 {
432 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
433 }
434
435 enum radv_meta_dst_layout {
436 RADV_META_DST_LAYOUT_GENERAL,
437 RADV_META_DST_LAYOUT_OPTIMAL,
438 RADV_META_DST_LAYOUT_COUNT,
439 };
440
441 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
442 {
443 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
444 }
445
446 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
447 {
448 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
449 }
450
451 struct radv_meta_state {
452 VkAllocationCallbacks alloc;
453
454 struct radv_pipeline_cache cache;
455
456 /*
457 * For on-demand pipeline creation, makes sure that
458 * only one thread tries to build a pipeline at the same time.
459 */
460 mtx_t mtx;
461
462 /**
463 * Use array element `i` for images with `2^i` samples.
464 */
465 struct {
466 VkRenderPass render_pass[NUM_META_FS_KEYS];
467 VkPipeline color_pipelines[NUM_META_FS_KEYS];
468
469 VkRenderPass depthstencil_rp;
470 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
471 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
472 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
473 } clear[1 + MAX_SAMPLES_LOG2];
474
475 VkPipelineLayout clear_color_p_layout;
476 VkPipelineLayout clear_depth_p_layout;
477
478 /* Optimized compute fast HTILE clear for stencil or depth only. */
479 VkPipeline clear_htile_mask_pipeline;
480 VkPipelineLayout clear_htile_mask_p_layout;
481 VkDescriptorSetLayout clear_htile_mask_ds_layout;
482
483 struct {
484 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
485
486 /** Pipeline that blits from a 1D image. */
487 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
488
489 /** Pipeline that blits from a 2D image. */
490 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
491
492 /** Pipeline that blits from a 3D image. */
493 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
494
495 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
496 VkPipeline depth_only_1d_pipeline;
497 VkPipeline depth_only_2d_pipeline;
498 VkPipeline depth_only_3d_pipeline;
499
500 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
501 VkPipeline stencil_only_1d_pipeline;
502 VkPipeline stencil_only_2d_pipeline;
503 VkPipeline stencil_only_3d_pipeline;
504 VkPipelineLayout pipeline_layout;
505 VkDescriptorSetLayout ds_layout;
506 } blit;
507
508 struct {
509 VkPipelineLayout p_layouts[5];
510 VkDescriptorSetLayout ds_layouts[5];
511 VkPipeline pipelines[5][NUM_META_FS_KEYS];
512
513 VkPipeline depth_only_pipeline[5];
514
515 VkPipeline stencil_only_pipeline[5];
516 } blit2d[1 + MAX_SAMPLES_LOG2];
517
518 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
519 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
520 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
521
522 struct {
523 VkPipelineLayout img_p_layout;
524 VkDescriptorSetLayout img_ds_layout;
525 VkPipeline pipeline;
526 VkPipeline pipeline_3d;
527 } itob;
528 struct {
529 VkPipelineLayout img_p_layout;
530 VkDescriptorSetLayout img_ds_layout;
531 VkPipeline pipeline;
532 VkPipeline pipeline_3d;
533 } btoi;
534 struct {
535 VkPipelineLayout img_p_layout;
536 VkDescriptorSetLayout img_ds_layout;
537 VkPipeline pipeline;
538 } btoi_r32g32b32;
539 struct {
540 VkPipelineLayout img_p_layout;
541 VkDescriptorSetLayout img_ds_layout;
542 VkPipeline pipeline;
543 VkPipeline pipeline_3d;
544 } itoi;
545 struct {
546 VkPipelineLayout img_p_layout;
547 VkDescriptorSetLayout img_ds_layout;
548 VkPipeline pipeline;
549 } itoi_r32g32b32;
550 struct {
551 VkPipelineLayout img_p_layout;
552 VkDescriptorSetLayout img_ds_layout;
553 VkPipeline pipeline;
554 VkPipeline pipeline_3d;
555 } cleari;
556 struct {
557 VkPipelineLayout img_p_layout;
558 VkDescriptorSetLayout img_ds_layout;
559 VkPipeline pipeline;
560 } cleari_r32g32b32;
561
562 struct {
563 VkPipelineLayout p_layout;
564 VkPipeline pipeline[NUM_META_FS_KEYS];
565 VkRenderPass pass[NUM_META_FS_KEYS];
566 } resolve;
567
568 struct {
569 VkDescriptorSetLayout ds_layout;
570 VkPipelineLayout p_layout;
571 struct {
572 VkPipeline pipeline;
573 VkPipeline i_pipeline;
574 VkPipeline srgb_pipeline;
575 } rc[MAX_SAMPLES_LOG2];
576 } resolve_compute;
577
578 struct {
579 VkDescriptorSetLayout ds_layout;
580 VkPipelineLayout p_layout;
581
582 struct {
583 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
584 VkPipeline pipeline[NUM_META_FS_KEYS];
585 } rc[MAX_SAMPLES_LOG2];
586 } resolve_fragment;
587
588 struct {
589 VkPipelineLayout p_layout;
590 VkPipeline decompress_pipeline;
591 VkPipeline resummarize_pipeline;
592 VkRenderPass pass;
593 } depth_decomp[1 + MAX_SAMPLES_LOG2];
594
595 struct {
596 VkPipelineLayout p_layout;
597 VkPipeline cmask_eliminate_pipeline;
598 VkPipeline fmask_decompress_pipeline;
599 VkPipeline dcc_decompress_pipeline;
600 VkRenderPass pass;
601
602 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
603 VkPipelineLayout dcc_decompress_compute_p_layout;
604 VkPipeline dcc_decompress_compute_pipeline;
605 } fast_clear_flush;
606
607 struct {
608 VkPipelineLayout fill_p_layout;
609 VkPipelineLayout copy_p_layout;
610 VkDescriptorSetLayout fill_ds_layout;
611 VkDescriptorSetLayout copy_ds_layout;
612 VkPipeline fill_pipeline;
613 VkPipeline copy_pipeline;
614 } buffer;
615
616 struct {
617 VkDescriptorSetLayout ds_layout;
618 VkPipelineLayout p_layout;
619 VkPipeline occlusion_query_pipeline;
620 VkPipeline pipeline_statistics_query_pipeline;
621 VkPipeline tfb_query_pipeline;
622 } query;
623
624 struct {
625 VkDescriptorSetLayout ds_layout;
626 VkPipelineLayout p_layout;
627 VkPipeline pipeline[MAX_SAMPLES_LOG2];
628 } fmask_expand;
629 };
630
631 /* queue types */
632 #define RADV_QUEUE_GENERAL 0
633 #define RADV_QUEUE_COMPUTE 1
634 #define RADV_QUEUE_TRANSFER 2
635
636 #define RADV_MAX_QUEUE_FAMILIES 3
637
638 enum ring_type radv_queue_family_to_ring(int f);
639
640 struct radv_queue {
641 VK_LOADER_DATA _loader_data;
642 struct radv_device * device;
643 struct radeon_winsys_ctx *hw_ctx;
644 enum radeon_ctx_priority priority;
645 uint32_t queue_family_index;
646 int queue_idx;
647 VkDeviceQueueCreateFlags flags;
648
649 uint32_t scratch_size;
650 uint32_t compute_scratch_size;
651 uint32_t esgs_ring_size;
652 uint32_t gsvs_ring_size;
653 bool has_tess_rings;
654 bool has_sample_positions;
655
656 struct radeon_winsys_bo *scratch_bo;
657 struct radeon_winsys_bo *descriptor_bo;
658 struct radeon_winsys_bo *compute_scratch_bo;
659 struct radeon_winsys_bo *esgs_ring_bo;
660 struct radeon_winsys_bo *gsvs_ring_bo;
661 struct radeon_winsys_bo *tess_rings_bo;
662 struct radeon_cmdbuf *initial_preamble_cs;
663 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
664 struct radeon_cmdbuf *continue_preamble_cs;
665 };
666
667 struct radv_bo_list {
668 struct radv_winsys_bo_list list;
669 unsigned capacity;
670 pthread_mutex_t mutex;
671 };
672
673 struct radv_device {
674 VK_LOADER_DATA _loader_data;
675
676 VkAllocationCallbacks alloc;
677
678 struct radv_instance * instance;
679 struct radeon_winsys *ws;
680
681 struct radv_meta_state meta_state;
682
683 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
684 int queue_count[RADV_MAX_QUEUE_FAMILIES];
685 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
686
687 bool always_use_syncobj;
688 bool has_distributed_tess;
689 bool pbb_allowed;
690 bool dfsm_allowed;
691 uint32_t tess_offchip_block_dw_size;
692 uint32_t scratch_waves;
693 uint32_t dispatch_initiator;
694
695 uint32_t gs_table_depth;
696
697 /* MSAA sample locations.
698 * The first index is the sample index.
699 * The second index is the coordinate: X, Y. */
700 float sample_locations_1x[1][2];
701 float sample_locations_2x[2][2];
702 float sample_locations_4x[4][2];
703 float sample_locations_8x[8][2];
704 float sample_locations_16x[16][2];
705
706 /* GFX7 and later */
707 uint32_t gfx_init_size_dw;
708 struct radeon_winsys_bo *gfx_init;
709
710 struct radeon_winsys_bo *trace_bo;
711 uint32_t *trace_id_ptr;
712
713 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
714 bool keep_shader_info;
715
716 struct radv_physical_device *physical_device;
717
718 /* Backup in-memory cache to be used if the app doesn't provide one */
719 struct radv_pipeline_cache * mem_cache;
720
721 /*
722 * use different counters so MSAA MRTs get consecutive surface indices,
723 * even if MASK is allocated in between.
724 */
725 uint32_t image_mrt_offset_counter;
726 uint32_t fmask_mrt_offset_counter;
727 struct list_head shader_slabs;
728 mtx_t shader_slab_mutex;
729
730 /* For detecting VM faults reported by dmesg. */
731 uint64_t dmesg_timestamp;
732
733 struct radv_device_extension_table enabled_extensions;
734
735 /* Whether the driver uses a global BO list. */
736 bool use_global_bo_list;
737
738 struct radv_bo_list bo_list;
739
740 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
741 int force_aniso;
742 };
743
744 struct radv_device_memory {
745 struct radeon_winsys_bo *bo;
746 /* for dedicated allocations */
747 struct radv_image *image;
748 struct radv_buffer *buffer;
749 uint32_t type_index;
750 VkDeviceSize map_size;
751 void * map;
752 void * user_ptr;
753 };
754
755
756 struct radv_descriptor_range {
757 uint64_t va;
758 uint32_t size;
759 };
760
761 struct radv_descriptor_set {
762 const struct radv_descriptor_set_layout *layout;
763 uint32_t size;
764
765 struct radeon_winsys_bo *bo;
766 uint64_t va;
767 uint32_t *mapped_ptr;
768 struct radv_descriptor_range *dynamic_descriptors;
769
770 struct radeon_winsys_bo *descriptors[0];
771 };
772
773 struct radv_push_descriptor_set
774 {
775 struct radv_descriptor_set set;
776 uint32_t capacity;
777 };
778
779 struct radv_descriptor_pool_entry {
780 uint32_t offset;
781 uint32_t size;
782 struct radv_descriptor_set *set;
783 };
784
785 struct radv_descriptor_pool {
786 struct radeon_winsys_bo *bo;
787 uint8_t *mapped_ptr;
788 uint64_t current_offset;
789 uint64_t size;
790
791 uint8_t *host_memory_base;
792 uint8_t *host_memory_ptr;
793 uint8_t *host_memory_end;
794
795 uint32_t entry_count;
796 uint32_t max_entry_count;
797 struct radv_descriptor_pool_entry entries[0];
798 };
799
800 struct radv_descriptor_update_template_entry {
801 VkDescriptorType descriptor_type;
802
803 /* The number of descriptors to update */
804 uint32_t descriptor_count;
805
806 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
807 uint32_t dst_offset;
808
809 /* In dwords. Not valid/used for dynamic descriptors */
810 uint32_t dst_stride;
811
812 uint32_t buffer_offset;
813
814 /* Only valid for combined image samplers and samplers */
815 uint8_t has_sampler;
816 uint8_t sampler_offset;
817
818 /* In bytes */
819 size_t src_offset;
820 size_t src_stride;
821
822 /* For push descriptors */
823 const uint32_t *immutable_samplers;
824 };
825
826 struct radv_descriptor_update_template {
827 uint32_t entry_count;
828 VkPipelineBindPoint bind_point;
829 struct radv_descriptor_update_template_entry entry[0];
830 };
831
832 struct radv_buffer {
833 VkDeviceSize size;
834
835 VkBufferUsageFlags usage;
836 VkBufferCreateFlags flags;
837
838 /* Set when bound */
839 struct radeon_winsys_bo * bo;
840 VkDeviceSize offset;
841
842 bool shareable;
843 };
844
845 enum radv_dynamic_state_bits {
846 RADV_DYNAMIC_VIEWPORT = 1 << 0,
847 RADV_DYNAMIC_SCISSOR = 1 << 1,
848 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
849 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
850 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
851 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
852 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
853 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
854 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
855 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
856 RADV_DYNAMIC_ALL = (1 << 10) - 1,
857 };
858
859 enum radv_cmd_dirty_bits {
860 /* Keep the dynamic state dirty bits in sync with
861 * enum radv_dynamic_state_bits */
862 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
863 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
864 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
865 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
866 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
867 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
868 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
869 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
870 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
871 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
872 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
873 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
874 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
875 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
876 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
877 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 14,
878 };
879
880 enum radv_cmd_flush_bits {
881 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
882 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
883 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
884 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
885 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
886 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
887 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
888 /* Same as above, but only writes back and doesn't invalidate */
889 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
890 /* Framebuffer caches */
891 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
892 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
893 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
894 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
895 /* Engine synchronization. */
896 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
897 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
898 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
899 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
900 /* Pipeline query controls. */
901 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
902 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
903 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
904
905 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
906 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
907 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
908 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
909 };
910
911 struct radv_vertex_binding {
912 struct radv_buffer * buffer;
913 VkDeviceSize offset;
914 };
915
916 struct radv_streamout_binding {
917 struct radv_buffer *buffer;
918 VkDeviceSize offset;
919 VkDeviceSize size;
920 };
921
922 struct radv_streamout_state {
923 /* Mask of bound streamout buffers. */
924 uint8_t enabled_mask;
925
926 /* External state that comes from the last vertex stage, it must be
927 * set explicitely when binding a new graphics pipeline.
928 */
929 uint16_t stride_in_dw[MAX_SO_BUFFERS];
930 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
931
932 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
933 uint32_t hw_enabled_mask;
934
935 /* State of VGT_STRMOUT_(CONFIG|EN) */
936 bool streamout_enabled;
937 };
938
939 struct radv_viewport_state {
940 uint32_t count;
941 VkViewport viewports[MAX_VIEWPORTS];
942 };
943
944 struct radv_scissor_state {
945 uint32_t count;
946 VkRect2D scissors[MAX_SCISSORS];
947 };
948
949 struct radv_discard_rectangle_state {
950 uint32_t count;
951 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
952 };
953
954 struct radv_dynamic_state {
955 /**
956 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
957 * Defines the set of saved dynamic state.
958 */
959 uint32_t mask;
960
961 struct radv_viewport_state viewport;
962
963 struct radv_scissor_state scissor;
964
965 float line_width;
966
967 struct {
968 float bias;
969 float clamp;
970 float slope;
971 } depth_bias;
972
973 float blend_constants[4];
974
975 struct {
976 float min;
977 float max;
978 } depth_bounds;
979
980 struct {
981 uint32_t front;
982 uint32_t back;
983 } stencil_compare_mask;
984
985 struct {
986 uint32_t front;
987 uint32_t back;
988 } stencil_write_mask;
989
990 struct {
991 uint32_t front;
992 uint32_t back;
993 } stencil_reference;
994
995 struct radv_discard_rectangle_state discard_rectangle;
996 };
997
998 extern const struct radv_dynamic_state default_dynamic_state;
999
1000 const char *
1001 radv_get_debug_option_name(int id);
1002
1003 const char *
1004 radv_get_perftest_option_name(int id);
1005
1006 /**
1007 * Attachment state when recording a renderpass instance.
1008 *
1009 * The clear value is valid only if there exists a pending clear.
1010 */
1011 struct radv_attachment_state {
1012 VkImageAspectFlags pending_clear_aspects;
1013 uint32_t cleared_views;
1014 VkClearValue clear_value;
1015 VkImageLayout current_layout;
1016 };
1017
1018 struct radv_descriptor_state {
1019 struct radv_descriptor_set *sets[MAX_SETS];
1020 uint32_t dirty;
1021 uint32_t valid;
1022 struct radv_push_descriptor_set push_set;
1023 bool push_dirty;
1024 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1025 };
1026
1027 struct radv_cmd_state {
1028 /* Vertex descriptors */
1029 uint64_t vb_va;
1030 unsigned vb_size;
1031
1032 bool predicating;
1033 uint32_t dirty;
1034
1035 uint32_t prefetch_L2_mask;
1036
1037 struct radv_pipeline * pipeline;
1038 struct radv_pipeline * emitted_pipeline;
1039 struct radv_pipeline * compute_pipeline;
1040 struct radv_pipeline * emitted_compute_pipeline;
1041 struct radv_framebuffer * framebuffer;
1042 struct radv_render_pass * pass;
1043 const struct radv_subpass * subpass;
1044 struct radv_dynamic_state dynamic;
1045 struct radv_attachment_state * attachments;
1046 struct radv_streamout_state streamout;
1047 VkRect2D render_area;
1048
1049 /* Index buffer */
1050 struct radv_buffer *index_buffer;
1051 uint64_t index_offset;
1052 uint32_t index_type;
1053 uint32_t max_index_count;
1054 uint64_t index_va;
1055 int32_t last_index_type;
1056
1057 int32_t last_primitive_reset_en;
1058 uint32_t last_primitive_reset_index;
1059 enum radv_cmd_flush_bits flush_bits;
1060 unsigned active_occlusion_queries;
1061 bool perfect_occlusion_queries_enabled;
1062 unsigned active_pipeline_queries;
1063 float offset_scale;
1064 uint32_t trace_id;
1065 uint32_t last_ia_multi_vgt_param;
1066
1067 uint32_t last_num_instances;
1068 uint32_t last_first_instance;
1069 uint32_t last_vertex_offset;
1070
1071 /* Whether CP DMA is busy/idle. */
1072 bool dma_is_busy;
1073
1074 /* Conditional rendering info. */
1075 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1076 uint64_t predication_va;
1077
1078 bool context_roll_without_scissor_emitted;
1079 };
1080
1081 struct radv_cmd_pool {
1082 VkAllocationCallbacks alloc;
1083 struct list_head cmd_buffers;
1084 struct list_head free_cmd_buffers;
1085 uint32_t queue_family_index;
1086 };
1087
1088 struct radv_cmd_buffer_upload {
1089 uint8_t *map;
1090 unsigned offset;
1091 uint64_t size;
1092 struct radeon_winsys_bo *upload_bo;
1093 struct list_head list;
1094 };
1095
1096 enum radv_cmd_buffer_status {
1097 RADV_CMD_BUFFER_STATUS_INVALID,
1098 RADV_CMD_BUFFER_STATUS_INITIAL,
1099 RADV_CMD_BUFFER_STATUS_RECORDING,
1100 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1101 RADV_CMD_BUFFER_STATUS_PENDING,
1102 };
1103
1104 struct radv_cmd_buffer {
1105 VK_LOADER_DATA _loader_data;
1106
1107 struct radv_device * device;
1108
1109 struct radv_cmd_pool * pool;
1110 struct list_head pool_link;
1111
1112 VkCommandBufferUsageFlags usage_flags;
1113 VkCommandBufferLevel level;
1114 enum radv_cmd_buffer_status status;
1115 struct radeon_cmdbuf *cs;
1116 struct radv_cmd_state state;
1117 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1118 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1119 uint32_t queue_family_index;
1120
1121 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1122 VkShaderStageFlags push_constant_stages;
1123 struct radv_descriptor_set meta_push_descriptors;
1124
1125 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1126
1127 struct radv_cmd_buffer_upload upload;
1128
1129 uint32_t scratch_size_needed;
1130 uint32_t compute_scratch_size_needed;
1131 uint32_t esgs_ring_size_needed;
1132 uint32_t gsvs_ring_size_needed;
1133 bool tess_rings_needed;
1134 bool sample_positions_needed;
1135
1136 VkResult record_result;
1137
1138 uint64_t gfx9_fence_va;
1139 uint32_t gfx9_fence_idx;
1140 uint64_t gfx9_eop_bug_va;
1141
1142 /**
1143 * Whether a query pool has been resetted and we have to flush caches.
1144 */
1145 bool pending_reset_query;
1146 };
1147
1148 struct radv_image;
1149
1150 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1151
1152 void si_emit_graphics(struct radv_physical_device *physical_device,
1153 struct radeon_cmdbuf *cs);
1154 void si_emit_compute(struct radv_physical_device *physical_device,
1155 struct radeon_cmdbuf *cs);
1156
1157 void cik_create_gfx_config(struct radv_device *device);
1158
1159 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1160 int count, const VkViewport *viewports);
1161 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1162 int count, const VkRect2D *scissors,
1163 const VkViewport *viewports, bool can_use_guardband);
1164 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1165 bool instanced_draw, bool indirect_draw,
1166 bool count_from_stream_output,
1167 uint32_t draw_vertex_count);
1168 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1169 enum chip_class chip_class,
1170 bool is_mec,
1171 unsigned event, unsigned event_flags,
1172 unsigned data_sel,
1173 uint64_t va,
1174 uint32_t new_fence,
1175 uint64_t gfx9_eop_bug_va);
1176
1177 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1178 uint32_t ref, uint32_t mask);
1179 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1180 enum chip_class chip_class,
1181 uint32_t *fence_ptr, uint64_t va,
1182 bool is_mec,
1183 enum radv_cmd_flush_bits flush_bits,
1184 uint64_t gfx9_eop_bug_va);
1185 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1186 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1187 bool inverted, uint64_t va);
1188 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1189 uint64_t src_va, uint64_t dest_va,
1190 uint64_t size);
1191 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1192 unsigned size);
1193 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1194 uint64_t size, unsigned value);
1195 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1196
1197 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1198 bool
1199 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1200 unsigned size,
1201 unsigned alignment,
1202 unsigned *out_offset,
1203 void **ptr);
1204 void
1205 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1206 const struct radv_subpass *subpass);
1207 bool
1208 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1209 unsigned size, unsigned alignmnet,
1210 const void *data, unsigned *out_offset);
1211
1212 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1213 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1214 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1215 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1216 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
1217 unsigned radv_cayman_get_maxdist(int log_samples);
1218 void radv_device_init_msaa(struct radv_device *device);
1219
1220 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1221 struct radv_image *image,
1222 VkClearDepthStencilValue ds_clear_value,
1223 VkImageAspectFlags aspects);
1224
1225 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1226 struct radv_image *image,
1227 int cb_idx,
1228 uint32_t color_values[2]);
1229
1230 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1231 struct radv_image *image, bool value);
1232
1233 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1234 struct radv_image *image, bool value);
1235
1236 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1237 struct radeon_winsys_bo *bo,
1238 uint64_t offset, uint64_t size, uint32_t value);
1239 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1240 bool radv_get_memory_fd(struct radv_device *device,
1241 struct radv_device_memory *memory,
1242 int *pFD);
1243
1244 static inline void
1245 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1246 unsigned sh_offset, unsigned pointer_count,
1247 bool use_32bit_pointers)
1248 {
1249 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1250 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1251 }
1252
1253 static inline void
1254 radv_emit_shader_pointer_body(struct radv_device *device,
1255 struct radeon_cmdbuf *cs,
1256 uint64_t va, bool use_32bit_pointers)
1257 {
1258 radeon_emit(cs, va);
1259
1260 if (use_32bit_pointers) {
1261 assert(va == 0 ||
1262 (va >> 32) == device->physical_device->rad_info.address32_hi);
1263 } else {
1264 radeon_emit(cs, va >> 32);
1265 }
1266 }
1267
1268 static inline void
1269 radv_emit_shader_pointer(struct radv_device *device,
1270 struct radeon_cmdbuf *cs,
1271 uint32_t sh_offset, uint64_t va, bool global)
1272 {
1273 bool use_32bit_pointers = !global;
1274
1275 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1276 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1277 }
1278
1279 static inline struct radv_descriptor_state *
1280 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1281 VkPipelineBindPoint bind_point)
1282 {
1283 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1284 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1285 return &cmd_buffer->descriptors[bind_point];
1286 }
1287
1288 /*
1289 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1290 *
1291 * Limitations: Can't call normal dispatch functions without binding or rebinding
1292 * the compute pipeline.
1293 */
1294 void radv_unaligned_dispatch(
1295 struct radv_cmd_buffer *cmd_buffer,
1296 uint32_t x,
1297 uint32_t y,
1298 uint32_t z);
1299
1300 struct radv_event {
1301 struct radeon_winsys_bo *bo;
1302 uint64_t *map;
1303 };
1304
1305 struct radv_shader_module;
1306
1307 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1308 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1309 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1310 void
1311 radv_hash_shaders(unsigned char *hash,
1312 const VkPipelineShaderStageCreateInfo **stages,
1313 const struct radv_pipeline_layout *layout,
1314 const struct radv_pipeline_key *key,
1315 uint32_t flags);
1316
1317 static inline gl_shader_stage
1318 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1319 {
1320 assert(__builtin_popcount(vk_stage) == 1);
1321 return ffs(vk_stage) - 1;
1322 }
1323
1324 static inline VkShaderStageFlagBits
1325 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1326 {
1327 return (1 << mesa_stage);
1328 }
1329
1330 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1331
1332 #define radv_foreach_stage(stage, stage_bits) \
1333 for (gl_shader_stage stage, \
1334 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1335 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1336 __tmp &= ~(1 << (stage)))
1337
1338 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1339 unsigned radv_format_meta_fs_key(VkFormat format);
1340
1341 struct radv_multisample_state {
1342 uint32_t db_eqaa;
1343 uint32_t pa_sc_line_cntl;
1344 uint32_t pa_sc_mode_cntl_0;
1345 uint32_t pa_sc_mode_cntl_1;
1346 uint32_t pa_sc_aa_config;
1347 uint32_t pa_sc_aa_mask[2];
1348 unsigned num_samples;
1349 };
1350
1351 struct radv_prim_vertex_count {
1352 uint8_t min;
1353 uint8_t incr;
1354 };
1355
1356 struct radv_vertex_elements_info {
1357 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1358 };
1359
1360 struct radv_ia_multi_vgt_param_helpers {
1361 uint32_t base;
1362 bool partial_es_wave;
1363 uint8_t primgroup_size;
1364 bool wd_switch_on_eop;
1365 bool ia_switch_on_eoi;
1366 bool partial_vs_wave;
1367 };
1368
1369 #define SI_GS_PER_ES 128
1370
1371 struct radv_pipeline {
1372 struct radv_device * device;
1373 struct radv_dynamic_state dynamic_state;
1374
1375 struct radv_pipeline_layout * layout;
1376
1377 bool need_indirect_descriptor_sets;
1378 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1379 struct radv_shader_variant *gs_copy_shader;
1380 VkShaderStageFlags active_stages;
1381
1382 struct radeon_cmdbuf cs;
1383 uint32_t ctx_cs_hash;
1384 struct radeon_cmdbuf ctx_cs;
1385
1386 struct radv_vertex_elements_info vertex_elements;
1387
1388 uint32_t binding_stride[MAX_VBS];
1389 uint8_t num_vertex_bindings;
1390
1391 uint32_t user_data_0[MESA_SHADER_STAGES];
1392 union {
1393 struct {
1394 struct radv_multisample_state ms;
1395 uint32_t spi_baryc_cntl;
1396 bool prim_restart_enable;
1397 unsigned esgs_ring_size;
1398 unsigned gsvs_ring_size;
1399 uint32_t vtx_base_sgpr;
1400 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1401 uint8_t vtx_emit_num;
1402 struct radv_prim_vertex_count prim_vertex_count;
1403 bool can_use_guardband;
1404 uint32_t needed_dynamic_state;
1405 bool disable_out_of_order_rast_for_occlusion;
1406
1407 /* Used for rbplus */
1408 uint32_t col_format;
1409 uint32_t cb_target_mask;
1410 } graphics;
1411 };
1412
1413 unsigned max_waves;
1414 unsigned scratch_bytes_per_wave;
1415
1416 /* Not NULL if graphics pipeline uses streamout. */
1417 struct radv_shader_variant *streamout_shader;
1418 };
1419
1420 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1421 {
1422 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1423 }
1424
1425 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1426 {
1427 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1428 }
1429
1430 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1431 gl_shader_stage stage,
1432 int idx);
1433
1434 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1435 gl_shader_stage stage);
1436
1437 struct radv_graphics_pipeline_create_info {
1438 bool use_rectlist;
1439 bool db_depth_clear;
1440 bool db_stencil_clear;
1441 bool db_depth_disable_expclear;
1442 bool db_stencil_disable_expclear;
1443 bool db_flush_depth_inplace;
1444 bool db_flush_stencil_inplace;
1445 bool db_resummarize;
1446 uint32_t custom_blend_mode;
1447 };
1448
1449 VkResult
1450 radv_graphics_pipeline_create(VkDevice device,
1451 VkPipelineCache cache,
1452 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1453 const struct radv_graphics_pipeline_create_info *extra,
1454 const VkAllocationCallbacks *alloc,
1455 VkPipeline *pPipeline);
1456
1457 struct vk_format_description;
1458 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1459 int first_non_void);
1460 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1461 int first_non_void);
1462 uint32_t radv_translate_colorformat(VkFormat format);
1463 uint32_t radv_translate_color_numformat(VkFormat format,
1464 const struct vk_format_description *desc,
1465 int first_non_void);
1466 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1467 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1468 uint32_t radv_translate_dbformat(VkFormat format);
1469 uint32_t radv_translate_tex_dataformat(VkFormat format,
1470 const struct vk_format_description *desc,
1471 int first_non_void);
1472 uint32_t radv_translate_tex_numformat(VkFormat format,
1473 const struct vk_format_description *desc,
1474 int first_non_void);
1475 bool radv_format_pack_clear_color(VkFormat format,
1476 uint32_t clear_vals[2],
1477 VkClearColorValue *value);
1478 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1479 bool radv_dcc_formats_compatible(VkFormat format1,
1480 VkFormat format2);
1481 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
1482
1483 struct radv_fmask_info {
1484 uint64_t offset;
1485 uint64_t size;
1486 unsigned alignment;
1487 unsigned pitch_in_pixels;
1488 unsigned bank_height;
1489 unsigned slice_tile_max;
1490 unsigned tile_mode_index;
1491 unsigned tile_swizzle;
1492 };
1493
1494 struct radv_cmask_info {
1495 uint64_t offset;
1496 uint64_t size;
1497 unsigned alignment;
1498 unsigned slice_tile_max;
1499 };
1500
1501
1502 struct radv_image_plane {
1503 VkFormat format;
1504 struct radeon_surf surface;
1505 uint64_t offset;
1506 };
1507
1508 struct radv_image {
1509 VkImageType type;
1510 /* The original VkFormat provided by the client. This may not match any
1511 * of the actual surface formats.
1512 */
1513 VkFormat vk_format;
1514 VkImageAspectFlags aspects;
1515 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1516 struct ac_surf_info info;
1517 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1518 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1519
1520 VkDeviceSize size;
1521 uint32_t alignment;
1522
1523 unsigned queue_family_mask;
1524 bool exclusive;
1525 bool shareable;
1526
1527 /* Set when bound */
1528 struct radeon_winsys_bo *bo;
1529 VkDeviceSize offset;
1530 uint64_t dcc_offset;
1531 uint64_t htile_offset;
1532 bool tc_compatible_htile;
1533
1534 struct radv_fmask_info fmask;
1535 struct radv_cmask_info cmask;
1536 uint64_t clear_value_offset;
1537 uint64_t fce_pred_offset;
1538 uint64_t dcc_pred_offset;
1539
1540 /*
1541 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1542 * stored at this offset is UINT_MAX, the driver will emit
1543 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1544 * SET_CONTEXT_REG packet.
1545 */
1546 uint64_t tc_compat_zrange_offset;
1547
1548 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1549 VkDeviceMemory owned_memory;
1550
1551 unsigned plane_count;
1552 struct radv_image_plane planes[0];
1553 };
1554
1555 /* Whether the image has a htile that is known consistent with the contents of
1556 * the image. */
1557 bool radv_layout_has_htile(const struct radv_image *image,
1558 VkImageLayout layout,
1559 unsigned queue_mask);
1560
1561 /* Whether the image has a htile that is known consistent with the contents of
1562 * the image and is allowed to be in compressed form.
1563 *
1564 * If this is false reads that don't use the htile should be able to return
1565 * correct results.
1566 */
1567 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1568 VkImageLayout layout,
1569 unsigned queue_mask);
1570
1571 bool radv_layout_can_fast_clear(const struct radv_image *image,
1572 VkImageLayout layout,
1573 unsigned queue_mask);
1574
1575 bool radv_layout_dcc_compressed(const struct radv_image *image,
1576 VkImageLayout layout,
1577 unsigned queue_mask);
1578
1579 /**
1580 * Return whether the image has CMASK metadata for color surfaces.
1581 */
1582 static inline bool
1583 radv_image_has_cmask(const struct radv_image *image)
1584 {
1585 return image->cmask.size;
1586 }
1587
1588 /**
1589 * Return whether the image has FMASK metadata for color surfaces.
1590 */
1591 static inline bool
1592 radv_image_has_fmask(const struct radv_image *image)
1593 {
1594 return image->fmask.size;
1595 }
1596
1597 /**
1598 * Return whether the image has DCC metadata for color surfaces.
1599 */
1600 static inline bool
1601 radv_image_has_dcc(const struct radv_image *image)
1602 {
1603 return image->planes[0].surface.dcc_size;
1604 }
1605
1606 /**
1607 * Return whether DCC metadata is enabled for a level.
1608 */
1609 static inline bool
1610 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1611 {
1612 return radv_image_has_dcc(image) &&
1613 level < image->planes[0].surface.num_dcc_levels;
1614 }
1615
1616 /**
1617 * Return whether the image has CB metadata.
1618 */
1619 static inline bool
1620 radv_image_has_CB_metadata(const struct radv_image *image)
1621 {
1622 return radv_image_has_cmask(image) ||
1623 radv_image_has_fmask(image) ||
1624 radv_image_has_dcc(image);
1625 }
1626
1627 /**
1628 * Return whether the image has HTILE metadata for depth surfaces.
1629 */
1630 static inline bool
1631 radv_image_has_htile(const struct radv_image *image)
1632 {
1633 return image->planes[0].surface.htile_size;
1634 }
1635
1636 /**
1637 * Return whether HTILE metadata is enabled for a level.
1638 */
1639 static inline bool
1640 radv_htile_enabled(const struct radv_image *image, unsigned level)
1641 {
1642 return radv_image_has_htile(image) && level == 0;
1643 }
1644
1645 /**
1646 * Return whether the image is TC-compatible HTILE.
1647 */
1648 static inline bool
1649 radv_image_is_tc_compat_htile(const struct radv_image *image)
1650 {
1651 return radv_image_has_htile(image) && image->tc_compatible_htile;
1652 }
1653
1654 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1655
1656 static inline uint32_t
1657 radv_get_layerCount(const struct radv_image *image,
1658 const VkImageSubresourceRange *range)
1659 {
1660 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1661 image->info.array_size - range->baseArrayLayer : range->layerCount;
1662 }
1663
1664 static inline uint32_t
1665 radv_get_levelCount(const struct radv_image *image,
1666 const VkImageSubresourceRange *range)
1667 {
1668 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1669 image->info.levels - range->baseMipLevel : range->levelCount;
1670 }
1671
1672 struct radeon_bo_metadata;
1673 void
1674 radv_init_metadata(struct radv_device *device,
1675 struct radv_image *image,
1676 struct radeon_bo_metadata *metadata);
1677
1678 void
1679 radv_image_override_offset_stride(struct radv_device *device,
1680 struct radv_image *image,
1681 uint64_t offset, uint32_t stride);
1682
1683 union radv_descriptor {
1684 struct {
1685 uint32_t plane0_descriptor[8];
1686 uint32_t fmask_descriptor[8];
1687 };
1688 struct {
1689 uint32_t plane_descriptors[3][8];
1690 };
1691 };
1692
1693 struct radv_image_view {
1694 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1695 struct radeon_winsys_bo *bo;
1696
1697 VkImageViewType type;
1698 VkImageAspectFlags aspect_mask;
1699 VkFormat vk_format;
1700 unsigned plane_id;
1701 bool multiple_planes;
1702 uint32_t base_layer;
1703 uint32_t layer_count;
1704 uint32_t base_mip;
1705 uint32_t level_count;
1706 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1707
1708 union radv_descriptor descriptor;
1709
1710 /* Descriptor for use as a storage image as opposed to a sampled image.
1711 * This has a few differences for cube maps (e.g. type).
1712 */
1713 union radv_descriptor storage_descriptor;
1714 };
1715
1716 struct radv_image_create_info {
1717 const VkImageCreateInfo *vk_info;
1718 bool scanout;
1719 bool no_metadata_planes;
1720 };
1721
1722 VkResult radv_image_create(VkDevice _device,
1723 const struct radv_image_create_info *info,
1724 const VkAllocationCallbacks* alloc,
1725 VkImage *pImage);
1726
1727 VkResult
1728 radv_image_from_gralloc(VkDevice device_h,
1729 const VkImageCreateInfo *base_info,
1730 const VkNativeBufferANDROID *gralloc_info,
1731 const VkAllocationCallbacks *alloc,
1732 VkImage *out_image_h);
1733
1734 void radv_image_view_init(struct radv_image_view *view,
1735 struct radv_device *device,
1736 const VkImageViewCreateInfo* pCreateInfo);
1737
1738 VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
1739
1740 struct radv_sampler_ycbcr_conversion {
1741 VkFormat format;
1742 VkSamplerYcbcrModelConversion ycbcr_model;
1743 VkSamplerYcbcrRange ycbcr_range;
1744 VkComponentMapping components;
1745 VkChromaLocation chroma_offsets[2];
1746 VkFilter chroma_filter;
1747 };
1748
1749 struct radv_buffer_view {
1750 struct radeon_winsys_bo *bo;
1751 VkFormat vk_format;
1752 uint64_t range; /**< VkBufferViewCreateInfo::range */
1753 uint32_t state[4];
1754 };
1755 void radv_buffer_view_init(struct radv_buffer_view *view,
1756 struct radv_device *device,
1757 const VkBufferViewCreateInfo* pCreateInfo);
1758
1759 static inline struct VkExtent3D
1760 radv_sanitize_image_extent(const VkImageType imageType,
1761 const struct VkExtent3D imageExtent)
1762 {
1763 switch (imageType) {
1764 case VK_IMAGE_TYPE_1D:
1765 return (VkExtent3D) { imageExtent.width, 1, 1 };
1766 case VK_IMAGE_TYPE_2D:
1767 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1768 case VK_IMAGE_TYPE_3D:
1769 return imageExtent;
1770 default:
1771 unreachable("invalid image type");
1772 }
1773 }
1774
1775 static inline struct VkOffset3D
1776 radv_sanitize_image_offset(const VkImageType imageType,
1777 const struct VkOffset3D imageOffset)
1778 {
1779 switch (imageType) {
1780 case VK_IMAGE_TYPE_1D:
1781 return (VkOffset3D) { imageOffset.x, 0, 0 };
1782 case VK_IMAGE_TYPE_2D:
1783 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1784 case VK_IMAGE_TYPE_3D:
1785 return imageOffset;
1786 default:
1787 unreachable("invalid image type");
1788 }
1789 }
1790
1791 static inline bool
1792 radv_image_extent_compare(const struct radv_image *image,
1793 const VkExtent3D *extent)
1794 {
1795 if (extent->width != image->info.width ||
1796 extent->height != image->info.height ||
1797 extent->depth != image->info.depth)
1798 return false;
1799 return true;
1800 }
1801
1802 struct radv_sampler {
1803 uint32_t state[4];
1804 struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
1805 };
1806
1807 struct radv_color_buffer_info {
1808 uint64_t cb_color_base;
1809 uint64_t cb_color_cmask;
1810 uint64_t cb_color_fmask;
1811 uint64_t cb_dcc_base;
1812 uint32_t cb_color_slice;
1813 uint32_t cb_color_view;
1814 uint32_t cb_color_info;
1815 uint32_t cb_color_attrib;
1816 uint32_t cb_color_attrib2;
1817 uint32_t cb_dcc_control;
1818 uint32_t cb_color_cmask_slice;
1819 uint32_t cb_color_fmask_slice;
1820 union {
1821 uint32_t cb_color_pitch; // GFX6-GFX8
1822 uint32_t cb_mrt_epitch; // GFX9+
1823 };
1824 };
1825
1826 struct radv_ds_buffer_info {
1827 uint64_t db_z_read_base;
1828 uint64_t db_stencil_read_base;
1829 uint64_t db_z_write_base;
1830 uint64_t db_stencil_write_base;
1831 uint64_t db_htile_data_base;
1832 uint32_t db_depth_info;
1833 uint32_t db_z_info;
1834 uint32_t db_stencil_info;
1835 uint32_t db_depth_view;
1836 uint32_t db_depth_size;
1837 uint32_t db_depth_slice;
1838 uint32_t db_htile_surface;
1839 uint32_t pa_su_poly_offset_db_fmt_cntl;
1840 uint32_t db_z_info2;
1841 uint32_t db_stencil_info2;
1842 float offset_scale;
1843 };
1844
1845 struct radv_attachment_info {
1846 union {
1847 struct radv_color_buffer_info cb;
1848 struct radv_ds_buffer_info ds;
1849 };
1850 struct radv_image_view *attachment;
1851 };
1852
1853 struct radv_framebuffer {
1854 uint32_t width;
1855 uint32_t height;
1856 uint32_t layers;
1857
1858 uint32_t attachment_count;
1859 struct radv_attachment_info attachments[0];
1860 };
1861
1862 struct radv_subpass_barrier {
1863 VkPipelineStageFlags src_stage_mask;
1864 VkAccessFlags src_access_mask;
1865 VkAccessFlags dst_access_mask;
1866 };
1867
1868 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1869 const struct radv_subpass_barrier *barrier);
1870
1871 struct radv_subpass_attachment {
1872 uint32_t attachment;
1873 VkImageLayout layout;
1874 };
1875
1876 struct radv_subpass {
1877 uint32_t attachment_count;
1878 struct radv_subpass_attachment * attachments;
1879
1880 uint32_t input_count;
1881 uint32_t color_count;
1882 struct radv_subpass_attachment * input_attachments;
1883 struct radv_subpass_attachment * color_attachments;
1884 struct radv_subpass_attachment * resolve_attachments;
1885 struct radv_subpass_attachment * depth_stencil_attachment;
1886
1887 /** Subpass has at least one resolve attachment */
1888 bool has_resolve;
1889
1890 /** Subpass has at least one color attachment */
1891 bool has_color_att;
1892
1893 struct radv_subpass_barrier start_barrier;
1894
1895 uint32_t view_mask;
1896 VkSampleCountFlagBits max_sample_count;
1897 };
1898
1899 struct radv_render_pass_attachment {
1900 VkFormat format;
1901 uint32_t samples;
1902 VkAttachmentLoadOp load_op;
1903 VkAttachmentLoadOp stencil_load_op;
1904 VkImageLayout initial_layout;
1905 VkImageLayout final_layout;
1906
1907 /* The subpass id in which the attachment will be used last. */
1908 uint32_t last_subpass_idx;
1909 };
1910
1911 struct radv_render_pass {
1912 uint32_t attachment_count;
1913 uint32_t subpass_count;
1914 struct radv_subpass_attachment * subpass_attachments;
1915 struct radv_render_pass_attachment * attachments;
1916 struct radv_subpass_barrier end_barrier;
1917 struct radv_subpass subpasses[0];
1918 };
1919
1920 VkResult radv_device_init_meta(struct radv_device *device);
1921 void radv_device_finish_meta(struct radv_device *device);
1922
1923 struct radv_query_pool {
1924 struct radeon_winsys_bo *bo;
1925 uint32_t stride;
1926 uint32_t availability_offset;
1927 uint64_t size;
1928 char *ptr;
1929 VkQueryType type;
1930 uint32_t pipeline_stats_mask;
1931 };
1932
1933 struct radv_semaphore {
1934 /* use a winsys sem for non-exportable */
1935 struct radeon_winsys_sem *sem;
1936 uint32_t syncobj;
1937 uint32_t temp_syncobj;
1938 };
1939
1940 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1941 VkPipelineBindPoint bind_point,
1942 struct radv_descriptor_set *set,
1943 unsigned idx);
1944
1945 void
1946 radv_update_descriptor_sets(struct radv_device *device,
1947 struct radv_cmd_buffer *cmd_buffer,
1948 VkDescriptorSet overrideSet,
1949 uint32_t descriptorWriteCount,
1950 const VkWriteDescriptorSet *pDescriptorWrites,
1951 uint32_t descriptorCopyCount,
1952 const VkCopyDescriptorSet *pDescriptorCopies);
1953
1954 void
1955 radv_update_descriptor_set_with_template(struct radv_device *device,
1956 struct radv_cmd_buffer *cmd_buffer,
1957 struct radv_descriptor_set *set,
1958 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1959 const void *pData);
1960
1961 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1962 VkPipelineBindPoint pipelineBindPoint,
1963 VkPipelineLayout _layout,
1964 uint32_t set,
1965 uint32_t descriptorWriteCount,
1966 const VkWriteDescriptorSet *pDescriptorWrites);
1967
1968 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1969 struct radv_image *image, uint32_t value);
1970
1971 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
1972 struct radv_image *image);
1973
1974 struct radv_fence {
1975 struct radeon_winsys_fence *fence;
1976 struct wsi_fence *fence_wsi;
1977
1978 uint32_t syncobj;
1979 uint32_t temp_syncobj;
1980 };
1981
1982 /* radv_nir_to_llvm.c */
1983 struct radv_shader_variant_info;
1984 struct radv_nir_compiler_options;
1985
1986 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
1987 struct nir_shader *geom_shader,
1988 struct ac_shader_binary *binary,
1989 struct ac_shader_config *config,
1990 struct radv_shader_variant_info *shader_info,
1991 const struct radv_nir_compiler_options *option);
1992
1993 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
1994 struct ac_shader_binary *binary,
1995 struct ac_shader_config *config,
1996 struct radv_shader_variant_info *shader_info,
1997 struct nir_shader *const *nir,
1998 int nir_count,
1999 const struct radv_nir_compiler_options *options);
2000
2001 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
2002 const struct nir_shader *nir);
2003
2004 /* radv_shader_info.h */
2005 struct radv_shader_info;
2006
2007 void radv_nir_shader_info_pass(const struct nir_shader *nir,
2008 const struct radv_nir_compiler_options *options,
2009 struct radv_shader_info *info);
2010
2011 void radv_nir_shader_info_init(struct radv_shader_info *info);
2012
2013 struct radeon_winsys_sem;
2014
2015 uint64_t radv_get_current_time(void);
2016
2017 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2018 \
2019 static inline struct __radv_type * \
2020 __radv_type ## _from_handle(__VkType _handle) \
2021 { \
2022 return (struct __radv_type *) _handle; \
2023 } \
2024 \
2025 static inline __VkType \
2026 __radv_type ## _to_handle(struct __radv_type *_obj) \
2027 { \
2028 return (__VkType) _obj; \
2029 }
2030
2031 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2032 \
2033 static inline struct __radv_type * \
2034 __radv_type ## _from_handle(__VkType _handle) \
2035 { \
2036 return (struct __radv_type *)(uintptr_t) _handle; \
2037 } \
2038 \
2039 static inline __VkType \
2040 __radv_type ## _to_handle(struct __radv_type *_obj) \
2041 { \
2042 return (__VkType)(uintptr_t) _obj; \
2043 }
2044
2045 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2046 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2047
2048 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
2049 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
2050 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
2051 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
2052 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
2053
2054 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
2055 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
2056 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
2057 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
2058 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
2059 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
2060 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
2061 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
2062 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
2063 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
2064 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
2065 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
2066 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
2067 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
2068 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
2069 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2070 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2071 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2072 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2073 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
2074 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2075 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2076
2077 #endif /* RADV_PRIVATE_H */