2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
54 #include "vk_debug_report.h"
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_descriptor_set.h"
64 #include "radv_extensions.h"
67 #include <llvm-c/TargetMachine.h>
69 /* Pre-declarations needed for WSI entrypoints */
72 typedef struct xcb_connection_t xcb_connection_t
;
73 typedef uint32_t xcb_visualid_t
;
74 typedef uint32_t xcb_window_t
;
76 #include <vulkan/vulkan.h>
77 #include <vulkan/vulkan_intel.h>
78 #include <vulkan/vk_icd.h>
79 #include <vulkan/vk_android_native_buffer.h>
81 #include "radv_entrypoints.h"
83 #include "wsi_common.h"
84 #include "wsi_common_display.h"
86 #define ATI_VENDOR_ID 0x1002
89 #define MAX_VERTEX_ATTRIBS 32
91 #define MAX_VIEWPORTS 16
92 #define MAX_SCISSORS 16
93 #define MAX_DISCARD_RECTANGLES 4
94 #define MAX_SAMPLE_LOCATIONS 32
95 #define MAX_PUSH_CONSTANTS_SIZE 128
96 #define MAX_PUSH_DESCRIPTORS 32
97 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
98 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
99 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
100 #define MAX_SAMPLES_LOG2 4
101 #define NUM_META_FS_KEYS 12
102 #define RADV_MAX_DRM_DEVICES 8
104 #define MAX_SO_STREAMS 4
105 #define MAX_SO_BUFFERS 4
106 #define MAX_SO_OUTPUTS 64
107 #define MAX_INLINE_UNIFORM_BLOCK_SIZE (4ull * 1024 * 1024)
108 #define MAX_INLINE_UNIFORM_BLOCK_COUNT 64
110 #define NUM_DEPTH_CLEAR_PIPELINES 3
113 * This is the point we switch from using CP to compute shader
114 * for certain buffer operations.
116 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
118 #define RADV_BUFFER_UPDATE_THRESHOLD 1024
122 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
129 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
130 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
131 RADV_MEM_TYPE_GTT_CACHED
,
135 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
137 static inline uint32_t
138 align_u32(uint32_t v
, uint32_t a
)
140 assert(a
!= 0 && a
== (a
& -a
));
141 return (v
+ a
- 1) & ~(a
- 1);
144 static inline uint32_t
145 align_u32_npot(uint32_t v
, uint32_t a
)
147 return (v
+ a
- 1) / a
* a
;
150 static inline uint64_t
151 align_u64(uint64_t v
, uint64_t a
)
153 assert(a
!= 0 && a
== (a
& -a
));
154 return (v
+ a
- 1) & ~(a
- 1);
157 static inline int32_t
158 align_i32(int32_t v
, int32_t a
)
160 assert(a
!= 0 && a
== (a
& -a
));
161 return (v
+ a
- 1) & ~(a
- 1);
164 /** Alignment must be a power of 2. */
166 radv_is_aligned(uintmax_t n
, uintmax_t a
)
168 assert(a
== (a
& -a
));
169 return (n
& (a
- 1)) == 0;
172 static inline uint32_t
173 round_up_u32(uint32_t v
, uint32_t a
)
175 return (v
+ a
- 1) / a
;
178 static inline uint64_t
179 round_up_u64(uint64_t v
, uint64_t a
)
181 return (v
+ a
- 1) / a
;
184 static inline uint32_t
185 radv_minify(uint32_t n
, uint32_t levels
)
187 if (unlikely(n
== 0))
190 return MAX2(n
>> levels
, 1);
193 radv_clamp_f(float f
, float min
, float max
)
206 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
208 if (*inout_mask
& clear_mask
) {
209 *inout_mask
&= ~clear_mask
;
216 #define for_each_bit(b, dword) \
217 for (uint32_t __dword = (dword); \
218 (b) = __builtin_ffs(__dword) - 1, __dword; \
219 __dword &= ~(1 << (b)))
221 #define typed_memcpy(dest, src, count) ({ \
222 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
223 memcpy((dest), (src), (count) * sizeof(*(src))); \
226 /* Whenever we generate an error, pass it through this function. Useful for
227 * debugging, where we can break on it. Only call at error site, not when
228 * propagating errors. Might be useful to plug in a stack trace here.
231 struct radv_instance
;
233 VkResult
__vk_errorf(struct radv_instance
*instance
, VkResult error
, const char *file
, int line
, const char *format
, ...);
235 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
236 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
238 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
239 radv_printflike(3, 4);
240 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
241 void radv_loge_v(const char *format
, va_list va
);
242 void radv_logi(const char *format
, ...) radv_printflike(1, 2);
243 void radv_logi_v(const char *format
, va_list va
);
246 * Print a FINISHME message, including its source location.
248 #define radv_finishme(format, ...) \
250 static bool reported = false; \
252 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
257 /* A non-fatal assert. Useful for debugging. */
259 #define radv_assert(x) ({ \
260 if (unlikely(!(x))) \
261 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
264 #define radv_assert(x)
267 #define stub_return(v) \
269 radv_finishme("stub %s", __func__); \
275 radv_finishme("stub %s", __func__); \
279 void *radv_lookup_entrypoint_unchecked(const char *name
);
280 void *radv_lookup_entrypoint_checked(const char *name
,
281 uint32_t core_version
,
282 const struct radv_instance_extension_table
*instance
,
283 const struct radv_device_extension_table
*device
);
284 void *radv_lookup_physical_device_entrypoint_checked(const char *name
,
285 uint32_t core_version
,
286 const struct radv_instance_extension_table
*instance
);
288 struct radv_physical_device
{
289 VK_LOADER_DATA _loader_data
;
291 struct radv_instance
* instance
;
293 struct radeon_winsys
*ws
;
294 struct radeon_info rad_info
;
295 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
296 uint8_t driver_uuid
[VK_UUID_SIZE
];
297 uint8_t device_uuid
[VK_UUID_SIZE
];
298 uint8_t cache_uuid
[VK_UUID_SIZE
];
302 struct wsi_device wsi_device
;
304 bool has_rbplus
; /* if RB+ register exist */
305 bool rbplus_allowed
; /* if RB+ is allowed */
306 bool has_clear_state
;
307 bool cpdma_prefetch_writes_memory
;
308 bool has_scissor_bug
;
310 bool has_out_of_order_rast
;
311 bool out_of_order_rast_allowed
;
313 /* Whether DCC should be enabled for MSAA textures. */
314 bool dcc_msaa_allowed
;
316 /* Whether LOAD_CONTEXT_REG packets are supported. */
317 bool has_load_ctx_reg_pkt
;
319 /* Whether to enable the AMD_shader_ballot extension */
320 bool use_shader_ballot
;
322 /* This is the drivers on-disk cache used as a fallback as opposed to
323 * the pipeline cache defined by apps.
325 struct disk_cache
* disk_cache
;
327 VkPhysicalDeviceMemoryProperties memory_properties
;
328 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
330 drmPciBusInfo bus_info
;
332 struct radv_device_extension_table supported_extensions
;
335 struct radv_instance
{
336 VK_LOADER_DATA _loader_data
;
338 VkAllocationCallbacks alloc
;
341 int physicalDeviceCount
;
342 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
344 uint64_t debug_flags
;
345 uint64_t perftest_flags
;
347 struct vk_debug_report_instance debug_report_callbacks
;
349 struct radv_instance_extension_table enabled_extensions
;
351 struct driOptionCache dri_options
;
352 struct driOptionCache available_dri_options
;
355 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
356 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
358 bool radv_instance_extension_supported(const char *name
);
359 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
360 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
365 struct radv_pipeline_cache
{
366 struct radv_device
* device
;
367 pthread_mutex_t mutex
;
371 uint32_t kernel_count
;
372 struct cache_entry
** hash_table
;
375 VkAllocationCallbacks alloc
;
378 struct radv_pipeline_key
{
379 uint32_t instance_rate_inputs
;
380 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
381 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
382 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
383 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
384 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
385 uint64_t vertex_alpha_adjust
;
386 uint32_t vertex_post_shuffle
;
387 unsigned tess_input_vertices
;
391 uint8_t log2_ps_iter_samples
;
393 uint32_t has_multiview_view_index
: 1;
394 uint32_t optimisations_disabled
: 1;
398 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
399 struct radv_device
*device
);
401 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
403 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
404 const void *data
, size_t size
);
406 struct radv_shader_variant
;
409 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
410 struct radv_pipeline_cache
*cache
,
411 const unsigned char *sha1
,
412 struct radv_shader_variant
**variants
,
413 bool *found_in_application_cache
);
416 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
417 struct radv_pipeline_cache
*cache
,
418 const unsigned char *sha1
,
419 struct radv_shader_variant
**variants
,
420 const void *const *codes
,
421 const unsigned *code_sizes
);
423 enum radv_blit_ds_layout
{
424 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
425 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
426 RADV_BLIT_DS_LAYOUT_COUNT
,
429 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
431 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
434 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
436 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
439 enum radv_meta_dst_layout
{
440 RADV_META_DST_LAYOUT_GENERAL
,
441 RADV_META_DST_LAYOUT_OPTIMAL
,
442 RADV_META_DST_LAYOUT_COUNT
,
445 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
447 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
450 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
452 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
455 struct radv_meta_state
{
456 VkAllocationCallbacks alloc
;
458 struct radv_pipeline_cache cache
;
461 * For on-demand pipeline creation, makes sure that
462 * only one thread tries to build a pipeline at the same time.
467 * Use array element `i` for images with `2^i` samples.
470 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
471 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
473 VkRenderPass depthstencil_rp
;
474 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
475 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
476 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
477 } clear
[1 + MAX_SAMPLES_LOG2
];
479 VkPipelineLayout clear_color_p_layout
;
480 VkPipelineLayout clear_depth_p_layout
;
482 /* Optimized compute fast HTILE clear for stencil or depth only. */
483 VkPipeline clear_htile_mask_pipeline
;
484 VkPipelineLayout clear_htile_mask_p_layout
;
485 VkDescriptorSetLayout clear_htile_mask_ds_layout
;
488 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
490 /** Pipeline that blits from a 1D image. */
491 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
493 /** Pipeline that blits from a 2D image. */
494 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
496 /** Pipeline that blits from a 3D image. */
497 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
499 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
500 VkPipeline depth_only_1d_pipeline
;
501 VkPipeline depth_only_2d_pipeline
;
502 VkPipeline depth_only_3d_pipeline
;
504 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
505 VkPipeline stencil_only_1d_pipeline
;
506 VkPipeline stencil_only_2d_pipeline
;
507 VkPipeline stencil_only_3d_pipeline
;
508 VkPipelineLayout pipeline_layout
;
509 VkDescriptorSetLayout ds_layout
;
513 VkPipelineLayout p_layouts
[5];
514 VkDescriptorSetLayout ds_layouts
[5];
515 VkPipeline pipelines
[5][NUM_META_FS_KEYS
];
517 VkPipeline depth_only_pipeline
[5];
519 VkPipeline stencil_only_pipeline
[5];
520 } blit2d
[1 + MAX_SAMPLES_LOG2
];
522 VkRenderPass blit2d_render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
523 VkRenderPass blit2d_depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
524 VkRenderPass blit2d_stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
527 VkPipelineLayout img_p_layout
;
528 VkDescriptorSetLayout img_ds_layout
;
530 VkPipeline pipeline_3d
;
533 VkPipelineLayout img_p_layout
;
534 VkDescriptorSetLayout img_ds_layout
;
536 VkPipeline pipeline_3d
;
539 VkPipelineLayout img_p_layout
;
540 VkDescriptorSetLayout img_ds_layout
;
544 VkPipelineLayout img_p_layout
;
545 VkDescriptorSetLayout img_ds_layout
;
547 VkPipeline pipeline_3d
;
550 VkPipelineLayout img_p_layout
;
551 VkDescriptorSetLayout img_ds_layout
;
555 VkPipelineLayout img_p_layout
;
556 VkDescriptorSetLayout img_ds_layout
;
558 VkPipeline pipeline_3d
;
561 VkPipelineLayout img_p_layout
;
562 VkDescriptorSetLayout img_ds_layout
;
567 VkPipelineLayout p_layout
;
568 VkPipeline pipeline
[NUM_META_FS_KEYS
];
569 VkRenderPass pass
[NUM_META_FS_KEYS
];
573 VkDescriptorSetLayout ds_layout
;
574 VkPipelineLayout p_layout
;
577 VkPipeline i_pipeline
;
578 VkPipeline srgb_pipeline
;
579 } rc
[MAX_SAMPLES_LOG2
];
583 VkDescriptorSetLayout ds_layout
;
584 VkPipelineLayout p_layout
;
587 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
588 VkPipeline pipeline
[NUM_META_FS_KEYS
];
589 } rc
[MAX_SAMPLES_LOG2
];
591 VkRenderPass depth_render_pass
;
592 VkPipeline depth_zero_pipeline
;
594 VkPipeline average_pipeline
;
595 VkPipeline max_pipeline
;
596 VkPipeline min_pipeline
;
597 } depth
[MAX_SAMPLES_LOG2
];
599 VkRenderPass stencil_render_pass
;
600 VkPipeline stencil_zero_pipeline
;
602 VkPipeline max_pipeline
;
603 VkPipeline min_pipeline
;
604 } stencil
[MAX_SAMPLES_LOG2
];
608 VkPipelineLayout p_layout
;
609 VkPipeline decompress_pipeline
;
610 VkPipeline resummarize_pipeline
;
612 } depth_decomp
[1 + MAX_SAMPLES_LOG2
];
615 VkPipelineLayout p_layout
;
616 VkPipeline cmask_eliminate_pipeline
;
617 VkPipeline fmask_decompress_pipeline
;
618 VkPipeline dcc_decompress_pipeline
;
621 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
622 VkPipelineLayout dcc_decompress_compute_p_layout
;
623 VkPipeline dcc_decompress_compute_pipeline
;
627 VkPipelineLayout fill_p_layout
;
628 VkPipelineLayout copy_p_layout
;
629 VkDescriptorSetLayout fill_ds_layout
;
630 VkDescriptorSetLayout copy_ds_layout
;
631 VkPipeline fill_pipeline
;
632 VkPipeline copy_pipeline
;
636 VkDescriptorSetLayout ds_layout
;
637 VkPipelineLayout p_layout
;
638 VkPipeline occlusion_query_pipeline
;
639 VkPipeline pipeline_statistics_query_pipeline
;
640 VkPipeline tfb_query_pipeline
;
644 VkDescriptorSetLayout ds_layout
;
645 VkPipelineLayout p_layout
;
646 VkPipeline pipeline
[MAX_SAMPLES_LOG2
];
651 #define RADV_QUEUE_GENERAL 0
652 #define RADV_QUEUE_COMPUTE 1
653 #define RADV_QUEUE_TRANSFER 2
655 #define RADV_MAX_QUEUE_FAMILIES 3
657 enum ring_type
radv_queue_family_to_ring(int f
);
660 VK_LOADER_DATA _loader_data
;
661 struct radv_device
* device
;
662 struct radeon_winsys_ctx
*hw_ctx
;
663 enum radeon_ctx_priority priority
;
664 uint32_t queue_family_index
;
666 VkDeviceQueueCreateFlags flags
;
668 uint32_t scratch_size
;
669 uint32_t compute_scratch_size
;
670 uint32_t esgs_ring_size
;
671 uint32_t gsvs_ring_size
;
673 bool has_sample_positions
;
675 struct radeon_winsys_bo
*scratch_bo
;
676 struct radeon_winsys_bo
*descriptor_bo
;
677 struct radeon_winsys_bo
*compute_scratch_bo
;
678 struct radeon_winsys_bo
*esgs_ring_bo
;
679 struct radeon_winsys_bo
*gsvs_ring_bo
;
680 struct radeon_winsys_bo
*tess_rings_bo
;
681 struct radeon_cmdbuf
*initial_preamble_cs
;
682 struct radeon_cmdbuf
*initial_full_flush_preamble_cs
;
683 struct radeon_cmdbuf
*continue_preamble_cs
;
686 struct radv_bo_list
{
687 struct radv_winsys_bo_list list
;
689 pthread_mutex_t mutex
;
693 VK_LOADER_DATA _loader_data
;
695 VkAllocationCallbacks alloc
;
697 struct radv_instance
* instance
;
698 struct radeon_winsys
*ws
;
700 struct radv_meta_state meta_state
;
702 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
703 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
704 struct radeon_cmdbuf
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
706 bool always_use_syncobj
;
707 bool has_distributed_tess
;
710 uint32_t tess_offchip_block_dw_size
;
711 uint32_t scratch_waves
;
712 uint32_t dispatch_initiator
;
714 uint32_t gs_table_depth
;
716 /* MSAA sample locations.
717 * The first index is the sample index.
718 * The second index is the coordinate: X, Y. */
719 float sample_locations_1x
[1][2];
720 float sample_locations_2x
[2][2];
721 float sample_locations_4x
[4][2];
722 float sample_locations_8x
[8][2];
725 uint32_t gfx_init_size_dw
;
726 struct radeon_winsys_bo
*gfx_init
;
728 struct radeon_winsys_bo
*trace_bo
;
729 uint32_t *trace_id_ptr
;
731 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
732 bool keep_shader_info
;
734 struct radv_physical_device
*physical_device
;
736 /* Backup in-memory cache to be used if the app doesn't provide one */
737 struct radv_pipeline_cache
* mem_cache
;
740 * use different counters so MSAA MRTs get consecutive surface indices,
741 * even if MASK is allocated in between.
743 uint32_t image_mrt_offset_counter
;
744 uint32_t fmask_mrt_offset_counter
;
745 struct list_head shader_slabs
;
746 mtx_t shader_slab_mutex
;
748 /* For detecting VM faults reported by dmesg. */
749 uint64_t dmesg_timestamp
;
751 struct radv_device_extension_table enabled_extensions
;
753 /* Whether the driver uses a global BO list. */
754 bool use_global_bo_list
;
756 struct radv_bo_list bo_list
;
758 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
762 struct radv_device_memory
{
763 struct radeon_winsys_bo
*bo
;
764 /* for dedicated allocations */
765 struct radv_image
*image
;
766 struct radv_buffer
*buffer
;
768 VkDeviceSize map_size
;
774 struct radv_descriptor_range
{
779 struct radv_descriptor_set
{
780 const struct radv_descriptor_set_layout
*layout
;
783 struct radeon_winsys_bo
*bo
;
785 uint32_t *mapped_ptr
;
786 struct radv_descriptor_range
*dynamic_descriptors
;
788 struct radeon_winsys_bo
*descriptors
[0];
791 struct radv_push_descriptor_set
793 struct radv_descriptor_set set
;
797 struct radv_descriptor_pool_entry
{
800 struct radv_descriptor_set
*set
;
803 struct radv_descriptor_pool
{
804 struct radeon_winsys_bo
*bo
;
806 uint64_t current_offset
;
809 uint8_t *host_memory_base
;
810 uint8_t *host_memory_ptr
;
811 uint8_t *host_memory_end
;
813 uint32_t entry_count
;
814 uint32_t max_entry_count
;
815 struct radv_descriptor_pool_entry entries
[0];
818 struct radv_descriptor_update_template_entry
{
819 VkDescriptorType descriptor_type
;
821 /* The number of descriptors to update */
822 uint32_t descriptor_count
;
824 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
827 /* In dwords. Not valid/used for dynamic descriptors */
830 uint32_t buffer_offset
;
832 /* Only valid for combined image samplers and samplers */
834 uint8_t sampler_offset
;
840 /* For push descriptors */
841 const uint32_t *immutable_samplers
;
844 struct radv_descriptor_update_template
{
845 uint32_t entry_count
;
846 VkPipelineBindPoint bind_point
;
847 struct radv_descriptor_update_template_entry entry
[0];
853 VkBufferUsageFlags usage
;
854 VkBufferCreateFlags flags
;
857 struct radeon_winsys_bo
* bo
;
863 enum radv_dynamic_state_bits
{
864 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
865 RADV_DYNAMIC_SCISSOR
= 1 << 1,
866 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
867 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
868 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
869 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
870 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
871 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
872 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
873 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
874 RADV_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
875 RADV_DYNAMIC_ALL
= (1 << 11) - 1,
878 enum radv_cmd_dirty_bits
{
879 /* Keep the dynamic state dirty bits in sync with
880 * enum radv_dynamic_state_bits */
881 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
882 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
883 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
884 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
885 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
886 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
887 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
888 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
889 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
890 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
891 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
892 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 11) - 1,
893 RADV_CMD_DIRTY_PIPELINE
= 1 << 11,
894 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 12,
895 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 13,
896 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 14,
897 RADV_CMD_DIRTY_STREAMOUT_BUFFER
= 1 << 15,
900 enum radv_cmd_flush_bits
{
901 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
902 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
903 RADV_CMD_FLAG_INV_SMEM_L1
= 1 << 1,
904 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
905 RADV_CMD_FLAG_INV_VMEM_L1
= 1 << 2,
906 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
907 RADV_CMD_FLAG_INV_GLOBAL_L2
= 1 << 3,
908 /* Same as above, but only writes back and doesn't invalidate */
909 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
= 1 << 4,
910 /* Framebuffer caches */
911 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
912 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
913 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
914 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
915 /* Engine synchronization. */
916 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
917 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
918 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
919 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
920 /* Pipeline query controls. */
921 RADV_CMD_FLAG_START_PIPELINE_STATS
= 1 << 13,
922 RADV_CMD_FLAG_STOP_PIPELINE_STATS
= 1 << 14,
923 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
= 1 << 15,
925 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
926 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
927 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
928 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
931 struct radv_vertex_binding
{
932 struct radv_buffer
* buffer
;
936 struct radv_streamout_binding
{
937 struct radv_buffer
*buffer
;
942 struct radv_streamout_state
{
943 /* Mask of bound streamout buffers. */
944 uint8_t enabled_mask
;
946 /* External state that comes from the last vertex stage, it must be
947 * set explicitely when binding a new graphics pipeline.
949 uint16_t stride_in_dw
[MAX_SO_BUFFERS
];
950 uint32_t enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
952 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
953 uint32_t hw_enabled_mask
;
955 /* State of VGT_STRMOUT_(CONFIG|EN) */
956 bool streamout_enabled
;
959 struct radv_viewport_state
{
961 VkViewport viewports
[MAX_VIEWPORTS
];
964 struct radv_scissor_state
{
966 VkRect2D scissors
[MAX_SCISSORS
];
969 struct radv_discard_rectangle_state
{
971 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
974 struct radv_sample_locations_state
{
975 VkSampleCountFlagBits per_pixel
;
976 VkExtent2D grid_size
;
978 VkSampleLocationEXT locations
[MAX_SAMPLE_LOCATIONS
];
981 struct radv_dynamic_state
{
983 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
984 * Defines the set of saved dynamic state.
988 struct radv_viewport_state viewport
;
990 struct radv_scissor_state scissor
;
1000 float blend_constants
[4];
1010 } stencil_compare_mask
;
1015 } stencil_write_mask
;
1020 } stencil_reference
;
1022 struct radv_discard_rectangle_state discard_rectangle
;
1024 struct radv_sample_locations_state sample_location
;
1027 extern const struct radv_dynamic_state default_dynamic_state
;
1030 radv_get_debug_option_name(int id
);
1033 radv_get_perftest_option_name(int id
);
1036 * Attachment state when recording a renderpass instance.
1038 * The clear value is valid only if there exists a pending clear.
1040 struct radv_attachment_state
{
1041 VkImageAspectFlags pending_clear_aspects
;
1042 uint32_t cleared_views
;
1043 VkClearValue clear_value
;
1044 VkImageLayout current_layout
;
1045 struct radv_sample_locations_state sample_location
;
1048 struct radv_descriptor_state
{
1049 struct radv_descriptor_set
*sets
[MAX_SETS
];
1052 struct radv_push_descriptor_set push_set
;
1054 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
1057 struct radv_subpass_sample_locs_state
{
1058 uint32_t subpass_idx
;
1059 struct radv_sample_locations_state sample_location
;
1062 struct radv_cmd_state
{
1063 /* Vertex descriptors */
1070 uint32_t prefetch_L2_mask
;
1072 struct radv_pipeline
* pipeline
;
1073 struct radv_pipeline
* emitted_pipeline
;
1074 struct radv_pipeline
* compute_pipeline
;
1075 struct radv_pipeline
* emitted_compute_pipeline
;
1076 struct radv_framebuffer
* framebuffer
;
1077 struct radv_render_pass
* pass
;
1078 const struct radv_subpass
* subpass
;
1079 struct radv_dynamic_state dynamic
;
1080 struct radv_attachment_state
* attachments
;
1081 struct radv_streamout_state streamout
;
1082 VkRect2D render_area
;
1084 uint32_t num_subpass_sample_locs
;
1085 struct radv_subpass_sample_locs_state
* subpass_sample_locs
;
1088 struct radv_buffer
*index_buffer
;
1089 uint64_t index_offset
;
1090 uint32_t index_type
;
1091 uint32_t max_index_count
;
1093 int32_t last_index_type
;
1095 int32_t last_primitive_reset_en
;
1096 uint32_t last_primitive_reset_index
;
1097 enum radv_cmd_flush_bits flush_bits
;
1098 unsigned active_occlusion_queries
;
1099 bool perfect_occlusion_queries_enabled
;
1100 unsigned active_pipeline_queries
;
1103 uint32_t last_ia_multi_vgt_param
;
1105 uint32_t last_num_instances
;
1106 uint32_t last_first_instance
;
1107 uint32_t last_vertex_offset
;
1109 /* Whether CP DMA is busy/idle. */
1112 /* Conditional rendering info. */
1113 int predication_type
; /* -1: disabled, 0: normal, 1: inverted */
1114 uint64_t predication_va
;
1116 bool context_roll_without_scissor_emitted
;
1119 struct radv_cmd_pool
{
1120 VkAllocationCallbacks alloc
;
1121 struct list_head cmd_buffers
;
1122 struct list_head free_cmd_buffers
;
1123 uint32_t queue_family_index
;
1126 struct radv_cmd_buffer_upload
{
1130 struct radeon_winsys_bo
*upload_bo
;
1131 struct list_head list
;
1134 enum radv_cmd_buffer_status
{
1135 RADV_CMD_BUFFER_STATUS_INVALID
,
1136 RADV_CMD_BUFFER_STATUS_INITIAL
,
1137 RADV_CMD_BUFFER_STATUS_RECORDING
,
1138 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
1139 RADV_CMD_BUFFER_STATUS_PENDING
,
1142 struct radv_cmd_buffer
{
1143 VK_LOADER_DATA _loader_data
;
1145 struct radv_device
* device
;
1147 struct radv_cmd_pool
* pool
;
1148 struct list_head pool_link
;
1150 VkCommandBufferUsageFlags usage_flags
;
1151 VkCommandBufferLevel level
;
1152 enum radv_cmd_buffer_status status
;
1153 struct radeon_cmdbuf
*cs
;
1154 struct radv_cmd_state state
;
1155 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
1156 struct radv_streamout_binding streamout_bindings
[MAX_SO_BUFFERS
];
1157 uint32_t queue_family_index
;
1159 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1160 VkShaderStageFlags push_constant_stages
;
1161 struct radv_descriptor_set meta_push_descriptors
;
1163 struct radv_descriptor_state descriptors
[VK_PIPELINE_BIND_POINT_RANGE_SIZE
];
1165 struct radv_cmd_buffer_upload upload
;
1167 uint32_t scratch_size_needed
;
1168 uint32_t compute_scratch_size_needed
;
1169 uint32_t esgs_ring_size_needed
;
1170 uint32_t gsvs_ring_size_needed
;
1171 bool tess_rings_needed
;
1172 bool sample_positions_needed
;
1174 VkResult record_result
;
1176 uint64_t gfx9_fence_va
;
1177 uint32_t gfx9_fence_idx
;
1178 uint64_t gfx9_eop_bug_va
;
1181 * Whether a query pool has been resetted and we have to flush caches.
1183 bool pending_reset_query
;
1186 * Bitmask of pending active query flushes.
1188 enum radv_cmd_flush_bits active_query_flush_bits
;
1192 struct radv_image_view
;
1194 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1196 void si_emit_graphics(struct radv_physical_device
*physical_device
,
1197 struct radeon_cmdbuf
*cs
);
1198 void si_emit_compute(struct radv_physical_device
*physical_device
,
1199 struct radeon_cmdbuf
*cs
);
1201 void cik_create_gfx_config(struct radv_device
*device
);
1203 void si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
1204 int count
, const VkViewport
*viewports
);
1205 void si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
1206 int count
, const VkRect2D
*scissors
,
1207 const VkViewport
*viewports
, bool can_use_guardband
);
1208 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1209 bool instanced_draw
, bool indirect_draw
,
1210 bool count_from_stream_output
,
1211 uint32_t draw_vertex_count
);
1212 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
1213 enum chip_class chip_class
,
1215 unsigned event
, unsigned event_flags
,
1219 uint64_t gfx9_eop_bug_va
);
1221 void radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
1222 uint32_t ref
, uint32_t mask
);
1223 void si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1224 enum chip_class chip_class
,
1225 uint32_t *fence_ptr
, uint64_t va
,
1227 enum radv_cmd_flush_bits flush_bits
,
1228 uint64_t gfx9_eop_bug_va
);
1229 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1230 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1231 bool inverted
, uint64_t va
);
1232 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1233 uint64_t src_va
, uint64_t dest_va
,
1235 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1237 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1238 uint64_t size
, unsigned value
);
1239 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
);
1241 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1243 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1246 unsigned *out_offset
,
1249 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1250 const struct radv_subpass
*subpass
);
1252 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1253 unsigned size
, unsigned alignmnet
,
1254 const void *data
, unsigned *out_offset
);
1256 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1257 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1258 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1259 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1260 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
,
1261 VkImageAspectFlags aspects
,
1262 VkResolveModeFlagBitsKHR resolve_mode
);
1263 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
);
1264 unsigned radv_get_default_max_sample_dist(int log_samples
);
1265 void radv_device_init_msaa(struct radv_device
*device
);
1267 void radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1268 struct radv_image
*image
,
1269 VkClearDepthStencilValue ds_clear_value
,
1270 VkImageAspectFlags aspects
);
1272 void radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1273 const struct radv_image_view
*iview
,
1275 uint32_t color_values
[2]);
1277 void radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1278 struct radv_image
*image
,
1279 const VkImageSubresourceRange
*range
, bool value
);
1281 void radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1282 struct radv_image
*image
,
1283 const VkImageSubresourceRange
*range
, bool value
);
1285 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1286 struct radeon_winsys_bo
*bo
,
1287 uint64_t offset
, uint64_t size
, uint32_t value
);
1288 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1289 bool radv_get_memory_fd(struct radv_device
*device
,
1290 struct radv_device_memory
*memory
,
1294 radv_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
1295 unsigned sh_offset
, unsigned pointer_count
,
1296 bool use_32bit_pointers
)
1298 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (use_32bit_pointers
? 1 : 2), 0));
1299 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1303 radv_emit_shader_pointer_body(struct radv_device
*device
,
1304 struct radeon_cmdbuf
*cs
,
1305 uint64_t va
, bool use_32bit_pointers
)
1307 radeon_emit(cs
, va
);
1309 if (use_32bit_pointers
) {
1311 (va
>> 32) == device
->physical_device
->rad_info
.address32_hi
);
1313 radeon_emit(cs
, va
>> 32);
1318 radv_emit_shader_pointer(struct radv_device
*device
,
1319 struct radeon_cmdbuf
*cs
,
1320 uint32_t sh_offset
, uint64_t va
, bool global
)
1322 bool use_32bit_pointers
= !global
;
1324 radv_emit_shader_pointer_head(cs
, sh_offset
, 1, use_32bit_pointers
);
1325 radv_emit_shader_pointer_body(device
, cs
, va
, use_32bit_pointers
);
1328 static inline struct radv_descriptor_state
*
1329 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1330 VkPipelineBindPoint bind_point
)
1332 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1333 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1334 return &cmd_buffer
->descriptors
[bind_point
];
1338 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1340 * Limitations: Can't call normal dispatch functions without binding or rebinding
1341 * the compute pipeline.
1343 void radv_unaligned_dispatch(
1344 struct radv_cmd_buffer
*cmd_buffer
,
1350 struct radeon_winsys_bo
*bo
;
1354 struct radv_shader_module
;
1356 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1357 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1358 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1360 radv_hash_shaders(unsigned char *hash
,
1361 const VkPipelineShaderStageCreateInfo
**stages
,
1362 const struct radv_pipeline_layout
*layout
,
1363 const struct radv_pipeline_key
*key
,
1366 static inline gl_shader_stage
1367 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1369 assert(__builtin_popcount(vk_stage
) == 1);
1370 return ffs(vk_stage
) - 1;
1373 static inline VkShaderStageFlagBits
1374 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1376 return (1 << mesa_stage
);
1379 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1381 #define radv_foreach_stage(stage, stage_bits) \
1382 for (gl_shader_stage stage, \
1383 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1384 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1385 __tmp &= ~(1 << (stage)))
1387 extern const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
];
1388 unsigned radv_format_meta_fs_key(VkFormat format
);
1390 struct radv_multisample_state
{
1392 uint32_t pa_sc_line_cntl
;
1393 uint32_t pa_sc_mode_cntl_0
;
1394 uint32_t pa_sc_mode_cntl_1
;
1395 uint32_t pa_sc_aa_config
;
1396 uint32_t pa_sc_aa_mask
[2];
1397 unsigned num_samples
;
1400 struct radv_prim_vertex_count
{
1405 struct radv_vertex_elements_info
{
1406 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1409 struct radv_ia_multi_vgt_param_helpers
{
1411 bool partial_es_wave
;
1412 uint8_t primgroup_size
;
1413 bool wd_switch_on_eop
;
1414 bool ia_switch_on_eoi
;
1415 bool partial_vs_wave
;
1418 #define SI_GS_PER_ES 128
1420 struct radv_pipeline
{
1421 struct radv_device
* device
;
1422 struct radv_dynamic_state dynamic_state
;
1424 struct radv_pipeline_layout
* layout
;
1426 bool need_indirect_descriptor_sets
;
1427 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1428 struct radv_shader_variant
*gs_copy_shader
;
1429 VkShaderStageFlags active_stages
;
1431 struct radeon_cmdbuf cs
;
1432 uint32_t ctx_cs_hash
;
1433 struct radeon_cmdbuf ctx_cs
;
1435 struct radv_vertex_elements_info vertex_elements
;
1437 uint32_t binding_stride
[MAX_VBS
];
1438 uint8_t num_vertex_bindings
;
1440 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1443 struct radv_multisample_state ms
;
1444 uint32_t spi_baryc_cntl
;
1445 bool prim_restart_enable
;
1446 unsigned esgs_ring_size
;
1447 unsigned gsvs_ring_size
;
1448 uint32_t vtx_base_sgpr
;
1449 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1450 uint8_t vtx_emit_num
;
1451 struct radv_prim_vertex_count prim_vertex_count
;
1452 bool can_use_guardband
;
1453 uint32_t needed_dynamic_state
;
1454 bool disable_out_of_order_rast_for_occlusion
;
1456 /* Used for rbplus */
1457 uint32_t col_format
;
1458 uint32_t cb_target_mask
;
1463 unsigned scratch_bytes_per_wave
;
1465 /* Not NULL if graphics pipeline uses streamout. */
1466 struct radv_shader_variant
*streamout_shader
;
1469 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1471 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1474 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1476 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1479 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1480 gl_shader_stage stage
,
1483 struct radv_shader_variant
*radv_get_shader(struct radv_pipeline
*pipeline
,
1484 gl_shader_stage stage
);
1486 struct radv_graphics_pipeline_create_info
{
1488 bool db_depth_clear
;
1489 bool db_stencil_clear
;
1490 bool db_depth_disable_expclear
;
1491 bool db_stencil_disable_expclear
;
1492 bool db_flush_depth_inplace
;
1493 bool db_flush_stencil_inplace
;
1494 bool db_resummarize
;
1495 uint32_t custom_blend_mode
;
1499 radv_graphics_pipeline_create(VkDevice device
,
1500 VkPipelineCache cache
,
1501 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1502 const struct radv_graphics_pipeline_create_info
*extra
,
1503 const VkAllocationCallbacks
*alloc
,
1504 VkPipeline
*pPipeline
);
1506 struct vk_format_description
;
1507 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1508 int first_non_void
);
1509 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1510 int first_non_void
);
1511 bool radv_is_buffer_format_supported(VkFormat format
, bool *scaled
);
1512 uint32_t radv_translate_colorformat(VkFormat format
);
1513 uint32_t radv_translate_color_numformat(VkFormat format
,
1514 const struct vk_format_description
*desc
,
1515 int first_non_void
);
1516 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1517 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1518 uint32_t radv_translate_dbformat(VkFormat format
);
1519 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1520 const struct vk_format_description
*desc
,
1521 int first_non_void
);
1522 uint32_t radv_translate_tex_numformat(VkFormat format
,
1523 const struct vk_format_description
*desc
,
1524 int first_non_void
);
1525 bool radv_format_pack_clear_color(VkFormat format
,
1526 uint32_t clear_vals
[2],
1527 VkClearColorValue
*value
);
1528 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1529 bool radv_dcc_formats_compatible(VkFormat format1
,
1531 bool radv_device_supports_etc(struct radv_physical_device
*physical_device
);
1533 struct radv_fmask_info
{
1537 unsigned pitch_in_pixels
;
1538 unsigned bank_height
;
1539 unsigned slice_tile_max
;
1540 unsigned tile_mode_index
;
1541 unsigned tile_swizzle
;
1544 struct radv_cmask_info
{
1548 unsigned slice_tile_max
;
1552 struct radv_image_plane
{
1554 struct radeon_surf surface
;
1560 /* The original VkFormat provided by the client. This may not match any
1561 * of the actual surface formats.
1564 VkImageAspectFlags aspects
;
1565 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1566 struct ac_surf_info info
;
1567 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1568 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1573 unsigned queue_family_mask
;
1577 /* Set when bound */
1578 struct radeon_winsys_bo
*bo
;
1579 VkDeviceSize offset
;
1580 uint64_t dcc_offset
;
1581 uint64_t htile_offset
;
1582 bool tc_compatible_htile
;
1583 bool tc_compatible_cmask
;
1585 struct radv_fmask_info fmask
;
1586 struct radv_cmask_info cmask
;
1587 uint64_t clear_value_offset
;
1588 uint64_t fce_pred_offset
;
1589 uint64_t dcc_pred_offset
;
1592 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1593 * stored at this offset is UINT_MAX, the driver will emit
1594 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1595 * SET_CONTEXT_REG packet.
1597 uint64_t tc_compat_zrange_offset
;
1599 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1600 VkDeviceMemory owned_memory
;
1602 unsigned plane_count
;
1603 struct radv_image_plane planes
[0];
1606 /* Whether the image has a htile that is known consistent with the contents of
1608 bool radv_layout_has_htile(const struct radv_image
*image
,
1609 VkImageLayout layout
,
1610 unsigned queue_mask
);
1612 /* Whether the image has a htile that is known consistent with the contents of
1613 * the image and is allowed to be in compressed form.
1615 * If this is false reads that don't use the htile should be able to return
1618 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1619 VkImageLayout layout
,
1620 unsigned queue_mask
);
1622 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1623 VkImageLayout layout
,
1624 unsigned queue_mask
);
1626 bool radv_layout_dcc_compressed(const struct radv_image
*image
,
1627 VkImageLayout layout
,
1628 unsigned queue_mask
);
1631 * Return whether the image has CMASK metadata for color surfaces.
1634 radv_image_has_cmask(const struct radv_image
*image
)
1636 return image
->cmask
.size
;
1640 * Return whether the image has FMASK metadata for color surfaces.
1643 radv_image_has_fmask(const struct radv_image
*image
)
1645 return image
->fmask
.size
;
1649 * Return whether the image has DCC metadata for color surfaces.
1652 radv_image_has_dcc(const struct radv_image
*image
)
1654 return image
->planes
[0].surface
.dcc_size
;
1658 * Return whether the image is TC-compatible CMASK.
1661 radv_image_is_tc_compat_cmask(const struct radv_image
*image
)
1663 return radv_image_has_fmask(image
) && image
->tc_compatible_cmask
;
1667 * Return whether DCC metadata is enabled for a level.
1670 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1672 return radv_image_has_dcc(image
) &&
1673 level
< image
->planes
[0].surface
.num_dcc_levels
;
1677 * Return whether the image has CB metadata.
1680 radv_image_has_CB_metadata(const struct radv_image
*image
)
1682 return radv_image_has_cmask(image
) ||
1683 radv_image_has_fmask(image
) ||
1684 radv_image_has_dcc(image
);
1688 * Return whether the image has HTILE metadata for depth surfaces.
1691 radv_image_has_htile(const struct radv_image
*image
)
1693 return image
->planes
[0].surface
.htile_size
;
1697 * Return whether HTILE metadata is enabled for a level.
1700 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1702 return radv_image_has_htile(image
) && level
== 0;
1706 * Return whether the image is TC-compatible HTILE.
1709 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1711 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1714 static inline uint64_t
1715 radv_image_get_fast_clear_va(const struct radv_image
*image
,
1716 uint32_t base_level
)
1718 uint64_t va
= radv_buffer_get_va(image
->bo
);
1719 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1723 static inline uint64_t
1724 radv_image_get_fce_pred_va(const struct radv_image
*image
,
1725 uint32_t base_level
)
1727 uint64_t va
= radv_buffer_get_va(image
->bo
);
1728 va
+= image
->offset
+ image
->fce_pred_offset
+ base_level
* 8;
1732 static inline uint64_t
1733 radv_image_get_dcc_pred_va(const struct radv_image
*image
,
1734 uint32_t base_level
)
1736 uint64_t va
= radv_buffer_get_va(image
->bo
);
1737 va
+= image
->offset
+ image
->dcc_pred_offset
+ base_level
* 8;
1741 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1743 static inline uint32_t
1744 radv_get_layerCount(const struct radv_image
*image
,
1745 const VkImageSubresourceRange
*range
)
1747 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1748 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1751 static inline uint32_t
1752 radv_get_levelCount(const struct radv_image
*image
,
1753 const VkImageSubresourceRange
*range
)
1755 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1756 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1759 struct radeon_bo_metadata
;
1761 radv_init_metadata(struct radv_device
*device
,
1762 struct radv_image
*image
,
1763 struct radeon_bo_metadata
*metadata
);
1766 radv_image_override_offset_stride(struct radv_device
*device
,
1767 struct radv_image
*image
,
1768 uint64_t offset
, uint32_t stride
);
1770 union radv_descriptor
{
1772 uint32_t plane0_descriptor
[8];
1773 uint32_t fmask_descriptor
[8];
1776 uint32_t plane_descriptors
[3][8];
1780 struct radv_image_view
{
1781 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1782 struct radeon_winsys_bo
*bo
;
1784 VkImageViewType type
;
1785 VkImageAspectFlags aspect_mask
;
1788 bool multiple_planes
;
1789 uint32_t base_layer
;
1790 uint32_t layer_count
;
1792 uint32_t level_count
;
1793 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1795 union radv_descriptor descriptor
;
1797 /* Descriptor for use as a storage image as opposed to a sampled image.
1798 * This has a few differences for cube maps (e.g. type).
1800 union radv_descriptor storage_descriptor
;
1803 struct radv_image_create_info
{
1804 const VkImageCreateInfo
*vk_info
;
1806 bool no_metadata_planes
;
1807 const struct radeon_bo_metadata
*bo_metadata
;
1810 VkResult
radv_image_create(VkDevice _device
,
1811 const struct radv_image_create_info
*info
,
1812 const VkAllocationCallbacks
* alloc
,
1816 radv_image_from_gralloc(VkDevice device_h
,
1817 const VkImageCreateInfo
*base_info
,
1818 const VkNativeBufferANDROID
*gralloc_info
,
1819 const VkAllocationCallbacks
*alloc
,
1820 VkImage
*out_image_h
);
1822 void radv_image_view_init(struct radv_image_view
*view
,
1823 struct radv_device
*device
,
1824 const VkImageViewCreateInfo
* pCreateInfo
);
1826 VkFormat
radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
);
1828 struct radv_sampler_ycbcr_conversion
{
1830 VkSamplerYcbcrModelConversion ycbcr_model
;
1831 VkSamplerYcbcrRange ycbcr_range
;
1832 VkComponentMapping components
;
1833 VkChromaLocation chroma_offsets
[2];
1834 VkFilter chroma_filter
;
1837 struct radv_buffer_view
{
1838 struct radeon_winsys_bo
*bo
;
1840 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1843 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1844 struct radv_device
*device
,
1845 const VkBufferViewCreateInfo
* pCreateInfo
);
1847 static inline struct VkExtent3D
1848 radv_sanitize_image_extent(const VkImageType imageType
,
1849 const struct VkExtent3D imageExtent
)
1851 switch (imageType
) {
1852 case VK_IMAGE_TYPE_1D
:
1853 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1854 case VK_IMAGE_TYPE_2D
:
1855 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1856 case VK_IMAGE_TYPE_3D
:
1859 unreachable("invalid image type");
1863 static inline struct VkOffset3D
1864 radv_sanitize_image_offset(const VkImageType imageType
,
1865 const struct VkOffset3D imageOffset
)
1867 switch (imageType
) {
1868 case VK_IMAGE_TYPE_1D
:
1869 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1870 case VK_IMAGE_TYPE_2D
:
1871 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1872 case VK_IMAGE_TYPE_3D
:
1875 unreachable("invalid image type");
1880 radv_image_extent_compare(const struct radv_image
*image
,
1881 const VkExtent3D
*extent
)
1883 if (extent
->width
!= image
->info
.width
||
1884 extent
->height
!= image
->info
.height
||
1885 extent
->depth
!= image
->info
.depth
)
1890 struct radv_sampler
{
1892 struct radv_sampler_ycbcr_conversion
*ycbcr_sampler
;
1895 struct radv_color_buffer_info
{
1896 uint64_t cb_color_base
;
1897 uint64_t cb_color_cmask
;
1898 uint64_t cb_color_fmask
;
1899 uint64_t cb_dcc_base
;
1900 uint32_t cb_color_slice
;
1901 uint32_t cb_color_view
;
1902 uint32_t cb_color_info
;
1903 uint32_t cb_color_attrib
;
1904 uint32_t cb_color_attrib2
;
1905 uint32_t cb_dcc_control
;
1906 uint32_t cb_color_cmask_slice
;
1907 uint32_t cb_color_fmask_slice
;
1909 uint32_t cb_color_pitch
; // GFX6-GFX8
1910 uint32_t cb_mrt_epitch
; // GFX9+
1914 struct radv_ds_buffer_info
{
1915 uint64_t db_z_read_base
;
1916 uint64_t db_stencil_read_base
;
1917 uint64_t db_z_write_base
;
1918 uint64_t db_stencil_write_base
;
1919 uint64_t db_htile_data_base
;
1920 uint32_t db_depth_info
;
1922 uint32_t db_stencil_info
;
1923 uint32_t db_depth_view
;
1924 uint32_t db_depth_size
;
1925 uint32_t db_depth_slice
;
1926 uint32_t db_htile_surface
;
1927 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1928 uint32_t db_z_info2
;
1929 uint32_t db_stencil_info2
;
1933 struct radv_attachment_info
{
1935 struct radv_color_buffer_info cb
;
1936 struct radv_ds_buffer_info ds
;
1938 struct radv_image_view
*attachment
;
1941 struct radv_framebuffer
{
1946 uint32_t attachment_count
;
1947 struct radv_attachment_info attachments
[0];
1950 struct radv_subpass_barrier
{
1951 VkPipelineStageFlags src_stage_mask
;
1952 VkAccessFlags src_access_mask
;
1953 VkAccessFlags dst_access_mask
;
1956 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
1957 const struct radv_subpass_barrier
*barrier
);
1959 struct radv_subpass_attachment
{
1960 uint32_t attachment
;
1961 VkImageLayout layout
;
1964 struct radv_subpass
{
1965 uint32_t attachment_count
;
1966 struct radv_subpass_attachment
* attachments
;
1968 uint32_t input_count
;
1969 uint32_t color_count
;
1970 struct radv_subpass_attachment
* input_attachments
;
1971 struct radv_subpass_attachment
* color_attachments
;
1972 struct radv_subpass_attachment
* resolve_attachments
;
1973 struct radv_subpass_attachment
* depth_stencil_attachment
;
1974 struct radv_subpass_attachment
* ds_resolve_attachment
;
1975 VkResolveModeFlagBitsKHR depth_resolve_mode
;
1976 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
1978 /** Subpass has at least one color resolve attachment */
1979 bool has_color_resolve
;
1981 /** Subpass has at least one color attachment */
1984 struct radv_subpass_barrier start_barrier
;
1987 VkSampleCountFlagBits max_sample_count
;
1990 struct radv_render_pass_attachment
{
1993 VkAttachmentLoadOp load_op
;
1994 VkAttachmentLoadOp stencil_load_op
;
1995 VkImageLayout initial_layout
;
1996 VkImageLayout final_layout
;
1998 /* The subpass id in which the attachment will be used first/last. */
1999 uint32_t first_subpass_idx
;
2000 uint32_t last_subpass_idx
;
2003 struct radv_render_pass
{
2004 uint32_t attachment_count
;
2005 uint32_t subpass_count
;
2006 struct radv_subpass_attachment
* subpass_attachments
;
2007 struct radv_render_pass_attachment
* attachments
;
2008 struct radv_subpass_barrier end_barrier
;
2009 struct radv_subpass subpasses
[0];
2012 VkResult
radv_device_init_meta(struct radv_device
*device
);
2013 void radv_device_finish_meta(struct radv_device
*device
);
2015 struct radv_query_pool
{
2016 struct radeon_winsys_bo
*bo
;
2018 uint32_t availability_offset
;
2022 uint32_t pipeline_stats_mask
;
2025 struct radv_semaphore
{
2026 /* use a winsys sem for non-exportable */
2027 struct radeon_winsys_sem
*sem
;
2029 uint32_t temp_syncobj
;
2032 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2033 VkPipelineBindPoint bind_point
,
2034 struct radv_descriptor_set
*set
,
2038 radv_update_descriptor_sets(struct radv_device
*device
,
2039 struct radv_cmd_buffer
*cmd_buffer
,
2040 VkDescriptorSet overrideSet
,
2041 uint32_t descriptorWriteCount
,
2042 const VkWriteDescriptorSet
*pDescriptorWrites
,
2043 uint32_t descriptorCopyCount
,
2044 const VkCopyDescriptorSet
*pDescriptorCopies
);
2047 radv_update_descriptor_set_with_template(struct radv_device
*device
,
2048 struct radv_cmd_buffer
*cmd_buffer
,
2049 struct radv_descriptor_set
*set
,
2050 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
2053 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2054 VkPipelineBindPoint pipelineBindPoint
,
2055 VkPipelineLayout _layout
,
2057 uint32_t descriptorWriteCount
,
2058 const VkWriteDescriptorSet
*pDescriptorWrites
);
2060 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
2061 struct radv_image
*image
,
2062 const VkImageSubresourceRange
*range
, uint32_t value
);
2064 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
2065 struct radv_image
*image
);
2068 struct radeon_winsys_fence
*fence
;
2069 struct wsi_fence
*fence_wsi
;
2072 uint32_t temp_syncobj
;
2075 /* radv_nir_to_llvm.c */
2076 struct radv_shader_variant_info
;
2077 struct radv_nir_compiler_options
;
2079 void radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
2080 struct nir_shader
*geom_shader
,
2081 struct ac_shader_binary
*binary
,
2082 struct ac_shader_config
*config
,
2083 struct radv_shader_variant_info
*shader_info
,
2084 const struct radv_nir_compiler_options
*option
);
2086 void radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
2087 struct ac_shader_binary
*binary
,
2088 struct ac_shader_config
*config
,
2089 struct radv_shader_variant_info
*shader_info
,
2090 struct nir_shader
*const *nir
,
2092 const struct radv_nir_compiler_options
*options
);
2094 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
2095 const struct nir_shader
*nir
);
2097 /* radv_shader_info.h */
2098 struct radv_shader_info
;
2100 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
2101 const struct radv_nir_compiler_options
*options
,
2102 struct radv_shader_info
*info
);
2104 void radv_nir_shader_info_init(struct radv_shader_info
*info
);
2106 struct radeon_winsys_sem
;
2108 uint64_t radv_get_current_time(void);
2110 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2112 static inline struct __radv_type * \
2113 __radv_type ## _from_handle(__VkType _handle) \
2115 return (struct __radv_type *) _handle; \
2118 static inline __VkType \
2119 __radv_type ## _to_handle(struct __radv_type *_obj) \
2121 return (__VkType) _obj; \
2124 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2126 static inline struct __radv_type * \
2127 __radv_type ## _from_handle(__VkType _handle) \
2129 return (struct __radv_type *)(uintptr_t) _handle; \
2132 static inline __VkType \
2133 __radv_type ## _to_handle(struct __radv_type *_obj) \
2135 return (__VkType)(uintptr_t) _obj; \
2138 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2139 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2141 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
2142 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
2143 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
2144 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
2145 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
2147 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
2148 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
2149 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
2150 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
2151 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
2152 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
2153 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
2154 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
2155 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
2156 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
2157 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
2158 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
2159 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
2160 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
2161 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
2162 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
2163 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
2164 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
2165 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
2166 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
2167 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
2168 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
2170 #endif /* RADV_PRIVATE_H */