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radv/gfx9: fix 3d image to image transfers on compute queues.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
59
60 #include <llvm-c/TargetMachine.h>
61
62 /* Pre-declarations needed for WSI entrypoints */
63 struct wl_surface;
64 struct wl_display;
65 typedef struct xcb_connection_t xcb_connection_t;
66 typedef uint32_t xcb_visualid_t;
67 typedef uint32_t xcb_window_t;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "radv_entrypoints.h"
74
75 #include "wsi_common.h"
76
77 #define ATI_VENDOR_ID 0x1002
78
79 #define MAX_VBS 32
80 #define MAX_VERTEX_ATTRIBS 32
81 #define MAX_RTS 8
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
90 #define MAX_VIEWS 8
91
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
93
94 enum radv_mem_heap {
95 RADV_MEM_HEAP_VRAM,
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
97 RADV_MEM_HEAP_GTT,
98 RADV_MEM_HEAP_COUNT
99 };
100
101 enum radv_mem_type {
102 RADV_MEM_TYPE_VRAM,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
105 RADV_MEM_TYPE_GTT_CACHED,
106 RADV_MEM_TYPE_COUNT
107 };
108
109 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
110
111 static inline uint32_t
112 align_u32(uint32_t v, uint32_t a)
113 {
114 assert(a != 0 && a == (a & -a));
115 return (v + a - 1) & ~(a - 1);
116 }
117
118 static inline uint32_t
119 align_u32_npot(uint32_t v, uint32_t a)
120 {
121 return (v + a - 1) / a * a;
122 }
123
124 static inline uint64_t
125 align_u64(uint64_t v, uint64_t a)
126 {
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
129 }
130
131 static inline int32_t
132 align_i32(int32_t v, int32_t a)
133 {
134 assert(a != 0 && a == (a & -a));
135 return (v + a - 1) & ~(a - 1);
136 }
137
138 /** Alignment must be a power of 2. */
139 static inline bool
140 radv_is_aligned(uintmax_t n, uintmax_t a)
141 {
142 assert(a == (a & -a));
143 return (n & (a - 1)) == 0;
144 }
145
146 static inline uint32_t
147 round_up_u32(uint32_t v, uint32_t a)
148 {
149 return (v + a - 1) / a;
150 }
151
152 static inline uint64_t
153 round_up_u64(uint64_t v, uint64_t a)
154 {
155 return (v + a - 1) / a;
156 }
157
158 static inline uint32_t
159 radv_minify(uint32_t n, uint32_t levels)
160 {
161 if (unlikely(n == 0))
162 return 0;
163 else
164 return MAX2(n >> levels, 1);
165 }
166 static inline float
167 radv_clamp_f(float f, float min, float max)
168 {
169 assert(min < max);
170
171 if (f > max)
172 return max;
173 else if (f < min)
174 return min;
175 else
176 return f;
177 }
178
179 static inline bool
180 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
181 {
182 if (*inout_mask & clear_mask) {
183 *inout_mask &= ~clear_mask;
184 return true;
185 } else {
186 return false;
187 }
188 }
189
190 #define for_each_bit(b, dword) \
191 for (uint32_t __dword = (dword); \
192 (b) = __builtin_ffs(__dword) - 1, __dword; \
193 __dword &= ~(1 << (b)))
194
195 #define typed_memcpy(dest, src, count) ({ \
196 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
197 memcpy((dest), (src), (count) * sizeof(*(src))); \
198 })
199
200 /* Whenever we generate an error, pass it through this function. Useful for
201 * debugging, where we can break on it. Only call at error site, not when
202 * propagating errors. Might be useful to plug in a stack trace here.
203 */
204
205 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
206
207 #ifdef DEBUG
208 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
209 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
210 #else
211 #define vk_error(error) error
212 #define vk_errorf(error, format, ...) error
213 #endif
214
215 void __radv_finishme(const char *file, int line, const char *format, ...)
216 radv_printflike(3, 4);
217 void radv_loge(const char *format, ...) radv_printflike(1, 2);
218 void radv_loge_v(const char *format, va_list va);
219
220 /**
221 * Print a FINISHME message, including its source location.
222 */
223 #define radv_finishme(format, ...) \
224 do { \
225 static bool reported = false; \
226 if (!reported) { \
227 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
228 reported = true; \
229 } \
230 } while (0)
231
232 /* A non-fatal assert. Useful for debugging. */
233 #ifdef DEBUG
234 #define radv_assert(x) ({ \
235 if (unlikely(!(x))) \
236 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
237 })
238 #else
239 #define radv_assert(x)
240 #endif
241
242 #define stub_return(v) \
243 do { \
244 radv_finishme("stub %s", __func__); \
245 return (v); \
246 } while (0)
247
248 #define stub() \
249 do { \
250 radv_finishme("stub %s", __func__); \
251 return; \
252 } while (0)
253
254 void *radv_lookup_entrypoint(const char *name);
255
256 struct radv_physical_device {
257 VK_LOADER_DATA _loader_data;
258
259 struct radv_instance * instance;
260
261 struct radeon_winsys *ws;
262 struct radeon_info rad_info;
263 char path[20];
264 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
265 uint8_t driver_uuid[VK_UUID_SIZE];
266 uint8_t device_uuid[VK_UUID_SIZE];
267 uint8_t cache_uuid[VK_UUID_SIZE];
268
269 int local_fd;
270 struct wsi_device wsi_device;
271
272 bool has_rbplus; /* if RB+ register exist */
273 bool rbplus_allowed; /* if RB+ is allowed */
274 bool has_clear_state;
275
276 /* This is the drivers on-disk cache used as a fallback as opposed to
277 * the pipeline cache defined by apps.
278 */
279 struct disk_cache * disk_cache;
280
281 VkPhysicalDeviceMemoryProperties memory_properties;
282 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
283 };
284
285 struct radv_instance {
286 VK_LOADER_DATA _loader_data;
287
288 VkAllocationCallbacks alloc;
289
290 uint32_t apiVersion;
291 int physicalDeviceCount;
292 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
293
294 uint64_t debug_flags;
295 uint64_t perftest_flags;
296 };
297
298 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
299 void radv_finish_wsi(struct radv_physical_device *physical_device);
300
301 bool radv_instance_extension_supported(const char *name);
302 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
303 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
304 const char *name);
305
306 struct cache_entry;
307
308 struct radv_pipeline_cache {
309 struct radv_device * device;
310 pthread_mutex_t mutex;
311
312 uint32_t total_size;
313 uint32_t table_size;
314 uint32_t kernel_count;
315 struct cache_entry ** hash_table;
316 bool modified;
317
318 VkAllocationCallbacks alloc;
319 };
320
321 struct radv_pipeline_key {
322 uint32_t instance_rate_inputs;
323 unsigned tess_input_vertices;
324 uint32_t col_format;
325 uint32_t is_int8;
326 uint32_t is_int10;
327 uint32_t multisample : 1;
328 uint32_t has_multiview_view_index : 1;
329 };
330
331 void
332 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
333 struct radv_device *device);
334 void
335 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
336 void
337 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
338 const void *data, size_t size);
339
340 struct radv_shader_variant;
341
342 bool
343 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
344 struct radv_pipeline_cache *cache,
345 const unsigned char *sha1,
346 struct radv_shader_variant **variants);
347
348 void
349 radv_pipeline_cache_insert_shaders(struct radv_device *device,
350 struct radv_pipeline_cache *cache,
351 const unsigned char *sha1,
352 struct radv_shader_variant **variants,
353 const void *const *codes,
354 const unsigned *code_sizes);
355
356 enum radv_blit_ds_layout {
357 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
358 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
359 RADV_BLIT_DS_LAYOUT_COUNT,
360 };
361
362 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
363 {
364 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
365 }
366
367 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
368 {
369 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
370 }
371
372 struct radv_meta_state {
373 VkAllocationCallbacks alloc;
374
375 struct radv_pipeline_cache cache;
376
377 /**
378 * Use array element `i` for images with `2^i` samples.
379 */
380 struct {
381 VkRenderPass render_pass[NUM_META_FS_KEYS];
382 VkPipeline color_pipelines[NUM_META_FS_KEYS];
383
384 VkRenderPass depthstencil_rp;
385 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
386 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
387 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
388 } clear[1 + MAX_SAMPLES_LOG2];
389
390 VkPipelineLayout clear_color_p_layout;
391 VkPipelineLayout clear_depth_p_layout;
392 struct {
393 VkRenderPass render_pass[NUM_META_FS_KEYS];
394
395 /** Pipeline that blits from a 1D image. */
396 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
397
398 /** Pipeline that blits from a 2D image. */
399 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
400
401 /** Pipeline that blits from a 3D image. */
402 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
403
404 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
405 VkPipeline depth_only_1d_pipeline;
406 VkPipeline depth_only_2d_pipeline;
407 VkPipeline depth_only_3d_pipeline;
408
409 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
410 VkPipeline stencil_only_1d_pipeline;
411 VkPipeline stencil_only_2d_pipeline;
412 VkPipeline stencil_only_3d_pipeline;
413 VkPipelineLayout pipeline_layout;
414 VkDescriptorSetLayout ds_layout;
415 } blit;
416
417 struct {
418 VkRenderPass render_passes[NUM_META_FS_KEYS];
419
420 VkPipelineLayout p_layouts[3];
421 VkDescriptorSetLayout ds_layouts[3];
422 VkPipeline pipelines[3][NUM_META_FS_KEYS];
423
424 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
425 VkPipeline depth_only_pipeline[3];
426
427 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
428 VkPipeline stencil_only_pipeline[3];
429 } blit2d;
430
431 struct {
432 VkPipelineLayout img_p_layout;
433 VkDescriptorSetLayout img_ds_layout;
434 VkPipeline pipeline;
435 VkPipeline pipeline_3d;
436 } itob;
437 struct {
438 VkPipelineLayout img_p_layout;
439 VkDescriptorSetLayout img_ds_layout;
440 VkPipeline pipeline;
441 } btoi;
442 struct {
443 VkPipelineLayout img_p_layout;
444 VkDescriptorSetLayout img_ds_layout;
445 VkPipeline pipeline;
446 VkPipeline pipeline_3d;
447 } itoi;
448 struct {
449 VkPipelineLayout img_p_layout;
450 VkDescriptorSetLayout img_ds_layout;
451 VkPipeline pipeline;
452 } cleari;
453
454 struct {
455 VkPipelineLayout p_layout;
456 VkPipeline pipeline;
457 VkRenderPass pass;
458 } resolve;
459
460 struct {
461 VkDescriptorSetLayout ds_layout;
462 VkPipelineLayout p_layout;
463 struct {
464 VkPipeline pipeline;
465 VkPipeline i_pipeline;
466 VkPipeline srgb_pipeline;
467 } rc[MAX_SAMPLES_LOG2];
468 } resolve_compute;
469
470 struct {
471 VkDescriptorSetLayout ds_layout;
472 VkPipelineLayout p_layout;
473
474 struct {
475 VkRenderPass render_pass[NUM_META_FS_KEYS];
476 VkPipeline pipeline[NUM_META_FS_KEYS];
477 } rc[MAX_SAMPLES_LOG2];
478 } resolve_fragment;
479
480 struct {
481 VkPipelineLayout p_layout;
482 VkPipeline decompress_pipeline;
483 VkPipeline resummarize_pipeline;
484 VkRenderPass pass;
485 } depth_decomp[1 + MAX_SAMPLES_LOG2];
486
487 struct {
488 VkPipelineLayout p_layout;
489 VkPipeline cmask_eliminate_pipeline;
490 VkPipeline fmask_decompress_pipeline;
491 VkRenderPass pass;
492 } fast_clear_flush;
493
494 struct {
495 VkPipelineLayout fill_p_layout;
496 VkPipelineLayout copy_p_layout;
497 VkDescriptorSetLayout fill_ds_layout;
498 VkDescriptorSetLayout copy_ds_layout;
499 VkPipeline fill_pipeline;
500 VkPipeline copy_pipeline;
501 } buffer;
502
503 struct {
504 VkDescriptorSetLayout ds_layout;
505 VkPipelineLayout p_layout;
506 VkPipeline occlusion_query_pipeline;
507 VkPipeline pipeline_statistics_query_pipeline;
508 } query;
509 };
510
511 /* queue types */
512 #define RADV_QUEUE_GENERAL 0
513 #define RADV_QUEUE_COMPUTE 1
514 #define RADV_QUEUE_TRANSFER 2
515
516 #define RADV_MAX_QUEUE_FAMILIES 3
517
518 enum ring_type radv_queue_family_to_ring(int f);
519
520 struct radv_queue {
521 VK_LOADER_DATA _loader_data;
522 struct radv_device * device;
523 struct radeon_winsys_ctx *hw_ctx;
524 enum radeon_ctx_priority priority;
525 uint32_t queue_family_index;
526 int queue_idx;
527
528 uint32_t scratch_size;
529 uint32_t compute_scratch_size;
530 uint32_t esgs_ring_size;
531 uint32_t gsvs_ring_size;
532 bool has_tess_rings;
533 bool has_sample_positions;
534
535 struct radeon_winsys_bo *scratch_bo;
536 struct radeon_winsys_bo *descriptor_bo;
537 struct radeon_winsys_bo *compute_scratch_bo;
538 struct radeon_winsys_bo *esgs_ring_bo;
539 struct radeon_winsys_bo *gsvs_ring_bo;
540 struct radeon_winsys_bo *tess_factor_ring_bo;
541 struct radeon_winsys_bo *tess_offchip_ring_bo;
542 struct radeon_winsys_cs *initial_preamble_cs;
543 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
544 struct radeon_winsys_cs *continue_preamble_cs;
545 };
546
547 struct radv_device {
548 VK_LOADER_DATA _loader_data;
549
550 VkAllocationCallbacks alloc;
551
552 struct radv_instance * instance;
553 struct radeon_winsys *ws;
554
555 struct radv_meta_state meta_state;
556
557 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
558 int queue_count[RADV_MAX_QUEUE_FAMILIES];
559 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
560
561 bool llvm_supports_spill;
562 bool has_distributed_tess;
563 bool dfsm_allowed;
564 uint32_t tess_offchip_block_dw_size;
565 uint32_t scratch_waves;
566 uint32_t dispatch_initiator;
567
568 uint32_t gs_table_depth;
569
570 /* MSAA sample locations.
571 * The first index is the sample index.
572 * The second index is the coordinate: X, Y. */
573 float sample_locations_1x[1][2];
574 float sample_locations_2x[2][2];
575 float sample_locations_4x[4][2];
576 float sample_locations_8x[8][2];
577 float sample_locations_16x[16][2];
578
579 /* CIK and later */
580 uint32_t gfx_init_size_dw;
581 struct radeon_winsys_bo *gfx_init;
582
583 struct radeon_winsys_bo *trace_bo;
584 uint32_t *trace_id_ptr;
585
586 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
587 bool keep_shader_info;
588
589 struct radv_physical_device *physical_device;
590
591 /* Backup in-memory cache to be used if the app doesn't provide one */
592 struct radv_pipeline_cache * mem_cache;
593
594 /*
595 * use different counters so MSAA MRTs get consecutive surface indices,
596 * even if MASK is allocated in between.
597 */
598 uint32_t image_mrt_offset_counter;
599 uint32_t fmask_mrt_offset_counter;
600 struct list_head shader_slabs;
601 mtx_t shader_slab_mutex;
602
603 /* For detecting VM faults reported by dmesg. */
604 uint64_t dmesg_timestamp;
605 };
606
607 struct radv_device_memory {
608 struct radeon_winsys_bo *bo;
609 /* for dedicated allocations */
610 struct radv_image *image;
611 struct radv_buffer *buffer;
612 uint32_t type_index;
613 VkDeviceSize map_size;
614 void * map;
615 };
616
617
618 struct radv_descriptor_range {
619 uint64_t va;
620 uint32_t size;
621 };
622
623 struct radv_descriptor_set {
624 const struct radv_descriptor_set_layout *layout;
625 uint32_t size;
626
627 struct radeon_winsys_bo *bo;
628 uint64_t va;
629 uint32_t *mapped_ptr;
630 struct radv_descriptor_range *dynamic_descriptors;
631
632 struct radeon_winsys_bo *descriptors[0];
633 };
634
635 struct radv_push_descriptor_set
636 {
637 struct radv_descriptor_set set;
638 uint32_t capacity;
639 };
640
641 struct radv_descriptor_pool_entry {
642 uint32_t offset;
643 uint32_t size;
644 struct radv_descriptor_set *set;
645 };
646
647 struct radv_descriptor_pool {
648 struct radeon_winsys_bo *bo;
649 uint8_t *mapped_ptr;
650 uint64_t current_offset;
651 uint64_t size;
652
653 uint8_t *host_memory_base;
654 uint8_t *host_memory_ptr;
655 uint8_t *host_memory_end;
656
657 uint32_t entry_count;
658 uint32_t max_entry_count;
659 struct radv_descriptor_pool_entry entries[0];
660 };
661
662 struct radv_descriptor_update_template_entry {
663 VkDescriptorType descriptor_type;
664
665 /* The number of descriptors to update */
666 uint32_t descriptor_count;
667
668 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
669 uint32_t dst_offset;
670
671 /* In dwords. Not valid/used for dynamic descriptors */
672 uint32_t dst_stride;
673
674 uint32_t buffer_offset;
675
676 /* Only valid for combined image samplers and samplers */
677 uint16_t has_sampler;
678
679 /* In bytes */
680 size_t src_offset;
681 size_t src_stride;
682
683 /* For push descriptors */
684 const uint32_t *immutable_samplers;
685 };
686
687 struct radv_descriptor_update_template {
688 uint32_t entry_count;
689 struct radv_descriptor_update_template_entry entry[0];
690 };
691
692 struct radv_buffer {
693 struct radv_device * device;
694 VkDeviceSize size;
695
696 VkBufferUsageFlags usage;
697 VkBufferCreateFlags flags;
698
699 /* Set when bound */
700 struct radeon_winsys_bo * bo;
701 VkDeviceSize offset;
702
703 bool shareable;
704 };
705
706
707 enum radv_cmd_dirty_bits {
708 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
709 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
710 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
711 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
712 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
713 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
714 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
715 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
716 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
717 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
718 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
719 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
720 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 11,
721 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 12,
722 };
723
724 enum radv_cmd_flush_bits {
725 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
726 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
727 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
728 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
729 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
730 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
731 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
732 /* Same as above, but only writes back and doesn't invalidate */
733 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
734 /* Framebuffer caches */
735 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
736 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
737 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
738 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
739 /* Engine synchronization. */
740 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
741 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
742 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
743 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
744
745 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
746 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
747 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
748 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
749 };
750
751 struct radv_vertex_binding {
752 struct radv_buffer * buffer;
753 VkDeviceSize offset;
754 };
755
756 struct radv_viewport_state {
757 uint32_t count;
758 VkViewport viewports[MAX_VIEWPORTS];
759 };
760
761 struct radv_scissor_state {
762 uint32_t count;
763 VkRect2D scissors[MAX_SCISSORS];
764 };
765
766 struct radv_dynamic_state {
767 /**
768 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
769 * Defines the set of saved dynamic state.
770 */
771 uint32_t mask;
772
773 struct radv_viewport_state viewport;
774
775 struct radv_scissor_state scissor;
776
777 float line_width;
778
779 struct {
780 float bias;
781 float clamp;
782 float slope;
783 } depth_bias;
784
785 float blend_constants[4];
786
787 struct {
788 float min;
789 float max;
790 } depth_bounds;
791
792 struct {
793 uint32_t front;
794 uint32_t back;
795 } stencil_compare_mask;
796
797 struct {
798 uint32_t front;
799 uint32_t back;
800 } stencil_write_mask;
801
802 struct {
803 uint32_t front;
804 uint32_t back;
805 } stencil_reference;
806 };
807
808 extern const struct radv_dynamic_state default_dynamic_state;
809
810 const char *
811 radv_get_debug_option_name(int id);
812
813 const char *
814 radv_get_perftest_option_name(int id);
815
816 /**
817 * Attachment state when recording a renderpass instance.
818 *
819 * The clear value is valid only if there exists a pending clear.
820 */
821 struct radv_attachment_state {
822 VkImageAspectFlags pending_clear_aspects;
823 uint32_t cleared_views;
824 VkClearValue clear_value;
825 VkImageLayout current_layout;
826 };
827
828 struct radv_cmd_state {
829 /* Vertex descriptors */
830 bool vb_prefetch_dirty;
831 uint64_t vb_va;
832 unsigned vb_size;
833
834 bool push_descriptors_dirty;
835 bool predicating;
836 uint32_t dirty;
837
838 struct radv_pipeline * pipeline;
839 struct radv_pipeline * emitted_pipeline;
840 struct radv_pipeline * compute_pipeline;
841 struct radv_pipeline * emitted_compute_pipeline;
842 struct radv_framebuffer * framebuffer;
843 struct radv_render_pass * pass;
844 const struct radv_subpass * subpass;
845 struct radv_dynamic_state dynamic;
846 struct radv_attachment_state * attachments;
847 VkRect2D render_area;
848
849 /* Index buffer */
850 struct radv_buffer *index_buffer;
851 uint64_t index_offset;
852 uint32_t index_type;
853 uint32_t max_index_count;
854 uint64_t index_va;
855 int32_t last_index_type;
856
857 int32_t last_primitive_reset_en;
858 uint32_t last_primitive_reset_index;
859 enum radv_cmd_flush_bits flush_bits;
860 unsigned active_occlusion_queries;
861 float offset_scale;
862 uint32_t descriptors_dirty;
863 uint32_t valid_descriptors;
864 uint32_t trace_id;
865 uint32_t last_ia_multi_vgt_param;
866 };
867
868 struct radv_cmd_pool {
869 VkAllocationCallbacks alloc;
870 struct list_head cmd_buffers;
871 struct list_head free_cmd_buffers;
872 uint32_t queue_family_index;
873 };
874
875 struct radv_cmd_buffer_upload {
876 uint8_t *map;
877 unsigned offset;
878 uint64_t size;
879 struct radeon_winsys_bo *upload_bo;
880 struct list_head list;
881 };
882
883 enum radv_cmd_buffer_status {
884 RADV_CMD_BUFFER_STATUS_INVALID,
885 RADV_CMD_BUFFER_STATUS_INITIAL,
886 RADV_CMD_BUFFER_STATUS_RECORDING,
887 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
888 RADV_CMD_BUFFER_STATUS_PENDING,
889 };
890
891 struct radv_cmd_buffer {
892 VK_LOADER_DATA _loader_data;
893
894 struct radv_device * device;
895
896 struct radv_cmd_pool * pool;
897 struct list_head pool_link;
898
899 VkCommandBufferUsageFlags usage_flags;
900 VkCommandBufferLevel level;
901 enum radv_cmd_buffer_status status;
902 struct radeon_winsys_cs *cs;
903 struct radv_cmd_state state;
904 struct radv_vertex_binding vertex_bindings[MAX_VBS];
905 uint32_t queue_family_index;
906
907 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
908 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
909 VkShaderStageFlags push_constant_stages;
910 struct radv_push_descriptor_set push_descriptors;
911 struct radv_descriptor_set meta_push_descriptors;
912 struct radv_descriptor_set *descriptors[MAX_SETS];
913
914 struct radv_cmd_buffer_upload upload;
915
916 uint32_t scratch_size_needed;
917 uint32_t compute_scratch_size_needed;
918 uint32_t esgs_ring_size_needed;
919 uint32_t gsvs_ring_size_needed;
920 bool tess_rings_needed;
921 bool sample_positions_needed;
922
923 VkResult record_result;
924
925 int ring_offsets_idx; /* just used for verification */
926 uint32_t gfx9_fence_offset;
927 struct radeon_winsys_bo *gfx9_fence_bo;
928 uint32_t gfx9_fence_idx;
929 };
930
931 struct radv_image;
932
933 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
934
935 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
936 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
937
938 void cik_create_gfx_config(struct radv_device *device);
939
940 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
941 int count, const VkViewport *viewports);
942 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
943 int count, const VkRect2D *scissors,
944 const VkViewport *viewports, bool can_use_guardband);
945 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
946 bool instanced_draw, bool indirect_draw,
947 uint32_t draw_vertex_count);
948 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
949 bool predicated,
950 enum chip_class chip_class,
951 bool is_mec,
952 unsigned event, unsigned event_flags,
953 unsigned data_sel,
954 uint64_t va,
955 uint32_t old_fence,
956 uint32_t new_fence);
957
958 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
959 bool predicated,
960 uint64_t va, uint32_t ref,
961 uint32_t mask);
962 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
963 bool predicated,
964 enum chip_class chip_class,
965 uint32_t *fence_ptr, uint64_t va,
966 bool is_mec,
967 enum radv_cmd_flush_bits flush_bits);
968 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
969 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
970 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
971 uint64_t src_va, uint64_t dest_va,
972 uint64_t size);
973 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
974 unsigned size);
975 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
976 uint64_t size, unsigned value);
977 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
978 bool
979 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
980 unsigned size,
981 unsigned alignment,
982 unsigned *out_offset,
983 void **ptr);
984 void
985 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
986 const struct radv_subpass *subpass,
987 bool transitions);
988 bool
989 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
990 unsigned size, unsigned alignmnet,
991 const void *data, unsigned *out_offset);
992
993 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
994 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
995 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
996 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
997 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
998 unsigned radv_cayman_get_maxdist(int log_samples);
999 void radv_device_init_msaa(struct radv_device *device);
1000 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1001 struct radv_image *image,
1002 VkClearDepthStencilValue ds_clear_value,
1003 VkImageAspectFlags aspects);
1004 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1005 struct radv_image *image,
1006 int idx,
1007 uint32_t color_values[2]);
1008 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1009 struct radv_image *image,
1010 bool value);
1011 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1012 struct radeon_winsys_bo *bo,
1013 uint64_t offset, uint64_t size, uint32_t value);
1014 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1015 bool radv_get_memory_fd(struct radv_device *device,
1016 struct radv_device_memory *memory,
1017 int *pFD);
1018
1019 /*
1020 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1021 *
1022 * Limitations: Can't call normal dispatch functions without binding or rebinding
1023 * the compute pipeline.
1024 */
1025 void radv_unaligned_dispatch(
1026 struct radv_cmd_buffer *cmd_buffer,
1027 uint32_t x,
1028 uint32_t y,
1029 uint32_t z);
1030
1031 struct radv_event {
1032 struct radeon_winsys_bo *bo;
1033 uint64_t *map;
1034 };
1035
1036 struct radv_shader_module;
1037
1038 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1039 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1040 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1041 void
1042 radv_hash_shaders(unsigned char *hash,
1043 const VkPipelineShaderStageCreateInfo **stages,
1044 const struct radv_pipeline_layout *layout,
1045 const struct radv_pipeline_key *key,
1046 uint32_t flags);
1047
1048 static inline gl_shader_stage
1049 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1050 {
1051 assert(__builtin_popcount(vk_stage) == 1);
1052 return ffs(vk_stage) - 1;
1053 }
1054
1055 static inline VkShaderStageFlagBits
1056 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1057 {
1058 return (1 << mesa_stage);
1059 }
1060
1061 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1062
1063 #define radv_foreach_stage(stage, stage_bits) \
1064 for (gl_shader_stage stage, \
1065 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1066 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1067 __tmp &= ~(1 << (stage)))
1068
1069 struct radv_depth_stencil_state {
1070 uint32_t db_depth_control;
1071 uint32_t db_stencil_control;
1072 uint32_t db_render_control;
1073 uint32_t db_render_override2;
1074 };
1075
1076 struct radv_blend_state {
1077 uint32_t cb_color_control;
1078 uint32_t cb_target_mask;
1079 uint32_t sx_mrt_blend_opt[8];
1080 uint32_t cb_blend_control[8];
1081
1082 uint32_t spi_shader_col_format;
1083 uint32_t cb_shader_mask;
1084 uint32_t db_alpha_to_mask;
1085 };
1086
1087 unsigned radv_format_meta_fs_key(VkFormat format);
1088
1089 struct radv_raster_state {
1090 uint32_t pa_cl_clip_cntl;
1091 uint32_t spi_interp_control;
1092 uint32_t pa_su_vtx_cntl;
1093 uint32_t pa_su_sc_mode_cntl;
1094 };
1095
1096 struct radv_multisample_state {
1097 uint32_t db_eqaa;
1098 uint32_t pa_sc_line_cntl;
1099 uint32_t pa_sc_mode_cntl_0;
1100 uint32_t pa_sc_mode_cntl_1;
1101 uint32_t pa_sc_aa_config;
1102 uint32_t pa_sc_aa_mask[2];
1103 unsigned num_samples;
1104 };
1105
1106 struct radv_prim_vertex_count {
1107 uint8_t min;
1108 uint8_t incr;
1109 };
1110
1111 struct radv_tessellation_state {
1112 uint32_t ls_hs_config;
1113 uint32_t tcs_in_layout;
1114 uint32_t tcs_out_layout;
1115 uint32_t tcs_out_offsets;
1116 uint32_t offchip_layout;
1117 unsigned num_patches;
1118 unsigned lds_size;
1119 unsigned num_tcs_input_cp;
1120 uint32_t tf_param;
1121 };
1122
1123 struct radv_gs_state {
1124 uint32_t vgt_gs_onchip_cntl;
1125 uint32_t vgt_gs_max_prims_per_subgroup;
1126 uint32_t vgt_esgs_ring_itemsize;
1127 uint32_t lds_size;
1128 };
1129
1130 struct radv_vertex_elements_info {
1131 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1132 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1133 uint32_t binding[MAX_VERTEX_ATTRIBS];
1134 uint32_t offset[MAX_VERTEX_ATTRIBS];
1135 uint32_t count;
1136 };
1137
1138 struct radv_vs_state {
1139 uint32_t pa_cl_vs_out_cntl;
1140 uint32_t spi_shader_pos_format;
1141 uint32_t spi_vs_out_config;
1142 uint32_t vgt_reuse_off;
1143 };
1144
1145 #define SI_GS_PER_ES 128
1146
1147 struct radv_pipeline {
1148 struct radv_device * device;
1149 struct radv_dynamic_state dynamic_state;
1150
1151 struct radv_pipeline_layout * layout;
1152
1153 bool needs_data_cache;
1154 bool need_indirect_descriptor_sets;
1155 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1156 struct radv_shader_variant *gs_copy_shader;
1157 VkShaderStageFlags active_stages;
1158
1159 struct radv_vertex_elements_info vertex_elements;
1160
1161 uint32_t binding_stride[MAX_VBS];
1162
1163 uint32_t user_data_0[MESA_SHADER_STAGES];
1164 union {
1165 struct {
1166 struct radv_blend_state blend;
1167 struct radv_depth_stencil_state ds;
1168 struct radv_raster_state raster;
1169 struct radv_multisample_state ms;
1170 struct radv_tessellation_state tess;
1171 struct radv_gs_state gs;
1172 struct radv_vs_state vs;
1173 uint32_t db_shader_control;
1174 uint32_t shader_z_format;
1175 unsigned prim;
1176 unsigned gs_out;
1177 uint32_t vgt_gs_mode;
1178 bool vgt_primitiveid_en;
1179 bool prim_restart_enable;
1180 bool partial_es_wave;
1181 uint8_t primgroup_size;
1182 unsigned esgs_ring_size;
1183 unsigned gsvs_ring_size;
1184 uint32_t ps_input_cntl[32];
1185 uint32_t ps_input_cntl_num;
1186 uint32_t vgt_shader_stages_en;
1187 uint32_t vtx_base_sgpr;
1188 uint32_t base_ia_multi_vgt_param;
1189 bool wd_switch_on_eop;
1190 bool ia_switch_on_eoi;
1191 bool partial_vs_wave;
1192 uint8_t vtx_emit_num;
1193 uint32_t vtx_reuse_depth;
1194 struct radv_prim_vertex_count prim_vertex_count;
1195 bool can_use_guardband;
1196 } graphics;
1197 };
1198
1199 unsigned max_waves;
1200 unsigned scratch_bytes_per_wave;
1201 };
1202
1203 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1204 {
1205 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1206 }
1207
1208 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1209 {
1210 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1211 }
1212
1213 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1214 gl_shader_stage stage,
1215 int idx);
1216
1217 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1218
1219 struct radv_graphics_pipeline_create_info {
1220 bool use_rectlist;
1221 bool db_depth_clear;
1222 bool db_stencil_clear;
1223 bool db_depth_disable_expclear;
1224 bool db_stencil_disable_expclear;
1225 bool db_flush_depth_inplace;
1226 bool db_flush_stencil_inplace;
1227 bool db_resummarize;
1228 uint32_t custom_blend_mode;
1229 };
1230
1231 VkResult
1232 radv_graphics_pipeline_create(VkDevice device,
1233 VkPipelineCache cache,
1234 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1235 const struct radv_graphics_pipeline_create_info *extra,
1236 const VkAllocationCallbacks *alloc,
1237 VkPipeline *pPipeline);
1238
1239 struct vk_format_description;
1240 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1241 int first_non_void);
1242 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1243 int first_non_void);
1244 uint32_t radv_translate_colorformat(VkFormat format);
1245 uint32_t radv_translate_color_numformat(VkFormat format,
1246 const struct vk_format_description *desc,
1247 int first_non_void);
1248 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1249 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1250 uint32_t radv_translate_dbformat(VkFormat format);
1251 uint32_t radv_translate_tex_dataformat(VkFormat format,
1252 const struct vk_format_description *desc,
1253 int first_non_void);
1254 uint32_t radv_translate_tex_numformat(VkFormat format,
1255 const struct vk_format_description *desc,
1256 int first_non_void);
1257 bool radv_format_pack_clear_color(VkFormat format,
1258 uint32_t clear_vals[2],
1259 VkClearColorValue *value);
1260 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1261 bool radv_dcc_formats_compatible(VkFormat format1,
1262 VkFormat format2);
1263
1264 struct radv_fmask_info {
1265 uint64_t offset;
1266 uint64_t size;
1267 unsigned alignment;
1268 unsigned pitch_in_pixels;
1269 unsigned bank_height;
1270 unsigned slice_tile_max;
1271 unsigned tile_mode_index;
1272 unsigned tile_swizzle;
1273 };
1274
1275 struct radv_cmask_info {
1276 uint64_t offset;
1277 uint64_t size;
1278 unsigned alignment;
1279 unsigned slice_tile_max;
1280 };
1281
1282 struct radv_image {
1283 VkImageType type;
1284 /* The original VkFormat provided by the client. This may not match any
1285 * of the actual surface formats.
1286 */
1287 VkFormat vk_format;
1288 VkImageAspectFlags aspects;
1289 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1290 struct ac_surf_info info;
1291 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1292 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1293
1294 VkDeviceSize size;
1295 uint32_t alignment;
1296
1297 unsigned queue_family_mask;
1298 bool exclusive;
1299 bool shareable;
1300
1301 /* Set when bound */
1302 struct radeon_winsys_bo *bo;
1303 VkDeviceSize offset;
1304 uint64_t dcc_offset;
1305 uint64_t htile_offset;
1306 bool tc_compatible_htile;
1307 struct radeon_surf surface;
1308
1309 struct radv_fmask_info fmask;
1310 struct radv_cmask_info cmask;
1311 uint64_t clear_value_offset;
1312 uint64_t dcc_pred_offset;
1313 };
1314
1315 /* Whether the image has a htile that is known consistent with the contents of
1316 * the image. */
1317 bool radv_layout_has_htile(const struct radv_image *image,
1318 VkImageLayout layout,
1319 unsigned queue_mask);
1320
1321 /* Whether the image has a htile that is known consistent with the contents of
1322 * the image and is allowed to be in compressed form.
1323 *
1324 * If this is false reads that don't use the htile should be able to return
1325 * correct results.
1326 */
1327 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1328 VkImageLayout layout,
1329 unsigned queue_mask);
1330
1331 bool radv_layout_can_fast_clear(const struct radv_image *image,
1332 VkImageLayout layout,
1333 unsigned queue_mask);
1334
1335 static inline bool
1336 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1337 {
1338 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1339 }
1340
1341 static inline bool
1342 radv_htile_enabled(const struct radv_image *image, unsigned level)
1343 {
1344 return image->surface.htile_size && level == 0;
1345 }
1346
1347 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1348
1349 static inline uint32_t
1350 radv_get_layerCount(const struct radv_image *image,
1351 const VkImageSubresourceRange *range)
1352 {
1353 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1354 image->info.array_size - range->baseArrayLayer : range->layerCount;
1355 }
1356
1357 static inline uint32_t
1358 radv_get_levelCount(const struct radv_image *image,
1359 const VkImageSubresourceRange *range)
1360 {
1361 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1362 image->info.levels - range->baseMipLevel : range->levelCount;
1363 }
1364
1365 struct radeon_bo_metadata;
1366 void
1367 radv_init_metadata(struct radv_device *device,
1368 struct radv_image *image,
1369 struct radeon_bo_metadata *metadata);
1370
1371 struct radv_image_view {
1372 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1373 struct radeon_winsys_bo *bo;
1374
1375 VkImageViewType type;
1376 VkImageAspectFlags aspect_mask;
1377 VkFormat vk_format;
1378 uint32_t base_layer;
1379 uint32_t layer_count;
1380 uint32_t base_mip;
1381 uint32_t level_count;
1382 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1383
1384 uint32_t descriptor[16];
1385
1386 /* Descriptor for use as a storage image as opposed to a sampled image.
1387 * This has a few differences for cube maps (e.g. type).
1388 */
1389 uint32_t storage_descriptor[16];
1390 };
1391
1392 struct radv_image_create_info {
1393 const VkImageCreateInfo *vk_info;
1394 bool scanout;
1395 };
1396
1397 VkResult radv_image_create(VkDevice _device,
1398 const struct radv_image_create_info *info,
1399 const VkAllocationCallbacks* alloc,
1400 VkImage *pImage);
1401
1402 void radv_image_view_init(struct radv_image_view *view,
1403 struct radv_device *device,
1404 const VkImageViewCreateInfo* pCreateInfo);
1405
1406 struct radv_buffer_view {
1407 struct radeon_winsys_bo *bo;
1408 VkFormat vk_format;
1409 uint64_t range; /**< VkBufferViewCreateInfo::range */
1410 uint32_t state[4];
1411 };
1412 void radv_buffer_view_init(struct radv_buffer_view *view,
1413 struct radv_device *device,
1414 const VkBufferViewCreateInfo* pCreateInfo);
1415
1416 static inline struct VkExtent3D
1417 radv_sanitize_image_extent(const VkImageType imageType,
1418 const struct VkExtent3D imageExtent)
1419 {
1420 switch (imageType) {
1421 case VK_IMAGE_TYPE_1D:
1422 return (VkExtent3D) { imageExtent.width, 1, 1 };
1423 case VK_IMAGE_TYPE_2D:
1424 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1425 case VK_IMAGE_TYPE_3D:
1426 return imageExtent;
1427 default:
1428 unreachable("invalid image type");
1429 }
1430 }
1431
1432 static inline struct VkOffset3D
1433 radv_sanitize_image_offset(const VkImageType imageType,
1434 const struct VkOffset3D imageOffset)
1435 {
1436 switch (imageType) {
1437 case VK_IMAGE_TYPE_1D:
1438 return (VkOffset3D) { imageOffset.x, 0, 0 };
1439 case VK_IMAGE_TYPE_2D:
1440 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1441 case VK_IMAGE_TYPE_3D:
1442 return imageOffset;
1443 default:
1444 unreachable("invalid image type");
1445 }
1446 }
1447
1448 static inline bool
1449 radv_image_extent_compare(const struct radv_image *image,
1450 const VkExtent3D *extent)
1451 {
1452 if (extent->width != image->info.width ||
1453 extent->height != image->info.height ||
1454 extent->depth != image->info.depth)
1455 return false;
1456 return true;
1457 }
1458
1459 struct radv_sampler {
1460 uint32_t state[4];
1461 };
1462
1463 struct radv_color_buffer_info {
1464 uint64_t cb_color_base;
1465 uint64_t cb_color_cmask;
1466 uint64_t cb_color_fmask;
1467 uint64_t cb_dcc_base;
1468 uint32_t cb_color_pitch;
1469 uint32_t cb_color_slice;
1470 uint32_t cb_color_view;
1471 uint32_t cb_color_info;
1472 uint32_t cb_color_attrib;
1473 uint32_t cb_color_attrib2;
1474 uint32_t cb_dcc_control;
1475 uint32_t cb_color_cmask_slice;
1476 uint32_t cb_color_fmask_slice;
1477 uint32_t cb_clear_value0;
1478 uint32_t cb_clear_value1;
1479 };
1480
1481 struct radv_ds_buffer_info {
1482 uint64_t db_z_read_base;
1483 uint64_t db_stencil_read_base;
1484 uint64_t db_z_write_base;
1485 uint64_t db_stencil_write_base;
1486 uint64_t db_htile_data_base;
1487 uint32_t db_depth_info;
1488 uint32_t db_z_info;
1489 uint32_t db_stencil_info;
1490 uint32_t db_depth_view;
1491 uint32_t db_depth_size;
1492 uint32_t db_depth_slice;
1493 uint32_t db_htile_surface;
1494 uint32_t pa_su_poly_offset_db_fmt_cntl;
1495 uint32_t db_z_info2;
1496 uint32_t db_stencil_info2;
1497 float offset_scale;
1498 };
1499
1500 struct radv_attachment_info {
1501 union {
1502 struct radv_color_buffer_info cb;
1503 struct radv_ds_buffer_info ds;
1504 };
1505 struct radv_image_view *attachment;
1506 };
1507
1508 struct radv_framebuffer {
1509 uint32_t width;
1510 uint32_t height;
1511 uint32_t layers;
1512
1513 uint32_t attachment_count;
1514 struct radv_attachment_info attachments[0];
1515 };
1516
1517 struct radv_subpass_barrier {
1518 VkPipelineStageFlags src_stage_mask;
1519 VkAccessFlags src_access_mask;
1520 VkAccessFlags dst_access_mask;
1521 };
1522
1523 struct radv_subpass {
1524 uint32_t input_count;
1525 uint32_t color_count;
1526 VkAttachmentReference * input_attachments;
1527 VkAttachmentReference * color_attachments;
1528 VkAttachmentReference * resolve_attachments;
1529 VkAttachmentReference depth_stencil_attachment;
1530
1531 /** Subpass has at least one resolve attachment */
1532 bool has_resolve;
1533
1534 struct radv_subpass_barrier start_barrier;
1535
1536 uint32_t view_mask;
1537 };
1538
1539 struct radv_render_pass_attachment {
1540 VkFormat format;
1541 uint32_t samples;
1542 VkAttachmentLoadOp load_op;
1543 VkAttachmentLoadOp stencil_load_op;
1544 VkImageLayout initial_layout;
1545 VkImageLayout final_layout;
1546 uint32_t view_mask;
1547 };
1548
1549 struct radv_render_pass {
1550 uint32_t attachment_count;
1551 uint32_t subpass_count;
1552 VkAttachmentReference * subpass_attachments;
1553 struct radv_render_pass_attachment * attachments;
1554 struct radv_subpass_barrier end_barrier;
1555 struct radv_subpass subpasses[0];
1556 };
1557
1558 VkResult radv_device_init_meta(struct radv_device *device);
1559 void radv_device_finish_meta(struct radv_device *device);
1560
1561 struct radv_query_pool {
1562 struct radeon_winsys_bo *bo;
1563 uint32_t stride;
1564 uint32_t availability_offset;
1565 char *ptr;
1566 VkQueryType type;
1567 uint32_t pipeline_stats_mask;
1568 };
1569
1570 struct radv_semaphore {
1571 /* use a winsys sem for non-exportable */
1572 struct radeon_winsys_sem *sem;
1573 uint32_t syncobj;
1574 uint32_t temp_syncobj;
1575 };
1576
1577 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1578 int num_wait_sems,
1579 const VkSemaphore *wait_sems,
1580 int num_signal_sems,
1581 const VkSemaphore *signal_sems,
1582 VkFence fence);
1583 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1584
1585 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1586 struct radv_descriptor_set *set,
1587 unsigned idx);
1588
1589 void
1590 radv_update_descriptor_sets(struct radv_device *device,
1591 struct radv_cmd_buffer *cmd_buffer,
1592 VkDescriptorSet overrideSet,
1593 uint32_t descriptorWriteCount,
1594 const VkWriteDescriptorSet *pDescriptorWrites,
1595 uint32_t descriptorCopyCount,
1596 const VkCopyDescriptorSet *pDescriptorCopies);
1597
1598 void
1599 radv_update_descriptor_set_with_template(struct radv_device *device,
1600 struct radv_cmd_buffer *cmd_buffer,
1601 struct radv_descriptor_set *set,
1602 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1603 const void *pData);
1604
1605 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1606 VkPipelineBindPoint pipelineBindPoint,
1607 VkPipelineLayout _layout,
1608 uint32_t set,
1609 uint32_t descriptorWriteCount,
1610 const VkWriteDescriptorSet *pDescriptorWrites);
1611
1612 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1613 struct radv_image *image, uint32_t value);
1614 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1615 struct radv_image *image, uint32_t value);
1616
1617 struct radv_fence {
1618 struct radeon_winsys_fence *fence;
1619 bool submitted;
1620 bool signalled;
1621
1622 uint32_t syncobj;
1623 uint32_t temp_syncobj;
1624 };
1625
1626 struct radeon_winsys_sem;
1627
1628 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1629 \
1630 static inline struct __radv_type * \
1631 __radv_type ## _from_handle(__VkType _handle) \
1632 { \
1633 return (struct __radv_type *) _handle; \
1634 } \
1635 \
1636 static inline __VkType \
1637 __radv_type ## _to_handle(struct __radv_type *_obj) \
1638 { \
1639 return (__VkType) _obj; \
1640 }
1641
1642 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1643 \
1644 static inline struct __radv_type * \
1645 __radv_type ## _from_handle(__VkType _handle) \
1646 { \
1647 return (struct __radv_type *)(uintptr_t) _handle; \
1648 } \
1649 \
1650 static inline __VkType \
1651 __radv_type ## _to_handle(struct __radv_type *_obj) \
1652 { \
1653 return (__VkType)(uintptr_t) _obj; \
1654 }
1655
1656 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1657 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1658
1659 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1660 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1661 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1662 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1663 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1664
1665 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1666 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1667 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1668 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1669 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1670 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1671 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1672 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1673 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1674 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1675 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1676 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1677 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1678 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1679 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1680 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1681 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1682 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1683 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1684 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1685 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1686
1687 #endif /* RADV_PRIVATE_H */