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radv: Add VkPhysicalDeviceIDProperties support.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/vk_alloc.h"
51 #include "main/macros.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "radv_debug.h"
57 #include "radv_descriptor_set.h"
58
59 #include <llvm-c/TargetMachine.h>
60
61 /* Pre-declarations needed for WSI entrypoints */
62 struct wl_surface;
63 struct wl_display;
64 typedef struct xcb_connection_t xcb_connection_t;
65 typedef uint32_t xcb_visualid_t;
66 typedef uint32_t xcb_window_t;
67
68 #include <vulkan/vulkan.h>
69 #include <vulkan/vulkan_intel.h>
70 #include <vulkan/vk_icd.h>
71
72 #include "radv_entrypoints.h"
73
74 #include "wsi_common.h"
75
76 #define MAX_VBS 32
77 #define MAX_VERTEX_ATTRIBS 32
78 #define MAX_RTS 8
79 #define MAX_VIEWPORTS 16
80 #define MAX_SCISSORS 16
81 #define MAX_PUSH_CONSTANTS_SIZE 128
82 #define MAX_PUSH_DESCRIPTORS 32
83 #define MAX_DYNAMIC_BUFFERS 16
84 #define MAX_SAMPLES_LOG2 4
85 #define NUM_META_FS_KEYS 11
86 #define RADV_MAX_DRM_DEVICES 8
87
88 #define NUM_DEPTH_CLEAR_PIPELINES 3
89
90 enum radv_mem_heap {
91 RADV_MEM_HEAP_VRAM,
92 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
93 RADV_MEM_HEAP_GTT,
94 RADV_MEM_HEAP_COUNT
95 };
96
97 enum radv_mem_type {
98 RADV_MEM_TYPE_VRAM,
99 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
100 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
101 RADV_MEM_TYPE_GTT_CACHED,
102 RADV_MEM_TYPE_COUNT
103 };
104
105 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
106
107 static inline uint32_t
108 align_u32(uint32_t v, uint32_t a)
109 {
110 assert(a != 0 && a == (a & -a));
111 return (v + a - 1) & ~(a - 1);
112 }
113
114 static inline uint32_t
115 align_u32_npot(uint32_t v, uint32_t a)
116 {
117 return (v + a - 1) / a * a;
118 }
119
120 static inline uint64_t
121 align_u64(uint64_t v, uint64_t a)
122 {
123 assert(a != 0 && a == (a & -a));
124 return (v + a - 1) & ~(a - 1);
125 }
126
127 static inline int32_t
128 align_i32(int32_t v, int32_t a)
129 {
130 assert(a != 0 && a == (a & -a));
131 return (v + a - 1) & ~(a - 1);
132 }
133
134 /** Alignment must be a power of 2. */
135 static inline bool
136 radv_is_aligned(uintmax_t n, uintmax_t a)
137 {
138 assert(a == (a & -a));
139 return (n & (a - 1)) == 0;
140 }
141
142 static inline uint32_t
143 round_up_u32(uint32_t v, uint32_t a)
144 {
145 return (v + a - 1) / a;
146 }
147
148 static inline uint64_t
149 round_up_u64(uint64_t v, uint64_t a)
150 {
151 return (v + a - 1) / a;
152 }
153
154 static inline uint32_t
155 radv_minify(uint32_t n, uint32_t levels)
156 {
157 if (unlikely(n == 0))
158 return 0;
159 else
160 return MAX2(n >> levels, 1);
161 }
162 static inline float
163 radv_clamp_f(float f, float min, float max)
164 {
165 assert(min < max);
166
167 if (f > max)
168 return max;
169 else if (f < min)
170 return min;
171 else
172 return f;
173 }
174
175 static inline bool
176 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
177 {
178 if (*inout_mask & clear_mask) {
179 *inout_mask &= ~clear_mask;
180 return true;
181 } else {
182 return false;
183 }
184 }
185
186 #define for_each_bit(b, dword) \
187 for (uint32_t __dword = (dword); \
188 (b) = __builtin_ffs(__dword) - 1, __dword; \
189 __dword &= ~(1 << (b)))
190
191 #define typed_memcpy(dest, src, count) ({ \
192 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
193 memcpy((dest), (src), (count) * sizeof(*(src))); \
194 })
195
196 #define zero(x) (memset(&(x), 0, sizeof(x)))
197
198 /* Whenever we generate an error, pass it through this function. Useful for
199 * debugging, where we can break on it. Only call at error site, not when
200 * propagating errors. Might be useful to plug in a stack trace here.
201 */
202
203 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
204
205 #ifdef DEBUG
206 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
207 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
208 #else
209 #define vk_error(error) error
210 #define vk_errorf(error, format, ...) error
211 #endif
212
213 void __radv_finishme(const char *file, int line, const char *format, ...)
214 radv_printflike(3, 4);
215 void radv_loge(const char *format, ...) radv_printflike(1, 2);
216 void radv_loge_v(const char *format, va_list va);
217
218 /**
219 * Print a FINISHME message, including its source location.
220 */
221 #define radv_finishme(format, ...) \
222 do { \
223 static bool reported = false; \
224 if (!reported) { \
225 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
226 reported = true; \
227 } \
228 } while (0)
229
230 /* A non-fatal assert. Useful for debugging. */
231 #ifdef DEBUG
232 #define radv_assert(x) ({ \
233 if (unlikely(!(x))) \
234 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
235 })
236 #else
237 #define radv_assert(x)
238 #endif
239
240 #define stub_return(v) \
241 do { \
242 radv_finishme("stub %s", __func__); \
243 return (v); \
244 } while (0)
245
246 #define stub() \
247 do { \
248 radv_finishme("stub %s", __func__); \
249 return; \
250 } while (0)
251
252 void *radv_lookup_entrypoint(const char *name);
253
254 struct radv_extensions {
255 VkExtensionProperties *ext_array;
256 uint32_t num_ext;
257 };
258
259 struct radv_physical_device {
260 VK_LOADER_DATA _loader_data;
261
262 struct radv_instance * instance;
263
264 struct radeon_winsys *ws;
265 struct radeon_info rad_info;
266 char path[20];
267 const char * name;
268 uint8_t uuid[VK_UUID_SIZE];
269 uint8_t device_uuid[VK_UUID_SIZE];
270
271 int local_fd;
272 struct wsi_device wsi_device;
273 struct radv_extensions extensions;
274 };
275
276 struct radv_instance {
277 VK_LOADER_DATA _loader_data;
278
279 VkAllocationCallbacks alloc;
280
281 uint32_t apiVersion;
282 int physicalDeviceCount;
283 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
284
285 uint64_t debug_flags;
286 };
287
288 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
289 void radv_finish_wsi(struct radv_physical_device *physical_device);
290
291 struct cache_entry;
292
293 struct radv_pipeline_cache {
294 struct radv_device * device;
295 pthread_mutex_t mutex;
296
297 uint32_t total_size;
298 uint32_t table_size;
299 uint32_t kernel_count;
300 struct cache_entry ** hash_table;
301 bool modified;
302
303 VkAllocationCallbacks alloc;
304 };
305
306 void
307 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
308 struct radv_device *device);
309 void
310 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
311 void
312 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
313 const void *data, size_t size);
314
315 struct radv_shader_variant *
316 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
317 struct radv_pipeline_cache *cache,
318 const unsigned char *sha1);
319
320 struct radv_shader_variant *
321 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
322 const unsigned char *sha1,
323 struct radv_shader_variant *variant,
324 const void *code, unsigned code_size);
325
326 void radv_shader_variant_destroy(struct radv_device *device,
327 struct radv_shader_variant *variant);
328
329 struct radv_meta_state {
330 VkAllocationCallbacks alloc;
331
332 struct radv_pipeline_cache cache;
333
334 /**
335 * Use array element `i` for images with `2^i` samples.
336 */
337 struct {
338 VkRenderPass render_pass[NUM_META_FS_KEYS];
339 struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
340
341 VkRenderPass depthstencil_rp;
342 struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
343 struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
344 struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
345 } clear[1 + MAX_SAMPLES_LOG2];
346
347 VkPipelineLayout clear_color_p_layout;
348 VkPipelineLayout clear_depth_p_layout;
349 struct {
350 VkRenderPass render_pass[NUM_META_FS_KEYS];
351
352 /** Pipeline that blits from a 1D image. */
353 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
354
355 /** Pipeline that blits from a 2D image. */
356 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
357
358 /** Pipeline that blits from a 3D image. */
359 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
360
361 VkRenderPass depth_only_rp;
362 VkPipeline depth_only_1d_pipeline;
363 VkPipeline depth_only_2d_pipeline;
364 VkPipeline depth_only_3d_pipeline;
365
366 VkRenderPass stencil_only_rp;
367 VkPipeline stencil_only_1d_pipeline;
368 VkPipeline stencil_only_2d_pipeline;
369 VkPipeline stencil_only_3d_pipeline;
370 VkPipelineLayout pipeline_layout;
371 VkDescriptorSetLayout ds_layout;
372 } blit;
373
374 struct {
375 VkRenderPass render_passes[NUM_META_FS_KEYS];
376
377 VkPipelineLayout p_layouts[2];
378 VkDescriptorSetLayout ds_layouts[2];
379 VkPipeline pipelines[2][NUM_META_FS_KEYS];
380
381 VkRenderPass depth_only_rp;
382 VkPipeline depth_only_pipeline[2];
383
384 VkRenderPass stencil_only_rp;
385 VkPipeline stencil_only_pipeline[2];
386 } blit2d;
387
388 struct {
389 VkPipelineLayout img_p_layout;
390 VkDescriptorSetLayout img_ds_layout;
391 VkPipeline pipeline;
392 } itob;
393 struct {
394 VkRenderPass render_pass;
395 VkPipelineLayout img_p_layout;
396 VkDescriptorSetLayout img_ds_layout;
397 VkPipeline pipeline;
398 } btoi;
399 struct {
400 VkPipelineLayout img_p_layout;
401 VkDescriptorSetLayout img_ds_layout;
402 VkPipeline pipeline;
403 } itoi;
404 struct {
405 VkPipelineLayout img_p_layout;
406 VkDescriptorSetLayout img_ds_layout;
407 VkPipeline pipeline;
408 } cleari;
409
410 struct {
411 VkPipeline pipeline;
412 VkRenderPass pass;
413 } resolve;
414
415 struct {
416 VkDescriptorSetLayout ds_layout;
417 VkPipelineLayout p_layout;
418 struct {
419 VkPipeline pipeline;
420 VkPipeline i_pipeline;
421 VkPipeline srgb_pipeline;
422 } rc[MAX_SAMPLES_LOG2];
423 } resolve_compute;
424
425 struct {
426 VkDescriptorSetLayout ds_layout;
427 VkPipelineLayout p_layout;
428
429 struct {
430 VkRenderPass srgb_render_pass;
431 VkPipeline srgb_pipeline;
432 VkRenderPass render_pass[NUM_META_FS_KEYS];
433 VkPipeline pipeline[NUM_META_FS_KEYS];
434 } rc[MAX_SAMPLES_LOG2];
435 } resolve_fragment;
436
437 struct {
438 VkPipeline decompress_pipeline;
439 VkPipeline resummarize_pipeline;
440 VkRenderPass pass;
441 } depth_decomp;
442
443 struct {
444 VkPipeline cmask_eliminate_pipeline;
445 VkPipeline fmask_decompress_pipeline;
446 VkRenderPass pass;
447 } fast_clear_flush;
448
449 struct {
450 VkPipelineLayout fill_p_layout;
451 VkPipelineLayout copy_p_layout;
452 VkDescriptorSetLayout fill_ds_layout;
453 VkDescriptorSetLayout copy_ds_layout;
454 VkPipeline fill_pipeline;
455 VkPipeline copy_pipeline;
456 } buffer;
457
458 struct {
459 VkDescriptorSetLayout ds_layout;
460 VkPipelineLayout p_layout;
461 VkPipeline occlusion_query_pipeline;
462 VkPipeline pipeline_statistics_query_pipeline;
463 } query;
464 };
465
466 /* queue types */
467 #define RADV_QUEUE_GENERAL 0
468 #define RADV_QUEUE_COMPUTE 1
469 #define RADV_QUEUE_TRANSFER 2
470
471 #define RADV_MAX_QUEUE_FAMILIES 3
472
473 enum ring_type radv_queue_family_to_ring(int f);
474
475 struct radv_queue {
476 VK_LOADER_DATA _loader_data;
477 struct radv_device * device;
478 struct radeon_winsys_ctx *hw_ctx;
479 int queue_family_index;
480 int queue_idx;
481
482 uint32_t scratch_size;
483 uint32_t compute_scratch_size;
484 uint32_t esgs_ring_size;
485 uint32_t gsvs_ring_size;
486 bool has_tess_rings;
487 bool has_sample_positions;
488
489 struct radeon_winsys_bo *scratch_bo;
490 struct radeon_winsys_bo *descriptor_bo;
491 struct radeon_winsys_bo *compute_scratch_bo;
492 struct radeon_winsys_bo *esgs_ring_bo;
493 struct radeon_winsys_bo *gsvs_ring_bo;
494 struct radeon_winsys_bo *tess_factor_ring_bo;
495 struct radeon_winsys_bo *tess_offchip_ring_bo;
496 struct radeon_winsys_cs *initial_preamble_cs;
497 struct radeon_winsys_cs *continue_preamble_cs;
498 };
499
500 struct radv_device {
501 VK_LOADER_DATA _loader_data;
502
503 VkAllocationCallbacks alloc;
504
505 struct radv_instance * instance;
506 struct radeon_winsys *ws;
507
508 struct radv_meta_state meta_state;
509
510 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
511 int queue_count[RADV_MAX_QUEUE_FAMILIES];
512 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
513 struct radeon_winsys_cs *flush_cs[RADV_MAX_QUEUE_FAMILIES];
514 struct radeon_winsys_cs *flush_shader_cs[RADV_MAX_QUEUE_FAMILIES];
515 uint64_t debug_flags;
516
517 bool llvm_supports_spill;
518 bool has_distributed_tess;
519 uint32_t tess_offchip_block_dw_size;
520 uint32_t scratch_waves;
521
522 uint32_t gs_table_depth;
523
524 /* MSAA sample locations.
525 * The first index is the sample index.
526 * The second index is the coordinate: X, Y. */
527 float sample_locations_1x[1][2];
528 float sample_locations_2x[2][2];
529 float sample_locations_4x[4][2];
530 float sample_locations_8x[8][2];
531 float sample_locations_16x[16][2];
532
533 /* CIK and later */
534 uint32_t gfx_init_size_dw;
535 struct radeon_winsys_bo *gfx_init;
536
537 struct radeon_winsys_bo *trace_bo;
538 uint32_t *trace_id_ptr;
539
540 struct radv_physical_device *physical_device;
541
542 /* Backup in-memory cache to be used if the app doesn't provide one */
543 struct radv_pipeline_cache * mem_cache;
544 };
545
546 struct radv_device_memory {
547 struct radeon_winsys_bo *bo;
548 /* for dedicated allocations */
549 struct radv_image *image;
550 struct radv_buffer *buffer;
551 uint32_t type_index;
552 VkDeviceSize map_size;
553 void * map;
554 };
555
556
557 struct radv_descriptor_range {
558 uint64_t va;
559 uint32_t size;
560 };
561
562 struct radv_descriptor_set {
563 const struct radv_descriptor_set_layout *layout;
564 uint32_t size;
565
566 struct radeon_winsys_bo *bo;
567 uint64_t va;
568 uint32_t *mapped_ptr;
569 struct radv_descriptor_range *dynamic_descriptors;
570
571 struct list_head vram_list;
572
573 struct radeon_winsys_bo *descriptors[0];
574 };
575
576 struct radv_push_descriptor_set
577 {
578 struct radv_descriptor_set set;
579 uint32_t capacity;
580 };
581
582 struct radv_descriptor_pool {
583 struct radeon_winsys_bo *bo;
584 uint8_t *mapped_ptr;
585 uint64_t current_offset;
586 uint64_t size;
587
588 struct list_head vram_list;
589
590 uint8_t *host_memory_base;
591 uint8_t *host_memory_ptr;
592 uint8_t *host_memory_end;
593 };
594
595 struct radv_descriptor_update_template_entry {
596 VkDescriptorType descriptor_type;
597
598 /* The number of descriptors to update */
599 uint32_t descriptor_count;
600
601 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
602 uint32_t dst_offset;
603
604 /* In dwords. Not valid/used for dynamic descriptors */
605 uint32_t dst_stride;
606
607 uint32_t buffer_offset;
608
609 /* Only valid for combined image samplers and samplers */
610 uint16_t has_sampler;
611
612 /* In bytes */
613 size_t src_offset;
614 size_t src_stride;
615
616 /* For push descriptors */
617 const uint32_t *immutable_samplers;
618 };
619
620 struct radv_descriptor_update_template {
621 uint32_t entry_count;
622 struct radv_descriptor_update_template_entry entry[0];
623 };
624
625 struct radv_buffer {
626 struct radv_device * device;
627 VkDeviceSize size;
628
629 VkBufferUsageFlags usage;
630 VkBufferCreateFlags flags;
631
632 /* Set when bound */
633 struct radeon_winsys_bo * bo;
634 VkDeviceSize offset;
635 };
636
637
638 enum radv_cmd_dirty_bits {
639 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
640 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
641 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
642 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
643 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
644 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
645 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
646 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
647 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
648 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
649 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
650 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
651 RADV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
652 };
653 typedef uint32_t radv_cmd_dirty_mask_t;
654
655 enum radv_cmd_flush_bits {
656 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
657 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
658 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
659 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
660 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
661 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
662 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
663 /* Same as above, but only writes back and doesn't invalidate */
664 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
665 /* Framebuffer caches */
666 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
667 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
668 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
669 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
670 /* Engine synchronization. */
671 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
672 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
673 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
674 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
675
676 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
677 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
678 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
679 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
680 };
681
682 struct radv_vertex_binding {
683 struct radv_buffer * buffer;
684 VkDeviceSize offset;
685 };
686
687 struct radv_dynamic_state {
688 struct {
689 uint32_t count;
690 VkViewport viewports[MAX_VIEWPORTS];
691 } viewport;
692
693 struct {
694 uint32_t count;
695 VkRect2D scissors[MAX_SCISSORS];
696 } scissor;
697
698 float line_width;
699
700 struct {
701 float bias;
702 float clamp;
703 float slope;
704 } depth_bias;
705
706 float blend_constants[4];
707
708 struct {
709 float min;
710 float max;
711 } depth_bounds;
712
713 struct {
714 uint32_t front;
715 uint32_t back;
716 } stencil_compare_mask;
717
718 struct {
719 uint32_t front;
720 uint32_t back;
721 } stencil_write_mask;
722
723 struct {
724 uint32_t front;
725 uint32_t back;
726 } stencil_reference;
727 };
728
729 extern const struct radv_dynamic_state default_dynamic_state;
730
731 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
732 const struct radv_dynamic_state *src,
733 uint32_t copy_mask);
734 /**
735 * Attachment state when recording a renderpass instance.
736 *
737 * The clear value is valid only if there exists a pending clear.
738 */
739 struct radv_attachment_state {
740 VkImageAspectFlags pending_clear_aspects;
741 VkClearValue clear_value;
742 VkImageLayout current_layout;
743 };
744
745 struct radv_cmd_state {
746 uint32_t vb_dirty;
747 radv_cmd_dirty_mask_t dirty;
748 bool vertex_descriptors_dirty;
749 bool push_descriptors_dirty;
750
751 struct radv_pipeline * pipeline;
752 struct radv_pipeline * emitted_pipeline;
753 struct radv_pipeline * compute_pipeline;
754 struct radv_pipeline * emitted_compute_pipeline;
755 struct radv_framebuffer * framebuffer;
756 struct radv_render_pass * pass;
757 const struct radv_subpass * subpass;
758 struct radv_dynamic_state dynamic;
759 struct radv_vertex_binding vertex_bindings[MAX_VBS];
760 struct radv_descriptor_set * descriptors[MAX_SETS];
761 struct radv_attachment_state * attachments;
762 VkRect2D render_area;
763 struct radv_buffer * index_buffer;
764 uint32_t index_type;
765 uint32_t index_offset;
766 int32_t last_primitive_reset_en;
767 uint32_t last_primitive_reset_index;
768 enum radv_cmd_flush_bits flush_bits;
769 unsigned active_occlusion_queries;
770 float offset_scale;
771 uint32_t descriptors_dirty;
772 uint32_t trace_id;
773 uint32_t last_ia_multi_vgt_param;
774 };
775
776 struct radv_cmd_pool {
777 VkAllocationCallbacks alloc;
778 struct list_head cmd_buffers;
779 struct list_head free_cmd_buffers;
780 uint32_t queue_family_index;
781 };
782
783 struct radv_cmd_buffer_upload {
784 uint8_t *map;
785 unsigned offset;
786 uint64_t size;
787 struct radeon_winsys_bo *upload_bo;
788 struct list_head list;
789 };
790
791 struct radv_cmd_buffer {
792 VK_LOADER_DATA _loader_data;
793
794 struct radv_device * device;
795
796 struct radv_cmd_pool * pool;
797 struct list_head pool_link;
798
799 VkCommandBufferUsageFlags usage_flags;
800 VkCommandBufferLevel level;
801 struct radeon_winsys_cs *cs;
802 struct radv_cmd_state state;
803 uint32_t queue_family_index;
804
805 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
806 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
807 VkShaderStageFlags push_constant_stages;
808 struct radv_push_descriptor_set push_descriptors;
809 struct radv_descriptor_set meta_push_descriptors;
810
811 struct radv_cmd_buffer_upload upload;
812
813 uint32_t scratch_size_needed;
814 uint32_t compute_scratch_size_needed;
815 uint32_t esgs_ring_size_needed;
816 uint32_t gsvs_ring_size_needed;
817 bool tess_rings_needed;
818 bool sample_positions_needed;
819
820 bool record_fail;
821
822 int ring_offsets_idx; /* just used for verification */
823 };
824
825 struct radv_image;
826
827 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
828
829 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
830 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
831
832 void cik_create_gfx_config(struct radv_device *device);
833
834 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
835 int count, const VkViewport *viewports);
836 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
837 int count, const VkRect2D *scissors,
838 const VkViewport *viewports, bool can_use_guardband);
839 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
840 bool instanced_draw, bool indirect_draw,
841 uint32_t draw_vertex_count);
842 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
843 enum chip_class chip_class,
844 bool is_mec,
845 unsigned event, unsigned event_flags,
846 unsigned data_sel,
847 uint64_t va,
848 uint32_t old_fence,
849 uint32_t new_fence);
850
851 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
852 uint64_t va, uint32_t ref,
853 uint32_t mask);
854 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
855 enum chip_class chip_class,
856 bool is_mec,
857 enum radv_cmd_flush_bits flush_bits);
858 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
859 enum chip_class chip_class,
860 bool is_mec,
861 enum radv_cmd_flush_bits flush_bits);
862 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
863 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
864 uint64_t src_va, uint64_t dest_va,
865 uint64_t size);
866 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
867 unsigned size);
868 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
869 uint64_t size, unsigned value);
870 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
871 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
872 struct radv_descriptor_set *set,
873 unsigned idx);
874 bool
875 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
876 unsigned size,
877 unsigned alignment,
878 unsigned *out_offset,
879 void **ptr);
880 void
881 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
882 const struct radv_subpass *subpass,
883 bool transitions);
884 bool
885 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
886 unsigned size, unsigned alignmnet,
887 const void *data, unsigned *out_offset);
888 void
889 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
890 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
891 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
892 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
893 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
894 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
895 unsigned radv_cayman_get_maxdist(int log_samples);
896 void radv_device_init_msaa(struct radv_device *device);
897 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
898 struct radv_image *image,
899 VkClearDepthStencilValue ds_clear_value,
900 VkImageAspectFlags aspects);
901 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
902 struct radv_image *image,
903 int idx,
904 uint32_t color_values[2]);
905 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
906 struct radeon_winsys_bo *bo,
907 uint64_t offset, uint64_t size, uint32_t value);
908 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
909 bool radv_get_memory_fd(struct radv_device *device,
910 struct radv_device_memory *memory,
911 int *pFD);
912 /*
913 * Takes x,y,z as exact numbers of invocations, instead of blocks.
914 *
915 * Limitations: Can't call normal dispatch functions without binding or rebinding
916 * the compute pipeline.
917 */
918 void radv_unaligned_dispatch(
919 struct radv_cmd_buffer *cmd_buffer,
920 uint32_t x,
921 uint32_t y,
922 uint32_t z);
923
924 struct radv_event {
925 struct radeon_winsys_bo *bo;
926 uint64_t *map;
927 };
928
929 struct nir_shader;
930
931 struct radv_shader_module {
932 struct nir_shader * nir;
933 unsigned char sha1[20];
934 uint32_t size;
935 char data[0];
936 };
937
938 union ac_shader_variant_key;
939
940 void
941 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
942 const char *entrypoint,
943 const VkSpecializationInfo *spec_info,
944 const struct radv_pipeline_layout *layout,
945 const union ac_shader_variant_key *key,
946 uint32_t is_geom_copy_shader);
947
948 static inline gl_shader_stage
949 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
950 {
951 assert(__builtin_popcount(vk_stage) == 1);
952 return ffs(vk_stage) - 1;
953 }
954
955 static inline VkShaderStageFlagBits
956 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
957 {
958 return (1 << mesa_stage);
959 }
960
961 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
962
963 #define radv_foreach_stage(stage, stage_bits) \
964 for (gl_shader_stage stage, \
965 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
966 stage = __builtin_ffs(__tmp) - 1, __tmp; \
967 __tmp &= ~(1 << (stage)))
968
969 struct radv_shader_variant {
970 uint32_t ref_count;
971
972 struct radeon_winsys_bo *bo;
973 struct ac_shader_config config;
974 struct ac_shader_variant_info info;
975 unsigned rsrc1;
976 unsigned rsrc2;
977 uint32_t code_size;
978 };
979
980 struct radv_depth_stencil_state {
981 uint32_t db_depth_control;
982 uint32_t db_stencil_control;
983 uint32_t db_render_control;
984 uint32_t db_render_override2;
985 };
986
987 struct radv_blend_state {
988 uint32_t cb_color_control;
989 uint32_t cb_target_mask;
990 uint32_t sx_mrt0_blend_opt[8];
991 uint32_t cb_blend_control[8];
992
993 uint32_t spi_shader_col_format;
994 uint32_t cb_shader_mask;
995 uint32_t db_alpha_to_mask;
996 };
997
998 unsigned radv_format_meta_fs_key(VkFormat format);
999
1000 struct radv_raster_state {
1001 uint32_t pa_cl_clip_cntl;
1002 uint32_t spi_interp_control;
1003 uint32_t pa_su_point_size;
1004 uint32_t pa_su_point_minmax;
1005 uint32_t pa_su_line_cntl;
1006 uint32_t pa_su_vtx_cntl;
1007 uint32_t pa_su_sc_mode_cntl;
1008 };
1009
1010 struct radv_multisample_state {
1011 uint32_t db_eqaa;
1012 uint32_t pa_sc_line_cntl;
1013 uint32_t pa_sc_mode_cntl_0;
1014 uint32_t pa_sc_mode_cntl_1;
1015 uint32_t pa_sc_aa_config;
1016 uint32_t pa_sc_aa_mask[2];
1017 unsigned num_samples;
1018 };
1019
1020 struct radv_prim_vertex_count {
1021 uint8_t min;
1022 uint8_t incr;
1023 };
1024
1025 struct radv_tessellation_state {
1026 uint32_t ls_hs_config;
1027 uint32_t tcs_in_layout;
1028 uint32_t tcs_out_layout;
1029 uint32_t tcs_out_offsets;
1030 uint32_t offchip_layout;
1031 unsigned num_patches;
1032 unsigned lds_size;
1033 unsigned num_tcs_input_cp;
1034 uint32_t tf_param;
1035 };
1036
1037 struct radv_pipeline {
1038 struct radv_device * device;
1039 uint32_t dynamic_state_mask;
1040 struct radv_dynamic_state dynamic_state;
1041
1042 struct radv_pipeline_layout * layout;
1043
1044 bool needs_data_cache;
1045 bool need_indirect_descriptor_sets;
1046 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1047 struct radv_shader_variant *gs_copy_shader;
1048 VkShaderStageFlags active_stages;
1049
1050 uint32_t va_rsrc_word3[MAX_VERTEX_ATTRIBS];
1051 uint32_t va_format_size[MAX_VERTEX_ATTRIBS];
1052 uint32_t va_binding[MAX_VERTEX_ATTRIBS];
1053 uint32_t va_offset[MAX_VERTEX_ATTRIBS];
1054 uint32_t num_vertex_attribs;
1055 uint32_t binding_stride[MAX_VBS];
1056
1057 union {
1058 struct {
1059 struct radv_blend_state blend;
1060 struct radv_depth_stencil_state ds;
1061 struct radv_raster_state raster;
1062 struct radv_multisample_state ms;
1063 struct radv_tessellation_state tess;
1064 uint32_t db_shader_control;
1065 uint32_t shader_z_format;
1066 unsigned prim;
1067 unsigned gs_out;
1068 uint32_t vgt_gs_mode;
1069 bool prim_restart_enable;
1070 unsigned esgs_ring_size;
1071 unsigned gsvs_ring_size;
1072 uint32_t ps_input_cntl[32];
1073 uint32_t ps_input_cntl_num;
1074 uint32_t pa_cl_vs_out_cntl;
1075 uint32_t vgt_shader_stages_en;
1076 struct radv_prim_vertex_count prim_vertex_count;
1077 bool can_use_guardband;
1078 } graphics;
1079 };
1080
1081 unsigned max_waves;
1082 unsigned scratch_bytes_per_wave;
1083 };
1084
1085 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1086 {
1087 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1088 }
1089
1090 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1091 {
1092 return pipeline->shaders[MESA_SHADER_TESS_EVAL] ? true : false;
1093 }
1094
1095 struct radv_graphics_pipeline_create_info {
1096 bool use_rectlist;
1097 bool db_depth_clear;
1098 bool db_stencil_clear;
1099 bool db_depth_disable_expclear;
1100 bool db_stencil_disable_expclear;
1101 bool db_flush_depth_inplace;
1102 bool db_flush_stencil_inplace;
1103 bool db_resummarize;
1104 uint32_t custom_blend_mode;
1105 };
1106
1107 VkResult
1108 radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
1109 struct radv_pipeline_cache *cache,
1110 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1111 const struct radv_graphics_pipeline_create_info *extra,
1112 const VkAllocationCallbacks *alloc);
1113
1114 VkResult
1115 radv_graphics_pipeline_create(VkDevice device,
1116 VkPipelineCache cache,
1117 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1118 const struct radv_graphics_pipeline_create_info *extra,
1119 const VkAllocationCallbacks *alloc,
1120 VkPipeline *pPipeline);
1121
1122 struct vk_format_description;
1123 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1124 int first_non_void);
1125 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1126 int first_non_void);
1127 uint32_t radv_translate_colorformat(VkFormat format);
1128 uint32_t radv_translate_color_numformat(VkFormat format,
1129 const struct vk_format_description *desc,
1130 int first_non_void);
1131 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1132 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1133 uint32_t radv_translate_dbformat(VkFormat format);
1134 uint32_t radv_translate_tex_dataformat(VkFormat format,
1135 const struct vk_format_description *desc,
1136 int first_non_void);
1137 uint32_t radv_translate_tex_numformat(VkFormat format,
1138 const struct vk_format_description *desc,
1139 int first_non_void);
1140 bool radv_format_pack_clear_color(VkFormat format,
1141 uint32_t clear_vals[2],
1142 VkClearColorValue *value);
1143 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1144
1145 struct radv_fmask_info {
1146 uint64_t offset;
1147 uint64_t size;
1148 unsigned alignment;
1149 unsigned pitch_in_pixels;
1150 unsigned bank_height;
1151 unsigned slice_tile_max;
1152 unsigned tile_mode_index;
1153 };
1154
1155 struct radv_cmask_info {
1156 uint64_t offset;
1157 uint64_t size;
1158 unsigned alignment;
1159 unsigned slice_tile_max;
1160 unsigned base_address_reg;
1161 };
1162
1163 struct r600_htile_info {
1164 uint64_t offset;
1165 uint64_t size;
1166 unsigned pitch;
1167 unsigned height;
1168 unsigned xalign;
1169 unsigned yalign;
1170 };
1171
1172 struct radv_image {
1173 VkImageType type;
1174 /* The original VkFormat provided by the client. This may not match any
1175 * of the actual surface formats.
1176 */
1177 VkFormat vk_format;
1178 VkImageAspectFlags aspects;
1179 struct radeon_surf_info info;
1180 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1181 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1182 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1183
1184 VkDeviceSize size;
1185 uint32_t alignment;
1186
1187 bool exclusive;
1188 unsigned queue_family_mask;
1189
1190 /* Set when bound */
1191 struct radeon_winsys_bo *bo;
1192 VkDeviceSize offset;
1193 uint32_t dcc_offset;
1194 uint32_t htile_offset;
1195 struct radeon_surf surface;
1196
1197 struct radv_fmask_info fmask;
1198 struct radv_cmask_info cmask;
1199 uint32_t clear_value_offset;
1200 };
1201
1202 /* Whether the image has a htile that is known consistent with the contents of
1203 * the image. */
1204 bool radv_layout_has_htile(const struct radv_image *image,
1205 VkImageLayout layout,
1206 unsigned queue_mask);
1207
1208 /* Whether the image has a htile that is known consistent with the contents of
1209 * the image and is allowed to be in compressed form.
1210 *
1211 * If this is false reads that don't use the htile should be able to return
1212 * correct results.
1213 */
1214 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1215 VkImageLayout layout,
1216 unsigned queue_mask);
1217
1218 bool radv_layout_can_fast_clear(const struct radv_image *image,
1219 VkImageLayout layout,
1220 unsigned queue_mask);
1221
1222
1223 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1224
1225 static inline uint32_t
1226 radv_get_layerCount(const struct radv_image *image,
1227 const VkImageSubresourceRange *range)
1228 {
1229 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1230 image->info.array_size - range->baseArrayLayer : range->layerCount;
1231 }
1232
1233 static inline uint32_t
1234 radv_get_levelCount(const struct radv_image *image,
1235 const VkImageSubresourceRange *range)
1236 {
1237 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1238 image->info.levels - range->baseMipLevel : range->levelCount;
1239 }
1240
1241 struct radeon_bo_metadata;
1242 void
1243 radv_init_metadata(struct radv_device *device,
1244 struct radv_image *image,
1245 struct radeon_bo_metadata *metadata);
1246
1247 struct radv_image_view {
1248 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1249 struct radeon_winsys_bo *bo;
1250
1251 VkImageViewType type;
1252 VkImageAspectFlags aspect_mask;
1253 VkFormat vk_format;
1254 uint32_t base_layer;
1255 uint32_t layer_count;
1256 uint32_t base_mip;
1257 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1258
1259 uint32_t descriptor[8];
1260 uint32_t fmask_descriptor[8];
1261 };
1262
1263 struct radv_image_create_info {
1264 const VkImageCreateInfo *vk_info;
1265 uint32_t stride;
1266 bool scanout;
1267 };
1268
1269 VkResult radv_image_create(VkDevice _device,
1270 const struct radv_image_create_info *info,
1271 const VkAllocationCallbacks* alloc,
1272 VkImage *pImage);
1273
1274 void radv_image_view_init(struct radv_image_view *view,
1275 struct radv_device *device,
1276 const VkImageViewCreateInfo* pCreateInfo,
1277 struct radv_cmd_buffer *cmd_buffer,
1278 VkImageUsageFlags usage_mask);
1279
1280 struct radv_buffer_view {
1281 struct radeon_winsys_bo *bo;
1282 VkFormat vk_format;
1283 uint64_t range; /**< VkBufferViewCreateInfo::range */
1284 uint32_t state[4];
1285 };
1286 void radv_buffer_view_init(struct radv_buffer_view *view,
1287 struct radv_device *device,
1288 const VkBufferViewCreateInfo* pCreateInfo,
1289 struct radv_cmd_buffer *cmd_buffer);
1290
1291 static inline struct VkExtent3D
1292 radv_sanitize_image_extent(const VkImageType imageType,
1293 const struct VkExtent3D imageExtent)
1294 {
1295 switch (imageType) {
1296 case VK_IMAGE_TYPE_1D:
1297 return (VkExtent3D) { imageExtent.width, 1, 1 };
1298 case VK_IMAGE_TYPE_2D:
1299 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1300 case VK_IMAGE_TYPE_3D:
1301 return imageExtent;
1302 default:
1303 unreachable("invalid image type");
1304 }
1305 }
1306
1307 static inline struct VkOffset3D
1308 radv_sanitize_image_offset(const VkImageType imageType,
1309 const struct VkOffset3D imageOffset)
1310 {
1311 switch (imageType) {
1312 case VK_IMAGE_TYPE_1D:
1313 return (VkOffset3D) { imageOffset.x, 0, 0 };
1314 case VK_IMAGE_TYPE_2D:
1315 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1316 case VK_IMAGE_TYPE_3D:
1317 return imageOffset;
1318 default:
1319 unreachable("invalid image type");
1320 }
1321 }
1322
1323 static inline bool
1324 radv_image_extent_compare(const struct radv_image *image,
1325 const VkExtent3D *extent)
1326 {
1327 if (extent->width != image->info.width ||
1328 extent->height != image->info.height ||
1329 extent->depth != image->info.depth)
1330 return false;
1331 return true;
1332 }
1333
1334 struct radv_sampler {
1335 uint32_t state[4];
1336 };
1337
1338 struct radv_color_buffer_info {
1339 uint64_t cb_color_base;
1340 uint64_t cb_color_cmask;
1341 uint64_t cb_color_fmask;
1342 uint64_t cb_dcc_base;
1343 uint32_t cb_color_pitch;
1344 uint32_t cb_color_slice;
1345 uint32_t cb_color_view;
1346 uint32_t cb_color_info;
1347 uint32_t cb_color_attrib;
1348 uint32_t cb_dcc_control;
1349 uint32_t cb_color_cmask_slice;
1350 uint32_t cb_color_fmask_slice;
1351 uint32_t cb_clear_value0;
1352 uint32_t cb_clear_value1;
1353 uint32_t micro_tile_mode;
1354 };
1355
1356 struct radv_ds_buffer_info {
1357 uint64_t db_z_read_base;
1358 uint64_t db_stencil_read_base;
1359 uint64_t db_z_write_base;
1360 uint64_t db_stencil_write_base;
1361 uint64_t db_htile_data_base;
1362 uint32_t db_depth_info;
1363 uint32_t db_z_info;
1364 uint32_t db_stencil_info;
1365 uint32_t db_depth_view;
1366 uint32_t db_depth_size;
1367 uint32_t db_depth_slice;
1368 uint32_t db_htile_surface;
1369 uint32_t pa_su_poly_offset_db_fmt_cntl;
1370 float offset_scale;
1371 };
1372
1373 struct radv_attachment_info {
1374 union {
1375 struct radv_color_buffer_info cb;
1376 struct radv_ds_buffer_info ds;
1377 };
1378 struct radv_image_view *attachment;
1379 };
1380
1381 struct radv_framebuffer {
1382 uint32_t width;
1383 uint32_t height;
1384 uint32_t layers;
1385
1386 uint32_t attachment_count;
1387 struct radv_attachment_info attachments[0];
1388 };
1389
1390 struct radv_subpass_barrier {
1391 VkPipelineStageFlags src_stage_mask;
1392 VkAccessFlags src_access_mask;
1393 VkAccessFlags dst_access_mask;
1394 };
1395
1396 struct radv_subpass {
1397 uint32_t input_count;
1398 uint32_t color_count;
1399 VkAttachmentReference * input_attachments;
1400 VkAttachmentReference * color_attachments;
1401 VkAttachmentReference * resolve_attachments;
1402 VkAttachmentReference depth_stencil_attachment;
1403
1404 /** Subpass has at least one resolve attachment */
1405 bool has_resolve;
1406
1407 struct radv_subpass_barrier start_barrier;
1408 };
1409
1410 struct radv_render_pass_attachment {
1411 VkFormat format;
1412 uint32_t samples;
1413 VkAttachmentLoadOp load_op;
1414 VkAttachmentLoadOp stencil_load_op;
1415 VkImageLayout initial_layout;
1416 VkImageLayout final_layout;
1417 };
1418
1419 struct radv_render_pass {
1420 uint32_t attachment_count;
1421 uint32_t subpass_count;
1422 VkAttachmentReference * subpass_attachments;
1423 struct radv_render_pass_attachment * attachments;
1424 struct radv_subpass_barrier end_barrier;
1425 struct radv_subpass subpasses[0];
1426 };
1427
1428 VkResult radv_device_init_meta(struct radv_device *device);
1429 void radv_device_finish_meta(struct radv_device *device);
1430
1431 struct radv_query_pool {
1432 struct radeon_winsys_bo *bo;
1433 uint32_t stride;
1434 uint32_t availability_offset;
1435 char *ptr;
1436 VkQueryType type;
1437 uint32_t pipeline_stats_mask;
1438 };
1439
1440 void
1441 radv_update_descriptor_sets(struct radv_device *device,
1442 struct radv_cmd_buffer *cmd_buffer,
1443 VkDescriptorSet overrideSet,
1444 uint32_t descriptorWriteCount,
1445 const VkWriteDescriptorSet *pDescriptorWrites,
1446 uint32_t descriptorCopyCount,
1447 const VkCopyDescriptorSet *pDescriptorCopies);
1448
1449 void
1450 radv_update_descriptor_set_with_template(struct radv_device *device,
1451 struct radv_cmd_buffer *cmd_buffer,
1452 struct radv_descriptor_set *set,
1453 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1454 const void *pData);
1455
1456 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1457 VkPipelineBindPoint pipelineBindPoint,
1458 VkPipelineLayout _layout,
1459 uint32_t set,
1460 uint32_t descriptorWriteCount,
1461 const VkWriteDescriptorSet *pDescriptorWrites);
1462
1463 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1464 struct radv_image *image, uint32_t value);
1465 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1466 struct radv_image *image, uint32_t value);
1467
1468 struct radv_fence {
1469 struct radeon_winsys_fence *fence;
1470 bool submitted;
1471 bool signalled;
1472 };
1473
1474 struct radeon_winsys_sem;
1475
1476 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1477 \
1478 static inline struct __radv_type * \
1479 __radv_type ## _from_handle(__VkType _handle) \
1480 { \
1481 return (struct __radv_type *) _handle; \
1482 } \
1483 \
1484 static inline __VkType \
1485 __radv_type ## _to_handle(struct __radv_type *_obj) \
1486 { \
1487 return (__VkType) _obj; \
1488 }
1489
1490 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1491 \
1492 static inline struct __radv_type * \
1493 __radv_type ## _from_handle(__VkType _handle) \
1494 { \
1495 return (struct __radv_type *)(uintptr_t) _handle; \
1496 } \
1497 \
1498 static inline __VkType \
1499 __radv_type ## _to_handle(struct __radv_type *_obj) \
1500 { \
1501 return (__VkType)(uintptr_t) _obj; \
1502 }
1503
1504 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1505 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1506
1507 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1508 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1509 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1510 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1511 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1512
1513 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1514 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1515 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1516 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1517 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1518 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1519 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1520 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1521 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1522 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1523 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1524 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1525 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1526 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1527 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1528 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1529 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1530 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1531 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1532 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1533 RADV_DEFINE_NONDISP_HANDLE_CASTS(radeon_winsys_sem, VkSemaphore)
1534
1535 #endif /* RADV_PRIVATE_H */