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radv: Use different allocator for descriptor set vram.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/vk_alloc.h"
51 #include "main/macros.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "radv_descriptor_set.h"
57
58 #include <llvm-c/TargetMachine.h>
59
60 /* Pre-declarations needed for WSI entrypoints */
61 struct wl_surface;
62 struct wl_display;
63 typedef struct xcb_connection_t xcb_connection_t;
64 typedef uint32_t xcb_visualid_t;
65 typedef uint32_t xcb_window_t;
66
67 #include <vulkan/vulkan.h>
68 #include <vulkan/vulkan_intel.h>
69 #include <vulkan/vk_icd.h>
70
71 #include "radv_entrypoints.h"
72
73 #include "wsi_common.h"
74
75 #define MAX_VBS 32
76 #define MAX_VERTEX_ATTRIBS 32
77 #define MAX_RTS 8
78 #define MAX_VIEWPORTS 16
79 #define MAX_SCISSORS 16
80 #define MAX_PUSH_CONSTANTS_SIZE 128
81 #define MAX_DYNAMIC_BUFFERS 16
82 #define MAX_SAMPLES_LOG2 4
83 #define NUM_META_FS_KEYS 11
84 #define RADV_MAX_DRM_DEVICES 8
85
86 #define NUM_DEPTH_CLEAR_PIPELINES 3
87
88 enum radv_mem_heap {
89 RADV_MEM_HEAP_VRAM,
90 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
91 RADV_MEM_HEAP_GTT,
92 RADV_MEM_HEAP_COUNT
93 };
94
95 enum radv_mem_type {
96 RADV_MEM_TYPE_VRAM,
97 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
98 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
99 RADV_MEM_TYPE_GTT_CACHED,
100 RADV_MEM_TYPE_COUNT
101 };
102
103
104 enum {
105 RADV_DEBUG_NO_FAST_CLEARS = 0x1,
106 RADV_DEBUG_NO_DCC = 0x2,
107 RADV_DEBUG_DUMP_SHADERS = 0x4,
108 RADV_DEBUG_NO_CACHE = 0x8,
109 RADV_DEBUG_DUMP_SHADER_STATS = 0x10,
110 RADV_DEBUG_NO_HIZ = 0x20,
111 RADV_DEBUG_NO_COMPUTE_QUEUE = 0x40,
112 RADV_DEBUG_UNSAFE_MATH = 0x80,
113 };
114
115 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
116
117 static inline uint32_t
118 align_u32(uint32_t v, uint32_t a)
119 {
120 assert(a != 0 && a == (a & -a));
121 return (v + a - 1) & ~(a - 1);
122 }
123
124 static inline uint32_t
125 align_u32_npot(uint32_t v, uint32_t a)
126 {
127 return (v + a - 1) / a * a;
128 }
129
130 static inline uint64_t
131 align_u64(uint64_t v, uint64_t a)
132 {
133 assert(a != 0 && a == (a & -a));
134 return (v + a - 1) & ~(a - 1);
135 }
136
137 static inline int32_t
138 align_i32(int32_t v, int32_t a)
139 {
140 assert(a != 0 && a == (a & -a));
141 return (v + a - 1) & ~(a - 1);
142 }
143
144 /** Alignment must be a power of 2. */
145 static inline bool
146 radv_is_aligned(uintmax_t n, uintmax_t a)
147 {
148 assert(a == (a & -a));
149 return (n & (a - 1)) == 0;
150 }
151
152 static inline uint32_t
153 round_up_u32(uint32_t v, uint32_t a)
154 {
155 return (v + a - 1) / a;
156 }
157
158 static inline uint64_t
159 round_up_u64(uint64_t v, uint64_t a)
160 {
161 return (v + a - 1) / a;
162 }
163
164 static inline uint32_t
165 radv_minify(uint32_t n, uint32_t levels)
166 {
167 if (unlikely(n == 0))
168 return 0;
169 else
170 return MAX2(n >> levels, 1);
171 }
172 static inline float
173 radv_clamp_f(float f, float min, float max)
174 {
175 assert(min < max);
176
177 if (f > max)
178 return max;
179 else if (f < min)
180 return min;
181 else
182 return f;
183 }
184
185 static inline bool
186 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
187 {
188 if (*inout_mask & clear_mask) {
189 *inout_mask &= ~clear_mask;
190 return true;
191 } else {
192 return false;
193 }
194 }
195
196 #define for_each_bit(b, dword) \
197 for (uint32_t __dword = (dword); \
198 (b) = __builtin_ffs(__dword) - 1, __dword; \
199 __dword &= ~(1 << (b)))
200
201 #define typed_memcpy(dest, src, count) ({ \
202 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
203 memcpy((dest), (src), (count) * sizeof(*(src))); \
204 })
205
206 #define zero(x) (memset(&(x), 0, sizeof(x)))
207
208 /* Whenever we generate an error, pass it through this function. Useful for
209 * debugging, where we can break on it. Only call at error site, not when
210 * propagating errors. Might be useful to plug in a stack trace here.
211 */
212
213 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
214
215 #ifdef DEBUG
216 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
217 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
218 #else
219 #define vk_error(error) error
220 #define vk_errorf(error, format, ...) error
221 #endif
222
223 void __radv_finishme(const char *file, int line, const char *format, ...)
224 radv_printflike(3, 4);
225 void radv_loge(const char *format, ...) radv_printflike(1, 2);
226 void radv_loge_v(const char *format, va_list va);
227
228 /**
229 * Print a FINISHME message, including its source location.
230 */
231 #define radv_finishme(format, ...) \
232 do { \
233 static bool reported = false; \
234 if (!reported) { \
235 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
236 reported = true; \
237 } \
238 } while (0)
239
240 /* A non-fatal assert. Useful for debugging. */
241 #ifdef DEBUG
242 #define radv_assert(x) ({ \
243 if (unlikely(!(x))) \
244 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
245 })
246 #else
247 #define radv_assert(x)
248 #endif
249
250 #define stub_return(v) \
251 do { \
252 radv_finishme("stub %s", __func__); \
253 return (v); \
254 } while (0)
255
256 #define stub() \
257 do { \
258 radv_finishme("stub %s", __func__); \
259 return; \
260 } while (0)
261
262 void *radv_resolve_entrypoint(uint32_t index);
263 void *radv_lookup_entrypoint(const char *name);
264
265 extern struct radv_dispatch_table dtable;
266
267 struct radv_extensions {
268 VkExtensionProperties *ext_array;
269 uint32_t num_ext;
270 };
271
272 struct radv_physical_device {
273 VK_LOADER_DATA _loader_data;
274
275 struct radv_instance * instance;
276
277 struct radeon_winsys *ws;
278 struct radeon_info rad_info;
279 char path[20];
280 const char * name;
281 uint8_t uuid[VK_UUID_SIZE];
282
283 struct wsi_device wsi_device;
284 struct radv_extensions extensions;
285 };
286
287 struct radv_instance {
288 VK_LOADER_DATA _loader_data;
289
290 VkAllocationCallbacks alloc;
291
292 uint32_t apiVersion;
293 int physicalDeviceCount;
294 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
295
296 uint64_t debug_flags;
297 };
298
299 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
300 void radv_finish_wsi(struct radv_physical_device *physical_device);
301
302 struct cache_entry;
303
304 struct radv_pipeline_cache {
305 struct radv_device * device;
306 pthread_mutex_t mutex;
307
308 uint32_t total_size;
309 uint32_t table_size;
310 uint32_t kernel_count;
311 struct cache_entry ** hash_table;
312 bool modified;
313
314 VkAllocationCallbacks alloc;
315 };
316
317 void
318 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
319 struct radv_device *device);
320 void
321 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
322 void
323 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
324 const void *data, size_t size);
325
326 struct radv_shader_variant *
327 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
328 struct radv_pipeline_cache *cache,
329 const unsigned char *sha1);
330
331 struct radv_shader_variant *
332 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
333 const unsigned char *sha1,
334 struct radv_shader_variant *variant,
335 const void *code, unsigned code_size);
336
337 void radv_shader_variant_destroy(struct radv_device *device,
338 struct radv_shader_variant *variant);
339
340 struct radv_meta_state {
341 VkAllocationCallbacks alloc;
342
343 struct radv_pipeline_cache cache;
344
345 /**
346 * Use array element `i` for images with `2^i` samples.
347 */
348 struct {
349 VkRenderPass render_pass[NUM_META_FS_KEYS];
350 struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
351
352 VkRenderPass depthstencil_rp;
353 struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
354 struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
355 struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
356 } clear[1 + MAX_SAMPLES_LOG2];
357
358 struct {
359 VkRenderPass render_pass[NUM_META_FS_KEYS];
360
361 /** Pipeline that blits from a 1D image. */
362 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
363
364 /** Pipeline that blits from a 2D image. */
365 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
366
367 /** Pipeline that blits from a 3D image. */
368 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
369
370 VkRenderPass depth_only_rp;
371 VkPipeline depth_only_1d_pipeline;
372 VkPipeline depth_only_2d_pipeline;
373 VkPipeline depth_only_3d_pipeline;
374
375 VkRenderPass stencil_only_rp;
376 VkPipeline stencil_only_1d_pipeline;
377 VkPipeline stencil_only_2d_pipeline;
378 VkPipeline stencil_only_3d_pipeline;
379 VkPipelineLayout pipeline_layout;
380 VkDescriptorSetLayout ds_layout;
381 } blit;
382
383 struct {
384 VkRenderPass render_passes[NUM_META_FS_KEYS];
385
386 VkPipelineLayout p_layouts[2];
387 VkDescriptorSetLayout ds_layouts[2];
388 VkPipeline pipelines[2][NUM_META_FS_KEYS];
389
390 VkRenderPass depth_only_rp;
391 VkPipeline depth_only_pipeline[2];
392
393 VkRenderPass stencil_only_rp;
394 VkPipeline stencil_only_pipeline[2];
395 } blit2d;
396
397 struct {
398 VkPipelineLayout img_p_layout;
399 VkDescriptorSetLayout img_ds_layout;
400 VkPipeline pipeline;
401 } itob;
402 struct {
403 VkRenderPass render_pass;
404 VkPipelineLayout img_p_layout;
405 VkDescriptorSetLayout img_ds_layout;
406 VkPipeline pipeline;
407 } btoi;
408 struct {
409 VkPipelineLayout img_p_layout;
410 VkDescriptorSetLayout img_ds_layout;
411 VkPipeline pipeline;
412 } itoi;
413 struct {
414 VkPipelineLayout img_p_layout;
415 VkDescriptorSetLayout img_ds_layout;
416 VkPipeline pipeline;
417 } cleari;
418
419 struct {
420 VkPipeline pipeline;
421 VkRenderPass pass;
422 } resolve;
423
424 struct {
425 VkDescriptorSetLayout ds_layout;
426 VkPipelineLayout p_layout;
427 struct {
428 VkPipeline pipeline;
429 VkPipeline i_pipeline;
430 } rc[MAX_SAMPLES_LOG2];
431 } resolve_compute;
432
433 struct {
434 VkPipeline decompress_pipeline;
435 VkPipeline resummarize_pipeline;
436 VkRenderPass pass;
437 } depth_decomp;
438
439 struct {
440 VkPipeline cmask_eliminate_pipeline;
441 VkPipeline fmask_decompress_pipeline;
442 VkRenderPass pass;
443 } fast_clear_flush;
444
445 struct {
446 VkPipelineLayout fill_p_layout;
447 VkPipelineLayout copy_p_layout;
448 VkDescriptorSetLayout fill_ds_layout;
449 VkDescriptorSetLayout copy_ds_layout;
450 VkPipeline fill_pipeline;
451 VkPipeline copy_pipeline;
452 } buffer;
453 };
454
455 /* queue types */
456 #define RADV_QUEUE_GENERAL 0
457 #define RADV_QUEUE_COMPUTE 1
458 #define RADV_QUEUE_TRANSFER 2
459
460 #define RADV_MAX_QUEUE_FAMILIES 3
461
462 enum ring_type radv_queue_family_to_ring(int f);
463
464 struct radv_queue {
465 VK_LOADER_DATA _loader_data;
466 struct radv_device * device;
467 struct radeon_winsys_ctx *hw_ctx;
468 int queue_family_index;
469 int queue_idx;
470
471 uint32_t scratch_size;
472 uint32_t compute_scratch_size;
473 uint32_t esgs_ring_size;
474 uint32_t gsvs_ring_size;
475
476 struct radeon_winsys_bo *scratch_bo;
477 struct radeon_winsys_bo *descriptor_bo;
478 struct radeon_winsys_bo *compute_scratch_bo;
479 struct radeon_winsys_bo *esgs_ring_bo;
480 struct radeon_winsys_bo *gsvs_ring_bo;
481 struct radeon_winsys_cs *preamble_cs;
482 };
483
484 struct radv_device {
485 VK_LOADER_DATA _loader_data;
486
487 VkAllocationCallbacks alloc;
488
489 struct radv_instance * instance;
490 struct radeon_winsys *ws;
491
492 struct radv_meta_state meta_state;
493
494 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
495 int queue_count[RADV_MAX_QUEUE_FAMILIES];
496 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
497
498 uint64_t debug_flags;
499
500 bool llvm_supports_spill;
501 uint32_t scratch_waves;
502
503 uint32_t gs_table_depth;
504
505 /* MSAA sample locations.
506 * The first index is the sample index.
507 * The second index is the coordinate: X, Y. */
508 float sample_locations_1x[1][2];
509 float sample_locations_2x[2][2];
510 float sample_locations_4x[4][2];
511 float sample_locations_8x[8][2];
512 float sample_locations_16x[16][2];
513
514 /* CIK and later */
515 uint32_t gfx_init_size_dw;
516 struct radeon_winsys_bo *gfx_init;
517
518 struct radeon_winsys_bo *trace_bo;
519 uint32_t *trace_id_ptr;
520
521 struct radv_physical_device *physical_device;
522 };
523
524 struct radv_device_memory {
525 struct radeon_winsys_bo *bo;
526 uint32_t type_index;
527 VkDeviceSize map_size;
528 void * map;
529 };
530
531
532 struct radv_descriptor_range {
533 uint64_t va;
534 uint32_t size;
535 };
536
537 struct radv_descriptor_set {
538 const struct radv_descriptor_set_layout *layout;
539 uint32_t size;
540
541 struct radv_buffer_view *buffer_views;
542 struct radeon_winsys_bo *bo;
543 uint64_t va;
544 uint32_t *mapped_ptr;
545 struct radv_descriptor_range *dynamic_descriptors;
546
547 struct list_head vram_list;
548
549 struct radeon_winsys_bo *descriptors[0];
550 };
551
552 struct radv_descriptor_pool {
553 struct radeon_winsys_bo *bo;
554 uint8_t *mapped_ptr;
555 uint64_t current_offset;
556 uint64_t size;
557
558 struct list_head vram_list;
559 };
560
561 struct radv_buffer {
562 struct radv_device * device;
563 VkDeviceSize size;
564
565 VkBufferUsageFlags usage;
566
567 /* Set when bound */
568 struct radeon_winsys_bo * bo;
569 VkDeviceSize offset;
570 };
571
572
573 enum radv_cmd_dirty_bits {
574 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
575 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
576 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
577 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
578 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
579 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
580 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
581 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
582 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
583 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
584 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
585 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
586 RADV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
587 };
588 typedef uint32_t radv_cmd_dirty_mask_t;
589
590 enum radv_cmd_flush_bits {
591 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
592 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
593 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
594 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
595 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
596 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
597 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
598 /* Framebuffer caches */
599 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 4,
600 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 5,
601 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 6,
602 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 7,
603 /* Engine synchronization. */
604 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 8,
605 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 9,
606 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 10,
607 RADV_CMD_FLAG_VGT_FLUSH = 1 << 11,
608
609 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
610 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
611 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
612 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
613 };
614
615 struct radv_vertex_binding {
616 struct radv_buffer * buffer;
617 VkDeviceSize offset;
618 };
619
620 struct radv_dynamic_state {
621 struct {
622 uint32_t count;
623 VkViewport viewports[MAX_VIEWPORTS];
624 } viewport;
625
626 struct {
627 uint32_t count;
628 VkRect2D scissors[MAX_SCISSORS];
629 } scissor;
630
631 float line_width;
632
633 struct {
634 float bias;
635 float clamp;
636 float slope;
637 } depth_bias;
638
639 float blend_constants[4];
640
641 struct {
642 float min;
643 float max;
644 } depth_bounds;
645
646 struct {
647 uint32_t front;
648 uint32_t back;
649 } stencil_compare_mask;
650
651 struct {
652 uint32_t front;
653 uint32_t back;
654 } stencil_write_mask;
655
656 struct {
657 uint32_t front;
658 uint32_t back;
659 } stencil_reference;
660 };
661
662 extern const struct radv_dynamic_state default_dynamic_state;
663
664 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
665 const struct radv_dynamic_state *src,
666 uint32_t copy_mask);
667 /**
668 * Attachment state when recording a renderpass instance.
669 *
670 * The clear value is valid only if there exists a pending clear.
671 */
672 struct radv_attachment_state {
673 VkImageAspectFlags pending_clear_aspects;
674 VkClearValue clear_value;
675 VkImageLayout current_layout;
676 };
677
678 struct radv_cmd_state {
679 uint32_t vb_dirty;
680 radv_cmd_dirty_mask_t dirty;
681 bool vertex_descriptors_dirty;
682
683 struct radv_pipeline * pipeline;
684 struct radv_pipeline * emitted_pipeline;
685 struct radv_pipeline * compute_pipeline;
686 struct radv_pipeline * emitted_compute_pipeline;
687 struct radv_framebuffer * framebuffer;
688 struct radv_render_pass * pass;
689 const struct radv_subpass * subpass;
690 struct radv_dynamic_state dynamic;
691 struct radv_vertex_binding vertex_bindings[MAX_VBS];
692 struct radv_descriptor_set * descriptors[MAX_SETS];
693 struct radv_attachment_state * attachments;
694 VkRect2D render_area;
695 struct radv_buffer * index_buffer;
696 uint32_t index_type;
697 uint32_t index_offset;
698 uint32_t last_primitive_reset_index;
699 enum radv_cmd_flush_bits flush_bits;
700 unsigned active_occlusion_queries;
701 float offset_scale;
702 uint32_t descriptors_dirty;
703 uint32_t trace_id;
704 uint32_t last_ia_multi_vgt_param;
705 };
706
707 struct radv_cmd_pool {
708 VkAllocationCallbacks alloc;
709 struct list_head cmd_buffers;
710 uint32_t queue_family_index;
711 };
712
713 struct radv_cmd_buffer_upload {
714 uint8_t *map;
715 unsigned offset;
716 uint64_t size;
717 struct radeon_winsys_bo *upload_bo;
718 struct list_head list;
719 };
720
721 struct radv_cmd_buffer {
722 VK_LOADER_DATA _loader_data;
723
724 struct radv_device * device;
725
726 struct radv_cmd_pool * pool;
727 struct list_head pool_link;
728
729 VkCommandBufferUsageFlags usage_flags;
730 VkCommandBufferLevel level;
731 struct radeon_winsys_cs *cs;
732 struct radv_cmd_state state;
733 uint32_t queue_family_index;
734
735 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
736 uint32_t dynamic_buffers[16 * MAX_DYNAMIC_BUFFERS];
737 VkShaderStageFlags push_constant_stages;
738
739 struct radv_cmd_buffer_upload upload;
740
741 bool record_fail;
742
743 uint32_t scratch_size_needed;
744 uint32_t compute_scratch_size_needed;
745 uint32_t esgs_ring_size_needed;
746 uint32_t gsvs_ring_size_needed;
747
748 int ring_offsets_idx; /* just used for verification */
749
750 bool no_draws;
751 };
752
753 struct radv_image;
754
755 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
756
757 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
758 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
759
760 void cik_create_gfx_config(struct radv_device *device);
761
762 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
763 int count, const VkViewport *viewports);
764 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
765 int count, const VkRect2D *scissors);
766 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
767 bool instanced_or_indirect_draw, uint32_t draw_vertex_count);
768 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
769 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
770 uint64_t src_va, uint64_t dest_va,
771 uint64_t size);
772 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
773 uint64_t size, unsigned value);
774 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
775 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
776 struct radv_descriptor_set *set,
777 unsigned idx);
778 bool
779 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
780 unsigned size,
781 unsigned alignment,
782 unsigned *out_offset,
783 void **ptr);
784 void
785 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
786 const struct radv_subpass *subpass,
787 bool transitions);
788 bool
789 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
790 unsigned size, unsigned alignmnet,
791 const void *data, unsigned *out_offset);
792 void
793 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
794 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
795 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
796 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
797 unsigned radv_cayman_get_maxdist(int log_samples);
798 void radv_device_init_msaa(struct radv_device *device);
799 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
800 struct radv_image *image,
801 VkClearDepthStencilValue ds_clear_value,
802 VkImageAspectFlags aspects);
803 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
804 struct radv_image *image,
805 int idx,
806 uint32_t color_values[2]);
807 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
808 struct radeon_winsys_bo *bo,
809 uint64_t offset, uint64_t size, uint32_t value);
810 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
811
812 /*
813 * Takes x,y,z as exact numbers of invocations, instead of blocks.
814 *
815 * Limitations: Can't call normal dispatch functions without binding or rebinding
816 * the compute pipeline.
817 */
818 void radv_unaligned_dispatch(
819 struct radv_cmd_buffer *cmd_buffer,
820 uint32_t x,
821 uint32_t y,
822 uint32_t z);
823
824 struct radv_event {
825 struct radeon_winsys_bo *bo;
826 uint64_t *map;
827 };
828
829 struct nir_shader;
830
831 struct radv_shader_module {
832 struct nir_shader * nir;
833 unsigned char sha1[20];
834 uint32_t size;
835 char data[0];
836 };
837
838 union ac_shader_variant_key;
839
840 void
841 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
842 const char *entrypoint,
843 const VkSpecializationInfo *spec_info,
844 const struct radv_pipeline_layout *layout,
845 const union ac_shader_variant_key *key,
846 uint32_t is_geom_copy_shader);
847
848 static inline gl_shader_stage
849 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
850 {
851 assert(__builtin_popcount(vk_stage) == 1);
852 return ffs(vk_stage) - 1;
853 }
854
855 static inline VkShaderStageFlagBits
856 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
857 {
858 return (1 << mesa_stage);
859 }
860
861 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
862
863 #define radv_foreach_stage(stage, stage_bits) \
864 for (gl_shader_stage stage, \
865 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
866 stage = __builtin_ffs(__tmp) - 1, __tmp; \
867 __tmp &= ~(1 << (stage)))
868
869 struct radv_shader_variant {
870 uint32_t ref_count;
871
872 struct radeon_winsys_bo *bo;
873 struct ac_shader_config config;
874 struct ac_shader_variant_info info;
875 unsigned rsrc1;
876 unsigned rsrc2;
877 uint32_t code_size;
878 };
879
880 struct radv_depth_stencil_state {
881 uint32_t db_depth_control;
882 uint32_t db_stencil_control;
883 uint32_t db_render_control;
884 uint32_t db_render_override2;
885 };
886
887 struct radv_blend_state {
888 uint32_t cb_color_control;
889 uint32_t cb_target_mask;
890 uint32_t sx_mrt0_blend_opt[8];
891 uint32_t cb_blend_control[8];
892
893 uint32_t spi_shader_col_format;
894 uint32_t cb_shader_mask;
895 uint32_t db_alpha_to_mask;
896 };
897
898 unsigned radv_format_meta_fs_key(VkFormat format);
899
900 struct radv_raster_state {
901 uint32_t pa_cl_clip_cntl;
902 uint32_t pa_cl_vs_out_cntl;
903 uint32_t spi_interp_control;
904 uint32_t pa_su_point_size;
905 uint32_t pa_su_point_minmax;
906 uint32_t pa_su_line_cntl;
907 uint32_t pa_su_vtx_cntl;
908 uint32_t pa_su_sc_mode_cntl;
909 };
910
911 struct radv_multisample_state {
912 uint32_t db_eqaa;
913 uint32_t pa_sc_line_cntl;
914 uint32_t pa_sc_mode_cntl_0;
915 uint32_t pa_sc_mode_cntl_1;
916 uint32_t pa_sc_aa_config;
917 uint32_t pa_sc_aa_mask[2];
918 unsigned num_samples;
919 };
920
921 struct radv_prim_vertex_count {
922 uint8_t min;
923 uint8_t incr;
924 };
925
926 struct radv_pipeline {
927 struct radv_device * device;
928 uint32_t dynamic_state_mask;
929 struct radv_dynamic_state dynamic_state;
930
931 struct radv_pipeline_layout * layout;
932
933 bool needs_data_cache;
934
935 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
936 struct radv_shader_variant *gs_copy_shader;
937 VkShaderStageFlags active_stages;
938
939 uint32_t va_rsrc_word3[MAX_VERTEX_ATTRIBS];
940 uint32_t va_format_size[MAX_VERTEX_ATTRIBS];
941 uint32_t va_binding[MAX_VERTEX_ATTRIBS];
942 uint32_t va_offset[MAX_VERTEX_ATTRIBS];
943 uint32_t num_vertex_attribs;
944 uint32_t binding_stride[MAX_VBS];
945
946 union {
947 struct {
948 struct radv_blend_state blend;
949 struct radv_depth_stencil_state ds;
950 struct radv_raster_state raster;
951 struct radv_multisample_state ms;
952 unsigned prim;
953 unsigned gs_out;
954 bool prim_restart_enable;
955 unsigned esgs_ring_size;
956 unsigned gsvs_ring_size;
957 struct radv_prim_vertex_count prim_vertex_count;
958 } graphics;
959 };
960
961 unsigned max_waves;
962 unsigned scratch_bytes_per_wave;
963 };
964
965 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
966 {
967 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
968 }
969
970 struct radv_graphics_pipeline_create_info {
971 bool use_rectlist;
972 bool db_depth_clear;
973 bool db_stencil_clear;
974 bool db_depth_disable_expclear;
975 bool db_stencil_disable_expclear;
976 bool db_flush_depth_inplace;
977 bool db_flush_stencil_inplace;
978 bool db_resummarize;
979 uint32_t custom_blend_mode;
980 };
981
982 VkResult
983 radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
984 struct radv_pipeline_cache *cache,
985 const VkGraphicsPipelineCreateInfo *pCreateInfo,
986 const struct radv_graphics_pipeline_create_info *extra,
987 const VkAllocationCallbacks *alloc);
988
989 VkResult
990 radv_graphics_pipeline_create(VkDevice device,
991 VkPipelineCache cache,
992 const VkGraphicsPipelineCreateInfo *pCreateInfo,
993 const struct radv_graphics_pipeline_create_info *extra,
994 const VkAllocationCallbacks *alloc,
995 VkPipeline *pPipeline);
996
997 struct vk_format_description;
998 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
999 int first_non_void);
1000 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1001 int first_non_void);
1002 uint32_t radv_translate_colorformat(VkFormat format);
1003 uint32_t radv_translate_color_numformat(VkFormat format,
1004 const struct vk_format_description *desc,
1005 int first_non_void);
1006 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1007 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1008 uint32_t radv_translate_dbformat(VkFormat format);
1009 uint32_t radv_translate_tex_dataformat(VkFormat format,
1010 const struct vk_format_description *desc,
1011 int first_non_void);
1012 uint32_t radv_translate_tex_numformat(VkFormat format,
1013 const struct vk_format_description *desc,
1014 int first_non_void);
1015 bool radv_format_pack_clear_color(VkFormat format,
1016 uint32_t clear_vals[2],
1017 VkClearColorValue *value);
1018 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1019
1020 struct radv_fmask_info {
1021 uint64_t offset;
1022 uint64_t size;
1023 unsigned alignment;
1024 unsigned pitch_in_pixels;
1025 unsigned bank_height;
1026 unsigned slice_tile_max;
1027 unsigned tile_mode_index;
1028 };
1029
1030 struct radv_cmask_info {
1031 uint64_t offset;
1032 uint64_t size;
1033 unsigned alignment;
1034 unsigned slice_tile_max;
1035 unsigned base_address_reg;
1036 };
1037
1038 struct r600_htile_info {
1039 uint64_t offset;
1040 uint64_t size;
1041 unsigned pitch;
1042 unsigned height;
1043 unsigned xalign;
1044 unsigned yalign;
1045 };
1046
1047 struct radv_image {
1048 VkImageType type;
1049 /* The original VkFormat provided by the client. This may not match any
1050 * of the actual surface formats.
1051 */
1052 VkFormat vk_format;
1053 VkImageAspectFlags aspects;
1054 VkExtent3D extent;
1055 uint32_t levels;
1056 uint32_t array_size;
1057 uint32_t samples; /**< VkImageCreateInfo::samples */
1058 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1059 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1060
1061 VkDeviceSize size;
1062 uint32_t alignment;
1063
1064 bool exclusive;
1065 unsigned queue_family_mask;
1066
1067 /* Set when bound */
1068 struct radeon_winsys_bo *bo;
1069 VkDeviceSize offset;
1070 uint32_t dcc_offset;
1071 struct radeon_surf surface;
1072
1073 struct radv_fmask_info fmask;
1074 struct radv_cmask_info cmask;
1075 uint32_t clear_value_offset;
1076
1077 /* Depth buffer compression and fast clear. */
1078 struct r600_htile_info htile;
1079 };
1080
1081 bool radv_layout_has_htile(const struct radv_image *image,
1082 VkImageLayout layout);
1083 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1084 VkImageLayout layout);
1085 bool radv_layout_can_expclear(const struct radv_image *image,
1086 VkImageLayout layout);
1087 bool radv_layout_can_fast_clear(const struct radv_image *image,
1088 VkImageLayout layout,
1089 unsigned queue_mask);
1090
1091
1092 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1093
1094 static inline uint32_t
1095 radv_get_layerCount(const struct radv_image *image,
1096 const VkImageSubresourceRange *range)
1097 {
1098 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1099 image->array_size - range->baseArrayLayer : range->layerCount;
1100 }
1101
1102 static inline uint32_t
1103 radv_get_levelCount(const struct radv_image *image,
1104 const VkImageSubresourceRange *range)
1105 {
1106 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1107 image->levels - range->baseMipLevel : range->levelCount;
1108 }
1109
1110 struct radeon_bo_metadata;
1111 void
1112 radv_init_metadata(struct radv_device *device,
1113 struct radv_image *image,
1114 struct radeon_bo_metadata *metadata);
1115
1116 struct radv_image_view {
1117 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1118 struct radeon_winsys_bo *bo;
1119
1120 VkImageViewType type;
1121 VkImageAspectFlags aspect_mask;
1122 VkFormat vk_format;
1123 uint32_t base_layer;
1124 uint32_t layer_count;
1125 uint32_t base_mip;
1126 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1127
1128 uint32_t descriptor[8];
1129 uint32_t fmask_descriptor[8];
1130 };
1131
1132 struct radv_image_create_info {
1133 const VkImageCreateInfo *vk_info;
1134 uint32_t stride;
1135 bool scanout;
1136 };
1137
1138 VkResult radv_image_create(VkDevice _device,
1139 const struct radv_image_create_info *info,
1140 const VkAllocationCallbacks* alloc,
1141 VkImage *pImage);
1142
1143 void radv_image_view_init(struct radv_image_view *view,
1144 struct radv_device *device,
1145 const VkImageViewCreateInfo* pCreateInfo,
1146 struct radv_cmd_buffer *cmd_buffer,
1147 VkImageUsageFlags usage_mask);
1148 void radv_image_set_optimal_micro_tile_mode(struct radv_device *device,
1149 struct radv_image *image, uint32_t micro_tile_mode);
1150 struct radv_buffer_view {
1151 struct radeon_winsys_bo *bo;
1152 VkFormat vk_format;
1153 uint64_t range; /**< VkBufferViewCreateInfo::range */
1154 uint32_t state[4];
1155 };
1156 void radv_buffer_view_init(struct radv_buffer_view *view,
1157 struct radv_device *device,
1158 const VkBufferViewCreateInfo* pCreateInfo,
1159 struct radv_cmd_buffer *cmd_buffer);
1160
1161 static inline struct VkExtent3D
1162 radv_sanitize_image_extent(const VkImageType imageType,
1163 const struct VkExtent3D imageExtent)
1164 {
1165 switch (imageType) {
1166 case VK_IMAGE_TYPE_1D:
1167 return (VkExtent3D) { imageExtent.width, 1, 1 };
1168 case VK_IMAGE_TYPE_2D:
1169 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1170 case VK_IMAGE_TYPE_3D:
1171 return imageExtent;
1172 default:
1173 unreachable("invalid image type");
1174 }
1175 }
1176
1177 static inline struct VkOffset3D
1178 radv_sanitize_image_offset(const VkImageType imageType,
1179 const struct VkOffset3D imageOffset)
1180 {
1181 switch (imageType) {
1182 case VK_IMAGE_TYPE_1D:
1183 return (VkOffset3D) { imageOffset.x, 0, 0 };
1184 case VK_IMAGE_TYPE_2D:
1185 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1186 case VK_IMAGE_TYPE_3D:
1187 return imageOffset;
1188 default:
1189 unreachable("invalid image type");
1190 }
1191 }
1192
1193 struct radv_sampler {
1194 uint32_t state[4];
1195 };
1196
1197 struct radv_color_buffer_info {
1198 uint32_t cb_color_base;
1199 uint32_t cb_color_pitch;
1200 uint32_t cb_color_slice;
1201 uint32_t cb_color_view;
1202 uint32_t cb_color_info;
1203 uint32_t cb_color_attrib;
1204 uint32_t cb_dcc_control;
1205 uint32_t cb_color_cmask;
1206 uint32_t cb_color_cmask_slice;
1207 uint32_t cb_color_fmask;
1208 uint32_t cb_color_fmask_slice;
1209 uint32_t cb_clear_value0;
1210 uint32_t cb_clear_value1;
1211 uint32_t cb_dcc_base;
1212 uint32_t micro_tile_mode;
1213 };
1214
1215 struct radv_ds_buffer_info {
1216 uint32_t db_depth_info;
1217 uint32_t db_z_info;
1218 uint32_t db_stencil_info;
1219 uint32_t db_z_read_base;
1220 uint32_t db_stencil_read_base;
1221 uint32_t db_z_write_base;
1222 uint32_t db_stencil_write_base;
1223 uint32_t db_depth_view;
1224 uint32_t db_depth_size;
1225 uint32_t db_depth_slice;
1226 uint32_t db_htile_surface;
1227 uint32_t db_htile_data_base;
1228 uint32_t pa_su_poly_offset_db_fmt_cntl;
1229 float offset_scale;
1230 };
1231
1232 struct radv_attachment_info {
1233 union {
1234 struct radv_color_buffer_info cb;
1235 struct radv_ds_buffer_info ds;
1236 };
1237 struct radv_image_view *attachment;
1238 };
1239
1240 struct radv_framebuffer {
1241 uint32_t width;
1242 uint32_t height;
1243 uint32_t layers;
1244
1245 uint32_t attachment_count;
1246 struct radv_attachment_info attachments[0];
1247 };
1248
1249 struct radv_subpass_barrier {
1250 VkPipelineStageFlags src_stage_mask;
1251 VkAccessFlags src_access_mask;
1252 VkAccessFlags dst_access_mask;
1253 };
1254
1255 struct radv_subpass {
1256 uint32_t input_count;
1257 VkAttachmentReference * input_attachments;
1258 uint32_t color_count;
1259 VkAttachmentReference * color_attachments;
1260 VkAttachmentReference * resolve_attachments;
1261 VkAttachmentReference depth_stencil_attachment;
1262
1263 /** Subpass has at least one resolve attachment */
1264 bool has_resolve;
1265
1266 struct radv_subpass_barrier start_barrier;
1267 };
1268
1269 struct radv_render_pass_attachment {
1270 VkFormat format;
1271 uint32_t samples;
1272 VkAttachmentLoadOp load_op;
1273 VkAttachmentLoadOp stencil_load_op;
1274 VkImageLayout initial_layout;
1275 VkImageLayout final_layout;
1276 };
1277
1278 struct radv_render_pass {
1279 uint32_t attachment_count;
1280 uint32_t subpass_count;
1281 VkAttachmentReference * subpass_attachments;
1282 struct radv_render_pass_attachment * attachments;
1283 struct radv_subpass_barrier end_barrier;
1284 struct radv_subpass subpasses[0];
1285 };
1286
1287 VkResult radv_device_init_meta(struct radv_device *device);
1288 void radv_device_finish_meta(struct radv_device *device);
1289
1290 struct radv_query_pool {
1291 struct radeon_winsys_bo *bo;
1292 uint32_t stride;
1293 uint32_t availability_offset;
1294 char *ptr;
1295 VkQueryType type;
1296 };
1297
1298 VkResult
1299 radv_temp_descriptor_set_create(struct radv_device *device,
1300 struct radv_cmd_buffer *cmd_buffer,
1301 VkDescriptorSetLayout _layout,
1302 VkDescriptorSet *_set);
1303
1304 void
1305 radv_temp_descriptor_set_destroy(struct radv_device *device,
1306 VkDescriptorSet _set);
1307 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1308 struct radv_image *image, uint32_t value);
1309 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1310 struct radv_image *image, uint32_t value);
1311
1312 struct radv_fence {
1313 struct radeon_winsys_fence *fence;
1314 bool submitted;
1315 bool signalled;
1316 };
1317
1318 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1319 \
1320 static inline struct __radv_type * \
1321 __radv_type ## _from_handle(__VkType _handle) \
1322 { \
1323 return (struct __radv_type *) _handle; \
1324 } \
1325 \
1326 static inline __VkType \
1327 __radv_type ## _to_handle(struct __radv_type *_obj) \
1328 { \
1329 return (__VkType) _obj; \
1330 }
1331
1332 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1333 \
1334 static inline struct __radv_type * \
1335 __radv_type ## _from_handle(__VkType _handle) \
1336 { \
1337 return (struct __radv_type *)(uintptr_t) _handle; \
1338 } \
1339 \
1340 static inline __VkType \
1341 __radv_type ## _to_handle(struct __radv_type *_obj) \
1342 { \
1343 return (__VkType)(uintptr_t) _obj; \
1344 }
1345
1346 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1347 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1348
1349 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1350 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1351 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1352 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1353 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1354
1355 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1356 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1357 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1358 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1359 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1360 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1361 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1362 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1363 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1364 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1365 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1366 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1367 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1368 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1369 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1370 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1371 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1372 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1373 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1374
1375 #endif /* RADV_PRIVATE_H */