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vulkan: Add KHR_display extension using DRM [v10]
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "radv_descriptor_set.h"
62 #include "radv_extensions.h"
63 #include "radv_cs.h"
64
65 #include <llvm-c/TargetMachine.h>
66
67 /* Pre-declarations needed for WSI entrypoints */
68 struct wl_surface;
69 struct wl_display;
70 typedef struct xcb_connection_t xcb_connection_t;
71 typedef uint32_t xcb_visualid_t;
72 typedef uint32_t xcb_window_t;
73
74 #include <vulkan/vulkan.h>
75 #include <vulkan/vulkan_intel.h>
76 #include <vulkan/vk_icd.h>
77 #include <vulkan/vk_android_native_buffer.h>
78
79 #include "radv_entrypoints.h"
80
81 #include "wsi_common.h"
82
83 #define ATI_VENDOR_ID 0x1002
84
85 #define MAX_VBS 32
86 #define MAX_VERTEX_ATTRIBS 32
87 #define MAX_RTS 8
88 #define MAX_VIEWPORTS 16
89 #define MAX_SCISSORS 16
90 #define MAX_DISCARD_RECTANGLES 4
91 #define MAX_PUSH_CONSTANTS_SIZE 128
92 #define MAX_PUSH_DESCRIPTORS 32
93 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
94 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
95 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
96 #define MAX_SAMPLES_LOG2 4
97 #define NUM_META_FS_KEYS 13
98 #define RADV_MAX_DRM_DEVICES 8
99 #define MAX_VIEWS 8
100
101 #define NUM_DEPTH_CLEAR_PIPELINES 3
102
103 /*
104 * This is the point we switch from using CP to compute shader
105 * for certain buffer operations.
106 */
107 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
108
109 enum radv_mem_heap {
110 RADV_MEM_HEAP_VRAM,
111 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
112 RADV_MEM_HEAP_GTT,
113 RADV_MEM_HEAP_COUNT
114 };
115
116 enum radv_mem_type {
117 RADV_MEM_TYPE_VRAM,
118 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
119 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
120 RADV_MEM_TYPE_GTT_CACHED,
121 RADV_MEM_TYPE_COUNT
122 };
123
124 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
125
126 static inline uint32_t
127 align_u32(uint32_t v, uint32_t a)
128 {
129 assert(a != 0 && a == (a & -a));
130 return (v + a - 1) & ~(a - 1);
131 }
132
133 static inline uint32_t
134 align_u32_npot(uint32_t v, uint32_t a)
135 {
136 return (v + a - 1) / a * a;
137 }
138
139 static inline uint64_t
140 align_u64(uint64_t v, uint64_t a)
141 {
142 assert(a != 0 && a == (a & -a));
143 return (v + a - 1) & ~(a - 1);
144 }
145
146 static inline int32_t
147 align_i32(int32_t v, int32_t a)
148 {
149 assert(a != 0 && a == (a & -a));
150 return (v + a - 1) & ~(a - 1);
151 }
152
153 /** Alignment must be a power of 2. */
154 static inline bool
155 radv_is_aligned(uintmax_t n, uintmax_t a)
156 {
157 assert(a == (a & -a));
158 return (n & (a - 1)) == 0;
159 }
160
161 static inline uint32_t
162 round_up_u32(uint32_t v, uint32_t a)
163 {
164 return (v + a - 1) / a;
165 }
166
167 static inline uint64_t
168 round_up_u64(uint64_t v, uint64_t a)
169 {
170 return (v + a - 1) / a;
171 }
172
173 static inline uint32_t
174 radv_minify(uint32_t n, uint32_t levels)
175 {
176 if (unlikely(n == 0))
177 return 0;
178 else
179 return MAX2(n >> levels, 1);
180 }
181 static inline float
182 radv_clamp_f(float f, float min, float max)
183 {
184 assert(min < max);
185
186 if (f > max)
187 return max;
188 else if (f < min)
189 return min;
190 else
191 return f;
192 }
193
194 static inline bool
195 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
196 {
197 if (*inout_mask & clear_mask) {
198 *inout_mask &= ~clear_mask;
199 return true;
200 } else {
201 return false;
202 }
203 }
204
205 #define for_each_bit(b, dword) \
206 for (uint32_t __dword = (dword); \
207 (b) = __builtin_ffs(__dword) - 1, __dword; \
208 __dword &= ~(1 << (b)))
209
210 #define typed_memcpy(dest, src, count) ({ \
211 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
212 memcpy((dest), (src), (count) * sizeof(*(src))); \
213 })
214
215 /* Whenever we generate an error, pass it through this function. Useful for
216 * debugging, where we can break on it. Only call at error site, not when
217 * propagating errors. Might be useful to plug in a stack trace here.
218 */
219
220 struct radv_instance;
221
222 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
223
224 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
225 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
226
227 void __radv_finishme(const char *file, int line, const char *format, ...)
228 radv_printflike(3, 4);
229 void radv_loge(const char *format, ...) radv_printflike(1, 2);
230 void radv_loge_v(const char *format, va_list va);
231 void radv_logi(const char *format, ...) radv_printflike(1, 2);
232 void radv_logi_v(const char *format, va_list va);
233
234 /**
235 * Print a FINISHME message, including its source location.
236 */
237 #define radv_finishme(format, ...) \
238 do { \
239 static bool reported = false; \
240 if (!reported) { \
241 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
242 reported = true; \
243 } \
244 } while (0)
245
246 /* A non-fatal assert. Useful for debugging. */
247 #ifdef DEBUG
248 #define radv_assert(x) ({ \
249 if (unlikely(!(x))) \
250 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
251 })
252 #else
253 #define radv_assert(x)
254 #endif
255
256 #define stub_return(v) \
257 do { \
258 radv_finishme("stub %s", __func__); \
259 return (v); \
260 } while (0)
261
262 #define stub() \
263 do { \
264 radv_finishme("stub %s", __func__); \
265 return; \
266 } while (0)
267
268 void *radv_lookup_entrypoint_unchecked(const char *name);
269 void *radv_lookup_entrypoint_checked(const char *name,
270 uint32_t core_version,
271 const struct radv_instance_extension_table *instance,
272 const struct radv_device_extension_table *device);
273
274 struct radv_physical_device {
275 VK_LOADER_DATA _loader_data;
276
277 struct radv_instance * instance;
278
279 struct radeon_winsys *ws;
280 struct radeon_info rad_info;
281 char path[20];
282 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
283 uint8_t driver_uuid[VK_UUID_SIZE];
284 uint8_t device_uuid[VK_UUID_SIZE];
285 uint8_t cache_uuid[VK_UUID_SIZE];
286
287 int local_fd;
288 int master_fd;
289 struct wsi_device wsi_device;
290
291 bool has_rbplus; /* if RB+ register exist */
292 bool rbplus_allowed; /* if RB+ is allowed */
293 bool has_clear_state;
294 bool cpdma_prefetch_writes_memory;
295 bool has_scissor_bug;
296
297 bool has_out_of_order_rast;
298 bool out_of_order_rast_allowed;
299
300 /* Whether DCC should be enabled for MSAA textures. */
301 bool dcc_msaa_allowed;
302
303 /* This is the drivers on-disk cache used as a fallback as opposed to
304 * the pipeline cache defined by apps.
305 */
306 struct disk_cache * disk_cache;
307
308 VkPhysicalDeviceMemoryProperties memory_properties;
309 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
310
311 struct radv_device_extension_table supported_extensions;
312 };
313
314 struct radv_instance {
315 VK_LOADER_DATA _loader_data;
316
317 VkAllocationCallbacks alloc;
318
319 uint32_t apiVersion;
320 int physicalDeviceCount;
321 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
322
323 uint64_t debug_flags;
324 uint64_t perftest_flags;
325
326 struct vk_debug_report_instance debug_report_callbacks;
327
328 struct radv_instance_extension_table enabled_extensions;
329 };
330
331 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
332 void radv_finish_wsi(struct radv_physical_device *physical_device);
333
334 bool radv_instance_extension_supported(const char *name);
335 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
336 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
337 const char *name);
338
339 struct cache_entry;
340
341 struct radv_pipeline_cache {
342 struct radv_device * device;
343 pthread_mutex_t mutex;
344
345 uint32_t total_size;
346 uint32_t table_size;
347 uint32_t kernel_count;
348 struct cache_entry ** hash_table;
349 bool modified;
350
351 VkAllocationCallbacks alloc;
352 };
353
354 struct radv_pipeline_key {
355 uint32_t instance_rate_inputs;
356 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
357 uint64_t vertex_alpha_adjust;
358 unsigned tess_input_vertices;
359 uint32_t col_format;
360 uint32_t is_int8;
361 uint32_t is_int10;
362 uint8_t log2_ps_iter_samples;
363 uint8_t log2_num_samples;
364 uint32_t has_multiview_view_index : 1;
365 uint32_t optimisations_disabled : 1;
366 };
367
368 void
369 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
370 struct radv_device *device);
371 void
372 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
373 void
374 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
375 const void *data, size_t size);
376
377 struct radv_shader_variant;
378
379 bool
380 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
381 struct radv_pipeline_cache *cache,
382 const unsigned char *sha1,
383 struct radv_shader_variant **variants);
384
385 void
386 radv_pipeline_cache_insert_shaders(struct radv_device *device,
387 struct radv_pipeline_cache *cache,
388 const unsigned char *sha1,
389 struct radv_shader_variant **variants,
390 const void *const *codes,
391 const unsigned *code_sizes);
392
393 enum radv_blit_ds_layout {
394 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
395 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
396 RADV_BLIT_DS_LAYOUT_COUNT,
397 };
398
399 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
400 {
401 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
402 }
403
404 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
405 {
406 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
407 }
408
409 enum radv_meta_dst_layout {
410 RADV_META_DST_LAYOUT_GENERAL,
411 RADV_META_DST_LAYOUT_OPTIMAL,
412 RADV_META_DST_LAYOUT_COUNT,
413 };
414
415 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
416 {
417 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
418 }
419
420 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
421 {
422 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
423 }
424
425 struct radv_meta_state {
426 VkAllocationCallbacks alloc;
427
428 struct radv_pipeline_cache cache;
429
430 /**
431 * Use array element `i` for images with `2^i` samples.
432 */
433 struct {
434 VkRenderPass render_pass[NUM_META_FS_KEYS];
435 VkPipeline color_pipelines[NUM_META_FS_KEYS];
436
437 VkRenderPass depthstencil_rp;
438 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
439 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
440 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
441 } clear[1 + MAX_SAMPLES_LOG2];
442
443 VkPipelineLayout clear_color_p_layout;
444 VkPipelineLayout clear_depth_p_layout;
445 struct {
446 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
447
448 /** Pipeline that blits from a 1D image. */
449 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
450
451 /** Pipeline that blits from a 2D image. */
452 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
453
454 /** Pipeline that blits from a 3D image. */
455 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
456
457 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
458 VkPipeline depth_only_1d_pipeline;
459 VkPipeline depth_only_2d_pipeline;
460 VkPipeline depth_only_3d_pipeline;
461
462 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
463 VkPipeline stencil_only_1d_pipeline;
464 VkPipeline stencil_only_2d_pipeline;
465 VkPipeline stencil_only_3d_pipeline;
466 VkPipelineLayout pipeline_layout;
467 VkDescriptorSetLayout ds_layout;
468 } blit;
469
470 struct {
471 VkPipelineLayout p_layouts[5];
472 VkDescriptorSetLayout ds_layouts[5];
473 VkPipeline pipelines[5][NUM_META_FS_KEYS];
474
475 VkPipeline depth_only_pipeline[5];
476
477 VkPipeline stencil_only_pipeline[5];
478 } blit2d[1 + MAX_SAMPLES_LOG2];
479
480 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
481 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
482 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
483
484 struct {
485 VkPipelineLayout img_p_layout;
486 VkDescriptorSetLayout img_ds_layout;
487 VkPipeline pipeline;
488 VkPipeline pipeline_3d;
489 } itob;
490 struct {
491 VkPipelineLayout img_p_layout;
492 VkDescriptorSetLayout img_ds_layout;
493 VkPipeline pipeline;
494 VkPipeline pipeline_3d;
495 } btoi;
496 struct {
497 VkPipelineLayout img_p_layout;
498 VkDescriptorSetLayout img_ds_layout;
499 VkPipeline pipeline;
500 VkPipeline pipeline_3d;
501 } itoi;
502 struct {
503 VkPipelineLayout img_p_layout;
504 VkDescriptorSetLayout img_ds_layout;
505 VkPipeline pipeline;
506 VkPipeline pipeline_3d;
507 } cleari;
508
509 struct {
510 VkPipelineLayout p_layout;
511 VkPipeline pipeline[NUM_META_FS_KEYS];
512 VkRenderPass pass[NUM_META_FS_KEYS];
513 } resolve;
514
515 struct {
516 VkDescriptorSetLayout ds_layout;
517 VkPipelineLayout p_layout;
518 struct {
519 VkPipeline pipeline;
520 VkPipeline i_pipeline;
521 VkPipeline srgb_pipeline;
522 } rc[MAX_SAMPLES_LOG2];
523 } resolve_compute;
524
525 struct {
526 VkDescriptorSetLayout ds_layout;
527 VkPipelineLayout p_layout;
528
529 struct {
530 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
531 VkPipeline pipeline[NUM_META_FS_KEYS];
532 } rc[MAX_SAMPLES_LOG2];
533 } resolve_fragment;
534
535 struct {
536 VkPipelineLayout p_layout;
537 VkPipeline decompress_pipeline;
538 VkPipeline resummarize_pipeline;
539 VkRenderPass pass;
540 } depth_decomp[1 + MAX_SAMPLES_LOG2];
541
542 struct {
543 VkPipelineLayout p_layout;
544 VkPipeline cmask_eliminate_pipeline;
545 VkPipeline fmask_decompress_pipeline;
546 VkPipeline dcc_decompress_pipeline;
547 VkRenderPass pass;
548
549 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
550 VkPipelineLayout dcc_decompress_compute_p_layout;
551 VkPipeline dcc_decompress_compute_pipeline;
552 } fast_clear_flush;
553
554 struct {
555 VkPipelineLayout fill_p_layout;
556 VkPipelineLayout copy_p_layout;
557 VkDescriptorSetLayout fill_ds_layout;
558 VkDescriptorSetLayout copy_ds_layout;
559 VkPipeline fill_pipeline;
560 VkPipeline copy_pipeline;
561 } buffer;
562
563 struct {
564 VkDescriptorSetLayout ds_layout;
565 VkPipelineLayout p_layout;
566 VkPipeline occlusion_query_pipeline;
567 VkPipeline pipeline_statistics_query_pipeline;
568 } query;
569 };
570
571 /* queue types */
572 #define RADV_QUEUE_GENERAL 0
573 #define RADV_QUEUE_COMPUTE 1
574 #define RADV_QUEUE_TRANSFER 2
575
576 #define RADV_MAX_QUEUE_FAMILIES 3
577
578 enum ring_type radv_queue_family_to_ring(int f);
579
580 struct radv_queue {
581 VK_LOADER_DATA _loader_data;
582 struct radv_device * device;
583 struct radeon_winsys_ctx *hw_ctx;
584 enum radeon_ctx_priority priority;
585 uint32_t queue_family_index;
586 int queue_idx;
587 VkDeviceQueueCreateFlags flags;
588
589 uint32_t scratch_size;
590 uint32_t compute_scratch_size;
591 uint32_t esgs_ring_size;
592 uint32_t gsvs_ring_size;
593 bool has_tess_rings;
594 bool has_sample_positions;
595
596 struct radeon_winsys_bo *scratch_bo;
597 struct radeon_winsys_bo *descriptor_bo;
598 struct radeon_winsys_bo *compute_scratch_bo;
599 struct radeon_winsys_bo *esgs_ring_bo;
600 struct radeon_winsys_bo *gsvs_ring_bo;
601 struct radeon_winsys_bo *tess_rings_bo;
602 struct radeon_cmdbuf *initial_preamble_cs;
603 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
604 struct radeon_cmdbuf *continue_preamble_cs;
605 };
606
607 struct radv_bo_list {
608 struct radv_winsys_bo_list list;
609 unsigned capacity;
610 pthread_mutex_t mutex;
611 };
612
613 struct radv_device {
614 VK_LOADER_DATA _loader_data;
615
616 VkAllocationCallbacks alloc;
617
618 struct radv_instance * instance;
619 struct radeon_winsys *ws;
620
621 struct radv_meta_state meta_state;
622
623 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
624 int queue_count[RADV_MAX_QUEUE_FAMILIES];
625 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
626
627 bool always_use_syncobj;
628 bool has_distributed_tess;
629 bool pbb_allowed;
630 bool dfsm_allowed;
631 uint32_t tess_offchip_block_dw_size;
632 uint32_t scratch_waves;
633 uint32_t dispatch_initiator;
634
635 uint32_t gs_table_depth;
636
637 /* MSAA sample locations.
638 * The first index is the sample index.
639 * The second index is the coordinate: X, Y. */
640 float sample_locations_1x[1][2];
641 float sample_locations_2x[2][2];
642 float sample_locations_4x[4][2];
643 float sample_locations_8x[8][2];
644 float sample_locations_16x[16][2];
645
646 /* CIK and later */
647 uint32_t gfx_init_size_dw;
648 struct radeon_winsys_bo *gfx_init;
649
650 struct radeon_winsys_bo *trace_bo;
651 uint32_t *trace_id_ptr;
652
653 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
654 bool keep_shader_info;
655
656 struct radv_physical_device *physical_device;
657
658 /* Backup in-memory cache to be used if the app doesn't provide one */
659 struct radv_pipeline_cache * mem_cache;
660
661 /*
662 * use different counters so MSAA MRTs get consecutive surface indices,
663 * even if MASK is allocated in between.
664 */
665 uint32_t image_mrt_offset_counter;
666 uint32_t fmask_mrt_offset_counter;
667 struct list_head shader_slabs;
668 mtx_t shader_slab_mutex;
669
670 /* For detecting VM faults reported by dmesg. */
671 uint64_t dmesg_timestamp;
672
673 struct radv_device_extension_table enabled_extensions;
674
675 /* Whether the driver uses a global BO list. */
676 bool use_global_bo_list;
677
678 struct radv_bo_list bo_list;
679 };
680
681 struct radv_device_memory {
682 struct radeon_winsys_bo *bo;
683 /* for dedicated allocations */
684 struct radv_image *image;
685 struct radv_buffer *buffer;
686 uint32_t type_index;
687 VkDeviceSize map_size;
688 void * map;
689 void * user_ptr;
690 };
691
692
693 struct radv_descriptor_range {
694 uint64_t va;
695 uint32_t size;
696 };
697
698 struct radv_descriptor_set {
699 const struct radv_descriptor_set_layout *layout;
700 uint32_t size;
701
702 struct radeon_winsys_bo *bo;
703 uint64_t va;
704 uint32_t *mapped_ptr;
705 struct radv_descriptor_range *dynamic_descriptors;
706
707 struct radeon_winsys_bo *descriptors[0];
708 };
709
710 struct radv_push_descriptor_set
711 {
712 struct radv_descriptor_set set;
713 uint32_t capacity;
714 };
715
716 struct radv_descriptor_pool_entry {
717 uint32_t offset;
718 uint32_t size;
719 struct radv_descriptor_set *set;
720 };
721
722 struct radv_descriptor_pool {
723 struct radeon_winsys_bo *bo;
724 uint8_t *mapped_ptr;
725 uint64_t current_offset;
726 uint64_t size;
727
728 uint8_t *host_memory_base;
729 uint8_t *host_memory_ptr;
730 uint8_t *host_memory_end;
731
732 uint32_t entry_count;
733 uint32_t max_entry_count;
734 struct radv_descriptor_pool_entry entries[0];
735 };
736
737 struct radv_descriptor_update_template_entry {
738 VkDescriptorType descriptor_type;
739
740 /* The number of descriptors to update */
741 uint32_t descriptor_count;
742
743 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
744 uint32_t dst_offset;
745
746 /* In dwords. Not valid/used for dynamic descriptors */
747 uint32_t dst_stride;
748
749 uint32_t buffer_offset;
750
751 /* Only valid for combined image samplers and samplers */
752 uint16_t has_sampler;
753
754 /* In bytes */
755 size_t src_offset;
756 size_t src_stride;
757
758 /* For push descriptors */
759 const uint32_t *immutable_samplers;
760 };
761
762 struct radv_descriptor_update_template {
763 uint32_t entry_count;
764 VkPipelineBindPoint bind_point;
765 struct radv_descriptor_update_template_entry entry[0];
766 };
767
768 struct radv_buffer {
769 VkDeviceSize size;
770
771 VkBufferUsageFlags usage;
772 VkBufferCreateFlags flags;
773
774 /* Set when bound */
775 struct radeon_winsys_bo * bo;
776 VkDeviceSize offset;
777
778 bool shareable;
779 };
780
781 enum radv_dynamic_state_bits {
782 RADV_DYNAMIC_VIEWPORT = 1 << 0,
783 RADV_DYNAMIC_SCISSOR = 1 << 1,
784 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
785 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
786 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
787 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
788 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
789 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
790 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
791 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
792 RADV_DYNAMIC_ALL = (1 << 10) - 1,
793 };
794
795 enum radv_cmd_dirty_bits {
796 /* Keep the dynamic state dirty bits in sync with
797 * enum radv_dynamic_state_bits */
798 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
799 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
800 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
801 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
802 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
803 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
804 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
805 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
806 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
807 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
808 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
809 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
810 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
811 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
812 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
813 };
814
815 enum radv_cmd_flush_bits {
816 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
817 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
818 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
819 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
820 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
821 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
822 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
823 /* Same as above, but only writes back and doesn't invalidate */
824 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
825 /* Framebuffer caches */
826 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
827 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
828 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
829 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
830 /* Engine synchronization. */
831 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
832 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
833 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
834 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
835
836 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
837 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
838 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
839 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
840 };
841
842 struct radv_vertex_binding {
843 struct radv_buffer * buffer;
844 VkDeviceSize offset;
845 };
846
847 struct radv_viewport_state {
848 uint32_t count;
849 VkViewport viewports[MAX_VIEWPORTS];
850 };
851
852 struct radv_scissor_state {
853 uint32_t count;
854 VkRect2D scissors[MAX_SCISSORS];
855 };
856
857 struct radv_discard_rectangle_state {
858 uint32_t count;
859 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
860 };
861
862 struct radv_dynamic_state {
863 /**
864 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
865 * Defines the set of saved dynamic state.
866 */
867 uint32_t mask;
868
869 struct radv_viewport_state viewport;
870
871 struct radv_scissor_state scissor;
872
873 float line_width;
874
875 struct {
876 float bias;
877 float clamp;
878 float slope;
879 } depth_bias;
880
881 float blend_constants[4];
882
883 struct {
884 float min;
885 float max;
886 } depth_bounds;
887
888 struct {
889 uint32_t front;
890 uint32_t back;
891 } stencil_compare_mask;
892
893 struct {
894 uint32_t front;
895 uint32_t back;
896 } stencil_write_mask;
897
898 struct {
899 uint32_t front;
900 uint32_t back;
901 } stencil_reference;
902
903 struct radv_discard_rectangle_state discard_rectangle;
904 };
905
906 extern const struct radv_dynamic_state default_dynamic_state;
907
908 const char *
909 radv_get_debug_option_name(int id);
910
911 const char *
912 radv_get_perftest_option_name(int id);
913
914 /**
915 * Attachment state when recording a renderpass instance.
916 *
917 * The clear value is valid only if there exists a pending clear.
918 */
919 struct radv_attachment_state {
920 VkImageAspectFlags pending_clear_aspects;
921 uint32_t cleared_views;
922 VkClearValue clear_value;
923 VkImageLayout current_layout;
924 };
925
926 struct radv_descriptor_state {
927 struct radv_descriptor_set *sets[MAX_SETS];
928 uint32_t dirty;
929 uint32_t valid;
930 struct radv_push_descriptor_set push_set;
931 bool push_dirty;
932 };
933
934 struct radv_cmd_state {
935 /* Vertex descriptors */
936 uint64_t vb_va;
937 unsigned vb_size;
938
939 bool predicating;
940 uint32_t dirty;
941
942 uint32_t prefetch_L2_mask;
943
944 struct radv_pipeline * pipeline;
945 struct radv_pipeline * emitted_pipeline;
946 struct radv_pipeline * compute_pipeline;
947 struct radv_pipeline * emitted_compute_pipeline;
948 struct radv_framebuffer * framebuffer;
949 struct radv_render_pass * pass;
950 const struct radv_subpass * subpass;
951 struct radv_dynamic_state dynamic;
952 struct radv_attachment_state * attachments;
953 VkRect2D render_area;
954
955 /* Index buffer */
956 struct radv_buffer *index_buffer;
957 uint64_t index_offset;
958 uint32_t index_type;
959 uint32_t max_index_count;
960 uint64_t index_va;
961 int32_t last_index_type;
962
963 int32_t last_primitive_reset_en;
964 uint32_t last_primitive_reset_index;
965 enum radv_cmd_flush_bits flush_bits;
966 unsigned active_occlusion_queries;
967 bool perfect_occlusion_queries_enabled;
968 float offset_scale;
969 uint32_t trace_id;
970 uint32_t last_ia_multi_vgt_param;
971
972 uint32_t last_num_instances;
973 uint32_t last_first_instance;
974 uint32_t last_vertex_offset;
975 };
976
977 struct radv_cmd_pool {
978 VkAllocationCallbacks alloc;
979 struct list_head cmd_buffers;
980 struct list_head free_cmd_buffers;
981 uint32_t queue_family_index;
982 };
983
984 struct radv_cmd_buffer_upload {
985 uint8_t *map;
986 unsigned offset;
987 uint64_t size;
988 struct radeon_winsys_bo *upload_bo;
989 struct list_head list;
990 };
991
992 enum radv_cmd_buffer_status {
993 RADV_CMD_BUFFER_STATUS_INVALID,
994 RADV_CMD_BUFFER_STATUS_INITIAL,
995 RADV_CMD_BUFFER_STATUS_RECORDING,
996 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
997 RADV_CMD_BUFFER_STATUS_PENDING,
998 };
999
1000 struct radv_cmd_buffer {
1001 VK_LOADER_DATA _loader_data;
1002
1003 struct radv_device * device;
1004
1005 struct radv_cmd_pool * pool;
1006 struct list_head pool_link;
1007
1008 VkCommandBufferUsageFlags usage_flags;
1009 VkCommandBufferLevel level;
1010 enum radv_cmd_buffer_status status;
1011 struct radeon_cmdbuf *cs;
1012 struct radv_cmd_state state;
1013 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1014 uint32_t queue_family_index;
1015
1016 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1017 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1018 VkShaderStageFlags push_constant_stages;
1019 struct radv_descriptor_set meta_push_descriptors;
1020
1021 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1022
1023 struct radv_cmd_buffer_upload upload;
1024
1025 uint32_t scratch_size_needed;
1026 uint32_t compute_scratch_size_needed;
1027 uint32_t esgs_ring_size_needed;
1028 uint32_t gsvs_ring_size_needed;
1029 bool tess_rings_needed;
1030 bool sample_positions_needed;
1031
1032 VkResult record_result;
1033
1034 int ring_offsets_idx; /* just used for verification */
1035 uint32_t gfx9_fence_offset;
1036 struct radeon_winsys_bo *gfx9_fence_bo;
1037 uint32_t gfx9_fence_idx;
1038
1039 /**
1040 * Whether a query pool has been resetted and we have to flush caches.
1041 */
1042 bool pending_reset_query;
1043 };
1044
1045 struct radv_image;
1046
1047 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1048
1049 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
1050 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
1051
1052 void cik_create_gfx_config(struct radv_device *device);
1053
1054 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1055 int count, const VkViewport *viewports);
1056 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1057 int count, const VkRect2D *scissors,
1058 const VkViewport *viewports, bool can_use_guardband);
1059 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1060 bool instanced_draw, bool indirect_draw,
1061 uint32_t draw_vertex_count);
1062 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1063 bool predicated,
1064 enum chip_class chip_class,
1065 bool is_mec,
1066 unsigned event, unsigned event_flags,
1067 unsigned data_sel,
1068 uint64_t va,
1069 uint32_t old_fence,
1070 uint32_t new_fence);
1071
1072 void si_emit_wait_fence(struct radeon_cmdbuf *cs,
1073 bool predicated,
1074 uint64_t va, uint32_t ref,
1075 uint32_t mask);
1076 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1077 enum chip_class chip_class,
1078 uint32_t *fence_ptr, uint64_t va,
1079 bool is_mec,
1080 enum radv_cmd_flush_bits flush_bits);
1081 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1082 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1083 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1084 uint64_t src_va, uint64_t dest_va,
1085 uint64_t size);
1086 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1087 unsigned size);
1088 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1089 uint64_t size, unsigned value);
1090 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1091 bool
1092 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1093 unsigned size,
1094 unsigned alignment,
1095 unsigned *out_offset,
1096 void **ptr);
1097 void
1098 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1099 const struct radv_subpass *subpass,
1100 bool transitions);
1101 bool
1102 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1103 unsigned size, unsigned alignmnet,
1104 const void *data, unsigned *out_offset);
1105
1106 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1107 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1108 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1109 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1110 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
1111 unsigned radv_cayman_get_maxdist(int log_samples);
1112 void radv_device_init_msaa(struct radv_device *device);
1113
1114 void radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1115 struct radv_image *image,
1116 VkClearDepthStencilValue ds_clear_value,
1117 VkImageAspectFlags aspects);
1118
1119 void radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1120 struct radv_image *image,
1121 int cb_idx,
1122 uint32_t color_values[2]);
1123
1124 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1125 struct radv_image *image,
1126 bool value);
1127 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1128 struct radeon_winsys_bo *bo,
1129 uint64_t offset, uint64_t size, uint32_t value);
1130 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1131 bool radv_get_memory_fd(struct radv_device *device,
1132 struct radv_device_memory *memory,
1133 int *pFD);
1134
1135 static inline void
1136 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1137 unsigned sh_offset, unsigned pointer_count,
1138 bool use_32bit_pointers)
1139 {
1140 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1141 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1142 }
1143
1144 static inline void
1145 radv_emit_shader_pointer_body(struct radv_device *device,
1146 struct radeon_cmdbuf *cs,
1147 uint64_t va, bool use_32bit_pointers)
1148 {
1149 radeon_emit(cs, va);
1150
1151 if (use_32bit_pointers) {
1152 assert(va == 0 ||
1153 (va >> 32) == device->physical_device->rad_info.address32_hi);
1154 } else {
1155 radeon_emit(cs, va >> 32);
1156 }
1157 }
1158
1159 static inline void
1160 radv_emit_shader_pointer(struct radv_device *device,
1161 struct radeon_cmdbuf *cs,
1162 uint32_t sh_offset, uint64_t va, bool global)
1163 {
1164 bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
1165
1166 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1167 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1168 }
1169
1170 static inline struct radv_descriptor_state *
1171 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1172 VkPipelineBindPoint bind_point)
1173 {
1174 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1175 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1176 return &cmd_buffer->descriptors[bind_point];
1177 }
1178
1179 /*
1180 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1181 *
1182 * Limitations: Can't call normal dispatch functions without binding or rebinding
1183 * the compute pipeline.
1184 */
1185 void radv_unaligned_dispatch(
1186 struct radv_cmd_buffer *cmd_buffer,
1187 uint32_t x,
1188 uint32_t y,
1189 uint32_t z);
1190
1191 struct radv_event {
1192 struct radeon_winsys_bo *bo;
1193 uint64_t *map;
1194 };
1195
1196 struct radv_shader_module;
1197
1198 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1199 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1200 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1201 void
1202 radv_hash_shaders(unsigned char *hash,
1203 const VkPipelineShaderStageCreateInfo **stages,
1204 const struct radv_pipeline_layout *layout,
1205 const struct radv_pipeline_key *key,
1206 uint32_t flags);
1207
1208 static inline gl_shader_stage
1209 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1210 {
1211 assert(__builtin_popcount(vk_stage) == 1);
1212 return ffs(vk_stage) - 1;
1213 }
1214
1215 static inline VkShaderStageFlagBits
1216 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1217 {
1218 return (1 << mesa_stage);
1219 }
1220
1221 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1222
1223 #define radv_foreach_stage(stage, stage_bits) \
1224 for (gl_shader_stage stage, \
1225 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1226 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1227 __tmp &= ~(1 << (stage)))
1228
1229 unsigned radv_format_meta_fs_key(VkFormat format);
1230
1231 struct radv_multisample_state {
1232 uint32_t db_eqaa;
1233 uint32_t pa_sc_line_cntl;
1234 uint32_t pa_sc_mode_cntl_0;
1235 uint32_t pa_sc_mode_cntl_1;
1236 uint32_t pa_sc_aa_config;
1237 uint32_t pa_sc_aa_mask[2];
1238 unsigned num_samples;
1239 };
1240
1241 struct radv_prim_vertex_count {
1242 uint8_t min;
1243 uint8_t incr;
1244 };
1245
1246 struct radv_vertex_elements_info {
1247 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1248 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1249 uint32_t binding[MAX_VERTEX_ATTRIBS];
1250 uint32_t offset[MAX_VERTEX_ATTRIBS];
1251 uint32_t count;
1252 };
1253
1254 struct radv_ia_multi_vgt_param_helpers {
1255 uint32_t base;
1256 bool partial_es_wave;
1257 uint8_t primgroup_size;
1258 bool wd_switch_on_eop;
1259 bool ia_switch_on_eoi;
1260 bool partial_vs_wave;
1261 };
1262
1263 #define SI_GS_PER_ES 128
1264
1265 struct radv_pipeline {
1266 struct radv_device * device;
1267 struct radv_dynamic_state dynamic_state;
1268
1269 struct radv_pipeline_layout * layout;
1270
1271 bool need_indirect_descriptor_sets;
1272 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1273 struct radv_shader_variant *gs_copy_shader;
1274 VkShaderStageFlags active_stages;
1275
1276 struct radeon_cmdbuf cs;
1277
1278 struct radv_vertex_elements_info vertex_elements;
1279
1280 uint32_t binding_stride[MAX_VBS];
1281
1282 uint32_t user_data_0[MESA_SHADER_STAGES];
1283 union {
1284 struct {
1285 struct radv_multisample_state ms;
1286 uint32_t spi_baryc_cntl;
1287 bool prim_restart_enable;
1288 unsigned esgs_ring_size;
1289 unsigned gsvs_ring_size;
1290 uint32_t vtx_base_sgpr;
1291 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1292 uint8_t vtx_emit_num;
1293 struct radv_prim_vertex_count prim_vertex_count;
1294 bool can_use_guardband;
1295 uint32_t needed_dynamic_state;
1296 bool disable_out_of_order_rast_for_occlusion;
1297
1298 /* Used for rbplus */
1299 uint32_t col_format;
1300 uint32_t cb_target_mask;
1301 } graphics;
1302 };
1303
1304 unsigned max_waves;
1305 unsigned scratch_bytes_per_wave;
1306 };
1307
1308 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1309 {
1310 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1311 }
1312
1313 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1314 {
1315 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1316 }
1317
1318 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1319 gl_shader_stage stage,
1320 int idx);
1321
1322 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1323 gl_shader_stage stage);
1324
1325 struct radv_graphics_pipeline_create_info {
1326 bool use_rectlist;
1327 bool db_depth_clear;
1328 bool db_stencil_clear;
1329 bool db_depth_disable_expclear;
1330 bool db_stencil_disable_expclear;
1331 bool db_flush_depth_inplace;
1332 bool db_flush_stencil_inplace;
1333 bool db_resummarize;
1334 uint32_t custom_blend_mode;
1335 };
1336
1337 VkResult
1338 radv_graphics_pipeline_create(VkDevice device,
1339 VkPipelineCache cache,
1340 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1341 const struct radv_graphics_pipeline_create_info *extra,
1342 const VkAllocationCallbacks *alloc,
1343 VkPipeline *pPipeline);
1344
1345 struct vk_format_description;
1346 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1347 int first_non_void);
1348 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1349 int first_non_void);
1350 uint32_t radv_translate_colorformat(VkFormat format);
1351 uint32_t radv_translate_color_numformat(VkFormat format,
1352 const struct vk_format_description *desc,
1353 int first_non_void);
1354 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1355 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1356 uint32_t radv_translate_dbformat(VkFormat format);
1357 uint32_t radv_translate_tex_dataformat(VkFormat format,
1358 const struct vk_format_description *desc,
1359 int first_non_void);
1360 uint32_t radv_translate_tex_numformat(VkFormat format,
1361 const struct vk_format_description *desc,
1362 int first_non_void);
1363 bool radv_format_pack_clear_color(VkFormat format,
1364 uint32_t clear_vals[2],
1365 VkClearColorValue *value);
1366 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1367 bool radv_dcc_formats_compatible(VkFormat format1,
1368 VkFormat format2);
1369
1370 struct radv_fmask_info {
1371 uint64_t offset;
1372 uint64_t size;
1373 unsigned alignment;
1374 unsigned pitch_in_pixels;
1375 unsigned bank_height;
1376 unsigned slice_tile_max;
1377 unsigned tile_mode_index;
1378 unsigned tile_swizzle;
1379 };
1380
1381 struct radv_cmask_info {
1382 uint64_t offset;
1383 uint64_t size;
1384 unsigned alignment;
1385 unsigned slice_tile_max;
1386 };
1387
1388 struct radv_image {
1389 VkImageType type;
1390 /* The original VkFormat provided by the client. This may not match any
1391 * of the actual surface formats.
1392 */
1393 VkFormat vk_format;
1394 VkImageAspectFlags aspects;
1395 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1396 struct ac_surf_info info;
1397 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1398 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1399
1400 VkDeviceSize size;
1401 uint32_t alignment;
1402
1403 unsigned queue_family_mask;
1404 bool exclusive;
1405 bool shareable;
1406
1407 /* Set when bound */
1408 struct radeon_winsys_bo *bo;
1409 VkDeviceSize offset;
1410 uint64_t dcc_offset;
1411 uint64_t htile_offset;
1412 bool tc_compatible_htile;
1413 struct radeon_surf surface;
1414
1415 struct radv_fmask_info fmask;
1416 struct radv_cmask_info cmask;
1417 uint64_t clear_value_offset;
1418 uint64_t dcc_pred_offset;
1419
1420 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1421 VkDeviceMemory owned_memory;
1422 };
1423
1424 /* Whether the image has a htile that is known consistent with the contents of
1425 * the image. */
1426 bool radv_layout_has_htile(const struct radv_image *image,
1427 VkImageLayout layout,
1428 unsigned queue_mask);
1429
1430 /* Whether the image has a htile that is known consistent with the contents of
1431 * the image and is allowed to be in compressed form.
1432 *
1433 * If this is false reads that don't use the htile should be able to return
1434 * correct results.
1435 */
1436 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1437 VkImageLayout layout,
1438 unsigned queue_mask);
1439
1440 bool radv_layout_can_fast_clear(const struct radv_image *image,
1441 VkImageLayout layout,
1442 unsigned queue_mask);
1443
1444 bool radv_layout_dcc_compressed(const struct radv_image *image,
1445 VkImageLayout layout,
1446 unsigned queue_mask);
1447
1448 /**
1449 * Return whether the image has CMASK metadata for color surfaces.
1450 */
1451 static inline bool
1452 radv_image_has_cmask(const struct radv_image *image)
1453 {
1454 return image->cmask.size;
1455 }
1456
1457 /**
1458 * Return whether the image has FMASK metadata for color surfaces.
1459 */
1460 static inline bool
1461 radv_image_has_fmask(const struct radv_image *image)
1462 {
1463 return image->fmask.size;
1464 }
1465
1466 /**
1467 * Return whether the image has DCC metadata for color surfaces.
1468 */
1469 static inline bool
1470 radv_image_has_dcc(const struct radv_image *image)
1471 {
1472 return image->surface.dcc_size;
1473 }
1474
1475 /**
1476 * Return whether DCC metadata is enabled for a level.
1477 */
1478 static inline bool
1479 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1480 {
1481 return radv_image_has_dcc(image) &&
1482 level < image->surface.num_dcc_levels;
1483 }
1484
1485 /**
1486 * Return whether the image has HTILE metadata for depth surfaces.
1487 */
1488 static inline bool
1489 radv_image_has_htile(const struct radv_image *image)
1490 {
1491 return image->surface.htile_size;
1492 }
1493
1494 /**
1495 * Return whether HTILE metadata is enabled for a level.
1496 */
1497 static inline bool
1498 radv_htile_enabled(const struct radv_image *image, unsigned level)
1499 {
1500 return radv_image_has_htile(image) && level == 0;
1501 }
1502
1503 /**
1504 * Return whether the image is TC-compatible HTILE.
1505 */
1506 static inline bool
1507 radv_image_is_tc_compat_htile(const struct radv_image *image)
1508 {
1509 return radv_image_has_htile(image) && image->tc_compatible_htile;
1510 }
1511
1512 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1513
1514 static inline uint32_t
1515 radv_get_layerCount(const struct radv_image *image,
1516 const VkImageSubresourceRange *range)
1517 {
1518 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1519 image->info.array_size - range->baseArrayLayer : range->layerCount;
1520 }
1521
1522 static inline uint32_t
1523 radv_get_levelCount(const struct radv_image *image,
1524 const VkImageSubresourceRange *range)
1525 {
1526 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1527 image->info.levels - range->baseMipLevel : range->levelCount;
1528 }
1529
1530 struct radeon_bo_metadata;
1531 void
1532 radv_init_metadata(struct radv_device *device,
1533 struct radv_image *image,
1534 struct radeon_bo_metadata *metadata);
1535
1536 struct radv_image_view {
1537 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1538 struct radeon_winsys_bo *bo;
1539
1540 VkImageViewType type;
1541 VkImageAspectFlags aspect_mask;
1542 VkFormat vk_format;
1543 uint32_t base_layer;
1544 uint32_t layer_count;
1545 uint32_t base_mip;
1546 uint32_t level_count;
1547 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1548
1549 uint32_t descriptor[16];
1550
1551 /* Descriptor for use as a storage image as opposed to a sampled image.
1552 * This has a few differences for cube maps (e.g. type).
1553 */
1554 uint32_t storage_descriptor[16];
1555 };
1556
1557 struct radv_image_create_info {
1558 const VkImageCreateInfo *vk_info;
1559 bool scanout;
1560 bool no_metadata_planes;
1561 };
1562
1563 VkResult radv_image_create(VkDevice _device,
1564 const struct radv_image_create_info *info,
1565 const VkAllocationCallbacks* alloc,
1566 VkImage *pImage);
1567
1568 VkResult
1569 radv_image_from_gralloc(VkDevice device_h,
1570 const VkImageCreateInfo *base_info,
1571 const VkNativeBufferANDROID *gralloc_info,
1572 const VkAllocationCallbacks *alloc,
1573 VkImage *out_image_h);
1574
1575 void radv_image_view_init(struct radv_image_view *view,
1576 struct radv_device *device,
1577 const VkImageViewCreateInfo* pCreateInfo);
1578
1579 struct radv_buffer_view {
1580 struct radeon_winsys_bo *bo;
1581 VkFormat vk_format;
1582 uint64_t range; /**< VkBufferViewCreateInfo::range */
1583 uint32_t state[4];
1584 };
1585 void radv_buffer_view_init(struct radv_buffer_view *view,
1586 struct radv_device *device,
1587 const VkBufferViewCreateInfo* pCreateInfo);
1588
1589 static inline struct VkExtent3D
1590 radv_sanitize_image_extent(const VkImageType imageType,
1591 const struct VkExtent3D imageExtent)
1592 {
1593 switch (imageType) {
1594 case VK_IMAGE_TYPE_1D:
1595 return (VkExtent3D) { imageExtent.width, 1, 1 };
1596 case VK_IMAGE_TYPE_2D:
1597 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1598 case VK_IMAGE_TYPE_3D:
1599 return imageExtent;
1600 default:
1601 unreachable("invalid image type");
1602 }
1603 }
1604
1605 static inline struct VkOffset3D
1606 radv_sanitize_image_offset(const VkImageType imageType,
1607 const struct VkOffset3D imageOffset)
1608 {
1609 switch (imageType) {
1610 case VK_IMAGE_TYPE_1D:
1611 return (VkOffset3D) { imageOffset.x, 0, 0 };
1612 case VK_IMAGE_TYPE_2D:
1613 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1614 case VK_IMAGE_TYPE_3D:
1615 return imageOffset;
1616 default:
1617 unreachable("invalid image type");
1618 }
1619 }
1620
1621 static inline bool
1622 radv_image_extent_compare(const struct radv_image *image,
1623 const VkExtent3D *extent)
1624 {
1625 if (extent->width != image->info.width ||
1626 extent->height != image->info.height ||
1627 extent->depth != image->info.depth)
1628 return false;
1629 return true;
1630 }
1631
1632 struct radv_sampler {
1633 uint32_t state[4];
1634 };
1635
1636 struct radv_color_buffer_info {
1637 uint64_t cb_color_base;
1638 uint64_t cb_color_cmask;
1639 uint64_t cb_color_fmask;
1640 uint64_t cb_dcc_base;
1641 uint32_t cb_color_pitch;
1642 uint32_t cb_color_slice;
1643 uint32_t cb_color_view;
1644 uint32_t cb_color_info;
1645 uint32_t cb_color_attrib;
1646 uint32_t cb_color_attrib2;
1647 uint32_t cb_dcc_control;
1648 uint32_t cb_color_cmask_slice;
1649 uint32_t cb_color_fmask_slice;
1650 };
1651
1652 struct radv_ds_buffer_info {
1653 uint64_t db_z_read_base;
1654 uint64_t db_stencil_read_base;
1655 uint64_t db_z_write_base;
1656 uint64_t db_stencil_write_base;
1657 uint64_t db_htile_data_base;
1658 uint32_t db_depth_info;
1659 uint32_t db_z_info;
1660 uint32_t db_stencil_info;
1661 uint32_t db_depth_view;
1662 uint32_t db_depth_size;
1663 uint32_t db_depth_slice;
1664 uint32_t db_htile_surface;
1665 uint32_t pa_su_poly_offset_db_fmt_cntl;
1666 uint32_t db_z_info2;
1667 uint32_t db_stencil_info2;
1668 float offset_scale;
1669 };
1670
1671 struct radv_attachment_info {
1672 union {
1673 struct radv_color_buffer_info cb;
1674 struct radv_ds_buffer_info ds;
1675 };
1676 struct radv_image_view *attachment;
1677 };
1678
1679 struct radv_framebuffer {
1680 uint32_t width;
1681 uint32_t height;
1682 uint32_t layers;
1683
1684 uint32_t attachment_count;
1685 struct radv_attachment_info attachments[0];
1686 };
1687
1688 struct radv_subpass_barrier {
1689 VkPipelineStageFlags src_stage_mask;
1690 VkAccessFlags src_access_mask;
1691 VkAccessFlags dst_access_mask;
1692 };
1693
1694 struct radv_subpass {
1695 uint32_t input_count;
1696 uint32_t color_count;
1697 VkAttachmentReference * input_attachments;
1698 VkAttachmentReference * color_attachments;
1699 VkAttachmentReference * resolve_attachments;
1700 VkAttachmentReference depth_stencil_attachment;
1701
1702 /** Subpass has at least one resolve attachment */
1703 bool has_resolve;
1704
1705 struct radv_subpass_barrier start_barrier;
1706
1707 uint32_t view_mask;
1708 VkSampleCountFlagBits max_sample_count;
1709 };
1710
1711 struct radv_render_pass_attachment {
1712 VkFormat format;
1713 uint32_t samples;
1714 VkAttachmentLoadOp load_op;
1715 VkAttachmentLoadOp stencil_load_op;
1716 VkImageLayout initial_layout;
1717 VkImageLayout final_layout;
1718 uint32_t view_mask;
1719 };
1720
1721 struct radv_render_pass {
1722 uint32_t attachment_count;
1723 uint32_t subpass_count;
1724 VkAttachmentReference * subpass_attachments;
1725 struct radv_render_pass_attachment * attachments;
1726 struct radv_subpass_barrier end_barrier;
1727 struct radv_subpass subpasses[0];
1728 };
1729
1730 VkResult radv_device_init_meta(struct radv_device *device);
1731 void radv_device_finish_meta(struct radv_device *device);
1732
1733 struct radv_query_pool {
1734 struct radeon_winsys_bo *bo;
1735 uint32_t stride;
1736 uint32_t availability_offset;
1737 uint64_t size;
1738 char *ptr;
1739 VkQueryType type;
1740 uint32_t pipeline_stats_mask;
1741 };
1742
1743 struct radv_semaphore {
1744 /* use a winsys sem for non-exportable */
1745 struct radeon_winsys_sem *sem;
1746 uint32_t syncobj;
1747 uint32_t temp_syncobj;
1748 };
1749
1750 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1751 VkPipelineBindPoint bind_point,
1752 struct radv_descriptor_set *set,
1753 unsigned idx);
1754
1755 void
1756 radv_update_descriptor_sets(struct radv_device *device,
1757 struct radv_cmd_buffer *cmd_buffer,
1758 VkDescriptorSet overrideSet,
1759 uint32_t descriptorWriteCount,
1760 const VkWriteDescriptorSet *pDescriptorWrites,
1761 uint32_t descriptorCopyCount,
1762 const VkCopyDescriptorSet *pDescriptorCopies);
1763
1764 void
1765 radv_update_descriptor_set_with_template(struct radv_device *device,
1766 struct radv_cmd_buffer *cmd_buffer,
1767 struct radv_descriptor_set *set,
1768 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1769 const void *pData);
1770
1771 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1772 VkPipelineBindPoint pipelineBindPoint,
1773 VkPipelineLayout _layout,
1774 uint32_t set,
1775 uint32_t descriptorWriteCount,
1776 const VkWriteDescriptorSet *pDescriptorWrites);
1777
1778 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1779 struct radv_image *image, uint32_t value);
1780
1781 struct radv_fence {
1782 struct radeon_winsys_fence *fence;
1783 bool submitted;
1784 bool signalled;
1785
1786 uint32_t syncobj;
1787 uint32_t temp_syncobj;
1788 };
1789
1790 /* radv_nir_to_llvm.c */
1791 struct radv_shader_variant_info;
1792 struct radv_nir_compiler_options;
1793
1794 void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
1795 struct nir_shader *geom_shader,
1796 struct ac_shader_binary *binary,
1797 struct ac_shader_config *config,
1798 struct radv_shader_variant_info *shader_info,
1799 const struct radv_nir_compiler_options *option);
1800
1801 void radv_compile_nir_shader(LLVMTargetMachineRef tm,
1802 struct ac_shader_binary *binary,
1803 struct ac_shader_config *config,
1804 struct radv_shader_variant_info *shader_info,
1805 struct nir_shader *const *nir,
1806 int nir_count,
1807 const struct radv_nir_compiler_options *options);
1808
1809 /* radv_shader_info.h */
1810 struct radv_shader_info;
1811
1812 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1813 const struct radv_nir_compiler_options *options,
1814 struct radv_shader_info *info);
1815
1816 struct radeon_winsys_sem;
1817
1818 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1819 \
1820 static inline struct __radv_type * \
1821 __radv_type ## _from_handle(__VkType _handle) \
1822 { \
1823 return (struct __radv_type *) _handle; \
1824 } \
1825 \
1826 static inline __VkType \
1827 __radv_type ## _to_handle(struct __radv_type *_obj) \
1828 { \
1829 return (__VkType) _obj; \
1830 }
1831
1832 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1833 \
1834 static inline struct __radv_type * \
1835 __radv_type ## _from_handle(__VkType _handle) \
1836 { \
1837 return (struct __radv_type *)(uintptr_t) _handle; \
1838 } \
1839 \
1840 static inline __VkType \
1841 __radv_type ## _to_handle(struct __radv_type *_obj) \
1842 { \
1843 return (__VkType)(uintptr_t) _obj; \
1844 }
1845
1846 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1847 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1848
1849 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1850 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1851 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1852 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1853 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1854
1855 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1856 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1857 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1858 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1859 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1860 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1861 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1862 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1863 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1864 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1865 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1866 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1867 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1868 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1869 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1870 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1871 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1872 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1873 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1874 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1875 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1876
1877 #endif /* RADV_PRIVATE_H */