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radv: Implement VK_AMD_shader_info
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
59
60 #include <llvm-c/TargetMachine.h>
61
62 /* Pre-declarations needed for WSI entrypoints */
63 struct wl_surface;
64 struct wl_display;
65 typedef struct xcb_connection_t xcb_connection_t;
66 typedef uint32_t xcb_visualid_t;
67 typedef uint32_t xcb_window_t;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "radv_entrypoints.h"
74
75 #include "wsi_common.h"
76
77 #define ATI_VENDOR_ID 0x1002
78
79 #define MAX_VBS 32
80 #define MAX_VERTEX_ATTRIBS 32
81 #define MAX_RTS 8
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
90 #define MAX_VIEWS 8
91
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
93
94 enum radv_mem_heap {
95 RADV_MEM_HEAP_VRAM,
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
97 RADV_MEM_HEAP_GTT,
98 RADV_MEM_HEAP_COUNT
99 };
100
101 enum radv_mem_type {
102 RADV_MEM_TYPE_VRAM,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
105 RADV_MEM_TYPE_GTT_CACHED,
106 RADV_MEM_TYPE_COUNT
107 };
108
109 enum radv_mem_flags_bits {
110 /* enable implicit synchronization when accessing the underlying bo */
111 RADV_MEM_IMPLICIT_SYNC = 1 << 0,
112 };
113
114 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
115
116 static inline uint32_t
117 align_u32(uint32_t v, uint32_t a)
118 {
119 assert(a != 0 && a == (a & -a));
120 return (v + a - 1) & ~(a - 1);
121 }
122
123 static inline uint32_t
124 align_u32_npot(uint32_t v, uint32_t a)
125 {
126 return (v + a - 1) / a * a;
127 }
128
129 static inline uint64_t
130 align_u64(uint64_t v, uint64_t a)
131 {
132 assert(a != 0 && a == (a & -a));
133 return (v + a - 1) & ~(a - 1);
134 }
135
136 static inline int32_t
137 align_i32(int32_t v, int32_t a)
138 {
139 assert(a != 0 && a == (a & -a));
140 return (v + a - 1) & ~(a - 1);
141 }
142
143 /** Alignment must be a power of 2. */
144 static inline bool
145 radv_is_aligned(uintmax_t n, uintmax_t a)
146 {
147 assert(a == (a & -a));
148 return (n & (a - 1)) == 0;
149 }
150
151 static inline uint32_t
152 round_up_u32(uint32_t v, uint32_t a)
153 {
154 return (v + a - 1) / a;
155 }
156
157 static inline uint64_t
158 round_up_u64(uint64_t v, uint64_t a)
159 {
160 return (v + a - 1) / a;
161 }
162
163 static inline uint32_t
164 radv_minify(uint32_t n, uint32_t levels)
165 {
166 if (unlikely(n == 0))
167 return 0;
168 else
169 return MAX2(n >> levels, 1);
170 }
171 static inline float
172 radv_clamp_f(float f, float min, float max)
173 {
174 assert(min < max);
175
176 if (f > max)
177 return max;
178 else if (f < min)
179 return min;
180 else
181 return f;
182 }
183
184 static inline bool
185 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
186 {
187 if (*inout_mask & clear_mask) {
188 *inout_mask &= ~clear_mask;
189 return true;
190 } else {
191 return false;
192 }
193 }
194
195 #define for_each_bit(b, dword) \
196 for (uint32_t __dword = (dword); \
197 (b) = __builtin_ffs(__dword) - 1, __dword; \
198 __dword &= ~(1 << (b)))
199
200 #define typed_memcpy(dest, src, count) ({ \
201 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
202 memcpy((dest), (src), (count) * sizeof(*(src))); \
203 })
204
205 /* Whenever we generate an error, pass it through this function. Useful for
206 * debugging, where we can break on it. Only call at error site, not when
207 * propagating errors. Might be useful to plug in a stack trace here.
208 */
209
210 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
211
212 #ifdef DEBUG
213 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
214 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
215 #else
216 #define vk_error(error) error
217 #define vk_errorf(error, format, ...) error
218 #endif
219
220 void __radv_finishme(const char *file, int line, const char *format, ...)
221 radv_printflike(3, 4);
222 void radv_loge(const char *format, ...) radv_printflike(1, 2);
223 void radv_loge_v(const char *format, va_list va);
224
225 /**
226 * Print a FINISHME message, including its source location.
227 */
228 #define radv_finishme(format, ...) \
229 do { \
230 static bool reported = false; \
231 if (!reported) { \
232 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
233 reported = true; \
234 } \
235 } while (0)
236
237 /* A non-fatal assert. Useful for debugging. */
238 #ifdef DEBUG
239 #define radv_assert(x) ({ \
240 if (unlikely(!(x))) \
241 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
242 })
243 #else
244 #define radv_assert(x)
245 #endif
246
247 #define stub_return(v) \
248 do { \
249 radv_finishme("stub %s", __func__); \
250 return (v); \
251 } while (0)
252
253 #define stub() \
254 do { \
255 radv_finishme("stub %s", __func__); \
256 return; \
257 } while (0)
258
259 void *radv_lookup_entrypoint(const char *name);
260
261 struct radv_physical_device {
262 VK_LOADER_DATA _loader_data;
263
264 struct radv_instance * instance;
265
266 struct radeon_winsys *ws;
267 struct radeon_info rad_info;
268 char path[20];
269 const char * name;
270 uint8_t driver_uuid[VK_UUID_SIZE];
271 uint8_t device_uuid[VK_UUID_SIZE];
272 uint8_t cache_uuid[VK_UUID_SIZE];
273
274 int local_fd;
275 struct wsi_device wsi_device;
276
277 bool has_rbplus; /* if RB+ register exist */
278 bool rbplus_allowed; /* if RB+ is allowed */
279 bool has_clear_state;
280
281 /* This is the drivers on-disk cache used as a fallback as opposed to
282 * the pipeline cache defined by apps.
283 */
284 struct disk_cache * disk_cache;
285 };
286
287 struct radv_instance {
288 VK_LOADER_DATA _loader_data;
289
290 VkAllocationCallbacks alloc;
291
292 uint32_t apiVersion;
293 int physicalDeviceCount;
294 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
295
296 uint64_t debug_flags;
297 uint64_t perftest_flags;
298 };
299
300 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
301 void radv_finish_wsi(struct radv_physical_device *physical_device);
302
303 bool radv_instance_extension_supported(const char *name);
304 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
305 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
306 const char *name);
307
308 struct cache_entry;
309
310 struct radv_pipeline_cache {
311 struct radv_device * device;
312 pthread_mutex_t mutex;
313
314 uint32_t total_size;
315 uint32_t table_size;
316 uint32_t kernel_count;
317 struct cache_entry ** hash_table;
318 bool modified;
319
320 VkAllocationCallbacks alloc;
321 };
322
323 struct radv_pipeline_key {
324 uint32_t instance_rate_inputs;
325 unsigned tess_input_vertices;
326 uint32_t col_format;
327 uint32_t is_int8;
328 uint32_t is_int10;
329 uint32_t multisample : 1;
330 uint32_t has_multiview_view_index : 1;
331 };
332
333 void
334 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
335 struct radv_device *device);
336 void
337 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
338 void
339 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
340 const void *data, size_t size);
341
342 struct radv_shader_variant;
343
344 bool
345 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
346 struct radv_pipeline_cache *cache,
347 const unsigned char *sha1,
348 struct radv_shader_variant **variants);
349
350 void
351 radv_pipeline_cache_insert_shaders(struct radv_device *device,
352 struct radv_pipeline_cache *cache,
353 const unsigned char *sha1,
354 struct radv_shader_variant **variants,
355 const void *const *codes,
356 const unsigned *code_sizes);
357
358 struct radv_meta_state {
359 VkAllocationCallbacks alloc;
360
361 struct radv_pipeline_cache cache;
362
363 /**
364 * Use array element `i` for images with `2^i` samples.
365 */
366 struct {
367 VkRenderPass render_pass[NUM_META_FS_KEYS];
368 VkPipeline color_pipelines[NUM_META_FS_KEYS];
369
370 VkRenderPass depthstencil_rp;
371 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
372 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
373 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
374 } clear[1 + MAX_SAMPLES_LOG2];
375
376 VkPipelineLayout clear_color_p_layout;
377 VkPipelineLayout clear_depth_p_layout;
378 struct {
379 VkRenderPass render_pass[NUM_META_FS_KEYS];
380
381 /** Pipeline that blits from a 1D image. */
382 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
383
384 /** Pipeline that blits from a 2D image. */
385 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
386
387 /** Pipeline that blits from a 3D image. */
388 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
389
390 VkRenderPass depth_only_rp;
391 VkPipeline depth_only_1d_pipeline;
392 VkPipeline depth_only_2d_pipeline;
393 VkPipeline depth_only_3d_pipeline;
394
395 VkRenderPass stencil_only_rp;
396 VkPipeline stencil_only_1d_pipeline;
397 VkPipeline stencil_only_2d_pipeline;
398 VkPipeline stencil_only_3d_pipeline;
399 VkPipelineLayout pipeline_layout;
400 VkDescriptorSetLayout ds_layout;
401 } blit;
402
403 struct {
404 VkRenderPass render_passes[NUM_META_FS_KEYS];
405
406 VkPipelineLayout p_layouts[2];
407 VkDescriptorSetLayout ds_layouts[2];
408 VkPipeline pipelines[2][NUM_META_FS_KEYS];
409
410 VkRenderPass depth_only_rp;
411 VkPipeline depth_only_pipeline[2];
412
413 VkRenderPass stencil_only_rp;
414 VkPipeline stencil_only_pipeline[2];
415 } blit2d;
416
417 struct {
418 VkPipelineLayout img_p_layout;
419 VkDescriptorSetLayout img_ds_layout;
420 VkPipeline pipeline;
421 } itob;
422 struct {
423 VkPipelineLayout img_p_layout;
424 VkDescriptorSetLayout img_ds_layout;
425 VkPipeline pipeline;
426 } btoi;
427 struct {
428 VkPipelineLayout img_p_layout;
429 VkDescriptorSetLayout img_ds_layout;
430 VkPipeline pipeline;
431 } itoi;
432 struct {
433 VkPipelineLayout img_p_layout;
434 VkDescriptorSetLayout img_ds_layout;
435 VkPipeline pipeline;
436 } cleari;
437
438 struct {
439 VkPipeline pipeline;
440 VkRenderPass pass;
441 } resolve;
442
443 struct {
444 VkDescriptorSetLayout ds_layout;
445 VkPipelineLayout p_layout;
446 struct {
447 VkPipeline pipeline;
448 VkPipeline i_pipeline;
449 VkPipeline srgb_pipeline;
450 } rc[MAX_SAMPLES_LOG2];
451 } resolve_compute;
452
453 struct {
454 VkDescriptorSetLayout ds_layout;
455 VkPipelineLayout p_layout;
456
457 struct {
458 VkRenderPass render_pass[NUM_META_FS_KEYS];
459 VkPipeline pipeline[NUM_META_FS_KEYS];
460 } rc[MAX_SAMPLES_LOG2];
461 } resolve_fragment;
462
463 struct {
464 VkPipeline decompress_pipeline;
465 VkPipeline resummarize_pipeline;
466 VkRenderPass pass;
467 } depth_decomp[1 + MAX_SAMPLES_LOG2];
468
469 struct {
470 VkPipeline cmask_eliminate_pipeline;
471 VkPipeline fmask_decompress_pipeline;
472 VkRenderPass pass;
473 } fast_clear_flush;
474
475 struct {
476 VkPipelineLayout fill_p_layout;
477 VkPipelineLayout copy_p_layout;
478 VkDescriptorSetLayout fill_ds_layout;
479 VkDescriptorSetLayout copy_ds_layout;
480 VkPipeline fill_pipeline;
481 VkPipeline copy_pipeline;
482 } buffer;
483
484 struct {
485 VkDescriptorSetLayout ds_layout;
486 VkPipelineLayout p_layout;
487 VkPipeline occlusion_query_pipeline;
488 VkPipeline pipeline_statistics_query_pipeline;
489 } query;
490 };
491
492 /* queue types */
493 #define RADV_QUEUE_GENERAL 0
494 #define RADV_QUEUE_COMPUTE 1
495 #define RADV_QUEUE_TRANSFER 2
496
497 #define RADV_MAX_QUEUE_FAMILIES 3
498
499 enum ring_type radv_queue_family_to_ring(int f);
500
501 struct radv_queue {
502 VK_LOADER_DATA _loader_data;
503 struct radv_device * device;
504 struct radeon_winsys_ctx *hw_ctx;
505 enum radeon_ctx_priority priority;
506 int queue_family_index;
507 int queue_idx;
508
509 uint32_t scratch_size;
510 uint32_t compute_scratch_size;
511 uint32_t esgs_ring_size;
512 uint32_t gsvs_ring_size;
513 bool has_tess_rings;
514 bool has_sample_positions;
515
516 struct radeon_winsys_bo *scratch_bo;
517 struct radeon_winsys_bo *descriptor_bo;
518 struct radeon_winsys_bo *compute_scratch_bo;
519 struct radeon_winsys_bo *esgs_ring_bo;
520 struct radeon_winsys_bo *gsvs_ring_bo;
521 struct radeon_winsys_bo *tess_factor_ring_bo;
522 struct radeon_winsys_bo *tess_offchip_ring_bo;
523 struct radeon_winsys_cs *initial_preamble_cs;
524 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
525 struct radeon_winsys_cs *continue_preamble_cs;
526 };
527
528 struct radv_device {
529 VK_LOADER_DATA _loader_data;
530
531 VkAllocationCallbacks alloc;
532
533 struct radv_instance * instance;
534 struct radeon_winsys *ws;
535
536 struct radv_meta_state meta_state;
537
538 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
539 int queue_count[RADV_MAX_QUEUE_FAMILIES];
540 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
541
542 bool llvm_supports_spill;
543 bool has_distributed_tess;
544 bool dfsm_allowed;
545 uint32_t tess_offchip_block_dw_size;
546 uint32_t scratch_waves;
547
548 uint32_t gs_table_depth;
549
550 /* MSAA sample locations.
551 * The first index is the sample index.
552 * The second index is the coordinate: X, Y. */
553 float sample_locations_1x[1][2];
554 float sample_locations_2x[2][2];
555 float sample_locations_4x[4][2];
556 float sample_locations_8x[8][2];
557 float sample_locations_16x[16][2];
558
559 /* CIK and later */
560 uint32_t gfx_init_size_dw;
561 struct radeon_winsys_bo *gfx_init;
562
563 struct radeon_winsys_bo *trace_bo;
564 uint32_t *trace_id_ptr;
565
566 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
567 bool keep_shader_info;
568
569 struct radv_physical_device *physical_device;
570
571 /* Backup in-memory cache to be used if the app doesn't provide one */
572 struct radv_pipeline_cache * mem_cache;
573
574 /*
575 * use different counters so MSAA MRTs get consecutive surface indices,
576 * even if MASK is allocated in between.
577 */
578 uint32_t image_mrt_offset_counter;
579 uint32_t fmask_mrt_offset_counter;
580 struct list_head shader_slabs;
581 mtx_t shader_slab_mutex;
582
583 /* For detecting VM faults reported by dmesg. */
584 uint64_t dmesg_timestamp;
585 };
586
587 struct radv_device_memory {
588 struct radeon_winsys_bo *bo;
589 /* for dedicated allocations */
590 struct radv_image *image;
591 struct radv_buffer *buffer;
592 uint32_t type_index;
593 VkDeviceSize map_size;
594 void * map;
595 };
596
597
598 struct radv_descriptor_range {
599 uint64_t va;
600 uint32_t size;
601 };
602
603 struct radv_descriptor_set {
604 const struct radv_descriptor_set_layout *layout;
605 uint32_t size;
606
607 struct radeon_winsys_bo *bo;
608 uint64_t va;
609 uint32_t *mapped_ptr;
610 struct radv_descriptor_range *dynamic_descriptors;
611
612 struct list_head vram_list;
613
614 struct radeon_winsys_bo *descriptors[0];
615 };
616
617 struct radv_push_descriptor_set
618 {
619 struct radv_descriptor_set set;
620 uint32_t capacity;
621 };
622
623 struct radv_descriptor_pool {
624 struct radeon_winsys_bo *bo;
625 uint8_t *mapped_ptr;
626 uint64_t current_offset;
627 uint64_t size;
628
629 struct list_head vram_list;
630
631 uint8_t *host_memory_base;
632 uint8_t *host_memory_ptr;
633 uint8_t *host_memory_end;
634 };
635
636 struct radv_descriptor_update_template_entry {
637 VkDescriptorType descriptor_type;
638
639 /* The number of descriptors to update */
640 uint32_t descriptor_count;
641
642 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
643 uint32_t dst_offset;
644
645 /* In dwords. Not valid/used for dynamic descriptors */
646 uint32_t dst_stride;
647
648 uint32_t buffer_offset;
649
650 /* Only valid for combined image samplers and samplers */
651 uint16_t has_sampler;
652
653 /* In bytes */
654 size_t src_offset;
655 size_t src_stride;
656
657 /* For push descriptors */
658 const uint32_t *immutable_samplers;
659 };
660
661 struct radv_descriptor_update_template {
662 uint32_t entry_count;
663 struct radv_descriptor_update_template_entry entry[0];
664 };
665
666 struct radv_buffer {
667 struct radv_device * device;
668 VkDeviceSize size;
669
670 VkBufferUsageFlags usage;
671 VkBufferCreateFlags flags;
672
673 /* Set when bound */
674 struct radeon_winsys_bo * bo;
675 VkDeviceSize offset;
676 };
677
678
679 enum radv_cmd_dirty_bits {
680 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
681 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
682 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
683 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
684 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
685 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
686 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
687 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
688 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
689 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
690 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
691 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
692 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 11,
693 };
694 typedef uint32_t radv_cmd_dirty_mask_t;
695
696 enum radv_cmd_flush_bits {
697 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
698 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
699 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
700 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
701 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
702 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
703 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
704 /* Same as above, but only writes back and doesn't invalidate */
705 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
706 /* Framebuffer caches */
707 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
708 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
709 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
710 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
711 /* Engine synchronization. */
712 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
713 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
714 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
715 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
716
717 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
718 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
719 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
720 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
721 };
722
723 struct radv_vertex_binding {
724 struct radv_buffer * buffer;
725 VkDeviceSize offset;
726 };
727
728 struct radv_viewport_state {
729 uint32_t count;
730 VkViewport viewports[MAX_VIEWPORTS];
731 };
732
733 struct radv_scissor_state {
734 uint32_t count;
735 VkRect2D scissors[MAX_SCISSORS];
736 };
737
738 struct radv_dynamic_state {
739 /**
740 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
741 * Defines the set of saved dynamic state.
742 */
743 uint32_t mask;
744
745 struct radv_viewport_state viewport;
746
747 struct radv_scissor_state scissor;
748
749 float line_width;
750
751 struct {
752 float bias;
753 float clamp;
754 float slope;
755 } depth_bias;
756
757 float blend_constants[4];
758
759 struct {
760 float min;
761 float max;
762 } depth_bounds;
763
764 struct {
765 uint32_t front;
766 uint32_t back;
767 } stencil_compare_mask;
768
769 struct {
770 uint32_t front;
771 uint32_t back;
772 } stencil_write_mask;
773
774 struct {
775 uint32_t front;
776 uint32_t back;
777 } stencil_reference;
778 };
779
780 extern const struct radv_dynamic_state default_dynamic_state;
781
782 const char *
783 radv_get_debug_option_name(int id);
784
785 const char *
786 radv_get_perftest_option_name(int id);
787
788 /**
789 * Attachment state when recording a renderpass instance.
790 *
791 * The clear value is valid only if there exists a pending clear.
792 */
793 struct radv_attachment_state {
794 VkImageAspectFlags pending_clear_aspects;
795 uint32_t cleared_views;
796 VkClearValue clear_value;
797 VkImageLayout current_layout;
798 };
799
800 struct radv_cmd_state {
801 bool vb_dirty;
802 radv_cmd_dirty_mask_t dirty;
803 bool push_descriptors_dirty;
804 bool predicating;
805
806 struct radv_pipeline * pipeline;
807 struct radv_pipeline * emitted_pipeline;
808 struct radv_pipeline * compute_pipeline;
809 struct radv_pipeline * emitted_compute_pipeline;
810 struct radv_framebuffer * framebuffer;
811 struct radv_render_pass * pass;
812 const struct radv_subpass * subpass;
813 struct radv_dynamic_state dynamic;
814 struct radv_vertex_binding vertex_bindings[MAX_VBS];
815 struct radv_descriptor_set * descriptors[MAX_SETS];
816 struct radv_attachment_state * attachments;
817 VkRect2D render_area;
818 uint32_t index_type;
819 uint32_t max_index_count;
820 uint64_t index_va;
821 int32_t last_primitive_reset_en;
822 uint32_t last_primitive_reset_index;
823 enum radv_cmd_flush_bits flush_bits;
824 unsigned active_occlusion_queries;
825 float offset_scale;
826 uint32_t descriptors_dirty;
827 uint32_t trace_id;
828 uint32_t last_ia_multi_vgt_param;
829 };
830
831 struct radv_cmd_pool {
832 VkAllocationCallbacks alloc;
833 struct list_head cmd_buffers;
834 struct list_head free_cmd_buffers;
835 uint32_t queue_family_index;
836 };
837
838 struct radv_cmd_buffer_upload {
839 uint8_t *map;
840 unsigned offset;
841 uint64_t size;
842 struct radeon_winsys_bo *upload_bo;
843 struct list_head list;
844 };
845
846 struct radv_cmd_buffer {
847 VK_LOADER_DATA _loader_data;
848
849 struct radv_device * device;
850
851 struct radv_cmd_pool * pool;
852 struct list_head pool_link;
853
854 VkCommandBufferUsageFlags usage_flags;
855 VkCommandBufferLevel level;
856 struct radeon_winsys_cs *cs;
857 struct radv_cmd_state state;
858 uint32_t queue_family_index;
859
860 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
861 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
862 VkShaderStageFlags push_constant_stages;
863 struct radv_push_descriptor_set push_descriptors;
864 struct radv_descriptor_set meta_push_descriptors;
865
866 struct radv_cmd_buffer_upload upload;
867
868 uint32_t scratch_size_needed;
869 uint32_t compute_scratch_size_needed;
870 uint32_t esgs_ring_size_needed;
871 uint32_t gsvs_ring_size_needed;
872 bool tess_rings_needed;
873 bool sample_positions_needed;
874
875 VkResult record_result;
876
877 int ring_offsets_idx; /* just used for verification */
878 uint32_t gfx9_fence_offset;
879 struct radeon_winsys_bo *gfx9_fence_bo;
880 uint32_t gfx9_fence_idx;
881 };
882
883 struct radv_image;
884
885 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
886
887 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
888 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
889
890 void cik_create_gfx_config(struct radv_device *device);
891
892 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
893 int count, const VkViewport *viewports);
894 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
895 int count, const VkRect2D *scissors,
896 const VkViewport *viewports, bool can_use_guardband);
897 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
898 bool instanced_draw, bool indirect_draw,
899 uint32_t draw_vertex_count);
900 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
901 bool predicated,
902 enum chip_class chip_class,
903 bool is_mec,
904 unsigned event, unsigned event_flags,
905 unsigned data_sel,
906 uint64_t va,
907 uint32_t old_fence,
908 uint32_t new_fence);
909
910 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
911 bool predicated,
912 uint64_t va, uint32_t ref,
913 uint32_t mask);
914 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
915 bool predicated,
916 enum chip_class chip_class,
917 uint32_t *fence_ptr, uint64_t va,
918 bool is_mec,
919 enum radv_cmd_flush_bits flush_bits);
920 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
921 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
922 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
923 uint64_t src_va, uint64_t dest_va,
924 uint64_t size);
925 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
926 unsigned size);
927 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
928 uint64_t size, unsigned value);
929 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
930 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
931 struct radv_descriptor_set *set,
932 unsigned idx);
933 bool
934 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
935 unsigned size,
936 unsigned alignment,
937 unsigned *out_offset,
938 void **ptr);
939 void
940 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
941 const struct radv_subpass *subpass,
942 bool transitions);
943 bool
944 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
945 unsigned size, unsigned alignmnet,
946 const void *data, unsigned *out_offset);
947 void
948 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
949 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
950 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
951 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
952 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
953 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
954 unsigned radv_cayman_get_maxdist(int log_samples);
955 void radv_device_init_msaa(struct radv_device *device);
956 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
957 struct radv_image *image,
958 VkClearDepthStencilValue ds_clear_value,
959 VkImageAspectFlags aspects);
960 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
961 struct radv_image *image,
962 int idx,
963 uint32_t color_values[2]);
964 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
965 struct radv_image *image,
966 bool value);
967 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
968 struct radeon_winsys_bo *bo,
969 uint64_t offset, uint64_t size, uint32_t value);
970 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
971 bool radv_get_memory_fd(struct radv_device *device,
972 struct radv_device_memory *memory,
973 int *pFD);
974 VkResult radv_alloc_memory(VkDevice _device,
975 const VkMemoryAllocateInfo* pAllocateInfo,
976 const VkAllocationCallbacks* pAllocator,
977 enum radv_mem_flags_bits flags,
978 VkDeviceMemory* pMem);
979
980 /*
981 * Takes x,y,z as exact numbers of invocations, instead of blocks.
982 *
983 * Limitations: Can't call normal dispatch functions without binding or rebinding
984 * the compute pipeline.
985 */
986 void radv_unaligned_dispatch(
987 struct radv_cmd_buffer *cmd_buffer,
988 uint32_t x,
989 uint32_t y,
990 uint32_t z);
991
992 struct radv_event {
993 struct radeon_winsys_bo *bo;
994 uint64_t *map;
995 };
996
997 struct radv_shader_module;
998
999 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1000 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1001 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1002 void
1003 radv_hash_shaders(unsigned char *hash,
1004 const VkPipelineShaderStageCreateInfo **stages,
1005 const struct radv_pipeline_layout *layout,
1006 const struct radv_pipeline_key *key,
1007 uint32_t flags);
1008
1009 static inline gl_shader_stage
1010 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1011 {
1012 assert(__builtin_popcount(vk_stage) == 1);
1013 return ffs(vk_stage) - 1;
1014 }
1015
1016 static inline VkShaderStageFlagBits
1017 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1018 {
1019 return (1 << mesa_stage);
1020 }
1021
1022 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1023
1024 #define radv_foreach_stage(stage, stage_bits) \
1025 for (gl_shader_stage stage, \
1026 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1027 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1028 __tmp &= ~(1 << (stage)))
1029
1030 struct radv_depth_stencil_state {
1031 uint32_t db_depth_control;
1032 uint32_t db_stencil_control;
1033 uint32_t db_render_control;
1034 uint32_t db_render_override2;
1035 };
1036
1037 struct radv_blend_state {
1038 uint32_t cb_color_control;
1039 uint32_t cb_target_mask;
1040 uint32_t sx_mrt_blend_opt[8];
1041 uint32_t cb_blend_control[8];
1042
1043 uint32_t spi_shader_col_format;
1044 uint32_t cb_shader_mask;
1045 uint32_t db_alpha_to_mask;
1046 };
1047
1048 unsigned radv_format_meta_fs_key(VkFormat format);
1049
1050 struct radv_raster_state {
1051 uint32_t pa_cl_clip_cntl;
1052 uint32_t spi_interp_control;
1053 uint32_t pa_su_vtx_cntl;
1054 uint32_t pa_su_sc_mode_cntl;
1055 };
1056
1057 struct radv_multisample_state {
1058 uint32_t db_eqaa;
1059 uint32_t pa_sc_line_cntl;
1060 uint32_t pa_sc_mode_cntl_0;
1061 uint32_t pa_sc_mode_cntl_1;
1062 uint32_t pa_sc_aa_config;
1063 uint32_t pa_sc_aa_mask[2];
1064 unsigned num_samples;
1065 };
1066
1067 struct radv_prim_vertex_count {
1068 uint8_t min;
1069 uint8_t incr;
1070 };
1071
1072 struct radv_tessellation_state {
1073 uint32_t ls_hs_config;
1074 uint32_t tcs_in_layout;
1075 uint32_t tcs_out_layout;
1076 uint32_t tcs_out_offsets;
1077 uint32_t offchip_layout;
1078 unsigned num_patches;
1079 unsigned lds_size;
1080 unsigned num_tcs_input_cp;
1081 uint32_t tf_param;
1082 };
1083
1084 struct radv_gs_state {
1085 uint32_t vgt_gs_onchip_cntl;
1086 uint32_t vgt_gs_max_prims_per_subgroup;
1087 uint32_t vgt_esgs_ring_itemsize;
1088 uint32_t lds_size;
1089 };
1090
1091 struct radv_vertex_elements_info {
1092 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1093 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1094 uint32_t binding[MAX_VERTEX_ATTRIBS];
1095 uint32_t offset[MAX_VERTEX_ATTRIBS];
1096 uint32_t count;
1097 };
1098
1099 #define SI_GS_PER_ES 128
1100
1101 struct radv_pipeline {
1102 struct radv_device * device;
1103 struct radv_dynamic_state dynamic_state;
1104
1105 struct radv_pipeline_layout * layout;
1106
1107 bool needs_data_cache;
1108 bool need_indirect_descriptor_sets;
1109 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1110 struct radv_shader_variant *gs_copy_shader;
1111 VkShaderStageFlags active_stages;
1112
1113 struct radv_vertex_elements_info vertex_elements;
1114
1115 uint32_t binding_stride[MAX_VBS];
1116
1117 union {
1118 struct {
1119 struct radv_blend_state blend;
1120 struct radv_depth_stencil_state ds;
1121 struct radv_raster_state raster;
1122 struct radv_multisample_state ms;
1123 struct radv_tessellation_state tess;
1124 struct radv_gs_state gs;
1125 uint32_t db_shader_control;
1126 uint32_t shader_z_format;
1127 unsigned prim;
1128 unsigned gs_out;
1129 uint32_t vgt_gs_mode;
1130 bool vgt_primitiveid_en;
1131 bool prim_restart_enable;
1132 bool partial_es_wave;
1133 uint8_t primgroup_size;
1134 unsigned esgs_ring_size;
1135 unsigned gsvs_ring_size;
1136 uint32_t ps_input_cntl[32];
1137 uint32_t ps_input_cntl_num;
1138 uint32_t pa_cl_vs_out_cntl;
1139 uint32_t vgt_shader_stages_en;
1140 uint32_t vtx_base_sgpr;
1141 uint32_t base_ia_multi_vgt_param;
1142 bool wd_switch_on_eop;
1143 bool ia_switch_on_eoi;
1144 bool partial_vs_wave;
1145 uint8_t vtx_emit_num;
1146 uint32_t vtx_reuse_depth;
1147 struct radv_prim_vertex_count prim_vertex_count;
1148 bool can_use_guardband;
1149 } graphics;
1150 };
1151
1152 unsigned max_waves;
1153 unsigned scratch_bytes_per_wave;
1154 };
1155
1156 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1157 {
1158 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1159 }
1160
1161 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1162 {
1163 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1164 }
1165
1166 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1167 gl_shader_stage stage,
1168 int idx);
1169
1170 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1171
1172 struct radv_graphics_pipeline_create_info {
1173 bool use_rectlist;
1174 bool db_depth_clear;
1175 bool db_stencil_clear;
1176 bool db_depth_disable_expclear;
1177 bool db_stencil_disable_expclear;
1178 bool db_flush_depth_inplace;
1179 bool db_flush_stencil_inplace;
1180 bool db_resummarize;
1181 uint32_t custom_blend_mode;
1182 };
1183
1184 VkResult
1185 radv_graphics_pipeline_create(VkDevice device,
1186 VkPipelineCache cache,
1187 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1188 const struct radv_graphics_pipeline_create_info *extra,
1189 const VkAllocationCallbacks *alloc,
1190 VkPipeline *pPipeline);
1191
1192 struct vk_format_description;
1193 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1194 int first_non_void);
1195 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1196 int first_non_void);
1197 uint32_t radv_translate_colorformat(VkFormat format);
1198 uint32_t radv_translate_color_numformat(VkFormat format,
1199 const struct vk_format_description *desc,
1200 int first_non_void);
1201 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1202 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1203 uint32_t radv_translate_dbformat(VkFormat format);
1204 uint32_t radv_translate_tex_dataformat(VkFormat format,
1205 const struct vk_format_description *desc,
1206 int first_non_void);
1207 uint32_t radv_translate_tex_numformat(VkFormat format,
1208 const struct vk_format_description *desc,
1209 int first_non_void);
1210 bool radv_format_pack_clear_color(VkFormat format,
1211 uint32_t clear_vals[2],
1212 VkClearColorValue *value);
1213 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1214 bool radv_dcc_formats_compatible(VkFormat format1,
1215 VkFormat format2);
1216
1217 struct radv_fmask_info {
1218 uint64_t offset;
1219 uint64_t size;
1220 unsigned alignment;
1221 unsigned pitch_in_pixels;
1222 unsigned bank_height;
1223 unsigned slice_tile_max;
1224 unsigned tile_mode_index;
1225 unsigned tile_swizzle;
1226 };
1227
1228 struct radv_cmask_info {
1229 uint64_t offset;
1230 uint64_t size;
1231 unsigned alignment;
1232 unsigned slice_tile_max;
1233 unsigned base_address_reg;
1234 };
1235
1236 struct radv_image {
1237 VkImageType type;
1238 /* The original VkFormat provided by the client. This may not match any
1239 * of the actual surface formats.
1240 */
1241 VkFormat vk_format;
1242 VkImageAspectFlags aspects;
1243 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1244 struct ac_surf_info info;
1245 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1246 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1247
1248 VkDeviceSize size;
1249 uint32_t alignment;
1250
1251 unsigned queue_family_mask;
1252 bool exclusive;
1253 bool shareable;
1254
1255 /* Set when bound */
1256 struct radeon_winsys_bo *bo;
1257 VkDeviceSize offset;
1258 uint64_t dcc_offset;
1259 uint64_t htile_offset;
1260 bool tc_compatible_htile;
1261 struct radeon_surf surface;
1262
1263 struct radv_fmask_info fmask;
1264 struct radv_cmask_info cmask;
1265 uint64_t clear_value_offset;
1266 uint64_t dcc_pred_offset;
1267 };
1268
1269 /* Whether the image has a htile that is known consistent with the contents of
1270 * the image. */
1271 bool radv_layout_has_htile(const struct radv_image *image,
1272 VkImageLayout layout,
1273 unsigned queue_mask);
1274
1275 /* Whether the image has a htile that is known consistent with the contents of
1276 * the image and is allowed to be in compressed form.
1277 *
1278 * If this is false reads that don't use the htile should be able to return
1279 * correct results.
1280 */
1281 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1282 VkImageLayout layout,
1283 unsigned queue_mask);
1284
1285 bool radv_layout_can_fast_clear(const struct radv_image *image,
1286 VkImageLayout layout,
1287 unsigned queue_mask);
1288
1289 static inline bool
1290 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1291 {
1292 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1293 }
1294
1295 static inline bool
1296 radv_htile_enabled(const struct radv_image *image, unsigned level)
1297 {
1298 return image->surface.htile_size && level == 0;
1299 }
1300
1301 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1302
1303 static inline uint32_t
1304 radv_get_layerCount(const struct radv_image *image,
1305 const VkImageSubresourceRange *range)
1306 {
1307 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1308 image->info.array_size - range->baseArrayLayer : range->layerCount;
1309 }
1310
1311 static inline uint32_t
1312 radv_get_levelCount(const struct radv_image *image,
1313 const VkImageSubresourceRange *range)
1314 {
1315 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1316 image->info.levels - range->baseMipLevel : range->levelCount;
1317 }
1318
1319 struct radeon_bo_metadata;
1320 void
1321 radv_init_metadata(struct radv_device *device,
1322 struct radv_image *image,
1323 struct radeon_bo_metadata *metadata);
1324
1325 struct radv_image_view {
1326 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1327 struct radeon_winsys_bo *bo;
1328
1329 VkImageViewType type;
1330 VkImageAspectFlags aspect_mask;
1331 VkFormat vk_format;
1332 uint32_t base_layer;
1333 uint32_t layer_count;
1334 uint32_t base_mip;
1335 uint32_t level_count;
1336 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1337
1338 uint32_t descriptor[8];
1339 uint32_t fmask_descriptor[8];
1340
1341 /* Descriptor for use as a storage image as opposed to a sampled image.
1342 * This has a few differences for cube maps (e.g. type).
1343 */
1344 uint32_t storage_descriptor[8];
1345 uint32_t storage_fmask_descriptor[8];
1346 };
1347
1348 struct radv_image_create_info {
1349 const VkImageCreateInfo *vk_info;
1350 bool scanout;
1351 };
1352
1353 VkResult radv_image_create(VkDevice _device,
1354 const struct radv_image_create_info *info,
1355 const VkAllocationCallbacks* alloc,
1356 VkImage *pImage);
1357
1358 void radv_image_view_init(struct radv_image_view *view,
1359 struct radv_device *device,
1360 const VkImageViewCreateInfo* pCreateInfo);
1361
1362 struct radv_buffer_view {
1363 struct radeon_winsys_bo *bo;
1364 VkFormat vk_format;
1365 uint64_t range; /**< VkBufferViewCreateInfo::range */
1366 uint32_t state[4];
1367 };
1368 void radv_buffer_view_init(struct radv_buffer_view *view,
1369 struct radv_device *device,
1370 const VkBufferViewCreateInfo* pCreateInfo);
1371
1372 static inline struct VkExtent3D
1373 radv_sanitize_image_extent(const VkImageType imageType,
1374 const struct VkExtent3D imageExtent)
1375 {
1376 switch (imageType) {
1377 case VK_IMAGE_TYPE_1D:
1378 return (VkExtent3D) { imageExtent.width, 1, 1 };
1379 case VK_IMAGE_TYPE_2D:
1380 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1381 case VK_IMAGE_TYPE_3D:
1382 return imageExtent;
1383 default:
1384 unreachable("invalid image type");
1385 }
1386 }
1387
1388 static inline struct VkOffset3D
1389 radv_sanitize_image_offset(const VkImageType imageType,
1390 const struct VkOffset3D imageOffset)
1391 {
1392 switch (imageType) {
1393 case VK_IMAGE_TYPE_1D:
1394 return (VkOffset3D) { imageOffset.x, 0, 0 };
1395 case VK_IMAGE_TYPE_2D:
1396 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1397 case VK_IMAGE_TYPE_3D:
1398 return imageOffset;
1399 default:
1400 unreachable("invalid image type");
1401 }
1402 }
1403
1404 static inline bool
1405 radv_image_extent_compare(const struct radv_image *image,
1406 const VkExtent3D *extent)
1407 {
1408 if (extent->width != image->info.width ||
1409 extent->height != image->info.height ||
1410 extent->depth != image->info.depth)
1411 return false;
1412 return true;
1413 }
1414
1415 struct radv_sampler {
1416 uint32_t state[4];
1417 };
1418
1419 struct radv_color_buffer_info {
1420 uint64_t cb_color_base;
1421 uint64_t cb_color_cmask;
1422 uint64_t cb_color_fmask;
1423 uint64_t cb_dcc_base;
1424 uint32_t cb_color_pitch;
1425 uint32_t cb_color_slice;
1426 uint32_t cb_color_view;
1427 uint32_t cb_color_info;
1428 uint32_t cb_color_attrib;
1429 uint32_t cb_color_attrib2;
1430 uint32_t cb_dcc_control;
1431 uint32_t cb_color_cmask_slice;
1432 uint32_t cb_color_fmask_slice;
1433 uint32_t cb_clear_value0;
1434 uint32_t cb_clear_value1;
1435 uint32_t micro_tile_mode;
1436 uint32_t gfx9_epitch;
1437 };
1438
1439 struct radv_ds_buffer_info {
1440 uint64_t db_z_read_base;
1441 uint64_t db_stencil_read_base;
1442 uint64_t db_z_write_base;
1443 uint64_t db_stencil_write_base;
1444 uint64_t db_htile_data_base;
1445 uint32_t db_depth_info;
1446 uint32_t db_z_info;
1447 uint32_t db_stencil_info;
1448 uint32_t db_depth_view;
1449 uint32_t db_depth_size;
1450 uint32_t db_depth_slice;
1451 uint32_t db_htile_surface;
1452 uint32_t pa_su_poly_offset_db_fmt_cntl;
1453 uint32_t db_z_info2;
1454 uint32_t db_stencil_info2;
1455 float offset_scale;
1456 };
1457
1458 struct radv_attachment_info {
1459 union {
1460 struct radv_color_buffer_info cb;
1461 struct radv_ds_buffer_info ds;
1462 };
1463 struct radv_image_view *attachment;
1464 };
1465
1466 struct radv_framebuffer {
1467 uint32_t width;
1468 uint32_t height;
1469 uint32_t layers;
1470
1471 uint32_t attachment_count;
1472 struct radv_attachment_info attachments[0];
1473 };
1474
1475 struct radv_subpass_barrier {
1476 VkPipelineStageFlags src_stage_mask;
1477 VkAccessFlags src_access_mask;
1478 VkAccessFlags dst_access_mask;
1479 };
1480
1481 struct radv_subpass {
1482 uint32_t input_count;
1483 uint32_t color_count;
1484 VkAttachmentReference * input_attachments;
1485 VkAttachmentReference * color_attachments;
1486 VkAttachmentReference * resolve_attachments;
1487 VkAttachmentReference depth_stencil_attachment;
1488
1489 /** Subpass has at least one resolve attachment */
1490 bool has_resolve;
1491
1492 struct radv_subpass_barrier start_barrier;
1493
1494 uint32_t view_mask;
1495 };
1496
1497 struct radv_render_pass_attachment {
1498 VkFormat format;
1499 uint32_t samples;
1500 VkAttachmentLoadOp load_op;
1501 VkAttachmentLoadOp stencil_load_op;
1502 VkImageLayout initial_layout;
1503 VkImageLayout final_layout;
1504 uint32_t view_mask;
1505 };
1506
1507 struct radv_render_pass {
1508 uint32_t attachment_count;
1509 uint32_t subpass_count;
1510 VkAttachmentReference * subpass_attachments;
1511 struct radv_render_pass_attachment * attachments;
1512 struct radv_subpass_barrier end_barrier;
1513 struct radv_subpass subpasses[0];
1514 };
1515
1516 VkResult radv_device_init_meta(struct radv_device *device);
1517 void radv_device_finish_meta(struct radv_device *device);
1518
1519 struct radv_query_pool {
1520 struct radeon_winsys_bo *bo;
1521 uint32_t stride;
1522 uint32_t availability_offset;
1523 char *ptr;
1524 VkQueryType type;
1525 uint32_t pipeline_stats_mask;
1526 };
1527
1528 struct radv_semaphore {
1529 /* use a winsys sem for non-exportable */
1530 struct radeon_winsys_sem *sem;
1531 uint32_t syncobj;
1532 uint32_t temp_syncobj;
1533 };
1534
1535 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1536 int num_wait_sems,
1537 const VkSemaphore *wait_sems,
1538 int num_signal_sems,
1539 const VkSemaphore *signal_sems);
1540 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1541
1542 void
1543 radv_update_descriptor_sets(struct radv_device *device,
1544 struct radv_cmd_buffer *cmd_buffer,
1545 VkDescriptorSet overrideSet,
1546 uint32_t descriptorWriteCount,
1547 const VkWriteDescriptorSet *pDescriptorWrites,
1548 uint32_t descriptorCopyCount,
1549 const VkCopyDescriptorSet *pDescriptorCopies);
1550
1551 void
1552 radv_update_descriptor_set_with_template(struct radv_device *device,
1553 struct radv_cmd_buffer *cmd_buffer,
1554 struct radv_descriptor_set *set,
1555 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1556 const void *pData);
1557
1558 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1559 VkPipelineBindPoint pipelineBindPoint,
1560 VkPipelineLayout _layout,
1561 uint32_t set,
1562 uint32_t descriptorWriteCount,
1563 const VkWriteDescriptorSet *pDescriptorWrites);
1564
1565 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1566 struct radv_image *image, uint32_t value);
1567 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1568 struct radv_image *image, uint32_t value);
1569
1570 struct radv_fence {
1571 struct radeon_winsys_fence *fence;
1572 bool submitted;
1573 bool signalled;
1574 };
1575
1576 struct radeon_winsys_sem;
1577
1578 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1579 \
1580 static inline struct __radv_type * \
1581 __radv_type ## _from_handle(__VkType _handle) \
1582 { \
1583 return (struct __radv_type *) _handle; \
1584 } \
1585 \
1586 static inline __VkType \
1587 __radv_type ## _to_handle(struct __radv_type *_obj) \
1588 { \
1589 return (__VkType) _obj; \
1590 }
1591
1592 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1593 \
1594 static inline struct __radv_type * \
1595 __radv_type ## _from_handle(__VkType _handle) \
1596 { \
1597 return (struct __radv_type *)(uintptr_t) _handle; \
1598 } \
1599 \
1600 static inline __VkType \
1601 __radv_type ## _to_handle(struct __radv_type *_obj) \
1602 { \
1603 return (__VkType)(uintptr_t) _obj; \
1604 }
1605
1606 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1607 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1608
1609 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1610 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1611 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1612 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1613 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1614
1615 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1616 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1617 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1618 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1619 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1620 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1621 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1622 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1623 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1624 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1625 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1626 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1627 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1628 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1629 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1630 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1631 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1632 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1633 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1634 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1635 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1636
1637 #endif /* RADV_PRIVATE_H */