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radv: Split out cliprect rule generation.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52 #include "vk_debug_report.h"
53
54 #include "radv_radeon_winsys.h"
55 #include "ac_binary.h"
56 #include "ac_nir_to_llvm.h"
57 #include "ac_gpu_info.h"
58 #include "ac_surface.h"
59 #include "radv_descriptor_set.h"
60
61 #include <llvm-c/TargetMachine.h>
62
63 /* Pre-declarations needed for WSI entrypoints */
64 struct wl_surface;
65 struct wl_display;
66 typedef struct xcb_connection_t xcb_connection_t;
67 typedef uint32_t xcb_visualid_t;
68 typedef uint32_t xcb_window_t;
69
70 #include <vulkan/vulkan.h>
71 #include <vulkan/vulkan_intel.h>
72 #include <vulkan/vk_icd.h>
73 #include <vulkan/vk_android_native_buffer.h>
74
75 #include "radv_entrypoints.h"
76
77 #include "wsi_common.h"
78
79 #define ATI_VENDOR_ID 0x1002
80
81 #define MAX_VBS 32
82 #define MAX_VERTEX_ATTRIBS 32
83 #define MAX_RTS 8
84 #define MAX_VIEWPORTS 16
85 #define MAX_SCISSORS 16
86 #define MAX_DISCARD_RECTANGLES 4
87 #define MAX_PUSH_CONSTANTS_SIZE 128
88 #define MAX_PUSH_DESCRIPTORS 32
89 #define MAX_DYNAMIC_BUFFERS 16
90 #define MAX_SAMPLES_LOG2 4
91 #define NUM_META_FS_KEYS 13
92 #define RADV_MAX_DRM_DEVICES 8
93 #define MAX_VIEWS 8
94
95 #define NUM_DEPTH_CLEAR_PIPELINES 3
96
97 enum radv_mem_heap {
98 RADV_MEM_HEAP_VRAM,
99 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
100 RADV_MEM_HEAP_GTT,
101 RADV_MEM_HEAP_COUNT
102 };
103
104 enum radv_mem_type {
105 RADV_MEM_TYPE_VRAM,
106 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
107 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
108 RADV_MEM_TYPE_GTT_CACHED,
109 RADV_MEM_TYPE_COUNT
110 };
111
112 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
113
114 static inline uint32_t
115 align_u32(uint32_t v, uint32_t a)
116 {
117 assert(a != 0 && a == (a & -a));
118 return (v + a - 1) & ~(a - 1);
119 }
120
121 static inline uint32_t
122 align_u32_npot(uint32_t v, uint32_t a)
123 {
124 return (v + a - 1) / a * a;
125 }
126
127 static inline uint64_t
128 align_u64(uint64_t v, uint64_t a)
129 {
130 assert(a != 0 && a == (a & -a));
131 return (v + a - 1) & ~(a - 1);
132 }
133
134 static inline int32_t
135 align_i32(int32_t v, int32_t a)
136 {
137 assert(a != 0 && a == (a & -a));
138 return (v + a - 1) & ~(a - 1);
139 }
140
141 /** Alignment must be a power of 2. */
142 static inline bool
143 radv_is_aligned(uintmax_t n, uintmax_t a)
144 {
145 assert(a == (a & -a));
146 return (n & (a - 1)) == 0;
147 }
148
149 static inline uint32_t
150 round_up_u32(uint32_t v, uint32_t a)
151 {
152 return (v + a - 1) / a;
153 }
154
155 static inline uint64_t
156 round_up_u64(uint64_t v, uint64_t a)
157 {
158 return (v + a - 1) / a;
159 }
160
161 static inline uint32_t
162 radv_minify(uint32_t n, uint32_t levels)
163 {
164 if (unlikely(n == 0))
165 return 0;
166 else
167 return MAX2(n >> levels, 1);
168 }
169 static inline float
170 radv_clamp_f(float f, float min, float max)
171 {
172 assert(min < max);
173
174 if (f > max)
175 return max;
176 else if (f < min)
177 return min;
178 else
179 return f;
180 }
181
182 static inline bool
183 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
184 {
185 if (*inout_mask & clear_mask) {
186 *inout_mask &= ~clear_mask;
187 return true;
188 } else {
189 return false;
190 }
191 }
192
193 #define for_each_bit(b, dword) \
194 for (uint32_t __dword = (dword); \
195 (b) = __builtin_ffs(__dword) - 1, __dword; \
196 __dword &= ~(1 << (b)))
197
198 #define typed_memcpy(dest, src, count) ({ \
199 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
200 memcpy((dest), (src), (count) * sizeof(*(src))); \
201 })
202
203 /* Whenever we generate an error, pass it through this function. Useful for
204 * debugging, where we can break on it. Only call at error site, not when
205 * propagating errors. Might be useful to plug in a stack trace here.
206 */
207
208 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
209
210 #ifdef DEBUG
211 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
212 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
213 #else
214 #define vk_error(error) error
215 #define vk_errorf(error, format, ...) error
216 #endif
217
218 void __radv_finishme(const char *file, int line, const char *format, ...)
219 radv_printflike(3, 4);
220 void radv_loge(const char *format, ...) radv_printflike(1, 2);
221 void radv_loge_v(const char *format, va_list va);
222
223 /**
224 * Print a FINISHME message, including its source location.
225 */
226 #define radv_finishme(format, ...) \
227 do { \
228 static bool reported = false; \
229 if (!reported) { \
230 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
231 reported = true; \
232 } \
233 } while (0)
234
235 /* A non-fatal assert. Useful for debugging. */
236 #ifdef DEBUG
237 #define radv_assert(x) ({ \
238 if (unlikely(!(x))) \
239 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
240 })
241 #else
242 #define radv_assert(x)
243 #endif
244
245 #define stub_return(v) \
246 do { \
247 radv_finishme("stub %s", __func__); \
248 return (v); \
249 } while (0)
250
251 #define stub() \
252 do { \
253 radv_finishme("stub %s", __func__); \
254 return; \
255 } while (0)
256
257 void *radv_lookup_entrypoint(const char *name);
258
259 struct radv_physical_device {
260 VK_LOADER_DATA _loader_data;
261
262 struct radv_instance * instance;
263
264 struct radeon_winsys *ws;
265 struct radeon_info rad_info;
266 char path[20];
267 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
268 uint8_t driver_uuid[VK_UUID_SIZE];
269 uint8_t device_uuid[VK_UUID_SIZE];
270 uint8_t cache_uuid[VK_UUID_SIZE];
271
272 int local_fd;
273 struct wsi_device wsi_device;
274
275 bool has_rbplus; /* if RB+ register exist */
276 bool rbplus_allowed; /* if RB+ is allowed */
277 bool has_clear_state;
278 bool cpdma_prefetch_writes_memory;
279 bool has_scissor_bug;
280
281 /* This is the drivers on-disk cache used as a fallback as opposed to
282 * the pipeline cache defined by apps.
283 */
284 struct disk_cache * disk_cache;
285
286 VkPhysicalDeviceMemoryProperties memory_properties;
287 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
288 };
289
290 struct radv_instance {
291 VK_LOADER_DATA _loader_data;
292
293 VkAllocationCallbacks alloc;
294
295 uint32_t apiVersion;
296 int physicalDeviceCount;
297 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
298
299 uint64_t debug_flags;
300 uint64_t perftest_flags;
301
302 struct vk_debug_report_instance debug_report_callbacks;
303 };
304
305 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
306 void radv_finish_wsi(struct radv_physical_device *physical_device);
307
308 bool radv_instance_extension_supported(const char *name);
309 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
310 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
311 const char *name);
312
313 struct cache_entry;
314
315 struct radv_pipeline_cache {
316 struct radv_device * device;
317 pthread_mutex_t mutex;
318
319 uint32_t total_size;
320 uint32_t table_size;
321 uint32_t kernel_count;
322 struct cache_entry ** hash_table;
323 bool modified;
324
325 VkAllocationCallbacks alloc;
326 };
327
328 struct radv_pipeline_key {
329 uint32_t instance_rate_inputs;
330 unsigned tess_input_vertices;
331 uint32_t col_format;
332 uint32_t is_int8;
333 uint32_t is_int10;
334 uint8_t log2_ps_iter_samples;
335 uint8_t log2_num_samples;
336 uint32_t multisample : 1;
337 uint32_t has_multiview_view_index : 1;
338 };
339
340 void
341 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
342 struct radv_device *device);
343 void
344 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
345 void
346 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
347 const void *data, size_t size);
348
349 struct radv_shader_variant;
350
351 bool
352 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
353 struct radv_pipeline_cache *cache,
354 const unsigned char *sha1,
355 struct radv_shader_variant **variants);
356
357 void
358 radv_pipeline_cache_insert_shaders(struct radv_device *device,
359 struct radv_pipeline_cache *cache,
360 const unsigned char *sha1,
361 struct radv_shader_variant **variants,
362 const void *const *codes,
363 const unsigned *code_sizes);
364
365 enum radv_blit_ds_layout {
366 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
367 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
368 RADV_BLIT_DS_LAYOUT_COUNT,
369 };
370
371 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
372 {
373 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
374 }
375
376 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
377 {
378 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
379 }
380
381 enum radv_meta_dst_layout {
382 RADV_META_DST_LAYOUT_GENERAL,
383 RADV_META_DST_LAYOUT_OPTIMAL,
384 RADV_META_DST_LAYOUT_COUNT,
385 };
386
387 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
388 {
389 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
390 }
391
392 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
393 {
394 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
395 }
396
397 struct radv_meta_state {
398 VkAllocationCallbacks alloc;
399
400 struct radv_pipeline_cache cache;
401
402 /**
403 * Use array element `i` for images with `2^i` samples.
404 */
405 struct {
406 VkRenderPass render_pass[NUM_META_FS_KEYS];
407 VkPipeline color_pipelines[NUM_META_FS_KEYS];
408
409 VkRenderPass depthstencil_rp;
410 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
411 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
412 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
413 } clear[1 + MAX_SAMPLES_LOG2];
414
415 VkPipelineLayout clear_color_p_layout;
416 VkPipelineLayout clear_depth_p_layout;
417 struct {
418 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
419
420 /** Pipeline that blits from a 1D image. */
421 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
422
423 /** Pipeline that blits from a 2D image. */
424 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
425
426 /** Pipeline that blits from a 3D image. */
427 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
428
429 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
430 VkPipeline depth_only_1d_pipeline;
431 VkPipeline depth_only_2d_pipeline;
432 VkPipeline depth_only_3d_pipeline;
433
434 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
435 VkPipeline stencil_only_1d_pipeline;
436 VkPipeline stencil_only_2d_pipeline;
437 VkPipeline stencil_only_3d_pipeline;
438 VkPipelineLayout pipeline_layout;
439 VkDescriptorSetLayout ds_layout;
440 } blit;
441
442 struct {
443 VkRenderPass render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
444
445 VkPipelineLayout p_layouts[3];
446 VkDescriptorSetLayout ds_layouts[3];
447 VkPipeline pipelines[3][NUM_META_FS_KEYS];
448
449 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
450 VkPipeline depth_only_pipeline[3];
451
452 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
453 VkPipeline stencil_only_pipeline[3];
454 } blit2d;
455
456 struct {
457 VkPipelineLayout img_p_layout;
458 VkDescriptorSetLayout img_ds_layout;
459 VkPipeline pipeline;
460 VkPipeline pipeline_3d;
461 } itob;
462 struct {
463 VkPipelineLayout img_p_layout;
464 VkDescriptorSetLayout img_ds_layout;
465 VkPipeline pipeline;
466 VkPipeline pipeline_3d;
467 } btoi;
468 struct {
469 VkPipelineLayout img_p_layout;
470 VkDescriptorSetLayout img_ds_layout;
471 VkPipeline pipeline;
472 VkPipeline pipeline_3d;
473 } itoi;
474 struct {
475 VkPipelineLayout img_p_layout;
476 VkDescriptorSetLayout img_ds_layout;
477 VkPipeline pipeline;
478 VkPipeline pipeline_3d;
479 } cleari;
480
481 struct {
482 VkPipelineLayout p_layout;
483 VkPipeline pipeline[NUM_META_FS_KEYS];
484 VkRenderPass pass[NUM_META_FS_KEYS];
485 } resolve;
486
487 struct {
488 VkDescriptorSetLayout ds_layout;
489 VkPipelineLayout p_layout;
490 struct {
491 VkPipeline pipeline;
492 VkPipeline i_pipeline;
493 VkPipeline srgb_pipeline;
494 } rc[MAX_SAMPLES_LOG2];
495 } resolve_compute;
496
497 struct {
498 VkDescriptorSetLayout ds_layout;
499 VkPipelineLayout p_layout;
500
501 struct {
502 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
503 VkPipeline pipeline[NUM_META_FS_KEYS];
504 } rc[MAX_SAMPLES_LOG2];
505 } resolve_fragment;
506
507 struct {
508 VkPipelineLayout p_layout;
509 VkPipeline decompress_pipeline;
510 VkPipeline resummarize_pipeline;
511 VkRenderPass pass;
512 } depth_decomp[1 + MAX_SAMPLES_LOG2];
513
514 struct {
515 VkPipelineLayout p_layout;
516 VkPipeline cmask_eliminate_pipeline;
517 VkPipeline fmask_decompress_pipeline;
518 VkPipeline dcc_decompress_pipeline;
519 VkRenderPass pass;
520
521 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
522 VkPipelineLayout dcc_decompress_compute_p_layout;
523 VkPipeline dcc_decompress_compute_pipeline;
524 } fast_clear_flush;
525
526 struct {
527 VkPipelineLayout fill_p_layout;
528 VkPipelineLayout copy_p_layout;
529 VkDescriptorSetLayout fill_ds_layout;
530 VkDescriptorSetLayout copy_ds_layout;
531 VkPipeline fill_pipeline;
532 VkPipeline copy_pipeline;
533 } buffer;
534
535 struct {
536 VkDescriptorSetLayout ds_layout;
537 VkPipelineLayout p_layout;
538 VkPipeline occlusion_query_pipeline;
539 VkPipeline pipeline_statistics_query_pipeline;
540 } query;
541 };
542
543 /* queue types */
544 #define RADV_QUEUE_GENERAL 0
545 #define RADV_QUEUE_COMPUTE 1
546 #define RADV_QUEUE_TRANSFER 2
547
548 #define RADV_MAX_QUEUE_FAMILIES 3
549
550 enum ring_type radv_queue_family_to_ring(int f);
551
552 struct radv_queue {
553 VK_LOADER_DATA _loader_data;
554 struct radv_device * device;
555 struct radeon_winsys_ctx *hw_ctx;
556 enum radeon_ctx_priority priority;
557 uint32_t queue_family_index;
558 int queue_idx;
559
560 uint32_t scratch_size;
561 uint32_t compute_scratch_size;
562 uint32_t esgs_ring_size;
563 uint32_t gsvs_ring_size;
564 bool has_tess_rings;
565 bool has_sample_positions;
566
567 struct radeon_winsys_bo *scratch_bo;
568 struct radeon_winsys_bo *descriptor_bo;
569 struct radeon_winsys_bo *compute_scratch_bo;
570 struct radeon_winsys_bo *esgs_ring_bo;
571 struct radeon_winsys_bo *gsvs_ring_bo;
572 struct radeon_winsys_bo *tess_factor_ring_bo;
573 struct radeon_winsys_bo *tess_offchip_ring_bo;
574 struct radeon_winsys_cs *initial_preamble_cs;
575 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
576 struct radeon_winsys_cs *continue_preamble_cs;
577 };
578
579 struct radv_device {
580 VK_LOADER_DATA _loader_data;
581
582 VkAllocationCallbacks alloc;
583
584 struct radv_instance * instance;
585 struct radeon_winsys *ws;
586
587 struct radv_meta_state meta_state;
588
589 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
590 int queue_count[RADV_MAX_QUEUE_FAMILIES];
591 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
592
593 bool always_use_syncobj;
594 bool llvm_supports_spill;
595 bool has_distributed_tess;
596 bool pbb_allowed;
597 bool dfsm_allowed;
598 uint32_t tess_offchip_block_dw_size;
599 uint32_t scratch_waves;
600 uint32_t dispatch_initiator;
601
602 uint32_t gs_table_depth;
603
604 /* MSAA sample locations.
605 * The first index is the sample index.
606 * The second index is the coordinate: X, Y. */
607 float sample_locations_1x[1][2];
608 float sample_locations_2x[2][2];
609 float sample_locations_4x[4][2];
610 float sample_locations_8x[8][2];
611 float sample_locations_16x[16][2];
612
613 /* CIK and later */
614 uint32_t gfx_init_size_dw;
615 struct radeon_winsys_bo *gfx_init;
616
617 struct radeon_winsys_bo *trace_bo;
618 uint32_t *trace_id_ptr;
619
620 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
621 bool keep_shader_info;
622
623 struct radv_physical_device *physical_device;
624
625 /* Backup in-memory cache to be used if the app doesn't provide one */
626 struct radv_pipeline_cache * mem_cache;
627
628 /*
629 * use different counters so MSAA MRTs get consecutive surface indices,
630 * even if MASK is allocated in between.
631 */
632 uint32_t image_mrt_offset_counter;
633 uint32_t fmask_mrt_offset_counter;
634 struct list_head shader_slabs;
635 mtx_t shader_slab_mutex;
636
637 /* For detecting VM faults reported by dmesg. */
638 uint64_t dmesg_timestamp;
639 };
640
641 struct radv_device_memory {
642 struct radeon_winsys_bo *bo;
643 /* for dedicated allocations */
644 struct radv_image *image;
645 struct radv_buffer *buffer;
646 uint32_t type_index;
647 VkDeviceSize map_size;
648 void * map;
649 };
650
651
652 struct radv_descriptor_range {
653 uint64_t va;
654 uint32_t size;
655 };
656
657 struct radv_descriptor_set {
658 const struct radv_descriptor_set_layout *layout;
659 uint32_t size;
660
661 struct radeon_winsys_bo *bo;
662 uint64_t va;
663 uint32_t *mapped_ptr;
664 struct radv_descriptor_range *dynamic_descriptors;
665
666 struct radeon_winsys_bo *descriptors[0];
667 };
668
669 struct radv_push_descriptor_set
670 {
671 struct radv_descriptor_set set;
672 uint32_t capacity;
673 };
674
675 struct radv_descriptor_pool_entry {
676 uint32_t offset;
677 uint32_t size;
678 struct radv_descriptor_set *set;
679 };
680
681 struct radv_descriptor_pool {
682 struct radeon_winsys_bo *bo;
683 uint8_t *mapped_ptr;
684 uint64_t current_offset;
685 uint64_t size;
686
687 uint8_t *host_memory_base;
688 uint8_t *host_memory_ptr;
689 uint8_t *host_memory_end;
690
691 uint32_t entry_count;
692 uint32_t max_entry_count;
693 struct radv_descriptor_pool_entry entries[0];
694 };
695
696 struct radv_descriptor_update_template_entry {
697 VkDescriptorType descriptor_type;
698
699 /* The number of descriptors to update */
700 uint32_t descriptor_count;
701
702 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
703 uint32_t dst_offset;
704
705 /* In dwords. Not valid/used for dynamic descriptors */
706 uint32_t dst_stride;
707
708 uint32_t buffer_offset;
709
710 /* Only valid for combined image samplers and samplers */
711 uint16_t has_sampler;
712
713 /* In bytes */
714 size_t src_offset;
715 size_t src_stride;
716
717 /* For push descriptors */
718 const uint32_t *immutable_samplers;
719 };
720
721 struct radv_descriptor_update_template {
722 uint32_t entry_count;
723 struct radv_descriptor_update_template_entry entry[0];
724 };
725
726 struct radv_buffer {
727 struct radv_device * device;
728 VkDeviceSize size;
729
730 VkBufferUsageFlags usage;
731 VkBufferCreateFlags flags;
732
733 /* Set when bound */
734 struct radeon_winsys_bo * bo;
735 VkDeviceSize offset;
736
737 bool shareable;
738 };
739
740 enum radv_dynamic_state_bits {
741 RADV_DYNAMIC_VIEWPORT = 1 << 0,
742 RADV_DYNAMIC_SCISSOR = 1 << 1,
743 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
744 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
745 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
746 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
747 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
748 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
749 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
750 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
751 RADV_DYNAMIC_ALL = (1 << 10) - 1,
752 };
753
754 enum radv_cmd_dirty_bits {
755 /* Keep the dynamic state dirty bits in sync with
756 * enum radv_dynamic_state_bits */
757 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
758 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
759 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
760 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
761 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
762 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
763 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
764 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
765 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
766 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
767 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
768 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
769 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
770 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
771 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
772 };
773
774 enum radv_cmd_flush_bits {
775 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
776 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
777 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
778 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
779 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
780 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
781 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
782 /* Same as above, but only writes back and doesn't invalidate */
783 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
784 /* Framebuffer caches */
785 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
786 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
787 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
788 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
789 /* Engine synchronization. */
790 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
791 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
792 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
793 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
794
795 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
796 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
797 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
798 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
799 };
800
801 struct radv_vertex_binding {
802 struct radv_buffer * buffer;
803 VkDeviceSize offset;
804 };
805
806 struct radv_viewport_state {
807 uint32_t count;
808 VkViewport viewports[MAX_VIEWPORTS];
809 };
810
811 struct radv_scissor_state {
812 uint32_t count;
813 VkRect2D scissors[MAX_SCISSORS];
814 };
815
816 struct radv_discard_rectangle_state {
817 uint32_t count;
818 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
819 };
820
821 struct radv_dynamic_state {
822 /**
823 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
824 * Defines the set of saved dynamic state.
825 */
826 uint32_t mask;
827
828 struct radv_viewport_state viewport;
829
830 struct radv_scissor_state scissor;
831
832 float line_width;
833
834 struct {
835 float bias;
836 float clamp;
837 float slope;
838 } depth_bias;
839
840 float blend_constants[4];
841
842 struct {
843 float min;
844 float max;
845 } depth_bounds;
846
847 struct {
848 uint32_t front;
849 uint32_t back;
850 } stencil_compare_mask;
851
852 struct {
853 uint32_t front;
854 uint32_t back;
855 } stencil_write_mask;
856
857 struct {
858 uint32_t front;
859 uint32_t back;
860 } stencil_reference;
861
862 struct radv_discard_rectangle_state discard_rectangle;
863 };
864
865 extern const struct radv_dynamic_state default_dynamic_state;
866
867 const char *
868 radv_get_debug_option_name(int id);
869
870 const char *
871 radv_get_perftest_option_name(int id);
872
873 /**
874 * Attachment state when recording a renderpass instance.
875 *
876 * The clear value is valid only if there exists a pending clear.
877 */
878 struct radv_attachment_state {
879 VkImageAspectFlags pending_clear_aspects;
880 uint32_t cleared_views;
881 VkClearValue clear_value;
882 VkImageLayout current_layout;
883 };
884
885 struct radv_cmd_state {
886 /* Vertex descriptors */
887 bool vb_prefetch_dirty;
888 uint64_t vb_va;
889 unsigned vb_size;
890
891 bool push_descriptors_dirty;
892 bool predicating;
893 uint32_t dirty;
894
895 struct radv_pipeline * pipeline;
896 struct radv_pipeline * emitted_pipeline;
897 struct radv_pipeline * compute_pipeline;
898 struct radv_pipeline * emitted_compute_pipeline;
899 struct radv_framebuffer * framebuffer;
900 struct radv_render_pass * pass;
901 const struct radv_subpass * subpass;
902 struct radv_dynamic_state dynamic;
903 struct radv_attachment_state * attachments;
904 VkRect2D render_area;
905
906 /* Index buffer */
907 struct radv_buffer *index_buffer;
908 uint64_t index_offset;
909 uint32_t index_type;
910 uint32_t max_index_count;
911 uint64_t index_va;
912 int32_t last_index_type;
913
914 int32_t last_primitive_reset_en;
915 uint32_t last_primitive_reset_index;
916 enum radv_cmd_flush_bits flush_bits;
917 unsigned active_occlusion_queries;
918 float offset_scale;
919 uint32_t descriptors_dirty;
920 uint32_t valid_descriptors;
921 uint32_t trace_id;
922 uint32_t last_ia_multi_vgt_param;
923
924 uint32_t last_num_instances;
925 uint32_t last_first_instance;
926 uint32_t last_vertex_offset;
927 };
928
929 struct radv_cmd_pool {
930 VkAllocationCallbacks alloc;
931 struct list_head cmd_buffers;
932 struct list_head free_cmd_buffers;
933 uint32_t queue_family_index;
934 };
935
936 struct radv_cmd_buffer_upload {
937 uint8_t *map;
938 unsigned offset;
939 uint64_t size;
940 struct radeon_winsys_bo *upload_bo;
941 struct list_head list;
942 };
943
944 enum radv_cmd_buffer_status {
945 RADV_CMD_BUFFER_STATUS_INVALID,
946 RADV_CMD_BUFFER_STATUS_INITIAL,
947 RADV_CMD_BUFFER_STATUS_RECORDING,
948 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
949 RADV_CMD_BUFFER_STATUS_PENDING,
950 };
951
952 struct radv_cmd_buffer {
953 VK_LOADER_DATA _loader_data;
954
955 struct radv_device * device;
956
957 struct radv_cmd_pool * pool;
958 struct list_head pool_link;
959
960 VkCommandBufferUsageFlags usage_flags;
961 VkCommandBufferLevel level;
962 enum radv_cmd_buffer_status status;
963 struct radeon_winsys_cs *cs;
964 struct radv_cmd_state state;
965 struct radv_vertex_binding vertex_bindings[MAX_VBS];
966 uint32_t queue_family_index;
967
968 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
969 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
970 VkShaderStageFlags push_constant_stages;
971 struct radv_push_descriptor_set push_descriptors;
972 struct radv_descriptor_set meta_push_descriptors;
973 struct radv_descriptor_set *descriptors[MAX_SETS];
974
975 struct radv_cmd_buffer_upload upload;
976
977 uint32_t scratch_size_needed;
978 uint32_t compute_scratch_size_needed;
979 uint32_t esgs_ring_size_needed;
980 uint32_t gsvs_ring_size_needed;
981 bool tess_rings_needed;
982 bool sample_positions_needed;
983
984 VkResult record_result;
985
986 int ring_offsets_idx; /* just used for verification */
987 uint32_t gfx9_fence_offset;
988 struct radeon_winsys_bo *gfx9_fence_bo;
989 uint32_t gfx9_fence_idx;
990 };
991
992 struct radv_image;
993
994 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
995
996 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
997 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
998
999 void cik_create_gfx_config(struct radv_device *device);
1000
1001 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
1002 int count, const VkViewport *viewports);
1003 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
1004 int count, const VkRect2D *scissors,
1005 const VkViewport *viewports, bool can_use_guardband);
1006 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1007 bool instanced_draw, bool indirect_draw,
1008 uint32_t draw_vertex_count);
1009 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
1010 bool predicated,
1011 enum chip_class chip_class,
1012 bool is_mec,
1013 unsigned event, unsigned event_flags,
1014 unsigned data_sel,
1015 uint64_t va,
1016 uint32_t old_fence,
1017 uint32_t new_fence);
1018
1019 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
1020 bool predicated,
1021 uint64_t va, uint32_t ref,
1022 uint32_t mask);
1023 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
1024 bool predicated,
1025 enum chip_class chip_class,
1026 uint32_t *fence_ptr, uint64_t va,
1027 bool is_mec,
1028 enum radv_cmd_flush_bits flush_bits);
1029 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1030 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1031 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1032 uint64_t src_va, uint64_t dest_va,
1033 uint64_t size);
1034 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1035 unsigned size);
1036 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1037 uint64_t size, unsigned value);
1038 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1039 bool
1040 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1041 unsigned size,
1042 unsigned alignment,
1043 unsigned *out_offset,
1044 void **ptr);
1045 void
1046 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1047 const struct radv_subpass *subpass,
1048 bool transitions);
1049 bool
1050 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1051 unsigned size, unsigned alignmnet,
1052 const void *data, unsigned *out_offset);
1053
1054 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1055 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1056 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1057 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1058 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1059 unsigned radv_cayman_get_maxdist(int log_samples);
1060 void radv_device_init_msaa(struct radv_device *device);
1061 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1062 struct radv_image *image,
1063 VkClearDepthStencilValue ds_clear_value,
1064 VkImageAspectFlags aspects);
1065 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1066 struct radv_image *image,
1067 int idx,
1068 uint32_t color_values[2]);
1069 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1070 struct radv_image *image,
1071 bool value);
1072 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1073 struct radeon_winsys_bo *bo,
1074 uint64_t offset, uint64_t size, uint32_t value);
1075 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1076 bool radv_get_memory_fd(struct radv_device *device,
1077 struct radv_device_memory *memory,
1078 int *pFD);
1079
1080 /*
1081 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1082 *
1083 * Limitations: Can't call normal dispatch functions without binding or rebinding
1084 * the compute pipeline.
1085 */
1086 void radv_unaligned_dispatch(
1087 struct radv_cmd_buffer *cmd_buffer,
1088 uint32_t x,
1089 uint32_t y,
1090 uint32_t z);
1091
1092 struct radv_event {
1093 struct radeon_winsys_bo *bo;
1094 uint64_t *map;
1095 };
1096
1097 struct radv_shader_module;
1098
1099 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1100 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1101 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1102 void
1103 radv_hash_shaders(unsigned char *hash,
1104 const VkPipelineShaderStageCreateInfo **stages,
1105 const struct radv_pipeline_layout *layout,
1106 const struct radv_pipeline_key *key,
1107 uint32_t flags);
1108
1109 static inline gl_shader_stage
1110 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1111 {
1112 assert(__builtin_popcount(vk_stage) == 1);
1113 return ffs(vk_stage) - 1;
1114 }
1115
1116 static inline VkShaderStageFlagBits
1117 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1118 {
1119 return (1 << mesa_stage);
1120 }
1121
1122 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1123
1124 #define radv_foreach_stage(stage, stage_bits) \
1125 for (gl_shader_stage stage, \
1126 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1127 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1128 __tmp &= ~(1 << (stage)))
1129
1130 unsigned radv_format_meta_fs_key(VkFormat format);
1131
1132 struct radv_raster_state {
1133 uint32_t pa_cl_clip_cntl;
1134 uint32_t spi_interp_control;
1135 uint32_t pa_su_vtx_cntl;
1136 uint32_t pa_su_sc_mode_cntl;
1137 };
1138
1139 struct radv_multisample_state {
1140 uint32_t db_eqaa;
1141 uint32_t pa_sc_line_cntl;
1142 uint32_t pa_sc_mode_cntl_0;
1143 uint32_t pa_sc_mode_cntl_1;
1144 uint32_t pa_sc_aa_config;
1145 uint32_t pa_sc_aa_mask[2];
1146 unsigned num_samples;
1147 };
1148
1149 struct radv_prim_vertex_count {
1150 uint8_t min;
1151 uint8_t incr;
1152 };
1153
1154 struct radv_gs_state {
1155 uint32_t vgt_gs_onchip_cntl;
1156 uint32_t vgt_gs_max_prims_per_subgroup;
1157 uint32_t vgt_esgs_ring_itemsize;
1158 uint32_t lds_size;
1159 };
1160
1161 struct radv_vertex_elements_info {
1162 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1163 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1164 uint32_t binding[MAX_VERTEX_ATTRIBS];
1165 uint32_t offset[MAX_VERTEX_ATTRIBS];
1166 uint32_t count;
1167 };
1168
1169 struct radv_ia_multi_vgt_param_helpers {
1170 uint32_t base;
1171 bool partial_es_wave;
1172 uint8_t primgroup_size;
1173 bool wd_switch_on_eop;
1174 bool ia_switch_on_eoi;
1175 bool partial_vs_wave;
1176 };
1177
1178 #define SI_GS_PER_ES 128
1179
1180 struct radv_pipeline {
1181 struct radv_device * device;
1182 struct radv_dynamic_state dynamic_state;
1183
1184 struct radv_pipeline_layout * layout;
1185
1186 bool needs_data_cache;
1187 bool need_indirect_descriptor_sets;
1188 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1189 struct radv_shader_variant *gs_copy_shader;
1190 VkShaderStageFlags active_stages;
1191
1192 struct radeon_winsys_cs cs;
1193
1194 struct radv_vertex_elements_info vertex_elements;
1195
1196 uint32_t binding_stride[MAX_VBS];
1197
1198 uint32_t user_data_0[MESA_SHADER_STAGES];
1199 union {
1200 struct {
1201 struct radv_raster_state raster;
1202 struct radv_multisample_state ms;
1203 struct radv_gs_state gs;
1204 uint32_t spi_baryc_cntl;
1205 unsigned prim;
1206 unsigned gs_out;
1207 bool prim_restart_enable;
1208 unsigned esgs_ring_size;
1209 unsigned gsvs_ring_size;
1210 uint32_t vtx_base_sgpr;
1211 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1212 uint8_t vtx_emit_num;
1213 struct radv_prim_vertex_count prim_vertex_count;
1214 bool can_use_guardband;
1215 uint32_t needed_dynamic_state;
1216 } graphics;
1217 };
1218
1219 unsigned max_waves;
1220 unsigned scratch_bytes_per_wave;
1221 };
1222
1223 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1224 {
1225 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1226 }
1227
1228 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1229 {
1230 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1231 }
1232
1233 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1234 gl_shader_stage stage,
1235 int idx);
1236
1237 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1238
1239 struct radv_graphics_pipeline_create_info {
1240 bool use_rectlist;
1241 bool db_depth_clear;
1242 bool db_stencil_clear;
1243 bool db_depth_disable_expclear;
1244 bool db_stencil_disable_expclear;
1245 bool db_flush_depth_inplace;
1246 bool db_flush_stencil_inplace;
1247 bool db_resummarize;
1248 uint32_t custom_blend_mode;
1249 };
1250
1251 VkResult
1252 radv_graphics_pipeline_create(VkDevice device,
1253 VkPipelineCache cache,
1254 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1255 const struct radv_graphics_pipeline_create_info *extra,
1256 const VkAllocationCallbacks *alloc,
1257 VkPipeline *pPipeline);
1258
1259 struct vk_format_description;
1260 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1261 int first_non_void);
1262 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1263 int first_non_void);
1264 uint32_t radv_translate_colorformat(VkFormat format);
1265 uint32_t radv_translate_color_numformat(VkFormat format,
1266 const struct vk_format_description *desc,
1267 int first_non_void);
1268 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1269 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1270 uint32_t radv_translate_dbformat(VkFormat format);
1271 uint32_t radv_translate_tex_dataformat(VkFormat format,
1272 const struct vk_format_description *desc,
1273 int first_non_void);
1274 uint32_t radv_translate_tex_numformat(VkFormat format,
1275 const struct vk_format_description *desc,
1276 int first_non_void);
1277 bool radv_format_pack_clear_color(VkFormat format,
1278 uint32_t clear_vals[2],
1279 VkClearColorValue *value);
1280 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1281 bool radv_dcc_formats_compatible(VkFormat format1,
1282 VkFormat format2);
1283
1284 struct radv_fmask_info {
1285 uint64_t offset;
1286 uint64_t size;
1287 unsigned alignment;
1288 unsigned pitch_in_pixels;
1289 unsigned bank_height;
1290 unsigned slice_tile_max;
1291 unsigned tile_mode_index;
1292 unsigned tile_swizzle;
1293 };
1294
1295 struct radv_cmask_info {
1296 uint64_t offset;
1297 uint64_t size;
1298 unsigned alignment;
1299 unsigned slice_tile_max;
1300 };
1301
1302 struct radv_image {
1303 VkImageType type;
1304 /* The original VkFormat provided by the client. This may not match any
1305 * of the actual surface formats.
1306 */
1307 VkFormat vk_format;
1308 VkImageAspectFlags aspects;
1309 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1310 struct ac_surf_info info;
1311 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1312 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1313
1314 VkDeviceSize size;
1315 uint32_t alignment;
1316
1317 unsigned queue_family_mask;
1318 bool exclusive;
1319 bool shareable;
1320
1321 /* Set when bound */
1322 struct radeon_winsys_bo *bo;
1323 VkDeviceSize offset;
1324 uint64_t dcc_offset;
1325 uint64_t htile_offset;
1326 bool tc_compatible_htile;
1327 struct radeon_surf surface;
1328
1329 struct radv_fmask_info fmask;
1330 struct radv_cmask_info cmask;
1331 uint64_t clear_value_offset;
1332 uint64_t dcc_pred_offset;
1333
1334 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1335 VkDeviceMemory owned_memory;
1336 };
1337
1338 /* Whether the image has a htile that is known consistent with the contents of
1339 * the image. */
1340 bool radv_layout_has_htile(const struct radv_image *image,
1341 VkImageLayout layout,
1342 unsigned queue_mask);
1343
1344 /* Whether the image has a htile that is known consistent with the contents of
1345 * the image and is allowed to be in compressed form.
1346 *
1347 * If this is false reads that don't use the htile should be able to return
1348 * correct results.
1349 */
1350 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1351 VkImageLayout layout,
1352 unsigned queue_mask);
1353
1354 bool radv_layout_can_fast_clear(const struct radv_image *image,
1355 VkImageLayout layout,
1356 unsigned queue_mask);
1357
1358 bool radv_layout_dcc_compressed(const struct radv_image *image,
1359 VkImageLayout layout,
1360 unsigned queue_mask);
1361
1362 static inline bool
1363 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1364 {
1365 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1366 }
1367
1368 static inline bool
1369 radv_htile_enabled(const struct radv_image *image, unsigned level)
1370 {
1371 return image->surface.htile_size && level == 0;
1372 }
1373
1374 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1375
1376 static inline uint32_t
1377 radv_get_layerCount(const struct radv_image *image,
1378 const VkImageSubresourceRange *range)
1379 {
1380 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1381 image->info.array_size - range->baseArrayLayer : range->layerCount;
1382 }
1383
1384 static inline uint32_t
1385 radv_get_levelCount(const struct radv_image *image,
1386 const VkImageSubresourceRange *range)
1387 {
1388 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1389 image->info.levels - range->baseMipLevel : range->levelCount;
1390 }
1391
1392 struct radeon_bo_metadata;
1393 void
1394 radv_init_metadata(struct radv_device *device,
1395 struct radv_image *image,
1396 struct radeon_bo_metadata *metadata);
1397
1398 struct radv_image_view {
1399 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1400 struct radeon_winsys_bo *bo;
1401
1402 VkImageViewType type;
1403 VkImageAspectFlags aspect_mask;
1404 VkFormat vk_format;
1405 uint32_t base_layer;
1406 uint32_t layer_count;
1407 uint32_t base_mip;
1408 uint32_t level_count;
1409 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1410
1411 uint32_t descriptor[16];
1412
1413 /* Descriptor for use as a storage image as opposed to a sampled image.
1414 * This has a few differences for cube maps (e.g. type).
1415 */
1416 uint32_t storage_descriptor[16];
1417 };
1418
1419 struct radv_image_create_info {
1420 const VkImageCreateInfo *vk_info;
1421 bool scanout;
1422 bool no_metadata_planes;
1423 };
1424
1425 VkResult radv_image_create(VkDevice _device,
1426 const struct radv_image_create_info *info,
1427 const VkAllocationCallbacks* alloc,
1428 VkImage *pImage);
1429
1430 VkResult
1431 radv_image_from_gralloc(VkDevice device_h,
1432 const VkImageCreateInfo *base_info,
1433 const VkNativeBufferANDROID *gralloc_info,
1434 const VkAllocationCallbacks *alloc,
1435 VkImage *out_image_h);
1436
1437 void radv_image_view_init(struct radv_image_view *view,
1438 struct radv_device *device,
1439 const VkImageViewCreateInfo* pCreateInfo);
1440
1441 struct radv_buffer_view {
1442 struct radeon_winsys_bo *bo;
1443 VkFormat vk_format;
1444 uint64_t range; /**< VkBufferViewCreateInfo::range */
1445 uint32_t state[4];
1446 };
1447 void radv_buffer_view_init(struct radv_buffer_view *view,
1448 struct radv_device *device,
1449 const VkBufferViewCreateInfo* pCreateInfo);
1450
1451 static inline struct VkExtent3D
1452 radv_sanitize_image_extent(const VkImageType imageType,
1453 const struct VkExtent3D imageExtent)
1454 {
1455 switch (imageType) {
1456 case VK_IMAGE_TYPE_1D:
1457 return (VkExtent3D) { imageExtent.width, 1, 1 };
1458 case VK_IMAGE_TYPE_2D:
1459 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1460 case VK_IMAGE_TYPE_3D:
1461 return imageExtent;
1462 default:
1463 unreachable("invalid image type");
1464 }
1465 }
1466
1467 static inline struct VkOffset3D
1468 radv_sanitize_image_offset(const VkImageType imageType,
1469 const struct VkOffset3D imageOffset)
1470 {
1471 switch (imageType) {
1472 case VK_IMAGE_TYPE_1D:
1473 return (VkOffset3D) { imageOffset.x, 0, 0 };
1474 case VK_IMAGE_TYPE_2D:
1475 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1476 case VK_IMAGE_TYPE_3D:
1477 return imageOffset;
1478 default:
1479 unreachable("invalid image type");
1480 }
1481 }
1482
1483 static inline bool
1484 radv_image_extent_compare(const struct radv_image *image,
1485 const VkExtent3D *extent)
1486 {
1487 if (extent->width != image->info.width ||
1488 extent->height != image->info.height ||
1489 extent->depth != image->info.depth)
1490 return false;
1491 return true;
1492 }
1493
1494 struct radv_sampler {
1495 uint32_t state[4];
1496 };
1497
1498 struct radv_color_buffer_info {
1499 uint64_t cb_color_base;
1500 uint64_t cb_color_cmask;
1501 uint64_t cb_color_fmask;
1502 uint64_t cb_dcc_base;
1503 uint32_t cb_color_pitch;
1504 uint32_t cb_color_slice;
1505 uint32_t cb_color_view;
1506 uint32_t cb_color_info;
1507 uint32_t cb_color_attrib;
1508 uint32_t cb_color_attrib2;
1509 uint32_t cb_dcc_control;
1510 uint32_t cb_color_cmask_slice;
1511 uint32_t cb_color_fmask_slice;
1512 };
1513
1514 struct radv_ds_buffer_info {
1515 uint64_t db_z_read_base;
1516 uint64_t db_stencil_read_base;
1517 uint64_t db_z_write_base;
1518 uint64_t db_stencil_write_base;
1519 uint64_t db_htile_data_base;
1520 uint32_t db_depth_info;
1521 uint32_t db_z_info;
1522 uint32_t db_stencil_info;
1523 uint32_t db_depth_view;
1524 uint32_t db_depth_size;
1525 uint32_t db_depth_slice;
1526 uint32_t db_htile_surface;
1527 uint32_t pa_su_poly_offset_db_fmt_cntl;
1528 uint32_t db_z_info2;
1529 uint32_t db_stencil_info2;
1530 float offset_scale;
1531 };
1532
1533 struct radv_attachment_info {
1534 union {
1535 struct radv_color_buffer_info cb;
1536 struct radv_ds_buffer_info ds;
1537 };
1538 struct radv_image_view *attachment;
1539 };
1540
1541 struct radv_framebuffer {
1542 uint32_t width;
1543 uint32_t height;
1544 uint32_t layers;
1545
1546 uint32_t attachment_count;
1547 struct radv_attachment_info attachments[0];
1548 };
1549
1550 struct radv_subpass_barrier {
1551 VkPipelineStageFlags src_stage_mask;
1552 VkAccessFlags src_access_mask;
1553 VkAccessFlags dst_access_mask;
1554 };
1555
1556 struct radv_subpass {
1557 uint32_t input_count;
1558 uint32_t color_count;
1559 VkAttachmentReference * input_attachments;
1560 VkAttachmentReference * color_attachments;
1561 VkAttachmentReference * resolve_attachments;
1562 VkAttachmentReference depth_stencil_attachment;
1563
1564 /** Subpass has at least one resolve attachment */
1565 bool has_resolve;
1566
1567 struct radv_subpass_barrier start_barrier;
1568
1569 uint32_t view_mask;
1570 };
1571
1572 struct radv_render_pass_attachment {
1573 VkFormat format;
1574 uint32_t samples;
1575 VkAttachmentLoadOp load_op;
1576 VkAttachmentLoadOp stencil_load_op;
1577 VkImageLayout initial_layout;
1578 VkImageLayout final_layout;
1579 uint32_t view_mask;
1580 };
1581
1582 struct radv_render_pass {
1583 uint32_t attachment_count;
1584 uint32_t subpass_count;
1585 VkAttachmentReference * subpass_attachments;
1586 struct radv_render_pass_attachment * attachments;
1587 struct radv_subpass_barrier end_barrier;
1588 struct radv_subpass subpasses[0];
1589 };
1590
1591 VkResult radv_device_init_meta(struct radv_device *device);
1592 void radv_device_finish_meta(struct radv_device *device);
1593
1594 struct radv_query_pool {
1595 struct radeon_winsys_bo *bo;
1596 uint32_t stride;
1597 uint32_t availability_offset;
1598 char *ptr;
1599 VkQueryType type;
1600 uint32_t pipeline_stats_mask;
1601 };
1602
1603 struct radv_semaphore {
1604 /* use a winsys sem for non-exportable */
1605 struct radeon_winsys_sem *sem;
1606 uint32_t syncobj;
1607 uint32_t temp_syncobj;
1608 };
1609
1610 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1611 int num_wait_sems,
1612 const VkSemaphore *wait_sems,
1613 int num_signal_sems,
1614 const VkSemaphore *signal_sems,
1615 VkFence fence);
1616 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1617
1618 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1619 struct radv_descriptor_set *set,
1620 unsigned idx);
1621
1622 void
1623 radv_update_descriptor_sets(struct radv_device *device,
1624 struct radv_cmd_buffer *cmd_buffer,
1625 VkDescriptorSet overrideSet,
1626 uint32_t descriptorWriteCount,
1627 const VkWriteDescriptorSet *pDescriptorWrites,
1628 uint32_t descriptorCopyCount,
1629 const VkCopyDescriptorSet *pDescriptorCopies);
1630
1631 void
1632 radv_update_descriptor_set_with_template(struct radv_device *device,
1633 struct radv_cmd_buffer *cmd_buffer,
1634 struct radv_descriptor_set *set,
1635 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1636 const void *pData);
1637
1638 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1639 VkPipelineBindPoint pipelineBindPoint,
1640 VkPipelineLayout _layout,
1641 uint32_t set,
1642 uint32_t descriptorWriteCount,
1643 const VkWriteDescriptorSet *pDescriptorWrites);
1644
1645 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1646 struct radv_image *image, uint32_t value);
1647 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1648 struct radv_image *image, uint32_t value);
1649
1650 struct radv_fence {
1651 struct radeon_winsys_fence *fence;
1652 bool submitted;
1653 bool signalled;
1654
1655 uint32_t syncobj;
1656 uint32_t temp_syncobj;
1657 };
1658
1659 struct radeon_winsys_sem;
1660
1661 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1662 \
1663 static inline struct __radv_type * \
1664 __radv_type ## _from_handle(__VkType _handle) \
1665 { \
1666 return (struct __radv_type *) _handle; \
1667 } \
1668 \
1669 static inline __VkType \
1670 __radv_type ## _to_handle(struct __radv_type *_obj) \
1671 { \
1672 return (__VkType) _obj; \
1673 }
1674
1675 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1676 \
1677 static inline struct __radv_type * \
1678 __radv_type ## _from_handle(__VkType _handle) \
1679 { \
1680 return (struct __radv_type *)(uintptr_t) _handle; \
1681 } \
1682 \
1683 static inline __VkType \
1684 __radv_type ## _to_handle(struct __radv_type *_obj) \
1685 { \
1686 return (__VkType)(uintptr_t) _obj; \
1687 }
1688
1689 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1690 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1691
1692 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1693 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1694 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1695 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1696 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1697
1698 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1699 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1700 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1701 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1702 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1703 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1704 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1705 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1706 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1707 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1708 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1709 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1710 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1711 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1712 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1713 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1714 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1715 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1716 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1717 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1718 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1719
1720 #endif /* RADV_PRIVATE_H */