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radv/gfx10: add Wave32 support for compute shaders
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
53 #include "vk_alloc.h"
54 #include "vk_debug_report.h"
55
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
66 #include "sid.h"
67
68 #include <llvm-c/TargetMachine.h>
69
70 /* Pre-declarations needed for WSI entrypoints */
71 struct wl_surface;
72 struct wl_display;
73 typedef struct xcb_connection_t xcb_connection_t;
74 typedef uint32_t xcb_visualid_t;
75 typedef uint32_t xcb_window_t;
76
77 #include <vulkan/vulkan.h>
78 #include <vulkan/vulkan_intel.h>
79 #include <vulkan/vk_icd.h>
80 #include <vulkan/vk_android_native_buffer.h>
81
82 #include "radv_entrypoints.h"
83
84 #include "wsi_common.h"
85 #include "wsi_common_display.h"
86
87 struct gfx10_format {
88 unsigned img_format:9;
89
90 /* Various formats are only supported with workarounds for vertex fetch,
91 * and some 32_32_32 formats are supported natively, but only for buffers
92 * (possibly with some image support, actually, but no filtering). */
93 bool buffers_only:1;
94 };
95
96 #include "gfx10_format_table.h"
97
98 enum radv_mem_heap {
99 RADV_MEM_HEAP_VRAM,
100 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
101 RADV_MEM_HEAP_GTT,
102 RADV_MEM_HEAP_COUNT
103 };
104
105 enum radv_mem_type {
106 RADV_MEM_TYPE_VRAM,
107 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
108 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
109 RADV_MEM_TYPE_GTT_CACHED,
110 RADV_MEM_TYPE_COUNT
111 };
112
113 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
114
115 static inline uint32_t
116 align_u32(uint32_t v, uint32_t a)
117 {
118 assert(a != 0 && a == (a & -a));
119 return (v + a - 1) & ~(a - 1);
120 }
121
122 static inline uint32_t
123 align_u32_npot(uint32_t v, uint32_t a)
124 {
125 return (v + a - 1) / a * a;
126 }
127
128 static inline uint64_t
129 align_u64(uint64_t v, uint64_t a)
130 {
131 assert(a != 0 && a == (a & -a));
132 return (v + a - 1) & ~(a - 1);
133 }
134
135 static inline int32_t
136 align_i32(int32_t v, int32_t a)
137 {
138 assert(a != 0 && a == (a & -a));
139 return (v + a - 1) & ~(a - 1);
140 }
141
142 /** Alignment must be a power of 2. */
143 static inline bool
144 radv_is_aligned(uintmax_t n, uintmax_t a)
145 {
146 assert(a == (a & -a));
147 return (n & (a - 1)) == 0;
148 }
149
150 static inline uint32_t
151 round_up_u32(uint32_t v, uint32_t a)
152 {
153 return (v + a - 1) / a;
154 }
155
156 static inline uint64_t
157 round_up_u64(uint64_t v, uint64_t a)
158 {
159 return (v + a - 1) / a;
160 }
161
162 static inline uint32_t
163 radv_minify(uint32_t n, uint32_t levels)
164 {
165 if (unlikely(n == 0))
166 return 0;
167 else
168 return MAX2(n >> levels, 1);
169 }
170 static inline float
171 radv_clamp_f(float f, float min, float max)
172 {
173 assert(min < max);
174
175 if (f > max)
176 return max;
177 else if (f < min)
178 return min;
179 else
180 return f;
181 }
182
183 static inline bool
184 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
185 {
186 if (*inout_mask & clear_mask) {
187 *inout_mask &= ~clear_mask;
188 return true;
189 } else {
190 return false;
191 }
192 }
193
194 #define for_each_bit(b, dword) \
195 for (uint32_t __dword = (dword); \
196 (b) = __builtin_ffs(__dword) - 1, __dword; \
197 __dword &= ~(1 << (b)))
198
199 #define typed_memcpy(dest, src, count) ({ \
200 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
201 memcpy((dest), (src), (count) * sizeof(*(src))); \
202 })
203
204 /* Whenever we generate an error, pass it through this function. Useful for
205 * debugging, where we can break on it. Only call at error site, not when
206 * propagating errors. Might be useful to plug in a stack trace here.
207 */
208
209 struct radv_instance;
210
211 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
212
213 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
214 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
215
216 void __radv_finishme(const char *file, int line, const char *format, ...)
217 radv_printflike(3, 4);
218 void radv_loge(const char *format, ...) radv_printflike(1, 2);
219 void radv_loge_v(const char *format, va_list va);
220 void radv_logi(const char *format, ...) radv_printflike(1, 2);
221 void radv_logi_v(const char *format, va_list va);
222
223 /**
224 * Print a FINISHME message, including its source location.
225 */
226 #define radv_finishme(format, ...) \
227 do { \
228 static bool reported = false; \
229 if (!reported) { \
230 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
231 reported = true; \
232 } \
233 } while (0)
234
235 /* A non-fatal assert. Useful for debugging. */
236 #ifdef DEBUG
237 #define radv_assert(x) ({ \
238 if (unlikely(!(x))) \
239 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
240 })
241 #else
242 #define radv_assert(x)
243 #endif
244
245 #define stub_return(v) \
246 do { \
247 radv_finishme("stub %s", __func__); \
248 return (v); \
249 } while (0)
250
251 #define stub() \
252 do { \
253 radv_finishme("stub %s", __func__); \
254 return; \
255 } while (0)
256
257 void *radv_lookup_entrypoint_unchecked(const char *name);
258 void *radv_lookup_entrypoint_checked(const char *name,
259 uint32_t core_version,
260 const struct radv_instance_extension_table *instance,
261 const struct radv_device_extension_table *device);
262 void *radv_lookup_physical_device_entrypoint_checked(const char *name,
263 uint32_t core_version,
264 const struct radv_instance_extension_table *instance);
265
266 struct radv_physical_device {
267 VK_LOADER_DATA _loader_data;
268
269 struct radv_instance * instance;
270
271 struct radeon_winsys *ws;
272 struct radeon_info rad_info;
273 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
274 uint8_t driver_uuid[VK_UUID_SIZE];
275 uint8_t device_uuid[VK_UUID_SIZE];
276 uint8_t cache_uuid[VK_UUID_SIZE];
277
278 int local_fd;
279 int master_fd;
280 struct wsi_device wsi_device;
281
282 bool has_rbplus; /* if RB+ register exist */
283 bool rbplus_allowed; /* if RB+ is allowed */
284 bool has_clear_state;
285 bool cpdma_prefetch_writes_memory;
286 bool has_scissor_bug;
287 bool has_tc_compat_zrange_bug;
288
289 bool has_out_of_order_rast;
290 bool out_of_order_rast_allowed;
291
292 /* Whether DCC should be enabled for MSAA textures. */
293 bool dcc_msaa_allowed;
294
295 /* Whether LOAD_CONTEXT_REG packets are supported. */
296 bool has_load_ctx_reg_pkt;
297
298 /* Whether to enable the AMD_shader_ballot extension */
299 bool use_shader_ballot;
300
301 /* Whether DISABLE_CONSTANT_ENCODE_REG is supported. */
302 bool has_dcc_constant_encode;
303
304 /* Number of threads per wave. */
305 uint8_t cs_wave_size;
306
307 /* This is the drivers on-disk cache used as a fallback as opposed to
308 * the pipeline cache defined by apps.
309 */
310 struct disk_cache * disk_cache;
311
312 VkPhysicalDeviceMemoryProperties memory_properties;
313 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
314
315 drmPciBusInfo bus_info;
316
317 struct radv_device_extension_table supported_extensions;
318 };
319
320 struct radv_instance {
321 VK_LOADER_DATA _loader_data;
322
323 VkAllocationCallbacks alloc;
324
325 uint32_t apiVersion;
326 int physicalDeviceCount;
327 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
328
329 uint64_t debug_flags;
330 uint64_t perftest_flags;
331
332 struct vk_debug_report_instance debug_report_callbacks;
333
334 struct radv_instance_extension_table enabled_extensions;
335
336 struct driOptionCache dri_options;
337 struct driOptionCache available_dri_options;
338 };
339
340 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
341 void radv_finish_wsi(struct radv_physical_device *physical_device);
342
343 bool radv_instance_extension_supported(const char *name);
344 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
345 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
346 const char *name);
347
348 struct cache_entry;
349
350 struct radv_pipeline_cache {
351 struct radv_device * device;
352 pthread_mutex_t mutex;
353
354 uint32_t total_size;
355 uint32_t table_size;
356 uint32_t kernel_count;
357 struct cache_entry ** hash_table;
358 bool modified;
359
360 VkAllocationCallbacks alloc;
361 };
362
363 struct radv_pipeline_key {
364 uint32_t instance_rate_inputs;
365 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
366 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
367 uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
368 uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
369 uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
370 uint64_t vertex_alpha_adjust;
371 uint32_t vertex_post_shuffle;
372 unsigned tess_input_vertices;
373 uint32_t col_format;
374 uint32_t is_int8;
375 uint32_t is_int10;
376 uint8_t log2_ps_iter_samples;
377 uint8_t num_samples;
378 uint32_t has_multiview_view_index : 1;
379 uint32_t optimisations_disabled : 1;
380 };
381
382 struct radv_shader_binary;
383 struct radv_shader_variant;
384
385 void
386 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
387 struct radv_device *device);
388 void
389 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
390 bool
391 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
392 const void *data, size_t size);
393
394 bool
395 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
396 struct radv_pipeline_cache *cache,
397 const unsigned char *sha1,
398 struct radv_shader_variant **variants,
399 bool *found_in_application_cache);
400
401 void
402 radv_pipeline_cache_insert_shaders(struct radv_device *device,
403 struct radv_pipeline_cache *cache,
404 const unsigned char *sha1,
405 struct radv_shader_variant **variants,
406 struct radv_shader_binary *const *binaries);
407
408 enum radv_blit_ds_layout {
409 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
410 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
411 RADV_BLIT_DS_LAYOUT_COUNT,
412 };
413
414 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
415 {
416 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
417 }
418
419 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
420 {
421 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
422 }
423
424 enum radv_meta_dst_layout {
425 RADV_META_DST_LAYOUT_GENERAL,
426 RADV_META_DST_LAYOUT_OPTIMAL,
427 RADV_META_DST_LAYOUT_COUNT,
428 };
429
430 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
431 {
432 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
433 }
434
435 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
436 {
437 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
438 }
439
440 struct radv_meta_state {
441 VkAllocationCallbacks alloc;
442
443 struct radv_pipeline_cache cache;
444
445 /*
446 * For on-demand pipeline creation, makes sure that
447 * only one thread tries to build a pipeline at the same time.
448 */
449 mtx_t mtx;
450
451 /**
452 * Use array element `i` for images with `2^i` samples.
453 */
454 struct {
455 VkRenderPass render_pass[NUM_META_FS_KEYS];
456 VkPipeline color_pipelines[NUM_META_FS_KEYS];
457
458 VkRenderPass depthstencil_rp;
459 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
460 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
461 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
462 } clear[1 + MAX_SAMPLES_LOG2];
463
464 VkPipelineLayout clear_color_p_layout;
465 VkPipelineLayout clear_depth_p_layout;
466
467 /* Optimized compute fast HTILE clear for stencil or depth only. */
468 VkPipeline clear_htile_mask_pipeline;
469 VkPipelineLayout clear_htile_mask_p_layout;
470 VkDescriptorSetLayout clear_htile_mask_ds_layout;
471
472 struct {
473 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
474
475 /** Pipeline that blits from a 1D image. */
476 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
477
478 /** Pipeline that blits from a 2D image. */
479 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
480
481 /** Pipeline that blits from a 3D image. */
482 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
483
484 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
485 VkPipeline depth_only_1d_pipeline;
486 VkPipeline depth_only_2d_pipeline;
487 VkPipeline depth_only_3d_pipeline;
488
489 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
490 VkPipeline stencil_only_1d_pipeline;
491 VkPipeline stencil_only_2d_pipeline;
492 VkPipeline stencil_only_3d_pipeline;
493 VkPipelineLayout pipeline_layout;
494 VkDescriptorSetLayout ds_layout;
495 } blit;
496
497 struct {
498 VkPipelineLayout p_layouts[5];
499 VkDescriptorSetLayout ds_layouts[5];
500 VkPipeline pipelines[5][NUM_META_FS_KEYS];
501
502 VkPipeline depth_only_pipeline[5];
503
504 VkPipeline stencil_only_pipeline[5];
505 } blit2d[1 + MAX_SAMPLES_LOG2];
506
507 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
508 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
509 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
510
511 struct {
512 VkPipelineLayout img_p_layout;
513 VkDescriptorSetLayout img_ds_layout;
514 VkPipeline pipeline;
515 VkPipeline pipeline_3d;
516 } itob;
517 struct {
518 VkPipelineLayout img_p_layout;
519 VkDescriptorSetLayout img_ds_layout;
520 VkPipeline pipeline;
521 VkPipeline pipeline_3d;
522 } btoi;
523 struct {
524 VkPipelineLayout img_p_layout;
525 VkDescriptorSetLayout img_ds_layout;
526 VkPipeline pipeline;
527 } btoi_r32g32b32;
528 struct {
529 VkPipelineLayout img_p_layout;
530 VkDescriptorSetLayout img_ds_layout;
531 VkPipeline pipeline;
532 VkPipeline pipeline_3d;
533 } itoi;
534 struct {
535 VkPipelineLayout img_p_layout;
536 VkDescriptorSetLayout img_ds_layout;
537 VkPipeline pipeline;
538 } itoi_r32g32b32;
539 struct {
540 VkPipelineLayout img_p_layout;
541 VkDescriptorSetLayout img_ds_layout;
542 VkPipeline pipeline;
543 VkPipeline pipeline_3d;
544 } cleari;
545 struct {
546 VkPipelineLayout img_p_layout;
547 VkDescriptorSetLayout img_ds_layout;
548 VkPipeline pipeline;
549 } cleari_r32g32b32;
550
551 struct {
552 VkPipelineLayout p_layout;
553 VkPipeline pipeline[NUM_META_FS_KEYS];
554 VkRenderPass pass[NUM_META_FS_KEYS];
555 } resolve;
556
557 struct {
558 VkDescriptorSetLayout ds_layout;
559 VkPipelineLayout p_layout;
560 struct {
561 VkPipeline pipeline;
562 VkPipeline i_pipeline;
563 VkPipeline srgb_pipeline;
564 } rc[MAX_SAMPLES_LOG2];
565
566 VkPipeline depth_zero_pipeline;
567 struct {
568 VkPipeline average_pipeline;
569 VkPipeline max_pipeline;
570 VkPipeline min_pipeline;
571 } depth[MAX_SAMPLES_LOG2];
572
573 VkPipeline stencil_zero_pipeline;
574 struct {
575 VkPipeline max_pipeline;
576 VkPipeline min_pipeline;
577 } stencil[MAX_SAMPLES_LOG2];
578 } resolve_compute;
579
580 struct {
581 VkDescriptorSetLayout ds_layout;
582 VkPipelineLayout p_layout;
583
584 struct {
585 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
586 VkPipeline pipeline[NUM_META_FS_KEYS];
587 } rc[MAX_SAMPLES_LOG2];
588
589 VkRenderPass depth_render_pass;
590 VkPipeline depth_zero_pipeline;
591 struct {
592 VkPipeline average_pipeline;
593 VkPipeline max_pipeline;
594 VkPipeline min_pipeline;
595 } depth[MAX_SAMPLES_LOG2];
596
597 VkRenderPass stencil_render_pass;
598 VkPipeline stencil_zero_pipeline;
599 struct {
600 VkPipeline max_pipeline;
601 VkPipeline min_pipeline;
602 } stencil[MAX_SAMPLES_LOG2];
603 } resolve_fragment;
604
605 struct {
606 VkPipelineLayout p_layout;
607 VkPipeline decompress_pipeline;
608 VkPipeline resummarize_pipeline;
609 VkRenderPass pass;
610 } depth_decomp[1 + MAX_SAMPLES_LOG2];
611
612 struct {
613 VkPipelineLayout p_layout;
614 VkPipeline cmask_eliminate_pipeline;
615 VkPipeline fmask_decompress_pipeline;
616 VkPipeline dcc_decompress_pipeline;
617 VkRenderPass pass;
618
619 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
620 VkPipelineLayout dcc_decompress_compute_p_layout;
621 VkPipeline dcc_decompress_compute_pipeline;
622 } fast_clear_flush;
623
624 struct {
625 VkPipelineLayout fill_p_layout;
626 VkPipelineLayout copy_p_layout;
627 VkDescriptorSetLayout fill_ds_layout;
628 VkDescriptorSetLayout copy_ds_layout;
629 VkPipeline fill_pipeline;
630 VkPipeline copy_pipeline;
631 } buffer;
632
633 struct {
634 VkDescriptorSetLayout ds_layout;
635 VkPipelineLayout p_layout;
636 VkPipeline occlusion_query_pipeline;
637 VkPipeline pipeline_statistics_query_pipeline;
638 VkPipeline tfb_query_pipeline;
639 } query;
640
641 struct {
642 VkDescriptorSetLayout ds_layout;
643 VkPipelineLayout p_layout;
644 VkPipeline pipeline[MAX_SAMPLES_LOG2];
645 } fmask_expand;
646 };
647
648 /* queue types */
649 #define RADV_QUEUE_GENERAL 0
650 #define RADV_QUEUE_COMPUTE 1
651 #define RADV_QUEUE_TRANSFER 2
652
653 #define RADV_MAX_QUEUE_FAMILIES 3
654
655 enum ring_type radv_queue_family_to_ring(int f);
656
657 struct radv_queue {
658 VK_LOADER_DATA _loader_data;
659 struct radv_device * device;
660 struct radeon_winsys_ctx *hw_ctx;
661 enum radeon_ctx_priority priority;
662 uint32_t queue_family_index;
663 int queue_idx;
664 VkDeviceQueueCreateFlags flags;
665
666 uint32_t scratch_size;
667 uint32_t compute_scratch_size;
668 uint32_t esgs_ring_size;
669 uint32_t gsvs_ring_size;
670 bool has_tess_rings;
671 bool has_sample_positions;
672
673 struct radeon_winsys_bo *scratch_bo;
674 struct radeon_winsys_bo *descriptor_bo;
675 struct radeon_winsys_bo *compute_scratch_bo;
676 struct radeon_winsys_bo *esgs_ring_bo;
677 struct radeon_winsys_bo *gsvs_ring_bo;
678 struct radeon_winsys_bo *tess_rings_bo;
679 struct radeon_cmdbuf *initial_preamble_cs;
680 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
681 struct radeon_cmdbuf *continue_preamble_cs;
682 };
683
684 struct radv_bo_list {
685 struct radv_winsys_bo_list list;
686 unsigned capacity;
687 pthread_mutex_t mutex;
688 };
689
690 struct radv_device {
691 VK_LOADER_DATA _loader_data;
692
693 VkAllocationCallbacks alloc;
694
695 struct radv_instance * instance;
696 struct radeon_winsys *ws;
697
698 struct radv_meta_state meta_state;
699
700 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
701 int queue_count[RADV_MAX_QUEUE_FAMILIES];
702 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
703
704 bool always_use_syncobj;
705 bool has_distributed_tess;
706 bool pbb_allowed;
707 bool dfsm_allowed;
708 uint32_t tess_offchip_block_dw_size;
709 uint32_t scratch_waves;
710 uint32_t dispatch_initiator;
711
712 uint32_t gs_table_depth;
713
714 /* MSAA sample locations.
715 * The first index is the sample index.
716 * The second index is the coordinate: X, Y. */
717 float sample_locations_1x[1][2];
718 float sample_locations_2x[2][2];
719 float sample_locations_4x[4][2];
720 float sample_locations_8x[8][2];
721
722 /* GFX7 and later */
723 uint32_t gfx_init_size_dw;
724 struct radeon_winsys_bo *gfx_init;
725
726 struct radeon_winsys_bo *trace_bo;
727 uint32_t *trace_id_ptr;
728
729 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
730 bool keep_shader_info;
731
732 struct radv_physical_device *physical_device;
733
734 /* Backup in-memory cache to be used if the app doesn't provide one */
735 struct radv_pipeline_cache * mem_cache;
736
737 /*
738 * use different counters so MSAA MRTs get consecutive surface indices,
739 * even if MASK is allocated in between.
740 */
741 uint32_t image_mrt_offset_counter;
742 uint32_t fmask_mrt_offset_counter;
743 struct list_head shader_slabs;
744 mtx_t shader_slab_mutex;
745
746 /* For detecting VM faults reported by dmesg. */
747 uint64_t dmesg_timestamp;
748
749 struct radv_device_extension_table enabled_extensions;
750
751 /* Whether the driver uses a global BO list. */
752 bool use_global_bo_list;
753
754 struct radv_bo_list bo_list;
755
756 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
757 int force_aniso;
758 };
759
760 struct radv_device_memory {
761 struct radeon_winsys_bo *bo;
762 /* for dedicated allocations */
763 struct radv_image *image;
764 struct radv_buffer *buffer;
765 uint32_t type_index;
766 VkDeviceSize map_size;
767 void * map;
768 void * user_ptr;
769 };
770
771
772 struct radv_descriptor_range {
773 uint64_t va;
774 uint32_t size;
775 };
776
777 struct radv_descriptor_set {
778 const struct radv_descriptor_set_layout *layout;
779 uint32_t size;
780
781 struct radeon_winsys_bo *bo;
782 uint64_t va;
783 uint32_t *mapped_ptr;
784 struct radv_descriptor_range *dynamic_descriptors;
785
786 struct radeon_winsys_bo *descriptors[0];
787 };
788
789 struct radv_push_descriptor_set
790 {
791 struct radv_descriptor_set set;
792 uint32_t capacity;
793 };
794
795 struct radv_descriptor_pool_entry {
796 uint32_t offset;
797 uint32_t size;
798 struct radv_descriptor_set *set;
799 };
800
801 struct radv_descriptor_pool {
802 struct radeon_winsys_bo *bo;
803 uint8_t *mapped_ptr;
804 uint64_t current_offset;
805 uint64_t size;
806
807 uint8_t *host_memory_base;
808 uint8_t *host_memory_ptr;
809 uint8_t *host_memory_end;
810
811 uint32_t entry_count;
812 uint32_t max_entry_count;
813 struct radv_descriptor_pool_entry entries[0];
814 };
815
816 struct radv_descriptor_update_template_entry {
817 VkDescriptorType descriptor_type;
818
819 /* The number of descriptors to update */
820 uint32_t descriptor_count;
821
822 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
823 uint32_t dst_offset;
824
825 /* In dwords. Not valid/used for dynamic descriptors */
826 uint32_t dst_stride;
827
828 uint32_t buffer_offset;
829
830 /* Only valid for combined image samplers and samplers */
831 uint8_t has_sampler;
832 uint8_t sampler_offset;
833
834 /* In bytes */
835 size_t src_offset;
836 size_t src_stride;
837
838 /* For push descriptors */
839 const uint32_t *immutable_samplers;
840 };
841
842 struct radv_descriptor_update_template {
843 uint32_t entry_count;
844 VkPipelineBindPoint bind_point;
845 struct radv_descriptor_update_template_entry entry[0];
846 };
847
848 struct radv_buffer {
849 VkDeviceSize size;
850
851 VkBufferUsageFlags usage;
852 VkBufferCreateFlags flags;
853
854 /* Set when bound */
855 struct radeon_winsys_bo * bo;
856 VkDeviceSize offset;
857
858 bool shareable;
859 };
860
861 enum radv_dynamic_state_bits {
862 RADV_DYNAMIC_VIEWPORT = 1 << 0,
863 RADV_DYNAMIC_SCISSOR = 1 << 1,
864 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
865 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
866 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
867 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
868 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
869 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
870 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
871 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
872 RADV_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
873 RADV_DYNAMIC_ALL = (1 << 11) - 1,
874 };
875
876 enum radv_cmd_dirty_bits {
877 /* Keep the dynamic state dirty bits in sync with
878 * enum radv_dynamic_state_bits */
879 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
880 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
881 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
882 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
883 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
884 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
885 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
886 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
887 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
888 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
889 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
890 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 11) - 1,
891 RADV_CMD_DIRTY_PIPELINE = 1 << 11,
892 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 12,
893 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 13,
894 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 14,
895 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 15,
896 };
897
898 enum radv_cmd_flush_bits {
899 /* Instruction cache. */
900 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
901 /* Scalar L1 cache. */
902 RADV_CMD_FLAG_INV_SCACHE = 1 << 1,
903 /* Vector L1 cache. */
904 RADV_CMD_FLAG_INV_VCACHE = 1 << 2,
905 /* L2 cache + L2 metadata cache writeback & invalidate.
906 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
907 RADV_CMD_FLAG_INV_L2 = 1 << 3,
908 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
909 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
910 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
911 RADV_CMD_FLAG_WB_L2 = 1 << 4,
912 /* Framebuffer caches */
913 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
914 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
915 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
916 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
917 /* Engine synchronization. */
918 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
919 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
920 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
921 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
922 /* Pipeline query controls. */
923 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
924 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
925 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
926
927 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
928 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
929 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
930 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
931 };
932
933 struct radv_vertex_binding {
934 struct radv_buffer * buffer;
935 VkDeviceSize offset;
936 };
937
938 struct radv_streamout_binding {
939 struct radv_buffer *buffer;
940 VkDeviceSize offset;
941 VkDeviceSize size;
942 };
943
944 struct radv_streamout_state {
945 /* Mask of bound streamout buffers. */
946 uint8_t enabled_mask;
947
948 /* External state that comes from the last vertex stage, it must be
949 * set explicitely when binding a new graphics pipeline.
950 */
951 uint16_t stride_in_dw[MAX_SO_BUFFERS];
952 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
953
954 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
955 uint32_t hw_enabled_mask;
956
957 /* State of VGT_STRMOUT_(CONFIG|EN) */
958 bool streamout_enabled;
959 };
960
961 struct radv_viewport_state {
962 uint32_t count;
963 VkViewport viewports[MAX_VIEWPORTS];
964 };
965
966 struct radv_scissor_state {
967 uint32_t count;
968 VkRect2D scissors[MAX_SCISSORS];
969 };
970
971 struct radv_discard_rectangle_state {
972 uint32_t count;
973 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
974 };
975
976 struct radv_sample_locations_state {
977 VkSampleCountFlagBits per_pixel;
978 VkExtent2D grid_size;
979 uint32_t count;
980 VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
981 };
982
983 struct radv_dynamic_state {
984 /**
985 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
986 * Defines the set of saved dynamic state.
987 */
988 uint32_t mask;
989
990 struct radv_viewport_state viewport;
991
992 struct radv_scissor_state scissor;
993
994 float line_width;
995
996 struct {
997 float bias;
998 float clamp;
999 float slope;
1000 } depth_bias;
1001
1002 float blend_constants[4];
1003
1004 struct {
1005 float min;
1006 float max;
1007 } depth_bounds;
1008
1009 struct {
1010 uint32_t front;
1011 uint32_t back;
1012 } stencil_compare_mask;
1013
1014 struct {
1015 uint32_t front;
1016 uint32_t back;
1017 } stencil_write_mask;
1018
1019 struct {
1020 uint32_t front;
1021 uint32_t back;
1022 } stencil_reference;
1023
1024 struct radv_discard_rectangle_state discard_rectangle;
1025
1026 struct radv_sample_locations_state sample_location;
1027 };
1028
1029 extern const struct radv_dynamic_state default_dynamic_state;
1030
1031 const char *
1032 radv_get_debug_option_name(int id);
1033
1034 const char *
1035 radv_get_perftest_option_name(int id);
1036
1037 /**
1038 * Attachment state when recording a renderpass instance.
1039 *
1040 * The clear value is valid only if there exists a pending clear.
1041 */
1042 struct radv_attachment_state {
1043 VkImageAspectFlags pending_clear_aspects;
1044 uint32_t cleared_views;
1045 VkClearValue clear_value;
1046 VkImageLayout current_layout;
1047 struct radv_sample_locations_state sample_location;
1048 };
1049
1050 struct radv_descriptor_state {
1051 struct radv_descriptor_set *sets[MAX_SETS];
1052 uint32_t dirty;
1053 uint32_t valid;
1054 struct radv_push_descriptor_set push_set;
1055 bool push_dirty;
1056 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1057 };
1058
1059 struct radv_subpass_sample_locs_state {
1060 uint32_t subpass_idx;
1061 struct radv_sample_locations_state sample_location;
1062 };
1063
1064 struct radv_cmd_state {
1065 /* Vertex descriptors */
1066 uint64_t vb_va;
1067 unsigned vb_size;
1068
1069 bool predicating;
1070 uint32_t dirty;
1071
1072 uint32_t prefetch_L2_mask;
1073
1074 struct radv_pipeline * pipeline;
1075 struct radv_pipeline * emitted_pipeline;
1076 struct radv_pipeline * compute_pipeline;
1077 struct radv_pipeline * emitted_compute_pipeline;
1078 struct radv_framebuffer * framebuffer;
1079 struct radv_render_pass * pass;
1080 const struct radv_subpass * subpass;
1081 struct radv_dynamic_state dynamic;
1082 struct radv_attachment_state * attachments;
1083 struct radv_streamout_state streamout;
1084 VkRect2D render_area;
1085
1086 uint32_t num_subpass_sample_locs;
1087 struct radv_subpass_sample_locs_state * subpass_sample_locs;
1088
1089 /* Index buffer */
1090 struct radv_buffer *index_buffer;
1091 uint64_t index_offset;
1092 uint32_t index_type;
1093 uint32_t max_index_count;
1094 uint64_t index_va;
1095 int32_t last_index_type;
1096
1097 int32_t last_primitive_reset_en;
1098 uint32_t last_primitive_reset_index;
1099 enum radv_cmd_flush_bits flush_bits;
1100 unsigned active_occlusion_queries;
1101 bool perfect_occlusion_queries_enabled;
1102 unsigned active_pipeline_queries;
1103 float offset_scale;
1104 uint32_t trace_id;
1105 uint32_t last_ia_multi_vgt_param;
1106
1107 uint32_t last_num_instances;
1108 uint32_t last_first_instance;
1109 uint32_t last_vertex_offset;
1110
1111 /* Whether CP DMA is busy/idle. */
1112 bool dma_is_busy;
1113
1114 /* Conditional rendering info. */
1115 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1116 uint64_t predication_va;
1117
1118 bool context_roll_without_scissor_emitted;
1119 };
1120
1121 struct radv_cmd_pool {
1122 VkAllocationCallbacks alloc;
1123 struct list_head cmd_buffers;
1124 struct list_head free_cmd_buffers;
1125 uint32_t queue_family_index;
1126 };
1127
1128 struct radv_cmd_buffer_upload {
1129 uint8_t *map;
1130 unsigned offset;
1131 uint64_t size;
1132 struct radeon_winsys_bo *upload_bo;
1133 struct list_head list;
1134 };
1135
1136 enum radv_cmd_buffer_status {
1137 RADV_CMD_BUFFER_STATUS_INVALID,
1138 RADV_CMD_BUFFER_STATUS_INITIAL,
1139 RADV_CMD_BUFFER_STATUS_RECORDING,
1140 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1141 RADV_CMD_BUFFER_STATUS_PENDING,
1142 };
1143
1144 struct radv_cmd_buffer {
1145 VK_LOADER_DATA _loader_data;
1146
1147 struct radv_device * device;
1148
1149 struct radv_cmd_pool * pool;
1150 struct list_head pool_link;
1151
1152 VkCommandBufferUsageFlags usage_flags;
1153 VkCommandBufferLevel level;
1154 enum radv_cmd_buffer_status status;
1155 struct radeon_cmdbuf *cs;
1156 struct radv_cmd_state state;
1157 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1158 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1159 uint32_t queue_family_index;
1160
1161 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1162 VkShaderStageFlags push_constant_stages;
1163 struct radv_descriptor_set meta_push_descriptors;
1164
1165 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1166
1167 struct radv_cmd_buffer_upload upload;
1168
1169 uint32_t scratch_size_needed;
1170 uint32_t compute_scratch_size_needed;
1171 uint32_t esgs_ring_size_needed;
1172 uint32_t gsvs_ring_size_needed;
1173 bool tess_rings_needed;
1174 bool sample_positions_needed;
1175
1176 VkResult record_result;
1177
1178 uint64_t gfx9_fence_va;
1179 uint32_t gfx9_fence_idx;
1180 uint64_t gfx9_eop_bug_va;
1181
1182 /**
1183 * Whether a query pool has been resetted and we have to flush caches.
1184 */
1185 bool pending_reset_query;
1186
1187 /**
1188 * Bitmask of pending active query flushes.
1189 */
1190 enum radv_cmd_flush_bits active_query_flush_bits;
1191 };
1192
1193 struct radv_image;
1194 struct radv_image_view;
1195
1196 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1197
1198 void si_emit_graphics(struct radv_physical_device *physical_device,
1199 struct radeon_cmdbuf *cs);
1200 void si_emit_compute(struct radv_physical_device *physical_device,
1201 struct radeon_cmdbuf *cs);
1202
1203 void cik_create_gfx_config(struct radv_device *device);
1204
1205 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1206 int count, const VkViewport *viewports);
1207 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1208 int count, const VkRect2D *scissors,
1209 const VkViewport *viewports, bool can_use_guardband);
1210 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1211 bool instanced_draw, bool indirect_draw,
1212 bool count_from_stream_output,
1213 uint32_t draw_vertex_count);
1214 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1215 enum chip_class chip_class,
1216 bool is_mec,
1217 unsigned event, unsigned event_flags,
1218 unsigned dst_sel, unsigned data_sel,
1219 uint64_t va,
1220 uint32_t new_fence,
1221 uint64_t gfx9_eop_bug_va);
1222
1223 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1224 uint32_t ref, uint32_t mask);
1225 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1226 enum chip_class chip_class,
1227 uint32_t *fence_ptr, uint64_t va,
1228 bool is_mec,
1229 enum radv_cmd_flush_bits flush_bits,
1230 uint64_t gfx9_eop_bug_va);
1231 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1232 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1233 bool inverted, uint64_t va);
1234 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1235 uint64_t src_va, uint64_t dest_va,
1236 uint64_t size);
1237 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1238 unsigned size);
1239 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1240 uint64_t size, unsigned value);
1241 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1242
1243 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1244 bool
1245 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1246 unsigned size,
1247 unsigned alignment,
1248 unsigned *out_offset,
1249 void **ptr);
1250 void
1251 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1252 const struct radv_subpass *subpass);
1253 bool
1254 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1255 unsigned size, unsigned alignmnet,
1256 const void *data, unsigned *out_offset);
1257
1258 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1259 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1260 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1261 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
1262 VkImageAspectFlags aspects,
1263 VkResolveModeFlagBitsKHR resolve_mode);
1264 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1265 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
1266 VkImageAspectFlags aspects,
1267 VkResolveModeFlagBitsKHR resolve_mode);
1268 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
1269 unsigned radv_get_default_max_sample_dist(int log_samples);
1270 void radv_device_init_msaa(struct radv_device *device);
1271
1272 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1273 struct radv_image *image,
1274 VkClearDepthStencilValue ds_clear_value,
1275 VkImageAspectFlags aspects);
1276
1277 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1278 const struct radv_image_view *iview,
1279 int cb_idx,
1280 uint32_t color_values[2]);
1281
1282 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1283 struct radv_image *image,
1284 const VkImageSubresourceRange *range, bool value);
1285
1286 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1287 struct radv_image *image,
1288 const VkImageSubresourceRange *range, bool value);
1289
1290 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1291 struct radeon_winsys_bo *bo,
1292 uint64_t offset, uint64_t size, uint32_t value);
1293 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1294 bool radv_get_memory_fd(struct radv_device *device,
1295 struct radv_device_memory *memory,
1296 int *pFD);
1297
1298 static inline void
1299 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1300 unsigned sh_offset, unsigned pointer_count,
1301 bool use_32bit_pointers)
1302 {
1303 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1304 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1305 }
1306
1307 static inline void
1308 radv_emit_shader_pointer_body(struct radv_device *device,
1309 struct radeon_cmdbuf *cs,
1310 uint64_t va, bool use_32bit_pointers)
1311 {
1312 radeon_emit(cs, va);
1313
1314 if (use_32bit_pointers) {
1315 assert(va == 0 ||
1316 (va >> 32) == device->physical_device->rad_info.address32_hi);
1317 } else {
1318 radeon_emit(cs, va >> 32);
1319 }
1320 }
1321
1322 static inline void
1323 radv_emit_shader_pointer(struct radv_device *device,
1324 struct radeon_cmdbuf *cs,
1325 uint32_t sh_offset, uint64_t va, bool global)
1326 {
1327 bool use_32bit_pointers = !global;
1328
1329 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1330 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1331 }
1332
1333 static inline struct radv_descriptor_state *
1334 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1335 VkPipelineBindPoint bind_point)
1336 {
1337 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1338 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1339 return &cmd_buffer->descriptors[bind_point];
1340 }
1341
1342 /*
1343 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1344 *
1345 * Limitations: Can't call normal dispatch functions without binding or rebinding
1346 * the compute pipeline.
1347 */
1348 void radv_unaligned_dispatch(
1349 struct radv_cmd_buffer *cmd_buffer,
1350 uint32_t x,
1351 uint32_t y,
1352 uint32_t z);
1353
1354 struct radv_event {
1355 struct radeon_winsys_bo *bo;
1356 uint64_t *map;
1357 };
1358
1359 struct radv_shader_module;
1360
1361 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1362 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1363 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1364 #define RADV_HASH_SHADER_NO_NGG (1 << 3)
1365
1366 void
1367 radv_hash_shaders(unsigned char *hash,
1368 const VkPipelineShaderStageCreateInfo **stages,
1369 const struct radv_pipeline_layout *layout,
1370 const struct radv_pipeline_key *key,
1371 uint32_t flags);
1372
1373 static inline gl_shader_stage
1374 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1375 {
1376 assert(__builtin_popcount(vk_stage) == 1);
1377 return ffs(vk_stage) - 1;
1378 }
1379
1380 static inline VkShaderStageFlagBits
1381 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1382 {
1383 return (1 << mesa_stage);
1384 }
1385
1386 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1387
1388 #define radv_foreach_stage(stage, stage_bits) \
1389 for (gl_shader_stage stage, \
1390 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1391 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1392 __tmp &= ~(1 << (stage)))
1393
1394 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1395 unsigned radv_format_meta_fs_key(VkFormat format);
1396
1397 struct radv_multisample_state {
1398 uint32_t db_eqaa;
1399 uint32_t pa_sc_line_cntl;
1400 uint32_t pa_sc_mode_cntl_0;
1401 uint32_t pa_sc_mode_cntl_1;
1402 uint32_t pa_sc_aa_config;
1403 uint32_t pa_sc_aa_mask[2];
1404 unsigned num_samples;
1405 };
1406
1407 struct radv_prim_vertex_count {
1408 uint8_t min;
1409 uint8_t incr;
1410 };
1411
1412 struct radv_vertex_elements_info {
1413 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1414 };
1415
1416 struct radv_ia_multi_vgt_param_helpers {
1417 uint32_t base;
1418 bool partial_es_wave;
1419 uint8_t primgroup_size;
1420 bool wd_switch_on_eop;
1421 bool ia_switch_on_eoi;
1422 bool partial_vs_wave;
1423 };
1424
1425 struct radv_binning_state {
1426 uint32_t pa_sc_binner_cntl_0;
1427 uint32_t db_dfsm_control;
1428 };
1429
1430 #define SI_GS_PER_ES 128
1431
1432 struct radv_pipeline {
1433 struct radv_device * device;
1434 struct radv_dynamic_state dynamic_state;
1435
1436 struct radv_pipeline_layout * layout;
1437
1438 bool need_indirect_descriptor_sets;
1439 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1440 struct radv_shader_variant *gs_copy_shader;
1441 VkShaderStageFlags active_stages;
1442
1443 struct radeon_cmdbuf cs;
1444 uint32_t ctx_cs_hash;
1445 struct radeon_cmdbuf ctx_cs;
1446
1447 struct radv_vertex_elements_info vertex_elements;
1448
1449 uint32_t binding_stride[MAX_VBS];
1450 uint8_t num_vertex_bindings;
1451
1452 uint32_t user_data_0[MESA_SHADER_STAGES];
1453 union {
1454 struct {
1455 struct radv_multisample_state ms;
1456 struct radv_binning_state binning;
1457 uint32_t spi_baryc_cntl;
1458 bool prim_restart_enable;
1459 unsigned esgs_ring_size;
1460 unsigned gsvs_ring_size;
1461 uint32_t vtx_base_sgpr;
1462 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1463 uint8_t vtx_emit_num;
1464 struct radv_prim_vertex_count prim_vertex_count;
1465 bool can_use_guardband;
1466 uint32_t needed_dynamic_state;
1467 bool disable_out_of_order_rast_for_occlusion;
1468
1469 /* Used for rbplus */
1470 uint32_t col_format;
1471 uint32_t cb_target_mask;
1472 } graphics;
1473 };
1474
1475 unsigned max_waves;
1476 unsigned scratch_bytes_per_wave;
1477
1478 /* Not NULL if graphics pipeline uses streamout. */
1479 struct radv_shader_variant *streamout_shader;
1480 };
1481
1482 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1483 {
1484 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1485 }
1486
1487 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1488 {
1489 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1490 }
1491
1492 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline);
1493
1494 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline);
1495
1496 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1497 gl_shader_stage stage,
1498 int idx);
1499
1500 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1501 gl_shader_stage stage);
1502
1503 struct radv_graphics_pipeline_create_info {
1504 bool use_rectlist;
1505 bool db_depth_clear;
1506 bool db_stencil_clear;
1507 bool db_depth_disable_expclear;
1508 bool db_stencil_disable_expclear;
1509 bool db_flush_depth_inplace;
1510 bool db_flush_stencil_inplace;
1511 bool db_resummarize;
1512 uint32_t custom_blend_mode;
1513 };
1514
1515 VkResult
1516 radv_graphics_pipeline_create(VkDevice device,
1517 VkPipelineCache cache,
1518 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1519 const struct radv_graphics_pipeline_create_info *extra,
1520 const VkAllocationCallbacks *alloc,
1521 VkPipeline *pPipeline);
1522
1523 struct vk_format_description;
1524 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1525 int first_non_void);
1526 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1527 int first_non_void);
1528 bool radv_is_buffer_format_supported(VkFormat format, bool *scaled);
1529 uint32_t radv_translate_colorformat(VkFormat format);
1530 uint32_t radv_translate_color_numformat(VkFormat format,
1531 const struct vk_format_description *desc,
1532 int first_non_void);
1533 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1534 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1535 uint32_t radv_translate_dbformat(VkFormat format);
1536 uint32_t radv_translate_tex_dataformat(VkFormat format,
1537 const struct vk_format_description *desc,
1538 int first_non_void);
1539 uint32_t radv_translate_tex_numformat(VkFormat format,
1540 const struct vk_format_description *desc,
1541 int first_non_void);
1542 bool radv_format_pack_clear_color(VkFormat format,
1543 uint32_t clear_vals[2],
1544 VkClearColorValue *value);
1545 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1546 bool radv_dcc_formats_compatible(VkFormat format1,
1547 VkFormat format2);
1548 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
1549
1550 struct radv_fmask_info {
1551 uint64_t offset;
1552 uint64_t size;
1553 unsigned alignment;
1554 unsigned pitch_in_pixels;
1555 unsigned bank_height;
1556 unsigned slice_tile_max;
1557 unsigned tile_mode_index;
1558 unsigned tile_swizzle;
1559 uint64_t slice_size;
1560 };
1561
1562 struct radv_cmask_info {
1563 uint64_t offset;
1564 uint64_t size;
1565 unsigned alignment;
1566 unsigned slice_tile_max;
1567 unsigned slice_size;
1568 };
1569
1570
1571 struct radv_image_plane {
1572 VkFormat format;
1573 struct radeon_surf surface;
1574 uint64_t offset;
1575 };
1576
1577 struct radv_image {
1578 VkImageType type;
1579 /* The original VkFormat provided by the client. This may not match any
1580 * of the actual surface formats.
1581 */
1582 VkFormat vk_format;
1583 VkImageAspectFlags aspects;
1584 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1585 struct ac_surf_info info;
1586 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1587 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1588
1589 VkDeviceSize size;
1590 uint32_t alignment;
1591
1592 unsigned queue_family_mask;
1593 bool exclusive;
1594 bool shareable;
1595
1596 /* Set when bound */
1597 struct radeon_winsys_bo *bo;
1598 VkDeviceSize offset;
1599 uint64_t dcc_offset;
1600 uint64_t htile_offset;
1601 bool tc_compatible_htile;
1602 bool tc_compatible_cmask;
1603
1604 struct radv_fmask_info fmask;
1605 struct radv_cmask_info cmask;
1606 uint64_t clear_value_offset;
1607 uint64_t fce_pred_offset;
1608 uint64_t dcc_pred_offset;
1609
1610 /*
1611 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1612 * stored at this offset is UINT_MAX, the driver will emit
1613 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1614 * SET_CONTEXT_REG packet.
1615 */
1616 uint64_t tc_compat_zrange_offset;
1617
1618 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1619 VkDeviceMemory owned_memory;
1620
1621 unsigned plane_count;
1622 struct radv_image_plane planes[0];
1623 };
1624
1625 /* Whether the image has a htile that is known consistent with the contents of
1626 * the image. */
1627 bool radv_layout_has_htile(const struct radv_image *image,
1628 VkImageLayout layout,
1629 unsigned queue_mask);
1630
1631 /* Whether the image has a htile that is known consistent with the contents of
1632 * the image and is allowed to be in compressed form.
1633 *
1634 * If this is false reads that don't use the htile should be able to return
1635 * correct results.
1636 */
1637 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1638 VkImageLayout layout,
1639 unsigned queue_mask);
1640
1641 bool radv_layout_can_fast_clear(const struct radv_image *image,
1642 VkImageLayout layout,
1643 unsigned queue_mask);
1644
1645 bool radv_layout_dcc_compressed(const struct radv_image *image,
1646 VkImageLayout layout,
1647 unsigned queue_mask);
1648
1649 /**
1650 * Return whether the image has CMASK metadata for color surfaces.
1651 */
1652 static inline bool
1653 radv_image_has_cmask(const struct radv_image *image)
1654 {
1655 return image->cmask.size;
1656 }
1657
1658 /**
1659 * Return whether the image has FMASK metadata for color surfaces.
1660 */
1661 static inline bool
1662 radv_image_has_fmask(const struct radv_image *image)
1663 {
1664 return image->fmask.size;
1665 }
1666
1667 /**
1668 * Return whether the image has DCC metadata for color surfaces.
1669 */
1670 static inline bool
1671 radv_image_has_dcc(const struct radv_image *image)
1672 {
1673 return image->planes[0].surface.dcc_size;
1674 }
1675
1676 /**
1677 * Return whether the image is TC-compatible CMASK.
1678 */
1679 static inline bool
1680 radv_image_is_tc_compat_cmask(const struct radv_image *image)
1681 {
1682 return radv_image_has_fmask(image) && image->tc_compatible_cmask;
1683 }
1684
1685 /**
1686 * Return whether DCC metadata is enabled for a level.
1687 */
1688 static inline bool
1689 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1690 {
1691 return radv_image_has_dcc(image) &&
1692 level < image->planes[0].surface.num_dcc_levels;
1693 }
1694
1695 /**
1696 * Return whether the image has CB metadata.
1697 */
1698 static inline bool
1699 radv_image_has_CB_metadata(const struct radv_image *image)
1700 {
1701 return radv_image_has_cmask(image) ||
1702 radv_image_has_fmask(image) ||
1703 radv_image_has_dcc(image);
1704 }
1705
1706 /**
1707 * Return whether the image has HTILE metadata for depth surfaces.
1708 */
1709 static inline bool
1710 radv_image_has_htile(const struct radv_image *image)
1711 {
1712 return image->planes[0].surface.htile_size;
1713 }
1714
1715 /**
1716 * Return whether HTILE metadata is enabled for a level.
1717 */
1718 static inline bool
1719 radv_htile_enabled(const struct radv_image *image, unsigned level)
1720 {
1721 return radv_image_has_htile(image) && level == 0;
1722 }
1723
1724 /**
1725 * Return whether the image is TC-compatible HTILE.
1726 */
1727 static inline bool
1728 radv_image_is_tc_compat_htile(const struct radv_image *image)
1729 {
1730 return radv_image_has_htile(image) && image->tc_compatible_htile;
1731 }
1732
1733 static inline uint64_t
1734 radv_image_get_fast_clear_va(const struct radv_image *image,
1735 uint32_t base_level)
1736 {
1737 uint64_t va = radv_buffer_get_va(image->bo);
1738 va += image->offset + image->clear_value_offset + base_level * 8;
1739 return va;
1740 }
1741
1742 static inline uint64_t
1743 radv_image_get_fce_pred_va(const struct radv_image *image,
1744 uint32_t base_level)
1745 {
1746 uint64_t va = radv_buffer_get_va(image->bo);
1747 va += image->offset + image->fce_pred_offset + base_level * 8;
1748 return va;
1749 }
1750
1751 static inline uint64_t
1752 radv_image_get_dcc_pred_va(const struct radv_image *image,
1753 uint32_t base_level)
1754 {
1755 uint64_t va = radv_buffer_get_va(image->bo);
1756 va += image->offset + image->dcc_pred_offset + base_level * 8;
1757 return va;
1758 }
1759
1760 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1761
1762 static inline uint32_t
1763 radv_get_layerCount(const struct radv_image *image,
1764 const VkImageSubresourceRange *range)
1765 {
1766 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1767 image->info.array_size - range->baseArrayLayer : range->layerCount;
1768 }
1769
1770 static inline uint32_t
1771 radv_get_levelCount(const struct radv_image *image,
1772 const VkImageSubresourceRange *range)
1773 {
1774 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1775 image->info.levels - range->baseMipLevel : range->levelCount;
1776 }
1777
1778 struct radeon_bo_metadata;
1779 void
1780 radv_init_metadata(struct radv_device *device,
1781 struct radv_image *image,
1782 struct radeon_bo_metadata *metadata);
1783
1784 void
1785 radv_image_override_offset_stride(struct radv_device *device,
1786 struct radv_image *image,
1787 uint64_t offset, uint32_t stride);
1788
1789 union radv_descriptor {
1790 struct {
1791 uint32_t plane0_descriptor[8];
1792 uint32_t fmask_descriptor[8];
1793 };
1794 struct {
1795 uint32_t plane_descriptors[3][8];
1796 };
1797 };
1798
1799 struct radv_image_view {
1800 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1801 struct radeon_winsys_bo *bo;
1802
1803 VkImageViewType type;
1804 VkImageAspectFlags aspect_mask;
1805 VkFormat vk_format;
1806 unsigned plane_id;
1807 bool multiple_planes;
1808 uint32_t base_layer;
1809 uint32_t layer_count;
1810 uint32_t base_mip;
1811 uint32_t level_count;
1812 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1813
1814 union radv_descriptor descriptor;
1815
1816 /* Descriptor for use as a storage image as opposed to a sampled image.
1817 * This has a few differences for cube maps (e.g. type).
1818 */
1819 union radv_descriptor storage_descriptor;
1820 };
1821
1822 struct radv_image_create_info {
1823 const VkImageCreateInfo *vk_info;
1824 bool scanout;
1825 bool no_metadata_planes;
1826 const struct radeon_bo_metadata *bo_metadata;
1827 };
1828
1829 VkResult radv_image_create(VkDevice _device,
1830 const struct radv_image_create_info *info,
1831 const VkAllocationCallbacks* alloc,
1832 VkImage *pImage);
1833
1834 VkResult
1835 radv_image_from_gralloc(VkDevice device_h,
1836 const VkImageCreateInfo *base_info,
1837 const VkNativeBufferANDROID *gralloc_info,
1838 const VkAllocationCallbacks *alloc,
1839 VkImage *out_image_h);
1840
1841 void radv_image_view_init(struct radv_image_view *view,
1842 struct radv_device *device,
1843 const VkImageViewCreateInfo* pCreateInfo);
1844
1845 VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
1846
1847 struct radv_sampler_ycbcr_conversion {
1848 VkFormat format;
1849 VkSamplerYcbcrModelConversion ycbcr_model;
1850 VkSamplerYcbcrRange ycbcr_range;
1851 VkComponentMapping components;
1852 VkChromaLocation chroma_offsets[2];
1853 VkFilter chroma_filter;
1854 };
1855
1856 struct radv_buffer_view {
1857 struct radeon_winsys_bo *bo;
1858 VkFormat vk_format;
1859 uint64_t range; /**< VkBufferViewCreateInfo::range */
1860 uint32_t state[4];
1861 };
1862 void radv_buffer_view_init(struct radv_buffer_view *view,
1863 struct radv_device *device,
1864 const VkBufferViewCreateInfo* pCreateInfo);
1865
1866 static inline struct VkExtent3D
1867 radv_sanitize_image_extent(const VkImageType imageType,
1868 const struct VkExtent3D imageExtent)
1869 {
1870 switch (imageType) {
1871 case VK_IMAGE_TYPE_1D:
1872 return (VkExtent3D) { imageExtent.width, 1, 1 };
1873 case VK_IMAGE_TYPE_2D:
1874 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1875 case VK_IMAGE_TYPE_3D:
1876 return imageExtent;
1877 default:
1878 unreachable("invalid image type");
1879 }
1880 }
1881
1882 static inline struct VkOffset3D
1883 radv_sanitize_image_offset(const VkImageType imageType,
1884 const struct VkOffset3D imageOffset)
1885 {
1886 switch (imageType) {
1887 case VK_IMAGE_TYPE_1D:
1888 return (VkOffset3D) { imageOffset.x, 0, 0 };
1889 case VK_IMAGE_TYPE_2D:
1890 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1891 case VK_IMAGE_TYPE_3D:
1892 return imageOffset;
1893 default:
1894 unreachable("invalid image type");
1895 }
1896 }
1897
1898 static inline bool
1899 radv_image_extent_compare(const struct radv_image *image,
1900 const VkExtent3D *extent)
1901 {
1902 if (extent->width != image->info.width ||
1903 extent->height != image->info.height ||
1904 extent->depth != image->info.depth)
1905 return false;
1906 return true;
1907 }
1908
1909 struct radv_sampler {
1910 uint32_t state[4];
1911 struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
1912 };
1913
1914 struct radv_color_buffer_info {
1915 uint64_t cb_color_base;
1916 uint64_t cb_color_cmask;
1917 uint64_t cb_color_fmask;
1918 uint64_t cb_dcc_base;
1919 uint32_t cb_color_slice;
1920 uint32_t cb_color_view;
1921 uint32_t cb_color_info;
1922 uint32_t cb_color_attrib;
1923 uint32_t cb_color_attrib2; /* GFX9 and later */
1924 uint32_t cb_color_attrib3; /* GFX10 and later */
1925 uint32_t cb_dcc_control;
1926 uint32_t cb_color_cmask_slice;
1927 uint32_t cb_color_fmask_slice;
1928 union {
1929 uint32_t cb_color_pitch; // GFX6-GFX8
1930 uint32_t cb_mrt_epitch; // GFX9+
1931 };
1932 };
1933
1934 struct radv_ds_buffer_info {
1935 uint64_t db_z_read_base;
1936 uint64_t db_stencil_read_base;
1937 uint64_t db_z_write_base;
1938 uint64_t db_stencil_write_base;
1939 uint64_t db_htile_data_base;
1940 uint32_t db_depth_info;
1941 uint32_t db_z_info;
1942 uint32_t db_stencil_info;
1943 uint32_t db_depth_view;
1944 uint32_t db_depth_size;
1945 uint32_t db_depth_slice;
1946 uint32_t db_htile_surface;
1947 uint32_t pa_su_poly_offset_db_fmt_cntl;
1948 uint32_t db_z_info2; /* GFX9 only */
1949 uint32_t db_stencil_info2; /* GFX9 only */
1950 float offset_scale;
1951 };
1952
1953 struct radv_attachment_info {
1954 union {
1955 struct radv_color_buffer_info cb;
1956 struct radv_ds_buffer_info ds;
1957 };
1958 struct radv_image_view *attachment;
1959 };
1960
1961 struct radv_framebuffer {
1962 uint32_t width;
1963 uint32_t height;
1964 uint32_t layers;
1965
1966 uint32_t attachment_count;
1967 struct radv_attachment_info attachments[0];
1968 };
1969
1970 struct radv_subpass_barrier {
1971 VkPipelineStageFlags src_stage_mask;
1972 VkAccessFlags src_access_mask;
1973 VkAccessFlags dst_access_mask;
1974 };
1975
1976 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1977 const struct radv_subpass_barrier *barrier);
1978
1979 struct radv_subpass_attachment {
1980 uint32_t attachment;
1981 VkImageLayout layout;
1982 };
1983
1984 struct radv_subpass {
1985 uint32_t attachment_count;
1986 struct radv_subpass_attachment * attachments;
1987
1988 uint32_t input_count;
1989 uint32_t color_count;
1990 struct radv_subpass_attachment * input_attachments;
1991 struct radv_subpass_attachment * color_attachments;
1992 struct radv_subpass_attachment * resolve_attachments;
1993 struct radv_subpass_attachment * depth_stencil_attachment;
1994 struct radv_subpass_attachment * ds_resolve_attachment;
1995 VkResolveModeFlagBitsKHR depth_resolve_mode;
1996 VkResolveModeFlagBitsKHR stencil_resolve_mode;
1997
1998 /** Subpass has at least one color resolve attachment */
1999 bool has_color_resolve;
2000
2001 /** Subpass has at least one color attachment */
2002 bool has_color_att;
2003
2004 struct radv_subpass_barrier start_barrier;
2005
2006 uint32_t view_mask;
2007 VkSampleCountFlagBits max_sample_count;
2008 };
2009
2010 uint32_t
2011 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer);
2012
2013 struct radv_render_pass_attachment {
2014 VkFormat format;
2015 uint32_t samples;
2016 VkAttachmentLoadOp load_op;
2017 VkAttachmentLoadOp stencil_load_op;
2018 VkImageLayout initial_layout;
2019 VkImageLayout final_layout;
2020
2021 /* The subpass id in which the attachment will be used first/last. */
2022 uint32_t first_subpass_idx;
2023 uint32_t last_subpass_idx;
2024 };
2025
2026 struct radv_render_pass {
2027 uint32_t attachment_count;
2028 uint32_t subpass_count;
2029 struct radv_subpass_attachment * subpass_attachments;
2030 struct radv_render_pass_attachment * attachments;
2031 struct radv_subpass_barrier end_barrier;
2032 struct radv_subpass subpasses[0];
2033 };
2034
2035 VkResult radv_device_init_meta(struct radv_device *device);
2036 void radv_device_finish_meta(struct radv_device *device);
2037
2038 struct radv_query_pool {
2039 struct radeon_winsys_bo *bo;
2040 uint32_t stride;
2041 uint32_t availability_offset;
2042 uint64_t size;
2043 char *ptr;
2044 VkQueryType type;
2045 uint32_t pipeline_stats_mask;
2046 };
2047
2048 struct radv_semaphore {
2049 /* use a winsys sem for non-exportable */
2050 struct radeon_winsys_sem *sem;
2051 uint32_t syncobj;
2052 uint32_t temp_syncobj;
2053 };
2054
2055 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2056 VkPipelineBindPoint bind_point,
2057 struct radv_descriptor_set *set,
2058 unsigned idx);
2059
2060 void
2061 radv_update_descriptor_sets(struct radv_device *device,
2062 struct radv_cmd_buffer *cmd_buffer,
2063 VkDescriptorSet overrideSet,
2064 uint32_t descriptorWriteCount,
2065 const VkWriteDescriptorSet *pDescriptorWrites,
2066 uint32_t descriptorCopyCount,
2067 const VkCopyDescriptorSet *pDescriptorCopies);
2068
2069 void
2070 radv_update_descriptor_set_with_template(struct radv_device *device,
2071 struct radv_cmd_buffer *cmd_buffer,
2072 struct radv_descriptor_set *set,
2073 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2074 const void *pData);
2075
2076 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2077 VkPipelineBindPoint pipelineBindPoint,
2078 VkPipelineLayout _layout,
2079 uint32_t set,
2080 uint32_t descriptorWriteCount,
2081 const VkWriteDescriptorSet *pDescriptorWrites);
2082
2083 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2084 struct radv_image *image,
2085 const VkImageSubresourceRange *range, uint32_t value);
2086
2087 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
2088 struct radv_image *image,
2089 const VkImageSubresourceRange *range);
2090
2091 struct radv_fence {
2092 struct radeon_winsys_fence *fence;
2093 struct wsi_fence *fence_wsi;
2094
2095 uint32_t syncobj;
2096 uint32_t temp_syncobj;
2097 };
2098
2099 /* radv_nir_to_llvm.c */
2100 struct radv_shader_variant_info;
2101 struct radv_nir_compiler_options;
2102
2103 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
2104 struct nir_shader *geom_shader,
2105 struct radv_shader_binary **rbinary,
2106 struct radv_shader_variant_info *shader_info,
2107 const struct radv_nir_compiler_options *option);
2108
2109 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
2110 struct radv_shader_binary **rbinary,
2111 struct radv_shader_variant_info *shader_info,
2112 struct nir_shader *const *nir,
2113 int nir_count,
2114 const struct radv_nir_compiler_options *options);
2115
2116 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
2117 gl_shader_stage stage,
2118 const struct nir_shader *nir);
2119
2120 /* radv_shader_info.h */
2121 struct radv_shader_info;
2122
2123 void radv_nir_shader_info_pass(const struct nir_shader *nir,
2124 const struct radv_nir_compiler_options *options,
2125 struct radv_shader_info *info);
2126
2127 void radv_nir_shader_info_init(struct radv_shader_info *info);
2128
2129 struct radeon_winsys_sem;
2130
2131 uint64_t radv_get_current_time(void);
2132
2133 static inline uint32_t
2134 si_conv_gl_prim_to_vertices(unsigned gl_prim)
2135 {
2136 switch (gl_prim) {
2137 case 0: /* GL_POINTS */
2138 return 1;
2139 case 1: /* GL_LINES */
2140 case 3: /* GL_LINE_STRIP */
2141 return 2;
2142 case 4: /* GL_TRIANGLES */
2143 case 5: /* GL_TRIANGLE_STRIP */
2144 return 3;
2145 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2146 return 4;
2147 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2148 return 6;
2149 case 7: /* GL_QUADS */
2150 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2151 default:
2152 assert(0);
2153 return 0;
2154 }
2155 }
2156
2157 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2158 \
2159 static inline struct __radv_type * \
2160 __radv_type ## _from_handle(__VkType _handle) \
2161 { \
2162 return (struct __radv_type *) _handle; \
2163 } \
2164 \
2165 static inline __VkType \
2166 __radv_type ## _to_handle(struct __radv_type *_obj) \
2167 { \
2168 return (__VkType) _obj; \
2169 }
2170
2171 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2172 \
2173 static inline struct __radv_type * \
2174 __radv_type ## _from_handle(__VkType _handle) \
2175 { \
2176 return (struct __radv_type *)(uintptr_t) _handle; \
2177 } \
2178 \
2179 static inline __VkType \
2180 __radv_type ## _to_handle(struct __radv_type *_obj) \
2181 { \
2182 return (__VkType)(uintptr_t) _obj; \
2183 }
2184
2185 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2186 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2187
2188 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
2189 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
2190 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
2191 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
2192 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
2193
2194 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
2195 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
2196 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
2197 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
2198 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
2199 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
2200 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
2201 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
2202 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
2203 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
2204 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
2205 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
2206 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
2207 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
2208 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
2209 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2210 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2211 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2212 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2213 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
2214 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2215 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2216
2217 #endif /* RADV_PRIVATE_H */