2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
54 #include "vk_debug_report.h"
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
68 #include <llvm-c/TargetMachine.h>
70 /* Pre-declarations needed for WSI entrypoints */
73 typedef struct xcb_connection_t xcb_connection_t
;
74 typedef uint32_t xcb_visualid_t
;
75 typedef uint32_t xcb_window_t
;
77 #include <vulkan/vulkan.h>
78 #include <vulkan/vulkan_intel.h>
79 #include <vulkan/vulkan_android.h>
80 #include <vulkan/vk_icd.h>
81 #include <vulkan/vk_android_native_buffer.h>
83 #include "radv_entrypoints.h"
85 #include "wsi_common.h"
86 #include "wsi_common_display.h"
88 /* Helper to determine if we should compile
89 * any of the Android AHB support.
91 * To actually enable the ext we also need
92 * the necessary kernel support.
94 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
95 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 1
97 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
101 struct gfx10_format
{
102 unsigned img_format
:9;
104 /* Various formats are only supported with workarounds for vertex fetch,
105 * and some 32_32_32 formats are supported natively, but only for buffers
106 * (possibly with some image support, actually, but no filtering). */
110 #include "gfx10_format_table.h"
114 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
121 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
122 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
123 RADV_MEM_TYPE_GTT_CACHED
,
127 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
129 static inline uint32_t
130 align_u32(uint32_t v
, uint32_t a
)
132 assert(a
!= 0 && a
== (a
& -a
));
133 return (v
+ a
- 1) & ~(a
- 1);
136 static inline uint32_t
137 align_u32_npot(uint32_t v
, uint32_t a
)
139 return (v
+ a
- 1) / a
* a
;
142 static inline uint64_t
143 align_u64(uint64_t v
, uint64_t a
)
145 assert(a
!= 0 && a
== (a
& -a
));
146 return (v
+ a
- 1) & ~(a
- 1);
149 static inline int32_t
150 align_i32(int32_t v
, int32_t a
)
152 assert(a
!= 0 && a
== (a
& -a
));
153 return (v
+ a
- 1) & ~(a
- 1);
156 /** Alignment must be a power of 2. */
158 radv_is_aligned(uintmax_t n
, uintmax_t a
)
160 assert(a
== (a
& -a
));
161 return (n
& (a
- 1)) == 0;
164 static inline uint32_t
165 round_up_u32(uint32_t v
, uint32_t a
)
167 return (v
+ a
- 1) / a
;
170 static inline uint64_t
171 round_up_u64(uint64_t v
, uint64_t a
)
173 return (v
+ a
- 1) / a
;
176 static inline uint32_t
177 radv_minify(uint32_t n
, uint32_t levels
)
179 if (unlikely(n
== 0))
182 return MAX2(n
>> levels
, 1);
185 radv_clamp_f(float f
, float min
, float max
)
198 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
200 if (*inout_mask
& clear_mask
) {
201 *inout_mask
&= ~clear_mask
;
208 #define for_each_bit(b, dword) \
209 for (uint32_t __dword = (dword); \
210 (b) = __builtin_ffs(__dword) - 1, __dword; \
211 __dword &= ~(1 << (b)))
213 #define typed_memcpy(dest, src, count) ({ \
214 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
215 memcpy((dest), (src), (count) * sizeof(*(src))); \
218 /* Whenever we generate an error, pass it through this function. Useful for
219 * debugging, where we can break on it. Only call at error site, not when
220 * propagating errors. Might be useful to plug in a stack trace here.
223 struct radv_image_view
;
224 struct radv_instance
;
226 VkResult
__vk_errorf(struct radv_instance
*instance
, VkResult error
, const char *file
, int line
, const char *format
, ...);
228 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
229 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
231 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
232 radv_printflike(3, 4);
233 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
234 void radv_loge_v(const char *format
, va_list va
);
235 void radv_logi(const char *format
, ...) radv_printflike(1, 2);
236 void radv_logi_v(const char *format
, va_list va
);
239 * Print a FINISHME message, including its source location.
241 #define radv_finishme(format, ...) \
243 static bool reported = false; \
245 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
250 /* A non-fatal assert. Useful for debugging. */
252 #define radv_assert(x) ({ \
253 if (unlikely(!(x))) \
254 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
257 #define radv_assert(x)
260 #define stub_return(v) \
262 radv_finishme("stub %s", __func__); \
268 radv_finishme("stub %s", __func__); \
272 void *radv_lookup_entrypoint_unchecked(const char *name
);
273 void *radv_lookup_entrypoint_checked(const char *name
,
274 uint32_t core_version
,
275 const struct radv_instance_extension_table
*instance
,
276 const struct radv_device_extension_table
*device
);
277 void *radv_lookup_physical_device_entrypoint_checked(const char *name
,
278 uint32_t core_version
,
279 const struct radv_instance_extension_table
*instance
);
281 struct radv_physical_device
{
282 VK_LOADER_DATA _loader_data
;
284 struct radv_instance
* instance
;
286 struct radeon_winsys
*ws
;
287 struct radeon_info rad_info
;
288 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
289 uint8_t driver_uuid
[VK_UUID_SIZE
];
290 uint8_t device_uuid
[VK_UUID_SIZE
];
291 uint8_t cache_uuid
[VK_UUID_SIZE
];
295 struct wsi_device wsi_device
;
297 bool out_of_order_rast_allowed
;
299 /* Whether DCC should be enabled for MSAA textures. */
300 bool dcc_msaa_allowed
;
302 /* Whether to enable the AMD_shader_ballot extension */
303 bool use_shader_ballot
;
305 /* Whether to enable NGG. */
308 /* Whether to enable NGG streamout. */
309 bool use_ngg_streamout
;
311 /* Number of threads per wave. */
312 uint8_t ps_wave_size
;
313 uint8_t cs_wave_size
;
314 uint8_t ge_wave_size
;
316 /* Whether to use the experimental compiler backend */
319 /* This is the drivers on-disk cache used as a fallback as opposed to
320 * the pipeline cache defined by apps.
322 struct disk_cache
* disk_cache
;
324 VkPhysicalDeviceMemoryProperties memory_properties
;
325 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
327 drmPciBusInfo bus_info
;
329 struct radv_device_extension_table supported_extensions
;
332 struct radv_instance
{
333 VK_LOADER_DATA _loader_data
;
335 VkAllocationCallbacks alloc
;
338 int physicalDeviceCount
;
339 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
342 uint32_t engineVersion
;
344 uint64_t debug_flags
;
345 uint64_t perftest_flags
;
347 struct vk_debug_report_instance debug_report_callbacks
;
349 struct radv_instance_extension_table enabled_extensions
;
351 struct driOptionCache dri_options
;
352 struct driOptionCache available_dri_options
;
355 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
356 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
358 bool radv_instance_extension_supported(const char *name
);
359 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
360 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
365 struct radv_pipeline_cache
{
366 struct radv_device
* device
;
367 pthread_mutex_t mutex
;
371 uint32_t kernel_count
;
372 struct cache_entry
** hash_table
;
375 VkAllocationCallbacks alloc
;
378 struct radv_pipeline_key
{
379 uint32_t instance_rate_inputs
;
380 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
381 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
382 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
383 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
384 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
385 uint64_t vertex_alpha_adjust
;
386 uint32_t vertex_post_shuffle
;
387 unsigned tess_input_vertices
;
391 uint8_t log2_ps_iter_samples
;
393 uint32_t has_multiview_view_index
: 1;
394 uint32_t optimisations_disabled
: 1;
398 struct radv_shader_binary
;
399 struct radv_shader_variant
;
402 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
403 struct radv_device
*device
);
405 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
407 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
408 const void *data
, size_t size
);
411 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
412 struct radv_pipeline_cache
*cache
,
413 const unsigned char *sha1
,
414 struct radv_shader_variant
**variants
,
415 bool *found_in_application_cache
);
418 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
419 struct radv_pipeline_cache
*cache
,
420 const unsigned char *sha1
,
421 struct radv_shader_variant
**variants
,
422 struct radv_shader_binary
*const *binaries
);
424 enum radv_blit_ds_layout
{
425 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
426 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
427 RADV_BLIT_DS_LAYOUT_COUNT
,
430 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
432 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
435 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
437 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
440 enum radv_meta_dst_layout
{
441 RADV_META_DST_LAYOUT_GENERAL
,
442 RADV_META_DST_LAYOUT_OPTIMAL
,
443 RADV_META_DST_LAYOUT_COUNT
,
446 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
448 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
451 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
453 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
456 struct radv_meta_state
{
457 VkAllocationCallbacks alloc
;
459 struct radv_pipeline_cache cache
;
462 * For on-demand pipeline creation, makes sure that
463 * only one thread tries to build a pipeline at the same time.
468 * Use array element `i` for images with `2^i` samples.
471 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
472 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
474 VkRenderPass depthstencil_rp
;
475 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
476 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
477 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
479 VkPipeline depth_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
480 VkPipeline stencil_only_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
481 VkPipeline depthstencil_unrestricted_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
482 } clear
[MAX_SAMPLES_LOG2
];
484 VkPipelineLayout clear_color_p_layout
;
485 VkPipelineLayout clear_depth_p_layout
;
486 VkPipelineLayout clear_depth_unrestricted_p_layout
;
488 /* Optimized compute fast HTILE clear for stencil or depth only. */
489 VkPipeline clear_htile_mask_pipeline
;
490 VkPipelineLayout clear_htile_mask_p_layout
;
491 VkDescriptorSetLayout clear_htile_mask_ds_layout
;
494 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
496 /** Pipeline that blits from a 1D image. */
497 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
499 /** Pipeline that blits from a 2D image. */
500 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
502 /** Pipeline that blits from a 3D image. */
503 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
505 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
506 VkPipeline depth_only_1d_pipeline
;
507 VkPipeline depth_only_2d_pipeline
;
508 VkPipeline depth_only_3d_pipeline
;
510 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
511 VkPipeline stencil_only_1d_pipeline
;
512 VkPipeline stencil_only_2d_pipeline
;
513 VkPipeline stencil_only_3d_pipeline
;
514 VkPipelineLayout pipeline_layout
;
515 VkDescriptorSetLayout ds_layout
;
519 VkPipelineLayout p_layouts
[5];
520 VkDescriptorSetLayout ds_layouts
[5];
521 VkPipeline pipelines
[5][NUM_META_FS_KEYS
];
523 VkPipeline depth_only_pipeline
[5];
525 VkPipeline stencil_only_pipeline
[5];
526 } blit2d
[MAX_SAMPLES_LOG2
];
528 VkRenderPass blit2d_render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
529 VkRenderPass blit2d_depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
530 VkRenderPass blit2d_stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
533 VkPipelineLayout img_p_layout
;
534 VkDescriptorSetLayout img_ds_layout
;
536 VkPipeline pipeline_3d
;
539 VkPipelineLayout img_p_layout
;
540 VkDescriptorSetLayout img_ds_layout
;
542 VkPipeline pipeline_3d
;
545 VkPipelineLayout img_p_layout
;
546 VkDescriptorSetLayout img_ds_layout
;
550 VkPipelineLayout img_p_layout
;
551 VkDescriptorSetLayout img_ds_layout
;
553 VkPipeline pipeline_3d
;
556 VkPipelineLayout img_p_layout
;
557 VkDescriptorSetLayout img_ds_layout
;
561 VkPipelineLayout img_p_layout
;
562 VkDescriptorSetLayout img_ds_layout
;
564 VkPipeline pipeline_3d
;
567 VkPipelineLayout img_p_layout
;
568 VkDescriptorSetLayout img_ds_layout
;
573 VkPipelineLayout p_layout
;
574 VkPipeline pipeline
[NUM_META_FS_KEYS
];
575 VkRenderPass pass
[NUM_META_FS_KEYS
];
579 VkDescriptorSetLayout ds_layout
;
580 VkPipelineLayout p_layout
;
583 VkPipeline i_pipeline
;
584 VkPipeline srgb_pipeline
;
585 } rc
[MAX_SAMPLES_LOG2
];
587 VkPipeline depth_zero_pipeline
;
589 VkPipeline average_pipeline
;
590 VkPipeline max_pipeline
;
591 VkPipeline min_pipeline
;
592 } depth
[MAX_SAMPLES_LOG2
];
594 VkPipeline stencil_zero_pipeline
;
596 VkPipeline max_pipeline
;
597 VkPipeline min_pipeline
;
598 } stencil
[MAX_SAMPLES_LOG2
];
602 VkDescriptorSetLayout ds_layout
;
603 VkPipelineLayout p_layout
;
606 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
607 VkPipeline pipeline
[NUM_META_FS_KEYS
];
608 } rc
[MAX_SAMPLES_LOG2
];
610 VkRenderPass depth_render_pass
;
611 VkPipeline depth_zero_pipeline
;
613 VkPipeline average_pipeline
;
614 VkPipeline max_pipeline
;
615 VkPipeline min_pipeline
;
616 } depth
[MAX_SAMPLES_LOG2
];
618 VkRenderPass stencil_render_pass
;
619 VkPipeline stencil_zero_pipeline
;
621 VkPipeline max_pipeline
;
622 VkPipeline min_pipeline
;
623 } stencil
[MAX_SAMPLES_LOG2
];
627 VkPipelineLayout p_layout
;
628 VkPipeline decompress_pipeline
;
629 VkPipeline resummarize_pipeline
;
631 } depth_decomp
[MAX_SAMPLES_LOG2
];
634 VkPipelineLayout p_layout
;
635 VkPipeline cmask_eliminate_pipeline
;
636 VkPipeline fmask_decompress_pipeline
;
637 VkPipeline dcc_decompress_pipeline
;
640 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
641 VkPipelineLayout dcc_decompress_compute_p_layout
;
642 VkPipeline dcc_decompress_compute_pipeline
;
646 VkPipelineLayout fill_p_layout
;
647 VkPipelineLayout copy_p_layout
;
648 VkDescriptorSetLayout fill_ds_layout
;
649 VkDescriptorSetLayout copy_ds_layout
;
650 VkPipeline fill_pipeline
;
651 VkPipeline copy_pipeline
;
655 VkDescriptorSetLayout ds_layout
;
656 VkPipelineLayout p_layout
;
657 VkPipeline occlusion_query_pipeline
;
658 VkPipeline pipeline_statistics_query_pipeline
;
659 VkPipeline tfb_query_pipeline
;
660 VkPipeline timestamp_query_pipeline
;
664 VkDescriptorSetLayout ds_layout
;
665 VkPipelineLayout p_layout
;
666 VkPipeline pipeline
[MAX_SAMPLES_LOG2
];
671 #define RADV_QUEUE_GENERAL 0
672 #define RADV_QUEUE_COMPUTE 1
673 #define RADV_QUEUE_TRANSFER 2
675 #define RADV_MAX_QUEUE_FAMILIES 3
677 enum ring_type
radv_queue_family_to_ring(int f
);
680 VK_LOADER_DATA _loader_data
;
681 struct radv_device
* device
;
682 struct radeon_winsys_ctx
*hw_ctx
;
683 enum radeon_ctx_priority priority
;
684 uint32_t queue_family_index
;
686 VkDeviceQueueCreateFlags flags
;
688 uint32_t scratch_size
;
689 uint32_t compute_scratch_size
;
690 uint32_t esgs_ring_size
;
691 uint32_t gsvs_ring_size
;
694 bool has_sample_positions
;
696 struct radeon_winsys_bo
*scratch_bo
;
697 struct radeon_winsys_bo
*descriptor_bo
;
698 struct radeon_winsys_bo
*compute_scratch_bo
;
699 struct radeon_winsys_bo
*esgs_ring_bo
;
700 struct radeon_winsys_bo
*gsvs_ring_bo
;
701 struct radeon_winsys_bo
*tess_rings_bo
;
702 struct radeon_winsys_bo
*gds_bo
;
703 struct radeon_winsys_bo
*gds_oa_bo
;
704 struct radeon_cmdbuf
*initial_preamble_cs
;
705 struct radeon_cmdbuf
*initial_full_flush_preamble_cs
;
706 struct radeon_cmdbuf
*continue_preamble_cs
;
709 struct radv_bo_list
{
710 struct radv_winsys_bo_list list
;
712 pthread_mutex_t mutex
;
716 VK_LOADER_DATA _loader_data
;
718 VkAllocationCallbacks alloc
;
720 struct radv_instance
* instance
;
721 struct radeon_winsys
*ws
;
723 struct radv_meta_state meta_state
;
725 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
726 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
727 struct radeon_cmdbuf
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
729 bool always_use_syncobj
;
732 uint32_t tess_offchip_block_dw_size
;
733 uint32_t scratch_waves
;
734 uint32_t dispatch_initiator
;
736 uint32_t gs_table_depth
;
738 /* MSAA sample locations.
739 * The first index is the sample index.
740 * The second index is the coordinate: X, Y. */
741 float sample_locations_1x
[1][2];
742 float sample_locations_2x
[2][2];
743 float sample_locations_4x
[4][2];
744 float sample_locations_8x
[8][2];
747 uint32_t gfx_init_size_dw
;
748 struct radeon_winsys_bo
*gfx_init
;
750 struct radeon_winsys_bo
*trace_bo
;
751 uint32_t *trace_id_ptr
;
753 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
754 bool keep_shader_info
;
756 struct radv_physical_device
*physical_device
;
758 /* Backup in-memory cache to be used if the app doesn't provide one */
759 struct radv_pipeline_cache
* mem_cache
;
762 * use different counters so MSAA MRTs get consecutive surface indices,
763 * even if MASK is allocated in between.
765 uint32_t image_mrt_offset_counter
;
766 uint32_t fmask_mrt_offset_counter
;
767 struct list_head shader_slabs
;
768 mtx_t shader_slab_mutex
;
770 /* For detecting VM faults reported by dmesg. */
771 uint64_t dmesg_timestamp
;
773 struct radv_device_extension_table enabled_extensions
;
775 /* Whether the app has enabled the robustBufferAccess feature. */
776 bool robust_buffer_access
;
778 /* Whether the driver uses a global BO list. */
779 bool use_global_bo_list
;
781 struct radv_bo_list bo_list
;
783 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
787 struct radv_device_memory
{
788 struct radeon_winsys_bo
*bo
;
789 /* for dedicated allocations */
790 struct radv_image
*image
;
791 struct radv_buffer
*buffer
;
793 VkDeviceSize map_size
;
797 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
798 struct AHardwareBuffer
* android_hardware_buffer
;
803 struct radv_descriptor_range
{
808 struct radv_descriptor_set
{
809 const struct radv_descriptor_set_layout
*layout
;
812 struct radeon_winsys_bo
*bo
;
814 uint32_t *mapped_ptr
;
815 struct radv_descriptor_range
*dynamic_descriptors
;
817 struct radeon_winsys_bo
*descriptors
[0];
820 struct radv_push_descriptor_set
822 struct radv_descriptor_set set
;
826 struct radv_descriptor_pool_entry
{
829 struct radv_descriptor_set
*set
;
832 struct radv_descriptor_pool
{
833 struct radeon_winsys_bo
*bo
;
835 uint64_t current_offset
;
838 uint8_t *host_memory_base
;
839 uint8_t *host_memory_ptr
;
840 uint8_t *host_memory_end
;
842 uint32_t entry_count
;
843 uint32_t max_entry_count
;
844 struct radv_descriptor_pool_entry entries
[0];
847 struct radv_descriptor_update_template_entry
{
848 VkDescriptorType descriptor_type
;
850 /* The number of descriptors to update */
851 uint32_t descriptor_count
;
853 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
856 /* In dwords. Not valid/used for dynamic descriptors */
859 uint32_t buffer_offset
;
861 /* Only valid for combined image samplers and samplers */
863 uint8_t sampler_offset
;
869 /* For push descriptors */
870 const uint32_t *immutable_samplers
;
873 struct radv_descriptor_update_template
{
874 uint32_t entry_count
;
875 VkPipelineBindPoint bind_point
;
876 struct radv_descriptor_update_template_entry entry
[0];
882 VkBufferUsageFlags usage
;
883 VkBufferCreateFlags flags
;
886 struct radeon_winsys_bo
* bo
;
892 enum radv_dynamic_state_bits
{
893 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
894 RADV_DYNAMIC_SCISSOR
= 1 << 1,
895 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
896 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
897 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
898 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
899 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
900 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
901 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
902 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
903 RADV_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
904 RADV_DYNAMIC_ALL
= (1 << 11) - 1,
907 enum radv_cmd_dirty_bits
{
908 /* Keep the dynamic state dirty bits in sync with
909 * enum radv_dynamic_state_bits */
910 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
911 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
912 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
913 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
914 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
915 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
916 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
917 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
918 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
919 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
920 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
921 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 11) - 1,
922 RADV_CMD_DIRTY_PIPELINE
= 1 << 11,
923 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 12,
924 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 13,
925 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 14,
926 RADV_CMD_DIRTY_STREAMOUT_BUFFER
= 1 << 15,
929 enum radv_cmd_flush_bits
{
930 /* Instruction cache. */
931 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
932 /* Scalar L1 cache. */
933 RADV_CMD_FLAG_INV_SCACHE
= 1 << 1,
934 /* Vector L1 cache. */
935 RADV_CMD_FLAG_INV_VCACHE
= 1 << 2,
936 /* L2 cache + L2 metadata cache writeback & invalidate.
937 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
938 RADV_CMD_FLAG_INV_L2
= 1 << 3,
939 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
940 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
941 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
942 RADV_CMD_FLAG_WB_L2
= 1 << 4,
943 /* Framebuffer caches */
944 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
945 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
946 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
947 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
948 /* Engine synchronization. */
949 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
950 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
951 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
952 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
953 /* Pipeline query controls. */
954 RADV_CMD_FLAG_START_PIPELINE_STATS
= 1 << 13,
955 RADV_CMD_FLAG_STOP_PIPELINE_STATS
= 1 << 14,
956 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
= 1 << 15,
958 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
959 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
960 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
961 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
964 struct radv_vertex_binding
{
965 struct radv_buffer
* buffer
;
969 struct radv_streamout_binding
{
970 struct radv_buffer
*buffer
;
975 struct radv_streamout_state
{
976 /* Mask of bound streamout buffers. */
977 uint8_t enabled_mask
;
979 /* External state that comes from the last vertex stage, it must be
980 * set explicitely when binding a new graphics pipeline.
982 uint16_t stride_in_dw
[MAX_SO_BUFFERS
];
983 uint32_t enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
985 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
986 uint32_t hw_enabled_mask
;
988 /* State of VGT_STRMOUT_(CONFIG|EN) */
989 bool streamout_enabled
;
992 struct radv_viewport_state
{
994 VkViewport viewports
[MAX_VIEWPORTS
];
997 struct radv_scissor_state
{
999 VkRect2D scissors
[MAX_SCISSORS
];
1002 struct radv_discard_rectangle_state
{
1004 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
1007 struct radv_sample_locations_state
{
1008 VkSampleCountFlagBits per_pixel
;
1009 VkExtent2D grid_size
;
1011 VkSampleLocationEXT locations
[MAX_SAMPLE_LOCATIONS
];
1014 struct radv_dynamic_state
{
1016 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1017 * Defines the set of saved dynamic state.
1021 struct radv_viewport_state viewport
;
1023 struct radv_scissor_state scissor
;
1033 float blend_constants
[4];
1043 } stencil_compare_mask
;
1048 } stencil_write_mask
;
1053 } stencil_reference
;
1055 struct radv_discard_rectangle_state discard_rectangle
;
1057 struct radv_sample_locations_state sample_location
;
1060 extern const struct radv_dynamic_state default_dynamic_state
;
1063 radv_get_debug_option_name(int id
);
1066 radv_get_perftest_option_name(int id
);
1068 struct radv_color_buffer_info
{
1069 uint64_t cb_color_base
;
1070 uint64_t cb_color_cmask
;
1071 uint64_t cb_color_fmask
;
1072 uint64_t cb_dcc_base
;
1073 uint32_t cb_color_slice
;
1074 uint32_t cb_color_view
;
1075 uint32_t cb_color_info
;
1076 uint32_t cb_color_attrib
;
1077 uint32_t cb_color_attrib2
; /* GFX9 and later */
1078 uint32_t cb_color_attrib3
; /* GFX10 and later */
1079 uint32_t cb_dcc_control
;
1080 uint32_t cb_color_cmask_slice
;
1081 uint32_t cb_color_fmask_slice
;
1083 uint32_t cb_color_pitch
; // GFX6-GFX8
1084 uint32_t cb_mrt_epitch
; // GFX9+
1088 struct radv_ds_buffer_info
{
1089 uint64_t db_z_read_base
;
1090 uint64_t db_stencil_read_base
;
1091 uint64_t db_z_write_base
;
1092 uint64_t db_stencil_write_base
;
1093 uint64_t db_htile_data_base
;
1094 uint32_t db_depth_info
;
1096 uint32_t db_stencil_info
;
1097 uint32_t db_depth_view
;
1098 uint32_t db_depth_size
;
1099 uint32_t db_depth_slice
;
1100 uint32_t db_htile_surface
;
1101 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1102 uint32_t db_z_info2
; /* GFX9 only */
1103 uint32_t db_stencil_info2
; /* GFX9 only */
1108 radv_initialise_color_surface(struct radv_device
*device
,
1109 struct radv_color_buffer_info
*cb
,
1110 struct radv_image_view
*iview
);
1112 radv_initialise_ds_surface(struct radv_device
*device
,
1113 struct radv_ds_buffer_info
*ds
,
1114 struct radv_image_view
*iview
);
1117 * Attachment state when recording a renderpass instance.
1119 * The clear value is valid only if there exists a pending clear.
1121 struct radv_attachment_state
{
1122 VkImageAspectFlags pending_clear_aspects
;
1123 uint32_t cleared_views
;
1124 VkClearValue clear_value
;
1125 VkImageLayout current_layout
;
1126 bool current_in_render_loop
;
1127 struct radv_sample_locations_state sample_location
;
1130 struct radv_color_buffer_info cb
;
1131 struct radv_ds_buffer_info ds
;
1133 struct radv_image_view
*iview
;
1136 struct radv_descriptor_state
{
1137 struct radv_descriptor_set
*sets
[MAX_SETS
];
1140 struct radv_push_descriptor_set push_set
;
1142 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
1145 struct radv_subpass_sample_locs_state
{
1146 uint32_t subpass_idx
;
1147 struct radv_sample_locations_state sample_location
;
1150 struct radv_cmd_state
{
1151 /* Vertex descriptors */
1158 uint32_t prefetch_L2_mask
;
1160 struct radv_pipeline
* pipeline
;
1161 struct radv_pipeline
* emitted_pipeline
;
1162 struct radv_pipeline
* compute_pipeline
;
1163 struct radv_pipeline
* emitted_compute_pipeline
;
1164 struct radv_framebuffer
* framebuffer
;
1165 struct radv_render_pass
* pass
;
1166 const struct radv_subpass
* subpass
;
1167 struct radv_dynamic_state dynamic
;
1168 struct radv_attachment_state
* attachments
;
1169 struct radv_streamout_state streamout
;
1170 VkRect2D render_area
;
1172 uint32_t num_subpass_sample_locs
;
1173 struct radv_subpass_sample_locs_state
* subpass_sample_locs
;
1176 struct radv_buffer
*index_buffer
;
1177 uint64_t index_offset
;
1178 uint32_t index_type
;
1179 uint32_t max_index_count
;
1181 int32_t last_index_type
;
1183 int32_t last_primitive_reset_en
;
1184 uint32_t last_primitive_reset_index
;
1185 enum radv_cmd_flush_bits flush_bits
;
1186 unsigned active_occlusion_queries
;
1187 bool perfect_occlusion_queries_enabled
;
1188 unsigned active_pipeline_queries
;
1191 uint32_t last_ia_multi_vgt_param
;
1193 uint32_t last_num_instances
;
1194 uint32_t last_first_instance
;
1195 uint32_t last_vertex_offset
;
1197 /* Whether CP DMA is busy/idle. */
1200 /* Conditional rendering info. */
1201 int predication_type
; /* -1: disabled, 0: normal, 1: inverted */
1202 uint64_t predication_va
;
1204 bool context_roll_without_scissor_emitted
;
1207 struct radv_cmd_pool
{
1208 VkAllocationCallbacks alloc
;
1209 struct list_head cmd_buffers
;
1210 struct list_head free_cmd_buffers
;
1211 uint32_t queue_family_index
;
1214 struct radv_cmd_buffer_upload
{
1218 struct radeon_winsys_bo
*upload_bo
;
1219 struct list_head list
;
1222 enum radv_cmd_buffer_status
{
1223 RADV_CMD_BUFFER_STATUS_INVALID
,
1224 RADV_CMD_BUFFER_STATUS_INITIAL
,
1225 RADV_CMD_BUFFER_STATUS_RECORDING
,
1226 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
1227 RADV_CMD_BUFFER_STATUS_PENDING
,
1230 struct radv_cmd_buffer
{
1231 VK_LOADER_DATA _loader_data
;
1233 struct radv_device
* device
;
1235 struct radv_cmd_pool
* pool
;
1236 struct list_head pool_link
;
1238 VkCommandBufferUsageFlags usage_flags
;
1239 VkCommandBufferLevel level
;
1240 enum radv_cmd_buffer_status status
;
1241 struct radeon_cmdbuf
*cs
;
1242 struct radv_cmd_state state
;
1243 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
1244 struct radv_streamout_binding streamout_bindings
[MAX_SO_BUFFERS
];
1245 uint32_t queue_family_index
;
1247 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1248 VkShaderStageFlags push_constant_stages
;
1249 struct radv_descriptor_set meta_push_descriptors
;
1251 struct radv_descriptor_state descriptors
[VK_PIPELINE_BIND_POINT_RANGE_SIZE
];
1253 struct radv_cmd_buffer_upload upload
;
1255 uint32_t scratch_size_needed
;
1256 uint32_t compute_scratch_size_needed
;
1257 uint32_t esgs_ring_size_needed
;
1258 uint32_t gsvs_ring_size_needed
;
1259 bool tess_rings_needed
;
1260 bool gds_needed
; /* for GFX10 streamout */
1261 bool sample_positions_needed
;
1263 VkResult record_result
;
1265 uint64_t gfx9_fence_va
;
1266 uint32_t gfx9_fence_idx
;
1267 uint64_t gfx9_eop_bug_va
;
1270 * Whether a query pool has been resetted and we have to flush caches.
1272 bool pending_reset_query
;
1275 * Bitmask of pending active query flushes.
1277 enum radv_cmd_flush_bits active_query_flush_bits
;
1281 struct radv_image_view
;
1283 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1285 void si_emit_graphics(struct radv_physical_device
*physical_device
,
1286 struct radeon_cmdbuf
*cs
);
1287 void si_emit_compute(struct radv_physical_device
*physical_device
,
1288 struct radeon_cmdbuf
*cs
);
1290 void cik_create_gfx_config(struct radv_device
*device
);
1292 void si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
1293 int count
, const VkViewport
*viewports
);
1294 void si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
1295 int count
, const VkRect2D
*scissors
,
1296 const VkViewport
*viewports
, bool can_use_guardband
);
1297 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1298 bool instanced_draw
, bool indirect_draw
,
1299 bool count_from_stream_output
,
1300 uint32_t draw_vertex_count
);
1301 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
1302 enum chip_class chip_class
,
1304 unsigned event
, unsigned event_flags
,
1305 unsigned dst_sel
, unsigned data_sel
,
1308 uint64_t gfx9_eop_bug_va
);
1310 void radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
1311 uint32_t ref
, uint32_t mask
);
1312 void si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1313 enum chip_class chip_class
,
1314 uint32_t *fence_ptr
, uint64_t va
,
1316 enum radv_cmd_flush_bits flush_bits
,
1317 uint64_t gfx9_eop_bug_va
);
1318 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1319 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1320 bool inverted
, uint64_t va
);
1321 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1322 uint64_t src_va
, uint64_t dest_va
,
1324 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1326 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1327 uint64_t size
, unsigned value
);
1328 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
);
1330 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1332 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1335 unsigned *out_offset
,
1338 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1339 const struct radv_subpass
*subpass
);
1341 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1342 unsigned size
, unsigned alignmnet
,
1343 const void *data
, unsigned *out_offset
);
1345 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1346 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1347 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1348 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
,
1349 VkImageAspectFlags aspects
,
1350 VkResolveModeFlagBitsKHR resolve_mode
);
1351 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1352 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
,
1353 VkImageAspectFlags aspects
,
1354 VkResolveModeFlagBitsKHR resolve_mode
);
1355 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
);
1356 unsigned radv_get_default_max_sample_dist(int log_samples
);
1357 void radv_device_init_msaa(struct radv_device
*device
);
1359 void radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1360 const struct radv_image_view
*iview
,
1361 VkClearDepthStencilValue ds_clear_value
,
1362 VkImageAspectFlags aspects
);
1364 void radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1365 const struct radv_image_view
*iview
,
1367 uint32_t color_values
[2]);
1369 void radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1370 struct radv_image
*image
,
1371 const VkImageSubresourceRange
*range
, bool value
);
1373 void radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1374 struct radv_image
*image
,
1375 const VkImageSubresourceRange
*range
, bool value
);
1377 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1378 struct radeon_winsys_bo
*bo
,
1379 uint64_t offset
, uint64_t size
, uint32_t value
);
1380 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1381 bool radv_get_memory_fd(struct radv_device
*device
,
1382 struct radv_device_memory
*memory
,
1386 radv_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
1387 unsigned sh_offset
, unsigned pointer_count
,
1388 bool use_32bit_pointers
)
1390 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (use_32bit_pointers
? 1 : 2), 0));
1391 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1395 radv_emit_shader_pointer_body(struct radv_device
*device
,
1396 struct radeon_cmdbuf
*cs
,
1397 uint64_t va
, bool use_32bit_pointers
)
1399 radeon_emit(cs
, va
);
1401 if (use_32bit_pointers
) {
1403 (va
>> 32) == device
->physical_device
->rad_info
.address32_hi
);
1405 radeon_emit(cs
, va
>> 32);
1410 radv_emit_shader_pointer(struct radv_device
*device
,
1411 struct radeon_cmdbuf
*cs
,
1412 uint32_t sh_offset
, uint64_t va
, bool global
)
1414 bool use_32bit_pointers
= !global
;
1416 radv_emit_shader_pointer_head(cs
, sh_offset
, 1, use_32bit_pointers
);
1417 radv_emit_shader_pointer_body(device
, cs
, va
, use_32bit_pointers
);
1420 static inline struct radv_descriptor_state
*
1421 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1422 VkPipelineBindPoint bind_point
)
1424 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1425 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1426 return &cmd_buffer
->descriptors
[bind_point
];
1430 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1432 * Limitations: Can't call normal dispatch functions without binding or rebinding
1433 * the compute pipeline.
1435 void radv_unaligned_dispatch(
1436 struct radv_cmd_buffer
*cmd_buffer
,
1442 struct radeon_winsys_bo
*bo
;
1446 struct radv_shader_module
;
1448 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1449 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1450 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1451 #define RADV_HASH_SHADER_NO_NGG (1 << 3)
1452 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 4)
1453 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 5)
1454 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 6)
1455 #define RADV_HASH_SHADER_ACO (1 << 7)
1458 radv_hash_shaders(unsigned char *hash
,
1459 const VkPipelineShaderStageCreateInfo
**stages
,
1460 const struct radv_pipeline_layout
*layout
,
1461 const struct radv_pipeline_key
*key
,
1464 static inline gl_shader_stage
1465 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1467 assert(__builtin_popcount(vk_stage
) == 1);
1468 return ffs(vk_stage
) - 1;
1471 static inline VkShaderStageFlagBits
1472 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1474 return (1 << mesa_stage
);
1477 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1479 #define radv_foreach_stage(stage, stage_bits) \
1480 for (gl_shader_stage stage, \
1481 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1482 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1483 __tmp &= ~(1 << (stage)))
1485 extern const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
];
1486 unsigned radv_format_meta_fs_key(VkFormat format
);
1488 struct radv_multisample_state
{
1490 uint32_t pa_sc_line_cntl
;
1491 uint32_t pa_sc_mode_cntl_0
;
1492 uint32_t pa_sc_mode_cntl_1
;
1493 uint32_t pa_sc_aa_config
;
1494 uint32_t pa_sc_aa_mask
[2];
1495 unsigned num_samples
;
1498 struct radv_prim_vertex_count
{
1503 struct radv_vertex_elements_info
{
1504 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1507 struct radv_ia_multi_vgt_param_helpers
{
1509 bool partial_es_wave
;
1510 uint8_t primgroup_size
;
1511 bool wd_switch_on_eop
;
1512 bool ia_switch_on_eoi
;
1513 bool partial_vs_wave
;
1516 struct radv_binning_state
{
1517 uint32_t pa_sc_binner_cntl_0
;
1518 uint32_t db_dfsm_control
;
1521 #define SI_GS_PER_ES 128
1523 struct radv_pipeline
{
1524 struct radv_device
* device
;
1525 struct radv_dynamic_state dynamic_state
;
1527 struct radv_pipeline_layout
* layout
;
1529 bool need_indirect_descriptor_sets
;
1530 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1531 struct radv_shader_variant
*gs_copy_shader
;
1532 VkShaderStageFlags active_stages
;
1534 struct radeon_cmdbuf cs
;
1535 uint32_t ctx_cs_hash
;
1536 struct radeon_cmdbuf ctx_cs
;
1538 struct radv_vertex_elements_info vertex_elements
;
1540 uint32_t binding_stride
[MAX_VBS
];
1541 uint8_t num_vertex_bindings
;
1543 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1546 struct radv_multisample_state ms
;
1547 struct radv_binning_state binning
;
1548 uint32_t spi_baryc_cntl
;
1549 bool prim_restart_enable
;
1550 unsigned esgs_ring_size
;
1551 unsigned gsvs_ring_size
;
1552 uint32_t vtx_base_sgpr
;
1553 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1554 uint8_t vtx_emit_num
;
1555 struct radv_prim_vertex_count prim_vertex_count
;
1556 bool can_use_guardband
;
1557 uint32_t needed_dynamic_state
;
1558 bool disable_out_of_order_rast_for_occlusion
;
1560 /* Used for rbplus */
1561 uint32_t col_format
;
1562 uint32_t cb_target_mask
;
1567 unsigned scratch_bytes_per_wave
;
1569 /* Not NULL if graphics pipeline uses streamout. */
1570 struct radv_shader_variant
*streamout_shader
;
1573 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1575 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1578 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1580 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1583 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
);
1585 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
);
1587 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1588 gl_shader_stage stage
,
1591 struct radv_shader_variant
*radv_get_shader(struct radv_pipeline
*pipeline
,
1592 gl_shader_stage stage
);
1594 struct radv_graphics_pipeline_create_info
{
1596 bool db_depth_clear
;
1597 bool db_stencil_clear
;
1598 bool db_depth_disable_expclear
;
1599 bool db_stencil_disable_expclear
;
1600 bool db_flush_depth_inplace
;
1601 bool db_flush_stencil_inplace
;
1602 bool db_resummarize
;
1603 uint32_t custom_blend_mode
;
1607 radv_graphics_pipeline_create(VkDevice device
,
1608 VkPipelineCache cache
,
1609 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1610 const struct radv_graphics_pipeline_create_info
*extra
,
1611 const VkAllocationCallbacks
*alloc
,
1612 VkPipeline
*pPipeline
);
1614 struct vk_format_description
;
1615 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1616 int first_non_void
);
1617 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1618 int first_non_void
);
1619 bool radv_is_buffer_format_supported(VkFormat format
, bool *scaled
);
1620 uint32_t radv_translate_colorformat(VkFormat format
);
1621 uint32_t radv_translate_color_numformat(VkFormat format
,
1622 const struct vk_format_description
*desc
,
1623 int first_non_void
);
1624 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1625 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1626 uint32_t radv_translate_dbformat(VkFormat format
);
1627 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1628 const struct vk_format_description
*desc
,
1629 int first_non_void
);
1630 uint32_t radv_translate_tex_numformat(VkFormat format
,
1631 const struct vk_format_description
*desc
,
1632 int first_non_void
);
1633 bool radv_format_pack_clear_color(VkFormat format
,
1634 uint32_t clear_vals
[2],
1635 VkClearColorValue
*value
);
1636 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1637 bool radv_dcc_formats_compatible(VkFormat format1
,
1639 bool radv_device_supports_etc(struct radv_physical_device
*physical_device
);
1641 struct radv_image_plane
{
1643 struct radeon_surf surface
;
1649 /* The original VkFormat provided by the client. This may not match any
1650 * of the actual surface formats.
1653 VkImageAspectFlags aspects
;
1654 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1655 struct ac_surf_info info
;
1656 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1657 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1662 unsigned queue_family_mask
;
1666 /* Set when bound */
1667 struct radeon_winsys_bo
*bo
;
1668 VkDeviceSize offset
;
1669 uint64_t dcc_offset
;
1670 uint64_t htile_offset
;
1671 bool tc_compatible_htile
;
1672 bool tc_compatible_cmask
;
1674 uint64_t cmask_offset
;
1675 uint64_t fmask_offset
;
1676 uint64_t clear_value_offset
;
1677 uint64_t fce_pred_offset
;
1678 uint64_t dcc_pred_offset
;
1681 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1682 * stored at this offset is UINT_MAX, the driver will emit
1683 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1684 * SET_CONTEXT_REG packet.
1686 uint64_t tc_compat_zrange_offset
;
1688 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1689 VkDeviceMemory owned_memory
;
1691 unsigned plane_count
;
1692 struct radv_image_plane planes
[0];
1695 /* Whether the image has a htile that is known consistent with the contents of
1697 bool radv_layout_has_htile(const struct radv_image
*image
,
1698 VkImageLayout layout
,
1699 bool in_render_loop
,
1700 unsigned queue_mask
);
1702 /* Whether the image has a htile that is known consistent with the contents of
1703 * the image and is allowed to be in compressed form.
1705 * If this is false reads that don't use the htile should be able to return
1708 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1709 VkImageLayout layout
,
1710 bool in_render_loop
,
1711 unsigned queue_mask
);
1713 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1714 VkImageLayout layout
,
1715 bool in_render_loop
,
1716 unsigned queue_mask
);
1718 bool radv_layout_dcc_compressed(const struct radv_device
*device
,
1719 const struct radv_image
*image
,
1720 VkImageLayout layout
,
1721 bool in_render_loop
,
1722 unsigned queue_mask
);
1725 * Return whether the image has CMASK metadata for color surfaces.
1728 radv_image_has_cmask(const struct radv_image
*image
)
1730 return image
->cmask_offset
;
1734 * Return whether the image has FMASK metadata for color surfaces.
1737 radv_image_has_fmask(const struct radv_image
*image
)
1739 return image
->fmask_offset
;
1743 * Return whether the image has DCC metadata for color surfaces.
1746 radv_image_has_dcc(const struct radv_image
*image
)
1748 return image
->planes
[0].surface
.dcc_size
;
1752 * Return whether the image is TC-compatible CMASK.
1755 radv_image_is_tc_compat_cmask(const struct radv_image
*image
)
1757 return radv_image_has_fmask(image
) && image
->tc_compatible_cmask
;
1761 * Return whether DCC metadata is enabled for a level.
1764 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1766 return radv_image_has_dcc(image
) &&
1767 level
< image
->planes
[0].surface
.num_dcc_levels
;
1771 * Return whether the image has CB metadata.
1774 radv_image_has_CB_metadata(const struct radv_image
*image
)
1776 return radv_image_has_cmask(image
) ||
1777 radv_image_has_fmask(image
) ||
1778 radv_image_has_dcc(image
);
1782 * Return whether the image has HTILE metadata for depth surfaces.
1785 radv_image_has_htile(const struct radv_image
*image
)
1787 return image
->planes
[0].surface
.htile_size
;
1791 * Return whether HTILE metadata is enabled for a level.
1794 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1796 return radv_image_has_htile(image
) && level
== 0;
1800 * Return whether the image is TC-compatible HTILE.
1803 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1805 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1808 static inline uint64_t
1809 radv_image_get_fast_clear_va(const struct radv_image
*image
,
1810 uint32_t base_level
)
1812 uint64_t va
= radv_buffer_get_va(image
->bo
);
1813 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1817 static inline uint64_t
1818 radv_image_get_fce_pred_va(const struct radv_image
*image
,
1819 uint32_t base_level
)
1821 uint64_t va
= radv_buffer_get_va(image
->bo
);
1822 va
+= image
->offset
+ image
->fce_pred_offset
+ base_level
* 8;
1826 static inline uint64_t
1827 radv_image_get_dcc_pred_va(const struct radv_image
*image
,
1828 uint32_t base_level
)
1830 uint64_t va
= radv_buffer_get_va(image
->bo
);
1831 va
+= image
->offset
+ image
->dcc_pred_offset
+ base_level
* 8;
1835 static inline uint64_t
1836 radv_get_tc_compat_zrange_va(const struct radv_image
*image
,
1837 uint32_t base_level
)
1839 uint64_t va
= radv_buffer_get_va(image
->bo
);
1840 va
+= image
->offset
+ image
->tc_compat_zrange_offset
+ base_level
* 4;
1844 static inline uint64_t
1845 radv_get_ds_clear_value_va(const struct radv_image
*image
,
1846 uint32_t base_level
)
1848 uint64_t va
= radv_buffer_get_va(image
->bo
);
1849 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1853 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1855 static inline uint32_t
1856 radv_get_layerCount(const struct radv_image
*image
,
1857 const VkImageSubresourceRange
*range
)
1859 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1860 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1863 static inline uint32_t
1864 radv_get_levelCount(const struct radv_image
*image
,
1865 const VkImageSubresourceRange
*range
)
1867 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1868 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1871 struct radeon_bo_metadata
;
1873 radv_init_metadata(struct radv_device
*device
,
1874 struct radv_image
*image
,
1875 struct radeon_bo_metadata
*metadata
);
1878 radv_image_override_offset_stride(struct radv_device
*device
,
1879 struct radv_image
*image
,
1880 uint64_t offset
, uint32_t stride
);
1882 union radv_descriptor
{
1884 uint32_t plane0_descriptor
[8];
1885 uint32_t fmask_descriptor
[8];
1888 uint32_t plane_descriptors
[3][8];
1892 struct radv_image_view
{
1893 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1894 struct radeon_winsys_bo
*bo
;
1896 VkImageViewType type
;
1897 VkImageAspectFlags aspect_mask
;
1900 bool multiple_planes
;
1901 uint32_t base_layer
;
1902 uint32_t layer_count
;
1904 uint32_t level_count
;
1905 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1907 union radv_descriptor descriptor
;
1909 /* Descriptor for use as a storage image as opposed to a sampled image.
1910 * This has a few differences for cube maps (e.g. type).
1912 union radv_descriptor storage_descriptor
;
1915 struct radv_image_create_info
{
1916 const VkImageCreateInfo
*vk_info
;
1918 bool no_metadata_planes
;
1919 const struct radeon_bo_metadata
*bo_metadata
;
1923 radv_image_create_layout(struct radv_device
*device
,
1924 struct radv_image_create_info create_info
,
1925 struct radv_image
*image
);
1927 VkResult
radv_image_create(VkDevice _device
,
1928 const struct radv_image_create_info
*info
,
1929 const VkAllocationCallbacks
* alloc
,
1932 bool vi_alpha_is_on_msb(struct radv_device
*device
, VkFormat format
);
1935 radv_image_from_gralloc(VkDevice device_h
,
1936 const VkImageCreateInfo
*base_info
,
1937 const VkNativeBufferANDROID
*gralloc_info
,
1938 const VkAllocationCallbacks
*alloc
,
1939 VkImage
*out_image_h
);
1941 radv_ahb_usage_from_vk_usage(const VkImageCreateFlags vk_create
,
1942 const VkImageUsageFlags vk_usage
);
1944 radv_import_ahb_memory(struct radv_device
*device
,
1945 struct radv_device_memory
*mem
,
1947 const VkImportAndroidHardwareBufferInfoANDROID
*info
);
1949 radv_create_ahb_memory(struct radv_device
*device
,
1950 struct radv_device_memory
*mem
,
1952 const VkMemoryAllocateInfo
*pAllocateInfo
);
1955 radv_select_android_external_format(const void *next
, VkFormat default_format
);
1957 bool radv_android_gralloc_supports_format(VkFormat format
, VkImageUsageFlagBits usage
);
1959 struct radv_image_view_extra_create_info
{
1960 bool disable_compression
;
1963 void radv_image_view_init(struct radv_image_view
*view
,
1964 struct radv_device
*device
,
1965 const VkImageViewCreateInfo
*pCreateInfo
,
1966 const struct radv_image_view_extra_create_info
* extra_create_info
);
1968 VkFormat
radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
);
1970 struct radv_sampler_ycbcr_conversion
{
1972 VkSamplerYcbcrModelConversion ycbcr_model
;
1973 VkSamplerYcbcrRange ycbcr_range
;
1974 VkComponentMapping components
;
1975 VkChromaLocation chroma_offsets
[2];
1976 VkFilter chroma_filter
;
1979 struct radv_buffer_view
{
1980 struct radeon_winsys_bo
*bo
;
1982 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1985 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1986 struct radv_device
*device
,
1987 const VkBufferViewCreateInfo
* pCreateInfo
);
1989 static inline struct VkExtent3D
1990 radv_sanitize_image_extent(const VkImageType imageType
,
1991 const struct VkExtent3D imageExtent
)
1993 switch (imageType
) {
1994 case VK_IMAGE_TYPE_1D
:
1995 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1996 case VK_IMAGE_TYPE_2D
:
1997 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1998 case VK_IMAGE_TYPE_3D
:
2001 unreachable("invalid image type");
2005 static inline struct VkOffset3D
2006 radv_sanitize_image_offset(const VkImageType imageType
,
2007 const struct VkOffset3D imageOffset
)
2009 switch (imageType
) {
2010 case VK_IMAGE_TYPE_1D
:
2011 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
2012 case VK_IMAGE_TYPE_2D
:
2013 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
2014 case VK_IMAGE_TYPE_3D
:
2017 unreachable("invalid image type");
2022 radv_image_extent_compare(const struct radv_image
*image
,
2023 const VkExtent3D
*extent
)
2025 if (extent
->width
!= image
->info
.width
||
2026 extent
->height
!= image
->info
.height
||
2027 extent
->depth
!= image
->info
.depth
)
2032 struct radv_sampler
{
2034 struct radv_sampler_ycbcr_conversion
*ycbcr_sampler
;
2037 struct radv_framebuffer
{
2042 uint32_t attachment_count
;
2043 struct radv_image_view
*attachments
[0];
2046 struct radv_subpass_barrier
{
2047 VkPipelineStageFlags src_stage_mask
;
2048 VkAccessFlags src_access_mask
;
2049 VkAccessFlags dst_access_mask
;
2052 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2053 const struct radv_subpass_barrier
*barrier
);
2055 struct radv_subpass_attachment
{
2056 uint32_t attachment
;
2057 VkImageLayout layout
;
2058 bool in_render_loop
;
2061 struct radv_subpass
{
2062 uint32_t attachment_count
;
2063 struct radv_subpass_attachment
* attachments
;
2065 uint32_t input_count
;
2066 uint32_t color_count
;
2067 struct radv_subpass_attachment
* input_attachments
;
2068 struct radv_subpass_attachment
* color_attachments
;
2069 struct radv_subpass_attachment
* resolve_attachments
;
2070 struct radv_subpass_attachment
* depth_stencil_attachment
;
2071 struct radv_subpass_attachment
* ds_resolve_attachment
;
2072 VkResolveModeFlagBitsKHR depth_resolve_mode
;
2073 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
2075 /** Subpass has at least one color resolve attachment */
2076 bool has_color_resolve
;
2078 /** Subpass has at least one color attachment */
2081 struct radv_subpass_barrier start_barrier
;
2084 VkSampleCountFlagBits max_sample_count
;
2088 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
);
2090 struct radv_render_pass_attachment
{
2093 VkAttachmentLoadOp load_op
;
2094 VkAttachmentLoadOp stencil_load_op
;
2095 VkImageLayout initial_layout
;
2096 VkImageLayout final_layout
;
2098 /* The subpass id in which the attachment will be used first/last. */
2099 uint32_t first_subpass_idx
;
2100 uint32_t last_subpass_idx
;
2103 struct radv_render_pass
{
2104 uint32_t attachment_count
;
2105 uint32_t subpass_count
;
2106 struct radv_subpass_attachment
* subpass_attachments
;
2107 struct radv_render_pass_attachment
* attachments
;
2108 struct radv_subpass_barrier end_barrier
;
2109 struct radv_subpass subpasses
[0];
2112 VkResult
radv_device_init_meta(struct radv_device
*device
);
2113 void radv_device_finish_meta(struct radv_device
*device
);
2115 struct radv_query_pool
{
2116 struct radeon_winsys_bo
*bo
;
2118 uint32_t availability_offset
;
2122 uint32_t pipeline_stats_mask
;
2125 struct radv_semaphore
{
2126 /* use a winsys sem for non-exportable */
2127 struct radeon_winsys_sem
*sem
;
2129 uint32_t temp_syncobj
;
2132 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2133 VkPipelineBindPoint bind_point
,
2134 struct radv_descriptor_set
*set
,
2138 radv_update_descriptor_sets(struct radv_device
*device
,
2139 struct radv_cmd_buffer
*cmd_buffer
,
2140 VkDescriptorSet overrideSet
,
2141 uint32_t descriptorWriteCount
,
2142 const VkWriteDescriptorSet
*pDescriptorWrites
,
2143 uint32_t descriptorCopyCount
,
2144 const VkCopyDescriptorSet
*pDescriptorCopies
);
2147 radv_update_descriptor_set_with_template(struct radv_device
*device
,
2148 struct radv_cmd_buffer
*cmd_buffer
,
2149 struct radv_descriptor_set
*set
,
2150 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
2153 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2154 VkPipelineBindPoint pipelineBindPoint
,
2155 VkPipelineLayout _layout
,
2157 uint32_t descriptorWriteCount
,
2158 const VkWriteDescriptorSet
*pDescriptorWrites
);
2160 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
2161 struct radv_image
*image
,
2162 const VkImageSubresourceRange
*range
, uint32_t value
);
2164 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
2165 struct radv_image
*image
,
2166 const VkImageSubresourceRange
*range
);
2169 struct radeon_winsys_fence
*fence
;
2170 struct wsi_fence
*fence_wsi
;
2173 uint32_t temp_syncobj
;
2176 /* radv_nir_to_llvm.c */
2177 struct radv_shader_info
;
2178 struct radv_nir_compiler_options
;
2180 void radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
2181 struct nir_shader
*geom_shader
,
2182 struct radv_shader_binary
**rbinary
,
2183 struct radv_shader_info
*info
,
2184 const struct radv_nir_compiler_options
*option
);
2186 void radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
2187 struct radv_shader_binary
**rbinary
,
2188 struct radv_shader_info
*info
,
2189 struct nir_shader
*const *nir
,
2191 const struct radv_nir_compiler_options
*options
);
2193 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
2194 gl_shader_stage stage
,
2195 const struct nir_shader
*nir
);
2197 /* radv_shader_info.h */
2198 struct radv_shader_info
;
2199 struct radv_shader_variant_key
;
2201 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
2202 const struct radv_pipeline_layout
*layout
,
2203 const struct radv_shader_variant_key
*key
,
2204 struct radv_shader_info
*info
);
2206 void radv_nir_shader_info_init(struct radv_shader_info
*info
);
2208 struct radeon_winsys_sem
;
2210 uint64_t radv_get_current_time(void);
2212 static inline uint32_t
2213 si_conv_gl_prim_to_vertices(unsigned gl_prim
)
2216 case 0: /* GL_POINTS */
2218 case 1: /* GL_LINES */
2219 case 3: /* GL_LINE_STRIP */
2221 case 4: /* GL_TRIANGLES */
2222 case 5: /* GL_TRIANGLE_STRIP */
2224 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2226 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2228 case 7: /* GL_QUADS */
2229 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
2236 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2238 static inline struct __radv_type * \
2239 __radv_type ## _from_handle(__VkType _handle) \
2241 return (struct __radv_type *) _handle; \
2244 static inline __VkType \
2245 __radv_type ## _to_handle(struct __radv_type *_obj) \
2247 return (__VkType) _obj; \
2250 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2252 static inline struct __radv_type * \
2253 __radv_type ## _from_handle(__VkType _handle) \
2255 return (struct __radv_type *)(uintptr_t) _handle; \
2258 static inline __VkType \
2259 __radv_type ## _to_handle(struct __radv_type *_obj) \
2261 return (__VkType)(uintptr_t) _obj; \
2264 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2265 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2267 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
2268 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
2269 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
2270 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
2271 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
2273 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
2274 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
2275 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
2276 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
2277 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
2278 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
2279 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
2280 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
2281 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
2282 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
2283 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
2284 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
2285 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
2286 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
2287 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
2288 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
2289 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
2290 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
2291 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
2292 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
2293 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
2294 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
2296 #endif /* RADV_PRIVATE_H */