projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: gather stream output info
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "ac_llvm_util.h"
62 #include "radv_descriptor_set.h"
63 #include "radv_extensions.h"
64 #include "radv_cs.h"
65
66 #include <llvm-c/TargetMachine.h>
67
68 /* Pre-declarations needed for WSI entrypoints */
69 struct wl_surface;
70 struct wl_display;
71 typedef struct xcb_connection_t xcb_connection_t;
72 typedef uint32_t xcb_visualid_t;
73 typedef uint32_t xcb_window_t;
74
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vk_icd.h>
78 #include <vulkan/vk_android_native_buffer.h>
79
80 #include "radv_entrypoints.h"
81
82 #include "wsi_common.h"
83 #include "wsi_common_display.h"
84
85 #define ATI_VENDOR_ID 0x1002
86
87 #define MAX_VBS 32
88 #define MAX_VERTEX_ATTRIBS 32
89 #define MAX_RTS 8
90 #define MAX_VIEWPORTS 16
91 #define MAX_SCISSORS 16
92 #define MAX_DISCARD_RECTANGLES 4
93 #define MAX_PUSH_CONSTANTS_SIZE 128
94 #define MAX_PUSH_DESCRIPTORS 32
95 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
96 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
97 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
98 #define MAX_SAMPLES_LOG2 4
99 #define NUM_META_FS_KEYS 12
100 #define RADV_MAX_DRM_DEVICES 8
101 #define MAX_VIEWS 8
102 #define MAX_SO_STREAMS 4
103 #define MAX_SO_BUFFERS 4
104 #define MAX_SO_OUTPUTS 64
105
106 #define NUM_DEPTH_CLEAR_PIPELINES 3
107
108 /*
109 * This is the point we switch from using CP to compute shader
110 * for certain buffer operations.
111 */
112 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
113
114 #define RADV_BUFFER_UPDATE_THRESHOLD 1024
115
116 enum radv_mem_heap {
117 RADV_MEM_HEAP_VRAM,
118 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
119 RADV_MEM_HEAP_GTT,
120 RADV_MEM_HEAP_COUNT
121 };
122
123 enum radv_mem_type {
124 RADV_MEM_TYPE_VRAM,
125 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
126 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
127 RADV_MEM_TYPE_GTT_CACHED,
128 RADV_MEM_TYPE_COUNT
129 };
130
131 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
132
133 static inline uint32_t
134 align_u32(uint32_t v, uint32_t a)
135 {
136 assert(a != 0 && a == (a & -a));
137 return (v + a - 1) & ~(a - 1);
138 }
139
140 static inline uint32_t
141 align_u32_npot(uint32_t v, uint32_t a)
142 {
143 return (v + a - 1) / a * a;
144 }
145
146 static inline uint64_t
147 align_u64(uint64_t v, uint64_t a)
148 {
149 assert(a != 0 && a == (a & -a));
150 return (v + a - 1) & ~(a - 1);
151 }
152
153 static inline int32_t
154 align_i32(int32_t v, int32_t a)
155 {
156 assert(a != 0 && a == (a & -a));
157 return (v + a - 1) & ~(a - 1);
158 }
159
160 /** Alignment must be a power of 2. */
161 static inline bool
162 radv_is_aligned(uintmax_t n, uintmax_t a)
163 {
164 assert(a == (a & -a));
165 return (n & (a - 1)) == 0;
166 }
167
168 static inline uint32_t
169 round_up_u32(uint32_t v, uint32_t a)
170 {
171 return (v + a - 1) / a;
172 }
173
174 static inline uint64_t
175 round_up_u64(uint64_t v, uint64_t a)
176 {
177 return (v + a - 1) / a;
178 }
179
180 static inline uint32_t
181 radv_minify(uint32_t n, uint32_t levels)
182 {
183 if (unlikely(n == 0))
184 return 0;
185 else
186 return MAX2(n >> levels, 1);
187 }
188 static inline float
189 radv_clamp_f(float f, float min, float max)
190 {
191 assert(min < max);
192
193 if (f > max)
194 return max;
195 else if (f < min)
196 return min;
197 else
198 return f;
199 }
200
201 static inline bool
202 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
203 {
204 if (*inout_mask & clear_mask) {
205 *inout_mask &= ~clear_mask;
206 return true;
207 } else {
208 return false;
209 }
210 }
211
212 #define for_each_bit(b, dword) \
213 for (uint32_t __dword = (dword); \
214 (b) = __builtin_ffs(__dword) - 1, __dword; \
215 __dword &= ~(1 << (b)))
216
217 #define typed_memcpy(dest, src, count) ({ \
218 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
219 memcpy((dest), (src), (count) * sizeof(*(src))); \
220 })
221
222 /* Whenever we generate an error, pass it through this function. Useful for
223 * debugging, where we can break on it. Only call at error site, not when
224 * propagating errors. Might be useful to plug in a stack trace here.
225 */
226
227 struct radv_instance;
228
229 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
230
231 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
232 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
233
234 void __radv_finishme(const char *file, int line, const char *format, ...)
235 radv_printflike(3, 4);
236 void radv_loge(const char *format, ...) radv_printflike(1, 2);
237 void radv_loge_v(const char *format, va_list va);
238 void radv_logi(const char *format, ...) radv_printflike(1, 2);
239 void radv_logi_v(const char *format, va_list va);
240
241 /**
242 * Print a FINISHME message, including its source location.
243 */
244 #define radv_finishme(format, ...) \
245 do { \
246 static bool reported = false; \
247 if (!reported) { \
248 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
249 reported = true; \
250 } \
251 } while (0)
252
253 /* A non-fatal assert. Useful for debugging. */
254 #ifdef DEBUG
255 #define radv_assert(x) ({ \
256 if (unlikely(!(x))) \
257 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
258 })
259 #else
260 #define radv_assert(x)
261 #endif
262
263 #define stub_return(v) \
264 do { \
265 radv_finishme("stub %s", __func__); \
266 return (v); \
267 } while (0)
268
269 #define stub() \
270 do { \
271 radv_finishme("stub %s", __func__); \
272 return; \
273 } while (0)
274
275 void *radv_lookup_entrypoint_unchecked(const char *name);
276 void *radv_lookup_entrypoint_checked(const char *name,
277 uint32_t core_version,
278 const struct radv_instance_extension_table *instance,
279 const struct radv_device_extension_table *device);
280
281 struct radv_physical_device {
282 VK_LOADER_DATA _loader_data;
283
284 struct radv_instance * instance;
285
286 struct radeon_winsys *ws;
287 struct radeon_info rad_info;
288 char path[20];
289 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
290 uint8_t driver_uuid[VK_UUID_SIZE];
291 uint8_t device_uuid[VK_UUID_SIZE];
292 uint8_t cache_uuid[VK_UUID_SIZE];
293
294 int local_fd;
295 int master_fd;
296 struct wsi_device wsi_device;
297
298 bool has_rbplus; /* if RB+ register exist */
299 bool rbplus_allowed; /* if RB+ is allowed */
300 bool has_clear_state;
301 bool cpdma_prefetch_writes_memory;
302 bool has_scissor_bug;
303
304 bool has_out_of_order_rast;
305 bool out_of_order_rast_allowed;
306
307 /* Whether DCC should be enabled for MSAA textures. */
308 bool dcc_msaa_allowed;
309
310 /* This is the drivers on-disk cache used as a fallback as opposed to
311 * the pipeline cache defined by apps.
312 */
313 struct disk_cache * disk_cache;
314
315 VkPhysicalDeviceMemoryProperties memory_properties;
316 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
317
318 drmPciBusInfo bus_info;
319
320 struct radv_device_extension_table supported_extensions;
321 };
322
323 struct radv_instance {
324 VK_LOADER_DATA _loader_data;
325
326 VkAllocationCallbacks alloc;
327
328 uint32_t apiVersion;
329 int physicalDeviceCount;
330 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
331
332 uint64_t debug_flags;
333 uint64_t perftest_flags;
334
335 struct vk_debug_report_instance debug_report_callbacks;
336
337 struct radv_instance_extension_table enabled_extensions;
338 };
339
340 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
341 void radv_finish_wsi(struct radv_physical_device *physical_device);
342
343 bool radv_instance_extension_supported(const char *name);
344 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
345 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
346 const char *name);
347
348 struct cache_entry;
349
350 struct radv_pipeline_cache {
351 struct radv_device * device;
352 pthread_mutex_t mutex;
353
354 uint32_t total_size;
355 uint32_t table_size;
356 uint32_t kernel_count;
357 struct cache_entry ** hash_table;
358 bool modified;
359
360 VkAllocationCallbacks alloc;
361 };
362
363 struct radv_pipeline_key {
364 uint32_t instance_rate_inputs;
365 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
366 uint64_t vertex_alpha_adjust;
367 unsigned tess_input_vertices;
368 uint32_t col_format;
369 uint32_t is_int8;
370 uint32_t is_int10;
371 uint8_t log2_ps_iter_samples;
372 uint8_t num_samples;
373 uint32_t has_multiview_view_index : 1;
374 uint32_t optimisations_disabled : 1;
375 };
376
377 void
378 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
379 struct radv_device *device);
380 void
381 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
382 bool
383 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
384 const void *data, size_t size);
385
386 struct radv_shader_variant;
387
388 bool
389 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
390 struct radv_pipeline_cache *cache,
391 const unsigned char *sha1,
392 struct radv_shader_variant **variants);
393
394 void
395 radv_pipeline_cache_insert_shaders(struct radv_device *device,
396 struct radv_pipeline_cache *cache,
397 const unsigned char *sha1,
398 struct radv_shader_variant **variants,
399 const void *const *codes,
400 const unsigned *code_sizes);
401
402 enum radv_blit_ds_layout {
403 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
404 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
405 RADV_BLIT_DS_LAYOUT_COUNT,
406 };
407
408 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
409 {
410 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
411 }
412
413 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
414 {
415 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
416 }
417
418 enum radv_meta_dst_layout {
419 RADV_META_DST_LAYOUT_GENERAL,
420 RADV_META_DST_LAYOUT_OPTIMAL,
421 RADV_META_DST_LAYOUT_COUNT,
422 };
423
424 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
425 {
426 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
427 }
428
429 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
430 {
431 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
432 }
433
434 struct radv_meta_state {
435 VkAllocationCallbacks alloc;
436
437 struct radv_pipeline_cache cache;
438
439 /*
440 * For on-demand pipeline creation, makes sure that
441 * only one thread tries to build a pipeline at the same time.
442 */
443 mtx_t mtx;
444
445 /**
446 * Use array element `i` for images with `2^i` samples.
447 */
448 struct {
449 VkRenderPass render_pass[NUM_META_FS_KEYS];
450 VkPipeline color_pipelines[NUM_META_FS_KEYS];
451
452 VkRenderPass depthstencil_rp;
453 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
454 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
455 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
456 } clear[1 + MAX_SAMPLES_LOG2];
457
458 VkPipelineLayout clear_color_p_layout;
459 VkPipelineLayout clear_depth_p_layout;
460 struct {
461 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
462
463 /** Pipeline that blits from a 1D image. */
464 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
465
466 /** Pipeline that blits from a 2D image. */
467 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
468
469 /** Pipeline that blits from a 3D image. */
470 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
471
472 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
473 VkPipeline depth_only_1d_pipeline;
474 VkPipeline depth_only_2d_pipeline;
475 VkPipeline depth_only_3d_pipeline;
476
477 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
478 VkPipeline stencil_only_1d_pipeline;
479 VkPipeline stencil_only_2d_pipeline;
480 VkPipeline stencil_only_3d_pipeline;
481 VkPipelineLayout pipeline_layout;
482 VkDescriptorSetLayout ds_layout;
483 } blit;
484
485 struct {
486 VkPipelineLayout p_layouts[5];
487 VkDescriptorSetLayout ds_layouts[5];
488 VkPipeline pipelines[5][NUM_META_FS_KEYS];
489
490 VkPipeline depth_only_pipeline[5];
491
492 VkPipeline stencil_only_pipeline[5];
493 } blit2d[1 + MAX_SAMPLES_LOG2];
494
495 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
496 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
497 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
498
499 struct {
500 VkPipelineLayout img_p_layout;
501 VkDescriptorSetLayout img_ds_layout;
502 VkPipeline pipeline;
503 VkPipeline pipeline_3d;
504 } itob;
505 struct {
506 VkPipelineLayout img_p_layout;
507 VkDescriptorSetLayout img_ds_layout;
508 VkPipeline pipeline;
509 VkPipeline pipeline_3d;
510 } btoi;
511 struct {
512 VkPipelineLayout img_p_layout;
513 VkDescriptorSetLayout img_ds_layout;
514 VkPipeline pipeline;
515 } btoi_r32g32b32;
516 struct {
517 VkPipelineLayout img_p_layout;
518 VkDescriptorSetLayout img_ds_layout;
519 VkPipeline pipeline;
520 VkPipeline pipeline_3d;
521 } itoi;
522 struct {
523 VkPipelineLayout img_p_layout;
524 VkDescriptorSetLayout img_ds_layout;
525 VkPipeline pipeline;
526 } itoi_r32g32b32;
527 struct {
528 VkPipelineLayout img_p_layout;
529 VkDescriptorSetLayout img_ds_layout;
530 VkPipeline pipeline;
531 VkPipeline pipeline_3d;
532 } cleari;
533 struct {
534 VkPipelineLayout img_p_layout;
535 VkDescriptorSetLayout img_ds_layout;
536 VkPipeline pipeline;
537 } cleari_r32g32b32;
538
539 struct {
540 VkPipelineLayout p_layout;
541 VkPipeline pipeline[NUM_META_FS_KEYS];
542 VkRenderPass pass[NUM_META_FS_KEYS];
543 } resolve;
544
545 struct {
546 VkDescriptorSetLayout ds_layout;
547 VkPipelineLayout p_layout;
548 struct {
549 VkPipeline pipeline;
550 VkPipeline i_pipeline;
551 VkPipeline srgb_pipeline;
552 } rc[MAX_SAMPLES_LOG2];
553 } resolve_compute;
554
555 struct {
556 VkDescriptorSetLayout ds_layout;
557 VkPipelineLayout p_layout;
558
559 struct {
560 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
561 VkPipeline pipeline[NUM_META_FS_KEYS];
562 } rc[MAX_SAMPLES_LOG2];
563 } resolve_fragment;
564
565 struct {
566 VkPipelineLayout p_layout;
567 VkPipeline decompress_pipeline;
568 VkPipeline resummarize_pipeline;
569 VkRenderPass pass;
570 } depth_decomp[1 + MAX_SAMPLES_LOG2];
571
572 struct {
573 VkPipelineLayout p_layout;
574 VkPipeline cmask_eliminate_pipeline;
575 VkPipeline fmask_decompress_pipeline;
576 VkPipeline dcc_decompress_pipeline;
577 VkRenderPass pass;
578
579 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
580 VkPipelineLayout dcc_decompress_compute_p_layout;
581 VkPipeline dcc_decompress_compute_pipeline;
582 } fast_clear_flush;
583
584 struct {
585 VkPipelineLayout fill_p_layout;
586 VkPipelineLayout copy_p_layout;
587 VkDescriptorSetLayout fill_ds_layout;
588 VkDescriptorSetLayout copy_ds_layout;
589 VkPipeline fill_pipeline;
590 VkPipeline copy_pipeline;
591 } buffer;
592
593 struct {
594 VkDescriptorSetLayout ds_layout;
595 VkPipelineLayout p_layout;
596 VkPipeline occlusion_query_pipeline;
597 VkPipeline pipeline_statistics_query_pipeline;
598 } query;
599 };
600
601 /* queue types */
602 #define RADV_QUEUE_GENERAL 0
603 #define RADV_QUEUE_COMPUTE 1
604 #define RADV_QUEUE_TRANSFER 2
605
606 #define RADV_MAX_QUEUE_FAMILIES 3
607
608 enum ring_type radv_queue_family_to_ring(int f);
609
610 struct radv_queue {
611 VK_LOADER_DATA _loader_data;
612 struct radv_device * device;
613 struct radeon_winsys_ctx *hw_ctx;
614 enum radeon_ctx_priority priority;
615 uint32_t queue_family_index;
616 int queue_idx;
617 VkDeviceQueueCreateFlags flags;
618
619 uint32_t scratch_size;
620 uint32_t compute_scratch_size;
621 uint32_t esgs_ring_size;
622 uint32_t gsvs_ring_size;
623 bool has_tess_rings;
624 bool has_sample_positions;
625
626 struct radeon_winsys_bo *scratch_bo;
627 struct radeon_winsys_bo *descriptor_bo;
628 struct radeon_winsys_bo *compute_scratch_bo;
629 struct radeon_winsys_bo *esgs_ring_bo;
630 struct radeon_winsys_bo *gsvs_ring_bo;
631 struct radeon_winsys_bo *tess_rings_bo;
632 struct radeon_cmdbuf *initial_preamble_cs;
633 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
634 struct radeon_cmdbuf *continue_preamble_cs;
635 };
636
637 struct radv_bo_list {
638 struct radv_winsys_bo_list list;
639 unsigned capacity;
640 pthread_mutex_t mutex;
641 };
642
643 struct radv_device {
644 VK_LOADER_DATA _loader_data;
645
646 VkAllocationCallbacks alloc;
647
648 struct radv_instance * instance;
649 struct radeon_winsys *ws;
650
651 struct radv_meta_state meta_state;
652
653 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
654 int queue_count[RADV_MAX_QUEUE_FAMILIES];
655 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
656
657 bool always_use_syncobj;
658 bool has_distributed_tess;
659 bool pbb_allowed;
660 bool dfsm_allowed;
661 uint32_t tess_offchip_block_dw_size;
662 uint32_t scratch_waves;
663 uint32_t dispatch_initiator;
664
665 uint32_t gs_table_depth;
666
667 /* MSAA sample locations.
668 * The first index is the sample index.
669 * The second index is the coordinate: X, Y. */
670 float sample_locations_1x[1][2];
671 float sample_locations_2x[2][2];
672 float sample_locations_4x[4][2];
673 float sample_locations_8x[8][2];
674 float sample_locations_16x[16][2];
675
676 /* CIK and later */
677 uint32_t gfx_init_size_dw;
678 struct radeon_winsys_bo *gfx_init;
679
680 struct radeon_winsys_bo *trace_bo;
681 uint32_t *trace_id_ptr;
682
683 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
684 bool keep_shader_info;
685
686 struct radv_physical_device *physical_device;
687
688 /* Backup in-memory cache to be used if the app doesn't provide one */
689 struct radv_pipeline_cache * mem_cache;
690
691 /*
692 * use different counters so MSAA MRTs get consecutive surface indices,
693 * even if MASK is allocated in between.
694 */
695 uint32_t image_mrt_offset_counter;
696 uint32_t fmask_mrt_offset_counter;
697 struct list_head shader_slabs;
698 mtx_t shader_slab_mutex;
699
700 /* For detecting VM faults reported by dmesg. */
701 uint64_t dmesg_timestamp;
702
703 struct radv_device_extension_table enabled_extensions;
704
705 /* Whether the driver uses a global BO list. */
706 bool use_global_bo_list;
707
708 struct radv_bo_list bo_list;
709
710 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
711 int force_aniso;
712 };
713
714 struct radv_device_memory {
715 struct radeon_winsys_bo *bo;
716 /* for dedicated allocations */
717 struct radv_image *image;
718 struct radv_buffer *buffer;
719 uint32_t type_index;
720 VkDeviceSize map_size;
721 void * map;
722 void * user_ptr;
723 };
724
725
726 struct radv_descriptor_range {
727 uint64_t va;
728 uint32_t size;
729 };
730
731 struct radv_descriptor_set {
732 const struct radv_descriptor_set_layout *layout;
733 uint32_t size;
734
735 struct radeon_winsys_bo *bo;
736 uint64_t va;
737 uint32_t *mapped_ptr;
738 struct radv_descriptor_range *dynamic_descriptors;
739
740 struct radeon_winsys_bo *descriptors[0];
741 };
742
743 struct radv_push_descriptor_set
744 {
745 struct radv_descriptor_set set;
746 uint32_t capacity;
747 };
748
749 struct radv_descriptor_pool_entry {
750 uint32_t offset;
751 uint32_t size;
752 struct radv_descriptor_set *set;
753 };
754
755 struct radv_descriptor_pool {
756 struct radeon_winsys_bo *bo;
757 uint8_t *mapped_ptr;
758 uint64_t current_offset;
759 uint64_t size;
760
761 uint8_t *host_memory_base;
762 uint8_t *host_memory_ptr;
763 uint8_t *host_memory_end;
764
765 uint32_t entry_count;
766 uint32_t max_entry_count;
767 struct radv_descriptor_pool_entry entries[0];
768 };
769
770 struct radv_descriptor_update_template_entry {
771 VkDescriptorType descriptor_type;
772
773 /* The number of descriptors to update */
774 uint32_t descriptor_count;
775
776 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
777 uint32_t dst_offset;
778
779 /* In dwords. Not valid/used for dynamic descriptors */
780 uint32_t dst_stride;
781
782 uint32_t buffer_offset;
783
784 /* Only valid for combined image samplers and samplers */
785 uint16_t has_sampler;
786
787 /* In bytes */
788 size_t src_offset;
789 size_t src_stride;
790
791 /* For push descriptors */
792 const uint32_t *immutable_samplers;
793 };
794
795 struct radv_descriptor_update_template {
796 uint32_t entry_count;
797 VkPipelineBindPoint bind_point;
798 struct radv_descriptor_update_template_entry entry[0];
799 };
800
801 struct radv_buffer {
802 VkDeviceSize size;
803
804 VkBufferUsageFlags usage;
805 VkBufferCreateFlags flags;
806
807 /* Set when bound */
808 struct radeon_winsys_bo * bo;
809 VkDeviceSize offset;
810
811 bool shareable;
812 };
813
814 enum radv_dynamic_state_bits {
815 RADV_DYNAMIC_VIEWPORT = 1 << 0,
816 RADV_DYNAMIC_SCISSOR = 1 << 1,
817 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
818 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
819 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
820 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
821 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
822 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
823 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
824 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
825 RADV_DYNAMIC_ALL = (1 << 10) - 1,
826 };
827
828 enum radv_cmd_dirty_bits {
829 /* Keep the dynamic state dirty bits in sync with
830 * enum radv_dynamic_state_bits */
831 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
832 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
833 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
834 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
835 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
836 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
837 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
838 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
839 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
840 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
841 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
842 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
843 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
844 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
845 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
846 };
847
848 enum radv_cmd_flush_bits {
849 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
850 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
851 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
852 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
853 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
854 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
855 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
856 /* Same as above, but only writes back and doesn't invalidate */
857 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
858 /* Framebuffer caches */
859 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
860 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
861 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
862 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
863 /* Engine synchronization. */
864 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
865 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
866 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
867 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
868 /* Pipeline query controls. */
869 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
870 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
871
872 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
873 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
874 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
875 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
876 };
877
878 struct radv_vertex_binding {
879 struct radv_buffer * buffer;
880 VkDeviceSize offset;
881 };
882
883 struct radv_viewport_state {
884 uint32_t count;
885 VkViewport viewports[MAX_VIEWPORTS];
886 };
887
888 struct radv_scissor_state {
889 uint32_t count;
890 VkRect2D scissors[MAX_SCISSORS];
891 };
892
893 struct radv_discard_rectangle_state {
894 uint32_t count;
895 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
896 };
897
898 struct radv_dynamic_state {
899 /**
900 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
901 * Defines the set of saved dynamic state.
902 */
903 uint32_t mask;
904
905 struct radv_viewport_state viewport;
906
907 struct radv_scissor_state scissor;
908
909 float line_width;
910
911 struct {
912 float bias;
913 float clamp;
914 float slope;
915 } depth_bias;
916
917 float blend_constants[4];
918
919 struct {
920 float min;
921 float max;
922 } depth_bounds;
923
924 struct {
925 uint32_t front;
926 uint32_t back;
927 } stencil_compare_mask;
928
929 struct {
930 uint32_t front;
931 uint32_t back;
932 } stencil_write_mask;
933
934 struct {
935 uint32_t front;
936 uint32_t back;
937 } stencil_reference;
938
939 struct radv_discard_rectangle_state discard_rectangle;
940 };
941
942 extern const struct radv_dynamic_state default_dynamic_state;
943
944 const char *
945 radv_get_debug_option_name(int id);
946
947 const char *
948 radv_get_perftest_option_name(int id);
949
950 /**
951 * Attachment state when recording a renderpass instance.
952 *
953 * The clear value is valid only if there exists a pending clear.
954 */
955 struct radv_attachment_state {
956 VkImageAspectFlags pending_clear_aspects;
957 uint32_t cleared_views;
958 VkClearValue clear_value;
959 VkImageLayout current_layout;
960 };
961
962 struct radv_descriptor_state {
963 struct radv_descriptor_set *sets[MAX_SETS];
964 uint32_t dirty;
965 uint32_t valid;
966 struct radv_push_descriptor_set push_set;
967 bool push_dirty;
968 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
969 };
970
971 struct radv_cmd_state {
972 /* Vertex descriptors */
973 uint64_t vb_va;
974 unsigned vb_size;
975
976 bool predicating;
977 uint32_t dirty;
978
979 uint32_t prefetch_L2_mask;
980
981 struct radv_pipeline * pipeline;
982 struct radv_pipeline * emitted_pipeline;
983 struct radv_pipeline * compute_pipeline;
984 struct radv_pipeline * emitted_compute_pipeline;
985 struct radv_framebuffer * framebuffer;
986 struct radv_render_pass * pass;
987 const struct radv_subpass * subpass;
988 struct radv_dynamic_state dynamic;
989 struct radv_attachment_state * attachments;
990 VkRect2D render_area;
991
992 /* Index buffer */
993 struct radv_buffer *index_buffer;
994 uint64_t index_offset;
995 uint32_t index_type;
996 uint32_t max_index_count;
997 uint64_t index_va;
998 int32_t last_index_type;
999
1000 int32_t last_primitive_reset_en;
1001 uint32_t last_primitive_reset_index;
1002 enum radv_cmd_flush_bits flush_bits;
1003 unsigned active_occlusion_queries;
1004 bool perfect_occlusion_queries_enabled;
1005 unsigned active_pipeline_queries;
1006 float offset_scale;
1007 uint32_t trace_id;
1008 uint32_t last_ia_multi_vgt_param;
1009
1010 uint32_t last_num_instances;
1011 uint32_t last_first_instance;
1012 uint32_t last_vertex_offset;
1013
1014 /* Whether CP DMA is busy/idle. */
1015 bool dma_is_busy;
1016
1017 /* Conditional rendering info. */
1018 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1019 uint64_t predication_va;
1020 };
1021
1022 struct radv_cmd_pool {
1023 VkAllocationCallbacks alloc;
1024 struct list_head cmd_buffers;
1025 struct list_head free_cmd_buffers;
1026 uint32_t queue_family_index;
1027 };
1028
1029 struct radv_cmd_buffer_upload {
1030 uint8_t *map;
1031 unsigned offset;
1032 uint64_t size;
1033 struct radeon_winsys_bo *upload_bo;
1034 struct list_head list;
1035 };
1036
1037 enum radv_cmd_buffer_status {
1038 RADV_CMD_BUFFER_STATUS_INVALID,
1039 RADV_CMD_BUFFER_STATUS_INITIAL,
1040 RADV_CMD_BUFFER_STATUS_RECORDING,
1041 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1042 RADV_CMD_BUFFER_STATUS_PENDING,
1043 };
1044
1045 struct radv_cmd_buffer {
1046 VK_LOADER_DATA _loader_data;
1047
1048 struct radv_device * device;
1049
1050 struct radv_cmd_pool * pool;
1051 struct list_head pool_link;
1052
1053 VkCommandBufferUsageFlags usage_flags;
1054 VkCommandBufferLevel level;
1055 enum radv_cmd_buffer_status status;
1056 struct radeon_cmdbuf *cs;
1057 struct radv_cmd_state state;
1058 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1059 uint32_t queue_family_index;
1060
1061 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1062 VkShaderStageFlags push_constant_stages;
1063 struct radv_descriptor_set meta_push_descriptors;
1064
1065 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1066
1067 struct radv_cmd_buffer_upload upload;
1068
1069 uint32_t scratch_size_needed;
1070 uint32_t compute_scratch_size_needed;
1071 uint32_t esgs_ring_size_needed;
1072 uint32_t gsvs_ring_size_needed;
1073 bool tess_rings_needed;
1074 bool sample_positions_needed;
1075
1076 VkResult record_result;
1077
1078 uint32_t gfx9_fence_offset;
1079 struct radeon_winsys_bo *gfx9_fence_bo;
1080 uint32_t gfx9_fence_idx;
1081 uint64_t gfx9_eop_bug_va;
1082
1083 /**
1084 * Whether a query pool has been resetted and we have to flush caches.
1085 */
1086 bool pending_reset_query;
1087 };
1088
1089 struct radv_image;
1090
1091 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1092
1093 void si_emit_graphics(struct radv_physical_device *physical_device,
1094 struct radeon_cmdbuf *cs);
1095 void si_emit_compute(struct radv_physical_device *physical_device,
1096 struct radeon_cmdbuf *cs);
1097
1098 void cik_create_gfx_config(struct radv_device *device);
1099
1100 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1101 int count, const VkViewport *viewports);
1102 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1103 int count, const VkRect2D *scissors,
1104 const VkViewport *viewports, bool can_use_guardband);
1105 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1106 bool instanced_draw, bool indirect_draw,
1107 uint32_t draw_vertex_count);
1108 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1109 enum chip_class chip_class,
1110 bool is_mec,
1111 unsigned event, unsigned event_flags,
1112 unsigned data_sel,
1113 uint64_t va,
1114 uint32_t old_fence,
1115 uint32_t new_fence,
1116 uint64_t gfx9_eop_bug_va);
1117
1118 void si_emit_wait_fence(struct radeon_cmdbuf *cs,
1119 uint64_t va, uint32_t ref,
1120 uint32_t mask);
1121 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1122 enum chip_class chip_class,
1123 uint32_t *fence_ptr, uint64_t va,
1124 bool is_mec,
1125 enum radv_cmd_flush_bits flush_bits,
1126 uint64_t gfx9_eop_bug_va);
1127 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1128 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1129 bool inverted, uint64_t va);
1130 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1131 uint64_t src_va, uint64_t dest_va,
1132 uint64_t size);
1133 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1134 unsigned size);
1135 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1136 uint64_t size, unsigned value);
1137 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1138
1139 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1140 bool
1141 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1142 unsigned size,
1143 unsigned alignment,
1144 unsigned *out_offset,
1145 void **ptr);
1146 void
1147 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1148 const struct radv_subpass *subpass,
1149 bool transitions);
1150 bool
1151 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1152 unsigned size, unsigned alignmnet,
1153 const void *data, unsigned *out_offset);
1154
1155 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1156 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1157 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1158 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1159 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
1160 unsigned radv_cayman_get_maxdist(int log_samples);
1161 void radv_device_init_msaa(struct radv_device *device);
1162
1163 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1164 struct radv_image *image,
1165 VkClearDepthStencilValue ds_clear_value,
1166 VkImageAspectFlags aspects);
1167
1168 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1169 struct radv_image *image,
1170 int cb_idx,
1171 uint32_t color_values[2]);
1172
1173 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1174 struct radv_image *image,
1175 bool value);
1176 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1177 struct radeon_winsys_bo *bo,
1178 uint64_t offset, uint64_t size, uint32_t value);
1179 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1180 bool radv_get_memory_fd(struct radv_device *device,
1181 struct radv_device_memory *memory,
1182 int *pFD);
1183
1184 static inline void
1185 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1186 unsigned sh_offset, unsigned pointer_count,
1187 bool use_32bit_pointers)
1188 {
1189 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1190 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1191 }
1192
1193 static inline void
1194 radv_emit_shader_pointer_body(struct radv_device *device,
1195 struct radeon_cmdbuf *cs,
1196 uint64_t va, bool use_32bit_pointers)
1197 {
1198 radeon_emit(cs, va);
1199
1200 if (use_32bit_pointers) {
1201 assert(va == 0 ||
1202 (va >> 32) == device->physical_device->rad_info.address32_hi);
1203 } else {
1204 radeon_emit(cs, va >> 32);
1205 }
1206 }
1207
1208 static inline void
1209 radv_emit_shader_pointer(struct radv_device *device,
1210 struct radeon_cmdbuf *cs,
1211 uint32_t sh_offset, uint64_t va, bool global)
1212 {
1213 bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
1214
1215 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1216 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1217 }
1218
1219 static inline struct radv_descriptor_state *
1220 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1221 VkPipelineBindPoint bind_point)
1222 {
1223 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1224 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1225 return &cmd_buffer->descriptors[bind_point];
1226 }
1227
1228 /*
1229 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1230 *
1231 * Limitations: Can't call normal dispatch functions without binding or rebinding
1232 * the compute pipeline.
1233 */
1234 void radv_unaligned_dispatch(
1235 struct radv_cmd_buffer *cmd_buffer,
1236 uint32_t x,
1237 uint32_t y,
1238 uint32_t z);
1239
1240 struct radv_event {
1241 struct radeon_winsys_bo *bo;
1242 uint64_t *map;
1243 };
1244
1245 struct radv_shader_module;
1246
1247 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1248 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1249 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1250 void
1251 radv_hash_shaders(unsigned char *hash,
1252 const VkPipelineShaderStageCreateInfo **stages,
1253 const struct radv_pipeline_layout *layout,
1254 const struct radv_pipeline_key *key,
1255 uint32_t flags);
1256
1257 static inline gl_shader_stage
1258 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1259 {
1260 assert(__builtin_popcount(vk_stage) == 1);
1261 return ffs(vk_stage) - 1;
1262 }
1263
1264 static inline VkShaderStageFlagBits
1265 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1266 {
1267 return (1 << mesa_stage);
1268 }
1269
1270 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1271
1272 #define radv_foreach_stage(stage, stage_bits) \
1273 for (gl_shader_stage stage, \
1274 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1275 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1276 __tmp &= ~(1 << (stage)))
1277
1278 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1279 unsigned radv_format_meta_fs_key(VkFormat format);
1280
1281 struct radv_multisample_state {
1282 uint32_t db_eqaa;
1283 uint32_t pa_sc_line_cntl;
1284 uint32_t pa_sc_mode_cntl_0;
1285 uint32_t pa_sc_mode_cntl_1;
1286 uint32_t pa_sc_aa_config;
1287 uint32_t pa_sc_aa_mask[2];
1288 unsigned num_samples;
1289 };
1290
1291 struct radv_prim_vertex_count {
1292 uint8_t min;
1293 uint8_t incr;
1294 };
1295
1296 struct radv_vertex_elements_info {
1297 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1298 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1299 uint32_t binding[MAX_VERTEX_ATTRIBS];
1300 uint32_t offset[MAX_VERTEX_ATTRIBS];
1301 uint32_t count;
1302 };
1303
1304 struct radv_ia_multi_vgt_param_helpers {
1305 uint32_t base;
1306 bool partial_es_wave;
1307 uint8_t primgroup_size;
1308 bool wd_switch_on_eop;
1309 bool ia_switch_on_eoi;
1310 bool partial_vs_wave;
1311 };
1312
1313 #define SI_GS_PER_ES 128
1314
1315 struct radv_pipeline {
1316 struct radv_device * device;
1317 struct radv_dynamic_state dynamic_state;
1318
1319 struct radv_pipeline_layout * layout;
1320
1321 bool need_indirect_descriptor_sets;
1322 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1323 struct radv_shader_variant *gs_copy_shader;
1324 VkShaderStageFlags active_stages;
1325
1326 struct radeon_cmdbuf cs;
1327
1328 struct radv_vertex_elements_info vertex_elements;
1329
1330 uint32_t binding_stride[MAX_VBS];
1331
1332 uint32_t user_data_0[MESA_SHADER_STAGES];
1333 union {
1334 struct {
1335 struct radv_multisample_state ms;
1336 uint32_t spi_baryc_cntl;
1337 bool prim_restart_enable;
1338 unsigned esgs_ring_size;
1339 unsigned gsvs_ring_size;
1340 uint32_t vtx_base_sgpr;
1341 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1342 uint8_t vtx_emit_num;
1343 struct radv_prim_vertex_count prim_vertex_count;
1344 bool can_use_guardband;
1345 uint32_t needed_dynamic_state;
1346 bool disable_out_of_order_rast_for_occlusion;
1347
1348 /* Used for rbplus */
1349 uint32_t col_format;
1350 uint32_t cb_target_mask;
1351 } graphics;
1352 };
1353
1354 unsigned max_waves;
1355 unsigned scratch_bytes_per_wave;
1356 };
1357
1358 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1359 {
1360 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1361 }
1362
1363 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1364 {
1365 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1366 }
1367
1368 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1369 gl_shader_stage stage,
1370 int idx);
1371
1372 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1373 gl_shader_stage stage);
1374
1375 struct radv_graphics_pipeline_create_info {
1376 bool use_rectlist;
1377 bool db_depth_clear;
1378 bool db_stencil_clear;
1379 bool db_depth_disable_expclear;
1380 bool db_stencil_disable_expclear;
1381 bool db_flush_depth_inplace;
1382 bool db_flush_stencil_inplace;
1383 bool db_resummarize;
1384 uint32_t custom_blend_mode;
1385 };
1386
1387 VkResult
1388 radv_graphics_pipeline_create(VkDevice device,
1389 VkPipelineCache cache,
1390 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1391 const struct radv_graphics_pipeline_create_info *extra,
1392 const VkAllocationCallbacks *alloc,
1393 VkPipeline *pPipeline);
1394
1395 struct vk_format_description;
1396 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1397 int first_non_void);
1398 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1399 int first_non_void);
1400 uint32_t radv_translate_colorformat(VkFormat format);
1401 uint32_t radv_translate_color_numformat(VkFormat format,
1402 const struct vk_format_description *desc,
1403 int first_non_void);
1404 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1405 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1406 uint32_t radv_translate_dbformat(VkFormat format);
1407 uint32_t radv_translate_tex_dataformat(VkFormat format,
1408 const struct vk_format_description *desc,
1409 int first_non_void);
1410 uint32_t radv_translate_tex_numformat(VkFormat format,
1411 const struct vk_format_description *desc,
1412 int first_non_void);
1413 bool radv_format_pack_clear_color(VkFormat format,
1414 uint32_t clear_vals[2],
1415 VkClearColorValue *value);
1416 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1417 bool radv_dcc_formats_compatible(VkFormat format1,
1418 VkFormat format2);
1419
1420 struct radv_fmask_info {
1421 uint64_t offset;
1422 uint64_t size;
1423 unsigned alignment;
1424 unsigned pitch_in_pixels;
1425 unsigned bank_height;
1426 unsigned slice_tile_max;
1427 unsigned tile_mode_index;
1428 unsigned tile_swizzle;
1429 };
1430
1431 struct radv_cmask_info {
1432 uint64_t offset;
1433 uint64_t size;
1434 unsigned alignment;
1435 unsigned slice_tile_max;
1436 };
1437
1438 struct radv_image {
1439 VkImageType type;
1440 /* The original VkFormat provided by the client. This may not match any
1441 * of the actual surface formats.
1442 */
1443 VkFormat vk_format;
1444 VkImageAspectFlags aspects;
1445 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1446 struct ac_surf_info info;
1447 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1448 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1449
1450 VkDeviceSize size;
1451 uint32_t alignment;
1452
1453 unsigned queue_family_mask;
1454 bool exclusive;
1455 bool shareable;
1456
1457 /* Set when bound */
1458 struct radeon_winsys_bo *bo;
1459 VkDeviceSize offset;
1460 uint64_t dcc_offset;
1461 uint64_t htile_offset;
1462 bool tc_compatible_htile;
1463 struct radeon_surf surface;
1464
1465 struct radv_fmask_info fmask;
1466 struct radv_cmask_info cmask;
1467 uint64_t clear_value_offset;
1468 uint64_t dcc_pred_offset;
1469
1470 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1471 VkDeviceMemory owned_memory;
1472 };
1473
1474 /* Whether the image has a htile that is known consistent with the contents of
1475 * the image. */
1476 bool radv_layout_has_htile(const struct radv_image *image,
1477 VkImageLayout layout,
1478 unsigned queue_mask);
1479
1480 /* Whether the image has a htile that is known consistent with the contents of
1481 * the image and is allowed to be in compressed form.
1482 *
1483 * If this is false reads that don't use the htile should be able to return
1484 * correct results.
1485 */
1486 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1487 VkImageLayout layout,
1488 unsigned queue_mask);
1489
1490 bool radv_layout_can_fast_clear(const struct radv_image *image,
1491 VkImageLayout layout,
1492 unsigned queue_mask);
1493
1494 bool radv_layout_dcc_compressed(const struct radv_image *image,
1495 VkImageLayout layout,
1496 unsigned queue_mask);
1497
1498 /**
1499 * Return whether the image has CMASK metadata for color surfaces.
1500 */
1501 static inline bool
1502 radv_image_has_cmask(const struct radv_image *image)
1503 {
1504 return image->cmask.size;
1505 }
1506
1507 /**
1508 * Return whether the image has FMASK metadata for color surfaces.
1509 */
1510 static inline bool
1511 radv_image_has_fmask(const struct radv_image *image)
1512 {
1513 return image->fmask.size;
1514 }
1515
1516 /**
1517 * Return whether the image has DCC metadata for color surfaces.
1518 */
1519 static inline bool
1520 radv_image_has_dcc(const struct radv_image *image)
1521 {
1522 return image->surface.dcc_size;
1523 }
1524
1525 /**
1526 * Return whether DCC metadata is enabled for a level.
1527 */
1528 static inline bool
1529 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1530 {
1531 return radv_image_has_dcc(image) &&
1532 level < image->surface.num_dcc_levels;
1533 }
1534
1535 /**
1536 * Return whether the image has CB metadata.
1537 */
1538 static inline bool
1539 radv_image_has_CB_metadata(const struct radv_image *image)
1540 {
1541 return radv_image_has_cmask(image) ||
1542 radv_image_has_fmask(image) ||
1543 radv_image_has_dcc(image);
1544 }
1545
1546 /**
1547 * Return whether the image has HTILE metadata for depth surfaces.
1548 */
1549 static inline bool
1550 radv_image_has_htile(const struct radv_image *image)
1551 {
1552 return image->surface.htile_size;
1553 }
1554
1555 /**
1556 * Return whether HTILE metadata is enabled for a level.
1557 */
1558 static inline bool
1559 radv_htile_enabled(const struct radv_image *image, unsigned level)
1560 {
1561 return radv_image_has_htile(image) && level == 0;
1562 }
1563
1564 /**
1565 * Return whether the image is TC-compatible HTILE.
1566 */
1567 static inline bool
1568 radv_image_is_tc_compat_htile(const struct radv_image *image)
1569 {
1570 return radv_image_has_htile(image) && image->tc_compatible_htile;
1571 }
1572
1573 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1574
1575 static inline uint32_t
1576 radv_get_layerCount(const struct radv_image *image,
1577 const VkImageSubresourceRange *range)
1578 {
1579 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1580 image->info.array_size - range->baseArrayLayer : range->layerCount;
1581 }
1582
1583 static inline uint32_t
1584 radv_get_levelCount(const struct radv_image *image,
1585 const VkImageSubresourceRange *range)
1586 {
1587 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1588 image->info.levels - range->baseMipLevel : range->levelCount;
1589 }
1590
1591 struct radeon_bo_metadata;
1592 void
1593 radv_init_metadata(struct radv_device *device,
1594 struct radv_image *image,
1595 struct radeon_bo_metadata *metadata);
1596
1597 struct radv_image_view {
1598 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1599 struct radeon_winsys_bo *bo;
1600
1601 VkImageViewType type;
1602 VkImageAspectFlags aspect_mask;
1603 VkFormat vk_format;
1604 uint32_t base_layer;
1605 uint32_t layer_count;
1606 uint32_t base_mip;
1607 uint32_t level_count;
1608 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1609
1610 uint32_t descriptor[16];
1611
1612 /* Descriptor for use as a storage image as opposed to a sampled image.
1613 * This has a few differences for cube maps (e.g. type).
1614 */
1615 uint32_t storage_descriptor[16];
1616 };
1617
1618 struct radv_image_create_info {
1619 const VkImageCreateInfo *vk_info;
1620 bool scanout;
1621 bool no_metadata_planes;
1622 };
1623
1624 VkResult radv_image_create(VkDevice _device,
1625 const struct radv_image_create_info *info,
1626 const VkAllocationCallbacks* alloc,
1627 VkImage *pImage);
1628
1629 VkResult
1630 radv_image_from_gralloc(VkDevice device_h,
1631 const VkImageCreateInfo *base_info,
1632 const VkNativeBufferANDROID *gralloc_info,
1633 const VkAllocationCallbacks *alloc,
1634 VkImage *out_image_h);
1635
1636 void radv_image_view_init(struct radv_image_view *view,
1637 struct radv_device *device,
1638 const VkImageViewCreateInfo* pCreateInfo);
1639
1640 struct radv_buffer_view {
1641 struct radeon_winsys_bo *bo;
1642 VkFormat vk_format;
1643 uint64_t range; /**< VkBufferViewCreateInfo::range */
1644 uint32_t state[4];
1645 };
1646 void radv_buffer_view_init(struct radv_buffer_view *view,
1647 struct radv_device *device,
1648 const VkBufferViewCreateInfo* pCreateInfo);
1649
1650 static inline struct VkExtent3D
1651 radv_sanitize_image_extent(const VkImageType imageType,
1652 const struct VkExtent3D imageExtent)
1653 {
1654 switch (imageType) {
1655 case VK_IMAGE_TYPE_1D:
1656 return (VkExtent3D) { imageExtent.width, 1, 1 };
1657 case VK_IMAGE_TYPE_2D:
1658 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1659 case VK_IMAGE_TYPE_3D:
1660 return imageExtent;
1661 default:
1662 unreachable("invalid image type");
1663 }
1664 }
1665
1666 static inline struct VkOffset3D
1667 radv_sanitize_image_offset(const VkImageType imageType,
1668 const struct VkOffset3D imageOffset)
1669 {
1670 switch (imageType) {
1671 case VK_IMAGE_TYPE_1D:
1672 return (VkOffset3D) { imageOffset.x, 0, 0 };
1673 case VK_IMAGE_TYPE_2D:
1674 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1675 case VK_IMAGE_TYPE_3D:
1676 return imageOffset;
1677 default:
1678 unreachable("invalid image type");
1679 }
1680 }
1681
1682 static inline bool
1683 radv_image_extent_compare(const struct radv_image *image,
1684 const VkExtent3D *extent)
1685 {
1686 if (extent->width != image->info.width ||
1687 extent->height != image->info.height ||
1688 extent->depth != image->info.depth)
1689 return false;
1690 return true;
1691 }
1692
1693 struct radv_sampler {
1694 uint32_t state[4];
1695 };
1696
1697 struct radv_color_buffer_info {
1698 uint64_t cb_color_base;
1699 uint64_t cb_color_cmask;
1700 uint64_t cb_color_fmask;
1701 uint64_t cb_dcc_base;
1702 uint32_t cb_color_pitch;
1703 uint32_t cb_color_slice;
1704 uint32_t cb_color_view;
1705 uint32_t cb_color_info;
1706 uint32_t cb_color_attrib;
1707 uint32_t cb_color_attrib2;
1708 uint32_t cb_dcc_control;
1709 uint32_t cb_color_cmask_slice;
1710 uint32_t cb_color_fmask_slice;
1711 };
1712
1713 struct radv_ds_buffer_info {
1714 uint64_t db_z_read_base;
1715 uint64_t db_stencil_read_base;
1716 uint64_t db_z_write_base;
1717 uint64_t db_stencil_write_base;
1718 uint64_t db_htile_data_base;
1719 uint32_t db_depth_info;
1720 uint32_t db_z_info;
1721 uint32_t db_stencil_info;
1722 uint32_t db_depth_view;
1723 uint32_t db_depth_size;
1724 uint32_t db_depth_slice;
1725 uint32_t db_htile_surface;
1726 uint32_t pa_su_poly_offset_db_fmt_cntl;
1727 uint32_t db_z_info2;
1728 uint32_t db_stencil_info2;
1729 float offset_scale;
1730 };
1731
1732 struct radv_attachment_info {
1733 union {
1734 struct radv_color_buffer_info cb;
1735 struct radv_ds_buffer_info ds;
1736 };
1737 struct radv_image_view *attachment;
1738 };
1739
1740 struct radv_framebuffer {
1741 uint32_t width;
1742 uint32_t height;
1743 uint32_t layers;
1744
1745 uint32_t attachment_count;
1746 struct radv_attachment_info attachments[0];
1747 };
1748
1749 struct radv_subpass_barrier {
1750 VkPipelineStageFlags src_stage_mask;
1751 VkAccessFlags src_access_mask;
1752 VkAccessFlags dst_access_mask;
1753 };
1754
1755 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1756 const struct radv_subpass_barrier *barrier);
1757
1758 struct radv_subpass_attachment {
1759 uint32_t attachment;
1760 VkImageLayout layout;
1761 };
1762
1763 struct radv_subpass {
1764 uint32_t input_count;
1765 uint32_t color_count;
1766 struct radv_subpass_attachment * input_attachments;
1767 struct radv_subpass_attachment * color_attachments;
1768 struct radv_subpass_attachment * resolve_attachments;
1769 struct radv_subpass_attachment depth_stencil_attachment;
1770
1771 /** Subpass has at least one resolve attachment */
1772 bool has_resolve;
1773
1774 struct radv_subpass_barrier start_barrier;
1775
1776 uint32_t view_mask;
1777 VkSampleCountFlagBits max_sample_count;
1778 };
1779
1780 struct radv_render_pass_attachment {
1781 VkFormat format;
1782 uint32_t samples;
1783 VkAttachmentLoadOp load_op;
1784 VkAttachmentLoadOp stencil_load_op;
1785 VkImageLayout initial_layout;
1786 VkImageLayout final_layout;
1787 uint32_t view_mask;
1788 };
1789
1790 struct radv_render_pass {
1791 uint32_t attachment_count;
1792 uint32_t subpass_count;
1793 struct radv_subpass_attachment * subpass_attachments;
1794 struct radv_render_pass_attachment * attachments;
1795 struct radv_subpass_barrier end_barrier;
1796 struct radv_subpass subpasses[0];
1797 };
1798
1799 VkResult radv_device_init_meta(struct radv_device *device);
1800 void radv_device_finish_meta(struct radv_device *device);
1801
1802 struct radv_query_pool {
1803 struct radeon_winsys_bo *bo;
1804 uint32_t stride;
1805 uint32_t availability_offset;
1806 uint64_t size;
1807 char *ptr;
1808 VkQueryType type;
1809 uint32_t pipeline_stats_mask;
1810 };
1811
1812 struct radv_semaphore {
1813 /* use a winsys sem for non-exportable */
1814 struct radeon_winsys_sem *sem;
1815 uint32_t syncobj;
1816 uint32_t temp_syncobj;
1817 };
1818
1819 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1820 VkPipelineBindPoint bind_point,
1821 struct radv_descriptor_set *set,
1822 unsigned idx);
1823
1824 void
1825 radv_update_descriptor_sets(struct radv_device *device,
1826 struct radv_cmd_buffer *cmd_buffer,
1827 VkDescriptorSet overrideSet,
1828 uint32_t descriptorWriteCount,
1829 const VkWriteDescriptorSet *pDescriptorWrites,
1830 uint32_t descriptorCopyCount,
1831 const VkCopyDescriptorSet *pDescriptorCopies);
1832
1833 void
1834 radv_update_descriptor_set_with_template(struct radv_device *device,
1835 struct radv_cmd_buffer *cmd_buffer,
1836 struct radv_descriptor_set *set,
1837 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1838 const void *pData);
1839
1840 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1841 VkPipelineBindPoint pipelineBindPoint,
1842 VkPipelineLayout _layout,
1843 uint32_t set,
1844 uint32_t descriptorWriteCount,
1845 const VkWriteDescriptorSet *pDescriptorWrites);
1846
1847 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1848 struct radv_image *image, uint32_t value);
1849
1850 struct radv_fence {
1851 struct radeon_winsys_fence *fence;
1852 struct wsi_fence *fence_wsi;
1853 bool submitted;
1854 bool signalled;
1855
1856 uint32_t syncobj;
1857 uint32_t temp_syncobj;
1858 };
1859
1860 /* radv_nir_to_llvm.c */
1861 struct radv_shader_variant_info;
1862 struct radv_nir_compiler_options;
1863
1864 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
1865 struct nir_shader *geom_shader,
1866 struct ac_shader_binary *binary,
1867 struct ac_shader_config *config,
1868 struct radv_shader_variant_info *shader_info,
1869 const struct radv_nir_compiler_options *option);
1870
1871 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
1872 struct ac_shader_binary *binary,
1873 struct ac_shader_config *config,
1874 struct radv_shader_variant_info *shader_info,
1875 struct nir_shader *const *nir,
1876 int nir_count,
1877 const struct radv_nir_compiler_options *options);
1878
1879 /* radv_shader_info.h */
1880 struct radv_shader_info;
1881
1882 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1883 const struct radv_nir_compiler_options *options,
1884 struct radv_shader_info *info);
1885
1886 struct radeon_winsys_sem;
1887
1888 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1889 \
1890 static inline struct __radv_type * \
1891 __radv_type ## _from_handle(__VkType _handle) \
1892 { \
1893 return (struct __radv_type *) _handle; \
1894 } \
1895 \
1896 static inline __VkType \
1897 __radv_type ## _to_handle(struct __radv_type *_obj) \
1898 { \
1899 return (__VkType) _obj; \
1900 }
1901
1902 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1903 \
1904 static inline struct __radv_type * \
1905 __radv_type ## _from_handle(__VkType _handle) \
1906 { \
1907 return (struct __radv_type *)(uintptr_t) _handle; \
1908 } \
1909 \
1910 static inline __VkType \
1911 __radv_type ## _to_handle(struct __radv_type *_obj) \
1912 { \
1913 return (__VkType)(uintptr_t) _obj; \
1914 }
1915
1916 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1917 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1918
1919 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1920 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1921 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1922 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1923 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1924
1925 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1926 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1927 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1928 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1929 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1930 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1931 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1932 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1933 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1934 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1935 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1936 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1937 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1938 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1939 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1940 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1941 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1942 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1943 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1944 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1945 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1946
1947 #endif /* RADV_PRIVATE_H */