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radv: add radv_emit_shader_pointer() helper
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "radv_descriptor_set.h"
61 #include "radv_extensions.h"
62 #include "radv_cs.h"
63
64 #include <llvm-c/TargetMachine.h>
65
66 /* Pre-declarations needed for WSI entrypoints */
67 struct wl_surface;
68 struct wl_display;
69 typedef struct xcb_connection_t xcb_connection_t;
70 typedef uint32_t xcb_visualid_t;
71 typedef uint32_t xcb_window_t;
72
73 #include <vulkan/vulkan.h>
74 #include <vulkan/vulkan_intel.h>
75 #include <vulkan/vk_icd.h>
76 #include <vulkan/vk_android_native_buffer.h>
77
78 #include "radv_entrypoints.h"
79
80 #include "wsi_common.h"
81
82 #define ATI_VENDOR_ID 0x1002
83
84 #define MAX_VBS 32
85 #define MAX_VERTEX_ATTRIBS 32
86 #define MAX_RTS 8
87 #define MAX_VIEWPORTS 16
88 #define MAX_SCISSORS 16
89 #define MAX_DISCARD_RECTANGLES 4
90 #define MAX_PUSH_CONSTANTS_SIZE 128
91 #define MAX_PUSH_DESCRIPTORS 32
92 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
93 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
94 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
95 #define MAX_SAMPLES_LOG2 4
96 #define NUM_META_FS_KEYS 13
97 #define RADV_MAX_DRM_DEVICES 8
98 #define MAX_VIEWS 8
99
100 #define NUM_DEPTH_CLEAR_PIPELINES 3
101
102 /*
103 * This is the point we switch from using CP to compute shader
104 * for certain buffer operations.
105 */
106 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
107
108 enum radv_mem_heap {
109 RADV_MEM_HEAP_VRAM,
110 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
111 RADV_MEM_HEAP_GTT,
112 RADV_MEM_HEAP_COUNT
113 };
114
115 enum radv_mem_type {
116 RADV_MEM_TYPE_VRAM,
117 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
118 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
119 RADV_MEM_TYPE_GTT_CACHED,
120 RADV_MEM_TYPE_COUNT
121 };
122
123 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
124
125 static inline uint32_t
126 align_u32(uint32_t v, uint32_t a)
127 {
128 assert(a != 0 && a == (a & -a));
129 return (v + a - 1) & ~(a - 1);
130 }
131
132 static inline uint32_t
133 align_u32_npot(uint32_t v, uint32_t a)
134 {
135 return (v + a - 1) / a * a;
136 }
137
138 static inline uint64_t
139 align_u64(uint64_t v, uint64_t a)
140 {
141 assert(a != 0 && a == (a & -a));
142 return (v + a - 1) & ~(a - 1);
143 }
144
145 static inline int32_t
146 align_i32(int32_t v, int32_t a)
147 {
148 assert(a != 0 && a == (a & -a));
149 return (v + a - 1) & ~(a - 1);
150 }
151
152 /** Alignment must be a power of 2. */
153 static inline bool
154 radv_is_aligned(uintmax_t n, uintmax_t a)
155 {
156 assert(a == (a & -a));
157 return (n & (a - 1)) == 0;
158 }
159
160 static inline uint32_t
161 round_up_u32(uint32_t v, uint32_t a)
162 {
163 return (v + a - 1) / a;
164 }
165
166 static inline uint64_t
167 round_up_u64(uint64_t v, uint64_t a)
168 {
169 return (v + a - 1) / a;
170 }
171
172 static inline uint32_t
173 radv_minify(uint32_t n, uint32_t levels)
174 {
175 if (unlikely(n == 0))
176 return 0;
177 else
178 return MAX2(n >> levels, 1);
179 }
180 static inline float
181 radv_clamp_f(float f, float min, float max)
182 {
183 assert(min < max);
184
185 if (f > max)
186 return max;
187 else if (f < min)
188 return min;
189 else
190 return f;
191 }
192
193 static inline bool
194 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
195 {
196 if (*inout_mask & clear_mask) {
197 *inout_mask &= ~clear_mask;
198 return true;
199 } else {
200 return false;
201 }
202 }
203
204 #define for_each_bit(b, dword) \
205 for (uint32_t __dword = (dword); \
206 (b) = __builtin_ffs(__dword) - 1, __dword; \
207 __dword &= ~(1 << (b)))
208
209 #define typed_memcpy(dest, src, count) ({ \
210 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
211 memcpy((dest), (src), (count) * sizeof(*(src))); \
212 })
213
214 /* Whenever we generate an error, pass it through this function. Useful for
215 * debugging, where we can break on it. Only call at error site, not when
216 * propagating errors. Might be useful to plug in a stack trace here.
217 */
218
219 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
220
221 #ifdef DEBUG
222 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
223 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
224 #else
225 #define vk_error(error) error
226 #define vk_errorf(error, format, ...) error
227 #endif
228
229 void __radv_finishme(const char *file, int line, const char *format, ...)
230 radv_printflike(3, 4);
231 void radv_loge(const char *format, ...) radv_printflike(1, 2);
232 void radv_loge_v(const char *format, va_list va);
233
234 /**
235 * Print a FINISHME message, including its source location.
236 */
237 #define radv_finishme(format, ...) \
238 do { \
239 static bool reported = false; \
240 if (!reported) { \
241 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
242 reported = true; \
243 } \
244 } while (0)
245
246 /* A non-fatal assert. Useful for debugging. */
247 #ifdef DEBUG
248 #define radv_assert(x) ({ \
249 if (unlikely(!(x))) \
250 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
251 })
252 #else
253 #define radv_assert(x)
254 #endif
255
256 #define stub_return(v) \
257 do { \
258 radv_finishme("stub %s", __func__); \
259 return (v); \
260 } while (0)
261
262 #define stub() \
263 do { \
264 radv_finishme("stub %s", __func__); \
265 return; \
266 } while (0)
267
268 void *radv_lookup_entrypoint_unchecked(const char *name);
269 void *radv_lookup_entrypoint_checked(const char *name,
270 uint32_t core_version,
271 const struct radv_instance_extension_table *instance,
272 const struct radv_device_extension_table *device);
273
274 struct radv_physical_device {
275 VK_LOADER_DATA _loader_data;
276
277 struct radv_instance * instance;
278
279 struct radeon_winsys *ws;
280 struct radeon_info rad_info;
281 char path[20];
282 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
283 uint8_t driver_uuid[VK_UUID_SIZE];
284 uint8_t device_uuid[VK_UUID_SIZE];
285 uint8_t cache_uuid[VK_UUID_SIZE];
286
287 int local_fd;
288 struct wsi_device wsi_device;
289
290 bool has_rbplus; /* if RB+ register exist */
291 bool rbplus_allowed; /* if RB+ is allowed */
292 bool has_clear_state;
293 bool cpdma_prefetch_writes_memory;
294 bool has_scissor_bug;
295
296 bool has_out_of_order_rast;
297 bool out_of_order_rast_allowed;
298
299 /* Whether DCC should be enabled for MSAA textures. */
300 bool dcc_msaa_allowed;
301
302 /* This is the drivers on-disk cache used as a fallback as opposed to
303 * the pipeline cache defined by apps.
304 */
305 struct disk_cache * disk_cache;
306
307 VkPhysicalDeviceMemoryProperties memory_properties;
308 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
309
310 struct radv_device_extension_table supported_extensions;
311 };
312
313 struct radv_instance {
314 VK_LOADER_DATA _loader_data;
315
316 VkAllocationCallbacks alloc;
317
318 uint32_t apiVersion;
319 int physicalDeviceCount;
320 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
321
322 uint64_t debug_flags;
323 uint64_t perftest_flags;
324
325 struct vk_debug_report_instance debug_report_callbacks;
326
327 struct radv_instance_extension_table enabled_extensions;
328 };
329
330 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
331 void radv_finish_wsi(struct radv_physical_device *physical_device);
332
333 bool radv_instance_extension_supported(const char *name);
334 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
335 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
336 const char *name);
337
338 struct cache_entry;
339
340 struct radv_pipeline_cache {
341 struct radv_device * device;
342 pthread_mutex_t mutex;
343
344 uint32_t total_size;
345 uint32_t table_size;
346 uint32_t kernel_count;
347 struct cache_entry ** hash_table;
348 bool modified;
349
350 VkAllocationCallbacks alloc;
351 };
352
353 struct radv_pipeline_key {
354 uint32_t instance_rate_inputs;
355 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
356 uint64_t vertex_alpha_adjust;
357 unsigned tess_input_vertices;
358 uint32_t col_format;
359 uint32_t is_int8;
360 uint32_t is_int10;
361 uint8_t log2_ps_iter_samples;
362 uint8_t log2_num_samples;
363 uint32_t multisample : 1;
364 uint32_t has_multiview_view_index : 1;
365 uint32_t optimisations_disabled : 1;
366 };
367
368 void
369 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
370 struct radv_device *device);
371 void
372 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
373 void
374 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
375 const void *data, size_t size);
376
377 struct radv_shader_variant;
378
379 bool
380 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
381 struct radv_pipeline_cache *cache,
382 const unsigned char *sha1,
383 struct radv_shader_variant **variants);
384
385 void
386 radv_pipeline_cache_insert_shaders(struct radv_device *device,
387 struct radv_pipeline_cache *cache,
388 const unsigned char *sha1,
389 struct radv_shader_variant **variants,
390 const void *const *codes,
391 const unsigned *code_sizes);
392
393 enum radv_blit_ds_layout {
394 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
395 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
396 RADV_BLIT_DS_LAYOUT_COUNT,
397 };
398
399 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
400 {
401 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
402 }
403
404 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
405 {
406 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
407 }
408
409 enum radv_meta_dst_layout {
410 RADV_META_DST_LAYOUT_GENERAL,
411 RADV_META_DST_LAYOUT_OPTIMAL,
412 RADV_META_DST_LAYOUT_COUNT,
413 };
414
415 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
416 {
417 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
418 }
419
420 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
421 {
422 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
423 }
424
425 struct radv_meta_state {
426 VkAllocationCallbacks alloc;
427
428 struct radv_pipeline_cache cache;
429
430 /**
431 * Use array element `i` for images with `2^i` samples.
432 */
433 struct {
434 VkRenderPass render_pass[NUM_META_FS_KEYS];
435 VkPipeline color_pipelines[NUM_META_FS_KEYS];
436
437 VkRenderPass depthstencil_rp;
438 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
439 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
440 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
441 } clear[1 + MAX_SAMPLES_LOG2];
442
443 VkPipelineLayout clear_color_p_layout;
444 VkPipelineLayout clear_depth_p_layout;
445 struct {
446 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
447
448 /** Pipeline that blits from a 1D image. */
449 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
450
451 /** Pipeline that blits from a 2D image. */
452 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
453
454 /** Pipeline that blits from a 3D image. */
455 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
456
457 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
458 VkPipeline depth_only_1d_pipeline;
459 VkPipeline depth_only_2d_pipeline;
460 VkPipeline depth_only_3d_pipeline;
461
462 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
463 VkPipeline stencil_only_1d_pipeline;
464 VkPipeline stencil_only_2d_pipeline;
465 VkPipeline stencil_only_3d_pipeline;
466 VkPipelineLayout pipeline_layout;
467 VkDescriptorSetLayout ds_layout;
468 } blit;
469
470 struct {
471 VkPipelineLayout p_layouts[5];
472 VkDescriptorSetLayout ds_layouts[5];
473 VkPipeline pipelines[5][NUM_META_FS_KEYS];
474
475 VkPipeline depth_only_pipeline[5];
476
477 VkPipeline stencil_only_pipeline[5];
478 } blit2d[1 + MAX_SAMPLES_LOG2];
479
480 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
481 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
482 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
483
484 struct {
485 VkPipelineLayout img_p_layout;
486 VkDescriptorSetLayout img_ds_layout;
487 VkPipeline pipeline;
488 VkPipeline pipeline_3d;
489 } itob;
490 struct {
491 VkPipelineLayout img_p_layout;
492 VkDescriptorSetLayout img_ds_layout;
493 VkPipeline pipeline;
494 VkPipeline pipeline_3d;
495 } btoi;
496 struct {
497 VkPipelineLayout img_p_layout;
498 VkDescriptorSetLayout img_ds_layout;
499 VkPipeline pipeline;
500 VkPipeline pipeline_3d;
501 } itoi;
502 struct {
503 VkPipelineLayout img_p_layout;
504 VkDescriptorSetLayout img_ds_layout;
505 VkPipeline pipeline;
506 VkPipeline pipeline_3d;
507 } cleari;
508
509 struct {
510 VkPipelineLayout p_layout;
511 VkPipeline pipeline[NUM_META_FS_KEYS];
512 VkRenderPass pass[NUM_META_FS_KEYS];
513 } resolve;
514
515 struct {
516 VkDescriptorSetLayout ds_layout;
517 VkPipelineLayout p_layout;
518 struct {
519 VkPipeline pipeline;
520 VkPipeline i_pipeline;
521 VkPipeline srgb_pipeline;
522 } rc[MAX_SAMPLES_LOG2];
523 } resolve_compute;
524
525 struct {
526 VkDescriptorSetLayout ds_layout;
527 VkPipelineLayout p_layout;
528
529 struct {
530 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
531 VkPipeline pipeline[NUM_META_FS_KEYS];
532 } rc[MAX_SAMPLES_LOG2];
533 } resolve_fragment;
534
535 struct {
536 VkPipelineLayout p_layout;
537 VkPipeline decompress_pipeline;
538 VkPipeline resummarize_pipeline;
539 VkRenderPass pass;
540 } depth_decomp[1 + MAX_SAMPLES_LOG2];
541
542 struct {
543 VkPipelineLayout p_layout;
544 VkPipeline cmask_eliminate_pipeline;
545 VkPipeline fmask_decompress_pipeline;
546 VkPipeline dcc_decompress_pipeline;
547 VkRenderPass pass;
548
549 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
550 VkPipelineLayout dcc_decompress_compute_p_layout;
551 VkPipeline dcc_decompress_compute_pipeline;
552 } fast_clear_flush;
553
554 struct {
555 VkPipelineLayout fill_p_layout;
556 VkPipelineLayout copy_p_layout;
557 VkDescriptorSetLayout fill_ds_layout;
558 VkDescriptorSetLayout copy_ds_layout;
559 VkPipeline fill_pipeline;
560 VkPipeline copy_pipeline;
561 } buffer;
562
563 struct {
564 VkDescriptorSetLayout ds_layout;
565 VkPipelineLayout p_layout;
566 VkPipeline occlusion_query_pipeline;
567 VkPipeline pipeline_statistics_query_pipeline;
568 } query;
569 };
570
571 /* queue types */
572 #define RADV_QUEUE_GENERAL 0
573 #define RADV_QUEUE_COMPUTE 1
574 #define RADV_QUEUE_TRANSFER 2
575
576 #define RADV_MAX_QUEUE_FAMILIES 3
577
578 enum ring_type radv_queue_family_to_ring(int f);
579
580 struct radv_queue {
581 VK_LOADER_DATA _loader_data;
582 struct radv_device * device;
583 struct radeon_winsys_ctx *hw_ctx;
584 enum radeon_ctx_priority priority;
585 uint32_t queue_family_index;
586 int queue_idx;
587 VkDeviceQueueCreateFlags flags;
588
589 uint32_t scratch_size;
590 uint32_t compute_scratch_size;
591 uint32_t esgs_ring_size;
592 uint32_t gsvs_ring_size;
593 bool has_tess_rings;
594 bool has_sample_positions;
595
596 struct radeon_winsys_bo *scratch_bo;
597 struct radeon_winsys_bo *descriptor_bo;
598 struct radeon_winsys_bo *compute_scratch_bo;
599 struct radeon_winsys_bo *esgs_ring_bo;
600 struct radeon_winsys_bo *gsvs_ring_bo;
601 struct radeon_winsys_bo *tess_rings_bo;
602 struct radeon_winsys_cs *initial_preamble_cs;
603 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
604 struct radeon_winsys_cs *continue_preamble_cs;
605 };
606
607 struct radv_bo_list {
608 struct radv_winsys_bo_list list;
609 unsigned capacity;
610 pthread_mutex_t mutex;
611 };
612
613 struct radv_device {
614 VK_LOADER_DATA _loader_data;
615
616 VkAllocationCallbacks alloc;
617
618 struct radv_instance * instance;
619 struct radeon_winsys *ws;
620
621 struct radv_meta_state meta_state;
622
623 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
624 int queue_count[RADV_MAX_QUEUE_FAMILIES];
625 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
626
627 bool always_use_syncobj;
628 bool has_distributed_tess;
629 bool pbb_allowed;
630 bool dfsm_allowed;
631 uint32_t tess_offchip_block_dw_size;
632 uint32_t scratch_waves;
633 uint32_t dispatch_initiator;
634
635 uint32_t gs_table_depth;
636
637 /* MSAA sample locations.
638 * The first index is the sample index.
639 * The second index is the coordinate: X, Y. */
640 float sample_locations_1x[1][2];
641 float sample_locations_2x[2][2];
642 float sample_locations_4x[4][2];
643 float sample_locations_8x[8][2];
644 float sample_locations_16x[16][2];
645
646 /* CIK and later */
647 uint32_t gfx_init_size_dw;
648 struct radeon_winsys_bo *gfx_init;
649
650 struct radeon_winsys_bo *trace_bo;
651 uint32_t *trace_id_ptr;
652
653 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
654 bool keep_shader_info;
655
656 struct radv_physical_device *physical_device;
657
658 /* Backup in-memory cache to be used if the app doesn't provide one */
659 struct radv_pipeline_cache * mem_cache;
660
661 /*
662 * use different counters so MSAA MRTs get consecutive surface indices,
663 * even if MASK is allocated in between.
664 */
665 uint32_t image_mrt_offset_counter;
666 uint32_t fmask_mrt_offset_counter;
667 struct list_head shader_slabs;
668 mtx_t shader_slab_mutex;
669
670 /* For detecting VM faults reported by dmesg. */
671 uint64_t dmesg_timestamp;
672
673 struct radv_device_extension_table enabled_extensions;
674
675 /* Whether the driver uses a global BO list. */
676 bool use_global_bo_list;
677
678 struct radv_bo_list bo_list;
679 };
680
681 struct radv_device_memory {
682 struct radeon_winsys_bo *bo;
683 /* for dedicated allocations */
684 struct radv_image *image;
685 struct radv_buffer *buffer;
686 uint32_t type_index;
687 VkDeviceSize map_size;
688 void * map;
689 void * user_ptr;
690 };
691
692
693 struct radv_descriptor_range {
694 uint64_t va;
695 uint32_t size;
696 };
697
698 struct radv_descriptor_set {
699 const struct radv_descriptor_set_layout *layout;
700 uint32_t size;
701
702 struct radeon_winsys_bo *bo;
703 uint64_t va;
704 uint32_t *mapped_ptr;
705 struct radv_descriptor_range *dynamic_descriptors;
706
707 struct radeon_winsys_bo *descriptors[0];
708 };
709
710 struct radv_push_descriptor_set
711 {
712 struct radv_descriptor_set set;
713 uint32_t capacity;
714 };
715
716 struct radv_descriptor_pool_entry {
717 uint32_t offset;
718 uint32_t size;
719 struct radv_descriptor_set *set;
720 };
721
722 struct radv_descriptor_pool {
723 struct radeon_winsys_bo *bo;
724 uint8_t *mapped_ptr;
725 uint64_t current_offset;
726 uint64_t size;
727
728 uint8_t *host_memory_base;
729 uint8_t *host_memory_ptr;
730 uint8_t *host_memory_end;
731
732 uint32_t entry_count;
733 uint32_t max_entry_count;
734 struct radv_descriptor_pool_entry entries[0];
735 };
736
737 struct radv_descriptor_update_template_entry {
738 VkDescriptorType descriptor_type;
739
740 /* The number of descriptors to update */
741 uint32_t descriptor_count;
742
743 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
744 uint32_t dst_offset;
745
746 /* In dwords. Not valid/used for dynamic descriptors */
747 uint32_t dst_stride;
748
749 uint32_t buffer_offset;
750
751 /* Only valid for combined image samplers and samplers */
752 uint16_t has_sampler;
753
754 /* In bytes */
755 size_t src_offset;
756 size_t src_stride;
757
758 /* For push descriptors */
759 const uint32_t *immutable_samplers;
760 };
761
762 struct radv_descriptor_update_template {
763 uint32_t entry_count;
764 VkPipelineBindPoint bind_point;
765 struct radv_descriptor_update_template_entry entry[0];
766 };
767
768 struct radv_buffer {
769 VkDeviceSize size;
770
771 VkBufferUsageFlags usage;
772 VkBufferCreateFlags flags;
773
774 /* Set when bound */
775 struct radeon_winsys_bo * bo;
776 VkDeviceSize offset;
777
778 bool shareable;
779 };
780
781 enum radv_dynamic_state_bits {
782 RADV_DYNAMIC_VIEWPORT = 1 << 0,
783 RADV_DYNAMIC_SCISSOR = 1 << 1,
784 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
785 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
786 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
787 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
788 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
789 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
790 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
791 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
792 RADV_DYNAMIC_ALL = (1 << 10) - 1,
793 };
794
795 enum radv_cmd_dirty_bits {
796 /* Keep the dynamic state dirty bits in sync with
797 * enum radv_dynamic_state_bits */
798 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
799 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
800 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
801 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
802 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
803 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
804 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
805 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
806 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
807 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
808 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
809 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
810 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
811 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
812 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
813 };
814
815 enum radv_cmd_flush_bits {
816 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
817 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
818 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
819 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
820 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
821 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
822 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
823 /* Same as above, but only writes back and doesn't invalidate */
824 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
825 /* Framebuffer caches */
826 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
827 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
828 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
829 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
830 /* Engine synchronization. */
831 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
832 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
833 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
834 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
835
836 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
837 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
838 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
839 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
840 };
841
842 struct radv_vertex_binding {
843 struct radv_buffer * buffer;
844 VkDeviceSize offset;
845 };
846
847 struct radv_viewport_state {
848 uint32_t count;
849 VkViewport viewports[MAX_VIEWPORTS];
850 };
851
852 struct radv_scissor_state {
853 uint32_t count;
854 VkRect2D scissors[MAX_SCISSORS];
855 };
856
857 struct radv_discard_rectangle_state {
858 uint32_t count;
859 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
860 };
861
862 struct radv_dynamic_state {
863 /**
864 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
865 * Defines the set of saved dynamic state.
866 */
867 uint32_t mask;
868
869 struct radv_viewport_state viewport;
870
871 struct radv_scissor_state scissor;
872
873 float line_width;
874
875 struct {
876 float bias;
877 float clamp;
878 float slope;
879 } depth_bias;
880
881 float blend_constants[4];
882
883 struct {
884 float min;
885 float max;
886 } depth_bounds;
887
888 struct {
889 uint32_t front;
890 uint32_t back;
891 } stencil_compare_mask;
892
893 struct {
894 uint32_t front;
895 uint32_t back;
896 } stencil_write_mask;
897
898 struct {
899 uint32_t front;
900 uint32_t back;
901 } stencil_reference;
902
903 struct radv_discard_rectangle_state discard_rectangle;
904 };
905
906 extern const struct radv_dynamic_state default_dynamic_state;
907
908 const char *
909 radv_get_debug_option_name(int id);
910
911 const char *
912 radv_get_perftest_option_name(int id);
913
914 /**
915 * Attachment state when recording a renderpass instance.
916 *
917 * The clear value is valid only if there exists a pending clear.
918 */
919 struct radv_attachment_state {
920 VkImageAspectFlags pending_clear_aspects;
921 uint32_t cleared_views;
922 VkClearValue clear_value;
923 VkImageLayout current_layout;
924 };
925
926 struct radv_descriptor_state {
927 struct radv_descriptor_set *sets[MAX_SETS];
928 uint32_t dirty;
929 uint32_t valid;
930 struct radv_push_descriptor_set push_set;
931 bool push_dirty;
932 };
933
934 struct radv_cmd_state {
935 /* Vertex descriptors */
936 uint64_t vb_va;
937 unsigned vb_size;
938
939 bool predicating;
940 uint32_t dirty;
941
942 uint32_t prefetch_L2_mask;
943
944 struct radv_pipeline * pipeline;
945 struct radv_pipeline * emitted_pipeline;
946 struct radv_pipeline * compute_pipeline;
947 struct radv_pipeline * emitted_compute_pipeline;
948 struct radv_framebuffer * framebuffer;
949 struct radv_render_pass * pass;
950 const struct radv_subpass * subpass;
951 struct radv_dynamic_state dynamic;
952 struct radv_attachment_state * attachments;
953 VkRect2D render_area;
954
955 /* Index buffer */
956 struct radv_buffer *index_buffer;
957 uint64_t index_offset;
958 uint32_t index_type;
959 uint32_t max_index_count;
960 uint64_t index_va;
961 int32_t last_index_type;
962
963 int32_t last_primitive_reset_en;
964 uint32_t last_primitive_reset_index;
965 enum radv_cmd_flush_bits flush_bits;
966 unsigned active_occlusion_queries;
967 bool perfect_occlusion_queries_enabled;
968 float offset_scale;
969 uint32_t trace_id;
970 uint32_t last_ia_multi_vgt_param;
971
972 uint32_t last_num_instances;
973 uint32_t last_first_instance;
974 uint32_t last_vertex_offset;
975 };
976
977 struct radv_cmd_pool {
978 VkAllocationCallbacks alloc;
979 struct list_head cmd_buffers;
980 struct list_head free_cmd_buffers;
981 uint32_t queue_family_index;
982 };
983
984 struct radv_cmd_buffer_upload {
985 uint8_t *map;
986 unsigned offset;
987 uint64_t size;
988 struct radeon_winsys_bo *upload_bo;
989 struct list_head list;
990 };
991
992 enum radv_cmd_buffer_status {
993 RADV_CMD_BUFFER_STATUS_INVALID,
994 RADV_CMD_BUFFER_STATUS_INITIAL,
995 RADV_CMD_BUFFER_STATUS_RECORDING,
996 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
997 RADV_CMD_BUFFER_STATUS_PENDING,
998 };
999
1000 struct radv_cmd_buffer {
1001 VK_LOADER_DATA _loader_data;
1002
1003 struct radv_device * device;
1004
1005 struct radv_cmd_pool * pool;
1006 struct list_head pool_link;
1007
1008 VkCommandBufferUsageFlags usage_flags;
1009 VkCommandBufferLevel level;
1010 enum radv_cmd_buffer_status status;
1011 struct radeon_winsys_cs *cs;
1012 struct radv_cmd_state state;
1013 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1014 uint32_t queue_family_index;
1015
1016 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1017 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1018 VkShaderStageFlags push_constant_stages;
1019 struct radv_descriptor_set meta_push_descriptors;
1020
1021 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1022
1023 struct radv_cmd_buffer_upload upload;
1024
1025 uint32_t scratch_size_needed;
1026 uint32_t compute_scratch_size_needed;
1027 uint32_t esgs_ring_size_needed;
1028 uint32_t gsvs_ring_size_needed;
1029 bool tess_rings_needed;
1030 bool sample_positions_needed;
1031
1032 VkResult record_result;
1033
1034 int ring_offsets_idx; /* just used for verification */
1035 uint32_t gfx9_fence_offset;
1036 struct radeon_winsys_bo *gfx9_fence_bo;
1037 uint32_t gfx9_fence_idx;
1038
1039 /**
1040 * Whether a query pool has been resetted and we have to flush caches.
1041 */
1042 bool pending_reset_query;
1043 };
1044
1045 struct radv_image;
1046
1047 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1048
1049 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
1050 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
1051
1052 void cik_create_gfx_config(struct radv_device *device);
1053
1054 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
1055 int count, const VkViewport *viewports);
1056 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
1057 int count, const VkRect2D *scissors,
1058 const VkViewport *viewports, bool can_use_guardband);
1059 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1060 bool instanced_draw, bool indirect_draw,
1061 uint32_t draw_vertex_count);
1062 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
1063 bool predicated,
1064 enum chip_class chip_class,
1065 bool is_mec,
1066 unsigned event, unsigned event_flags,
1067 unsigned data_sel,
1068 uint64_t va,
1069 uint32_t old_fence,
1070 uint32_t new_fence);
1071
1072 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
1073 bool predicated,
1074 uint64_t va, uint32_t ref,
1075 uint32_t mask);
1076 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
1077 enum chip_class chip_class,
1078 uint32_t *fence_ptr, uint64_t va,
1079 bool is_mec,
1080 enum radv_cmd_flush_bits flush_bits);
1081 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1082 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1083 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1084 uint64_t src_va, uint64_t dest_va,
1085 uint64_t size);
1086 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1087 unsigned size);
1088 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1089 uint64_t size, unsigned value);
1090 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1091 bool
1092 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1093 unsigned size,
1094 unsigned alignment,
1095 unsigned *out_offset,
1096 void **ptr);
1097 void
1098 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1099 const struct radv_subpass *subpass,
1100 bool transitions);
1101 bool
1102 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1103 unsigned size, unsigned alignmnet,
1104 const void *data, unsigned *out_offset);
1105
1106 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1107 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1108 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1109 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1110 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1111 unsigned radv_cayman_get_maxdist(int log_samples);
1112 void radv_device_init_msaa(struct radv_device *device);
1113 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1114 struct radv_image *image,
1115 VkClearDepthStencilValue ds_clear_value,
1116 VkImageAspectFlags aspects);
1117 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1118 struct radv_image *image,
1119 int idx,
1120 uint32_t color_values[2]);
1121 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1122 struct radv_image *image,
1123 bool value);
1124 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1125 struct radeon_winsys_bo *bo,
1126 uint64_t offset, uint64_t size, uint32_t value);
1127 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1128 bool radv_get_memory_fd(struct radv_device *device,
1129 struct radv_device_memory *memory,
1130 int *pFD);
1131
1132 static inline void
1133 radv_emit_shader_pointer(struct radeon_winsys_cs *cs,
1134 uint32_t sh_offset, uint64_t va)
1135 {
1136 radeon_set_sh_reg_seq(cs, sh_offset, 2);
1137 radeon_emit(cs, va);
1138 radeon_emit(cs, va >> 32);
1139 }
1140
1141 static inline struct radv_descriptor_state *
1142 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1143 VkPipelineBindPoint bind_point)
1144 {
1145 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1146 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1147 return &cmd_buffer->descriptors[bind_point];
1148 }
1149
1150 /*
1151 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1152 *
1153 * Limitations: Can't call normal dispatch functions without binding or rebinding
1154 * the compute pipeline.
1155 */
1156 void radv_unaligned_dispatch(
1157 struct radv_cmd_buffer *cmd_buffer,
1158 uint32_t x,
1159 uint32_t y,
1160 uint32_t z);
1161
1162 struct radv_event {
1163 struct radeon_winsys_bo *bo;
1164 uint64_t *map;
1165 };
1166
1167 struct radv_shader_module;
1168
1169 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1170 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1171 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1172 void
1173 radv_hash_shaders(unsigned char *hash,
1174 const VkPipelineShaderStageCreateInfo **stages,
1175 const struct radv_pipeline_layout *layout,
1176 const struct radv_pipeline_key *key,
1177 uint32_t flags);
1178
1179 static inline gl_shader_stage
1180 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1181 {
1182 assert(__builtin_popcount(vk_stage) == 1);
1183 return ffs(vk_stage) - 1;
1184 }
1185
1186 static inline VkShaderStageFlagBits
1187 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1188 {
1189 return (1 << mesa_stage);
1190 }
1191
1192 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1193
1194 #define radv_foreach_stage(stage, stage_bits) \
1195 for (gl_shader_stage stage, \
1196 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1197 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1198 __tmp &= ~(1 << (stage)))
1199
1200 unsigned radv_format_meta_fs_key(VkFormat format);
1201
1202 struct radv_multisample_state {
1203 uint32_t db_eqaa;
1204 uint32_t pa_sc_line_cntl;
1205 uint32_t pa_sc_mode_cntl_0;
1206 uint32_t pa_sc_mode_cntl_1;
1207 uint32_t pa_sc_aa_config;
1208 uint32_t pa_sc_aa_mask[2];
1209 unsigned num_samples;
1210 };
1211
1212 struct radv_prim_vertex_count {
1213 uint8_t min;
1214 uint8_t incr;
1215 };
1216
1217 struct radv_vertex_elements_info {
1218 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1219 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1220 uint32_t binding[MAX_VERTEX_ATTRIBS];
1221 uint32_t offset[MAX_VERTEX_ATTRIBS];
1222 uint32_t count;
1223 };
1224
1225 struct radv_ia_multi_vgt_param_helpers {
1226 uint32_t base;
1227 bool partial_es_wave;
1228 uint8_t primgroup_size;
1229 bool wd_switch_on_eop;
1230 bool ia_switch_on_eoi;
1231 bool partial_vs_wave;
1232 };
1233
1234 #define SI_GS_PER_ES 128
1235
1236 struct radv_pipeline {
1237 struct radv_device * device;
1238 struct radv_dynamic_state dynamic_state;
1239
1240 struct radv_pipeline_layout * layout;
1241
1242 bool need_indirect_descriptor_sets;
1243 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1244 struct radv_shader_variant *gs_copy_shader;
1245 VkShaderStageFlags active_stages;
1246
1247 struct radeon_winsys_cs cs;
1248
1249 struct radv_vertex_elements_info vertex_elements;
1250
1251 uint32_t binding_stride[MAX_VBS];
1252
1253 uint32_t user_data_0[MESA_SHADER_STAGES];
1254 union {
1255 struct {
1256 struct radv_multisample_state ms;
1257 uint32_t spi_baryc_cntl;
1258 bool prim_restart_enable;
1259 unsigned esgs_ring_size;
1260 unsigned gsvs_ring_size;
1261 uint32_t vtx_base_sgpr;
1262 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1263 uint8_t vtx_emit_num;
1264 struct radv_prim_vertex_count prim_vertex_count;
1265 bool can_use_guardband;
1266 uint32_t needed_dynamic_state;
1267 bool disable_out_of_order_rast_for_occlusion;
1268
1269 /* Used for rbplus */
1270 uint32_t col_format;
1271 uint32_t cb_target_mask;
1272 } graphics;
1273 };
1274
1275 unsigned max_waves;
1276 unsigned scratch_bytes_per_wave;
1277 };
1278
1279 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1280 {
1281 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1282 }
1283
1284 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1285 {
1286 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1287 }
1288
1289 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1290 gl_shader_stage stage,
1291 int idx);
1292
1293 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1294
1295 struct radv_graphics_pipeline_create_info {
1296 bool use_rectlist;
1297 bool db_depth_clear;
1298 bool db_stencil_clear;
1299 bool db_depth_disable_expclear;
1300 bool db_stencil_disable_expclear;
1301 bool db_flush_depth_inplace;
1302 bool db_flush_stencil_inplace;
1303 bool db_resummarize;
1304 uint32_t custom_blend_mode;
1305 };
1306
1307 VkResult
1308 radv_graphics_pipeline_create(VkDevice device,
1309 VkPipelineCache cache,
1310 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1311 const struct radv_graphics_pipeline_create_info *extra,
1312 const VkAllocationCallbacks *alloc,
1313 VkPipeline *pPipeline);
1314
1315 struct vk_format_description;
1316 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1317 int first_non_void);
1318 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1319 int first_non_void);
1320 uint32_t radv_translate_colorformat(VkFormat format);
1321 uint32_t radv_translate_color_numformat(VkFormat format,
1322 const struct vk_format_description *desc,
1323 int first_non_void);
1324 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1325 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1326 uint32_t radv_translate_dbformat(VkFormat format);
1327 uint32_t radv_translate_tex_dataformat(VkFormat format,
1328 const struct vk_format_description *desc,
1329 int first_non_void);
1330 uint32_t radv_translate_tex_numformat(VkFormat format,
1331 const struct vk_format_description *desc,
1332 int first_non_void);
1333 bool radv_format_pack_clear_color(VkFormat format,
1334 uint32_t clear_vals[2],
1335 VkClearColorValue *value);
1336 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1337 bool radv_dcc_formats_compatible(VkFormat format1,
1338 VkFormat format2);
1339
1340 struct radv_fmask_info {
1341 uint64_t offset;
1342 uint64_t size;
1343 unsigned alignment;
1344 unsigned pitch_in_pixels;
1345 unsigned bank_height;
1346 unsigned slice_tile_max;
1347 unsigned tile_mode_index;
1348 unsigned tile_swizzle;
1349 };
1350
1351 struct radv_cmask_info {
1352 uint64_t offset;
1353 uint64_t size;
1354 unsigned alignment;
1355 unsigned slice_tile_max;
1356 };
1357
1358 struct radv_image {
1359 VkImageType type;
1360 /* The original VkFormat provided by the client. This may not match any
1361 * of the actual surface formats.
1362 */
1363 VkFormat vk_format;
1364 VkImageAspectFlags aspects;
1365 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1366 struct ac_surf_info info;
1367 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1368 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1369
1370 VkDeviceSize size;
1371 uint32_t alignment;
1372
1373 unsigned queue_family_mask;
1374 bool exclusive;
1375 bool shareable;
1376
1377 /* Set when bound */
1378 struct radeon_winsys_bo *bo;
1379 VkDeviceSize offset;
1380 uint64_t dcc_offset;
1381 uint64_t htile_offset;
1382 bool tc_compatible_htile;
1383 struct radeon_surf surface;
1384
1385 struct radv_fmask_info fmask;
1386 struct radv_cmask_info cmask;
1387 uint64_t clear_value_offset;
1388 uint64_t dcc_pred_offset;
1389
1390 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1391 VkDeviceMemory owned_memory;
1392 };
1393
1394 /* Whether the image has a htile that is known consistent with the contents of
1395 * the image. */
1396 bool radv_layout_has_htile(const struct radv_image *image,
1397 VkImageLayout layout,
1398 unsigned queue_mask);
1399
1400 /* Whether the image has a htile that is known consistent with the contents of
1401 * the image and is allowed to be in compressed form.
1402 *
1403 * If this is false reads that don't use the htile should be able to return
1404 * correct results.
1405 */
1406 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1407 VkImageLayout layout,
1408 unsigned queue_mask);
1409
1410 bool radv_layout_can_fast_clear(const struct radv_image *image,
1411 VkImageLayout layout,
1412 unsigned queue_mask);
1413
1414 bool radv_layout_dcc_compressed(const struct radv_image *image,
1415 VkImageLayout layout,
1416 unsigned queue_mask);
1417
1418 /**
1419 * Return whether the image has CMASK metadata for color surfaces.
1420 */
1421 static inline bool
1422 radv_image_has_cmask(const struct radv_image *image)
1423 {
1424 return image->cmask.size;
1425 }
1426
1427 /**
1428 * Return whether the image has FMASK metadata for color surfaces.
1429 */
1430 static inline bool
1431 radv_image_has_fmask(const struct radv_image *image)
1432 {
1433 return image->fmask.size;
1434 }
1435
1436 /**
1437 * Return whether the image has DCC metadata for color surfaces.
1438 */
1439 static inline bool
1440 radv_image_has_dcc(const struct radv_image *image)
1441 {
1442 return image->surface.dcc_size;
1443 }
1444
1445 /**
1446 * Return whether DCC metadata is enabled for a level.
1447 */
1448 static inline bool
1449 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1450 {
1451 return radv_image_has_dcc(image) &&
1452 level < image->surface.num_dcc_levels;
1453 }
1454
1455 /**
1456 * Return whether the image has HTILE metadata for depth surfaces.
1457 */
1458 static inline bool
1459 radv_image_has_htile(const struct radv_image *image)
1460 {
1461 return image->surface.htile_size;
1462 }
1463
1464 /**
1465 * Return whether HTILE metadata is enabled for a level.
1466 */
1467 static inline bool
1468 radv_htile_enabled(const struct radv_image *image, unsigned level)
1469 {
1470 return radv_image_has_htile(image) && level == 0;
1471 }
1472
1473 /**
1474 * Return whether the image is TC-compatible HTILE.
1475 */
1476 static inline bool
1477 radv_image_is_tc_compat_htile(const struct radv_image *image)
1478 {
1479 return radv_image_has_htile(image) && image->tc_compatible_htile;
1480 }
1481
1482 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1483
1484 static inline uint32_t
1485 radv_get_layerCount(const struct radv_image *image,
1486 const VkImageSubresourceRange *range)
1487 {
1488 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1489 image->info.array_size - range->baseArrayLayer : range->layerCount;
1490 }
1491
1492 static inline uint32_t
1493 radv_get_levelCount(const struct radv_image *image,
1494 const VkImageSubresourceRange *range)
1495 {
1496 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1497 image->info.levels - range->baseMipLevel : range->levelCount;
1498 }
1499
1500 struct radeon_bo_metadata;
1501 void
1502 radv_init_metadata(struct radv_device *device,
1503 struct radv_image *image,
1504 struct radeon_bo_metadata *metadata);
1505
1506 struct radv_image_view {
1507 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1508 struct radeon_winsys_bo *bo;
1509
1510 VkImageViewType type;
1511 VkImageAspectFlags aspect_mask;
1512 VkFormat vk_format;
1513 uint32_t base_layer;
1514 uint32_t layer_count;
1515 uint32_t base_mip;
1516 uint32_t level_count;
1517 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1518
1519 uint32_t descriptor[16];
1520
1521 /* Descriptor for use as a storage image as opposed to a sampled image.
1522 * This has a few differences for cube maps (e.g. type).
1523 */
1524 uint32_t storage_descriptor[16];
1525 };
1526
1527 struct radv_image_create_info {
1528 const VkImageCreateInfo *vk_info;
1529 bool scanout;
1530 bool no_metadata_planes;
1531 };
1532
1533 VkResult radv_image_create(VkDevice _device,
1534 const struct radv_image_create_info *info,
1535 const VkAllocationCallbacks* alloc,
1536 VkImage *pImage);
1537
1538 VkResult
1539 radv_image_from_gralloc(VkDevice device_h,
1540 const VkImageCreateInfo *base_info,
1541 const VkNativeBufferANDROID *gralloc_info,
1542 const VkAllocationCallbacks *alloc,
1543 VkImage *out_image_h);
1544
1545 void radv_image_view_init(struct radv_image_view *view,
1546 struct radv_device *device,
1547 const VkImageViewCreateInfo* pCreateInfo);
1548
1549 struct radv_buffer_view {
1550 struct radeon_winsys_bo *bo;
1551 VkFormat vk_format;
1552 uint64_t range; /**< VkBufferViewCreateInfo::range */
1553 uint32_t state[4];
1554 };
1555 void radv_buffer_view_init(struct radv_buffer_view *view,
1556 struct radv_device *device,
1557 const VkBufferViewCreateInfo* pCreateInfo);
1558
1559 static inline struct VkExtent3D
1560 radv_sanitize_image_extent(const VkImageType imageType,
1561 const struct VkExtent3D imageExtent)
1562 {
1563 switch (imageType) {
1564 case VK_IMAGE_TYPE_1D:
1565 return (VkExtent3D) { imageExtent.width, 1, 1 };
1566 case VK_IMAGE_TYPE_2D:
1567 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1568 case VK_IMAGE_TYPE_3D:
1569 return imageExtent;
1570 default:
1571 unreachable("invalid image type");
1572 }
1573 }
1574
1575 static inline struct VkOffset3D
1576 radv_sanitize_image_offset(const VkImageType imageType,
1577 const struct VkOffset3D imageOffset)
1578 {
1579 switch (imageType) {
1580 case VK_IMAGE_TYPE_1D:
1581 return (VkOffset3D) { imageOffset.x, 0, 0 };
1582 case VK_IMAGE_TYPE_2D:
1583 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1584 case VK_IMAGE_TYPE_3D:
1585 return imageOffset;
1586 default:
1587 unreachable("invalid image type");
1588 }
1589 }
1590
1591 static inline bool
1592 radv_image_extent_compare(const struct radv_image *image,
1593 const VkExtent3D *extent)
1594 {
1595 if (extent->width != image->info.width ||
1596 extent->height != image->info.height ||
1597 extent->depth != image->info.depth)
1598 return false;
1599 return true;
1600 }
1601
1602 struct radv_sampler {
1603 uint32_t state[4];
1604 };
1605
1606 struct radv_color_buffer_info {
1607 uint64_t cb_color_base;
1608 uint64_t cb_color_cmask;
1609 uint64_t cb_color_fmask;
1610 uint64_t cb_dcc_base;
1611 uint32_t cb_color_pitch;
1612 uint32_t cb_color_slice;
1613 uint32_t cb_color_view;
1614 uint32_t cb_color_info;
1615 uint32_t cb_color_attrib;
1616 uint32_t cb_color_attrib2;
1617 uint32_t cb_dcc_control;
1618 uint32_t cb_color_cmask_slice;
1619 uint32_t cb_color_fmask_slice;
1620 };
1621
1622 struct radv_ds_buffer_info {
1623 uint64_t db_z_read_base;
1624 uint64_t db_stencil_read_base;
1625 uint64_t db_z_write_base;
1626 uint64_t db_stencil_write_base;
1627 uint64_t db_htile_data_base;
1628 uint32_t db_depth_info;
1629 uint32_t db_z_info;
1630 uint32_t db_stencil_info;
1631 uint32_t db_depth_view;
1632 uint32_t db_depth_size;
1633 uint32_t db_depth_slice;
1634 uint32_t db_htile_surface;
1635 uint32_t pa_su_poly_offset_db_fmt_cntl;
1636 uint32_t db_z_info2;
1637 uint32_t db_stencil_info2;
1638 float offset_scale;
1639 };
1640
1641 struct radv_attachment_info {
1642 union {
1643 struct radv_color_buffer_info cb;
1644 struct radv_ds_buffer_info ds;
1645 };
1646 struct radv_image_view *attachment;
1647 };
1648
1649 struct radv_framebuffer {
1650 uint32_t width;
1651 uint32_t height;
1652 uint32_t layers;
1653
1654 uint32_t attachment_count;
1655 struct radv_attachment_info attachments[0];
1656 };
1657
1658 struct radv_subpass_barrier {
1659 VkPipelineStageFlags src_stage_mask;
1660 VkAccessFlags src_access_mask;
1661 VkAccessFlags dst_access_mask;
1662 };
1663
1664 struct radv_subpass {
1665 uint32_t input_count;
1666 uint32_t color_count;
1667 VkAttachmentReference * input_attachments;
1668 VkAttachmentReference * color_attachments;
1669 VkAttachmentReference * resolve_attachments;
1670 VkAttachmentReference depth_stencil_attachment;
1671
1672 /** Subpass has at least one resolve attachment */
1673 bool has_resolve;
1674
1675 struct radv_subpass_barrier start_barrier;
1676
1677 uint32_t view_mask;
1678 VkSampleCountFlagBits max_sample_count;
1679 };
1680
1681 struct radv_render_pass_attachment {
1682 VkFormat format;
1683 uint32_t samples;
1684 VkAttachmentLoadOp load_op;
1685 VkAttachmentLoadOp stencil_load_op;
1686 VkImageLayout initial_layout;
1687 VkImageLayout final_layout;
1688 uint32_t view_mask;
1689 };
1690
1691 struct radv_render_pass {
1692 uint32_t attachment_count;
1693 uint32_t subpass_count;
1694 VkAttachmentReference * subpass_attachments;
1695 struct radv_render_pass_attachment * attachments;
1696 struct radv_subpass_barrier end_barrier;
1697 struct radv_subpass subpasses[0];
1698 };
1699
1700 VkResult radv_device_init_meta(struct radv_device *device);
1701 void radv_device_finish_meta(struct radv_device *device);
1702
1703 struct radv_query_pool {
1704 struct radeon_winsys_bo *bo;
1705 uint32_t stride;
1706 uint32_t availability_offset;
1707 uint64_t size;
1708 char *ptr;
1709 VkQueryType type;
1710 uint32_t pipeline_stats_mask;
1711 };
1712
1713 struct radv_semaphore {
1714 /* use a winsys sem for non-exportable */
1715 struct radeon_winsys_sem *sem;
1716 uint32_t syncobj;
1717 uint32_t temp_syncobj;
1718 };
1719
1720 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1721 int num_wait_sems,
1722 const VkSemaphore *wait_sems,
1723 int num_signal_sems,
1724 const VkSemaphore *signal_sems,
1725 VkFence fence);
1726 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1727
1728 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1729 VkPipelineBindPoint bind_point,
1730 struct radv_descriptor_set *set,
1731 unsigned idx);
1732
1733 void
1734 radv_update_descriptor_sets(struct radv_device *device,
1735 struct radv_cmd_buffer *cmd_buffer,
1736 VkDescriptorSet overrideSet,
1737 uint32_t descriptorWriteCount,
1738 const VkWriteDescriptorSet *pDescriptorWrites,
1739 uint32_t descriptorCopyCount,
1740 const VkCopyDescriptorSet *pDescriptorCopies);
1741
1742 void
1743 radv_update_descriptor_set_with_template(struct radv_device *device,
1744 struct radv_cmd_buffer *cmd_buffer,
1745 struct radv_descriptor_set *set,
1746 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1747 const void *pData);
1748
1749 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1750 VkPipelineBindPoint pipelineBindPoint,
1751 VkPipelineLayout _layout,
1752 uint32_t set,
1753 uint32_t descriptorWriteCount,
1754 const VkWriteDescriptorSet *pDescriptorWrites);
1755
1756 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1757 struct radv_image *image, uint32_t value);
1758
1759 struct radv_fence {
1760 struct radeon_winsys_fence *fence;
1761 bool submitted;
1762 bool signalled;
1763
1764 uint32_t syncobj;
1765 uint32_t temp_syncobj;
1766 };
1767
1768 /* radv_nir_to_llvm.c */
1769 struct radv_shader_variant_info;
1770 struct radv_nir_compiler_options;
1771
1772 void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
1773 struct nir_shader *geom_shader,
1774 struct ac_shader_binary *binary,
1775 struct ac_shader_config *config,
1776 struct radv_shader_variant_info *shader_info,
1777 const struct radv_nir_compiler_options *option);
1778
1779 void radv_compile_nir_shader(LLVMTargetMachineRef tm,
1780 struct ac_shader_binary *binary,
1781 struct ac_shader_config *config,
1782 struct radv_shader_variant_info *shader_info,
1783 struct nir_shader *const *nir,
1784 int nir_count,
1785 const struct radv_nir_compiler_options *options);
1786
1787 /* radv_shader_info.h */
1788 struct radv_shader_info;
1789
1790 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1791 const struct radv_nir_compiler_options *options,
1792 struct radv_shader_info *info);
1793
1794 struct radeon_winsys_sem;
1795
1796 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1797 \
1798 static inline struct __radv_type * \
1799 __radv_type ## _from_handle(__VkType _handle) \
1800 { \
1801 return (struct __radv_type *) _handle; \
1802 } \
1803 \
1804 static inline __VkType \
1805 __radv_type ## _to_handle(struct __radv_type *_obj) \
1806 { \
1807 return (__VkType) _obj; \
1808 }
1809
1810 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1811 \
1812 static inline struct __radv_type * \
1813 __radv_type ## _from_handle(__VkType _handle) \
1814 { \
1815 return (struct __radv_type *)(uintptr_t) _handle; \
1816 } \
1817 \
1818 static inline __VkType \
1819 __radv_type ## _to_handle(struct __radv_type *_obj) \
1820 { \
1821 return (__VkType)(uintptr_t) _obj; \
1822 }
1823
1824 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1825 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1826
1827 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1828 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1829 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1830 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1831 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1832
1833 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1834 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1835 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1836 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1837 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1838 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1839 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1840 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1841 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1842 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1843 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1844 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1845 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1846 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1847 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1848 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1849 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1850 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1851 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1852 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1853 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1854
1855 #endif /* RADV_PRIVATE_H */