2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
53 #include "vk_debug_report.h"
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "radv_descriptor_set.h"
61 #include "radv_extensions.h"
63 #include <llvm-c/TargetMachine.h>
65 /* Pre-declarations needed for WSI entrypoints */
68 typedef struct xcb_connection_t xcb_connection_t
;
69 typedef uint32_t xcb_visualid_t
;
70 typedef uint32_t xcb_window_t
;
72 #include <vulkan/vulkan.h>
73 #include <vulkan/vulkan_intel.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vk_android_native_buffer.h>
77 #include "radv_entrypoints.h"
79 #include "wsi_common.h"
81 #define ATI_VENDOR_ID 0x1002
84 #define MAX_VERTEX_ATTRIBS 32
86 #define MAX_VIEWPORTS 16
87 #define MAX_SCISSORS 16
88 #define MAX_DISCARD_RECTANGLES 4
89 #define MAX_PUSH_CONSTANTS_SIZE 128
90 #define MAX_PUSH_DESCRIPTORS 32
91 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
92 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
93 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
94 #define MAX_SAMPLES_LOG2 4
95 #define NUM_META_FS_KEYS 13
96 #define RADV_MAX_DRM_DEVICES 8
99 #define NUM_DEPTH_CLEAR_PIPELINES 3
102 * This is the point we switch from using CP to compute shader
103 * for certain buffer operations.
105 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
109 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
116 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
117 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
118 RADV_MEM_TYPE_GTT_CACHED
,
122 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
124 static inline uint32_t
125 align_u32(uint32_t v
, uint32_t a
)
127 assert(a
!= 0 && a
== (a
& -a
));
128 return (v
+ a
- 1) & ~(a
- 1);
131 static inline uint32_t
132 align_u32_npot(uint32_t v
, uint32_t a
)
134 return (v
+ a
- 1) / a
* a
;
137 static inline uint64_t
138 align_u64(uint64_t v
, uint64_t a
)
140 assert(a
!= 0 && a
== (a
& -a
));
141 return (v
+ a
- 1) & ~(a
- 1);
144 static inline int32_t
145 align_i32(int32_t v
, int32_t a
)
147 assert(a
!= 0 && a
== (a
& -a
));
148 return (v
+ a
- 1) & ~(a
- 1);
151 /** Alignment must be a power of 2. */
153 radv_is_aligned(uintmax_t n
, uintmax_t a
)
155 assert(a
== (a
& -a
));
156 return (n
& (a
- 1)) == 0;
159 static inline uint32_t
160 round_up_u32(uint32_t v
, uint32_t a
)
162 return (v
+ a
- 1) / a
;
165 static inline uint64_t
166 round_up_u64(uint64_t v
, uint64_t a
)
168 return (v
+ a
- 1) / a
;
171 static inline uint32_t
172 radv_minify(uint32_t n
, uint32_t levels
)
174 if (unlikely(n
== 0))
177 return MAX2(n
>> levels
, 1);
180 radv_clamp_f(float f
, float min
, float max
)
193 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
195 if (*inout_mask
& clear_mask
) {
196 *inout_mask
&= ~clear_mask
;
203 #define for_each_bit(b, dword) \
204 for (uint32_t __dword = (dword); \
205 (b) = __builtin_ffs(__dword) - 1, __dword; \
206 __dword &= ~(1 << (b)))
208 #define typed_memcpy(dest, src, count) ({ \
209 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
210 memcpy((dest), (src), (count) * sizeof(*(src))); \
213 /* Whenever we generate an error, pass it through this function. Useful for
214 * debugging, where we can break on it. Only call at error site, not when
215 * propagating errors. Might be useful to plug in a stack trace here.
218 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
221 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
222 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
224 #define vk_error(error) error
225 #define vk_errorf(error, format, ...) error
228 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
229 radv_printflike(3, 4);
230 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
231 void radv_loge_v(const char *format
, va_list va
);
234 * Print a FINISHME message, including its source location.
236 #define radv_finishme(format, ...) \
238 static bool reported = false; \
240 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
245 /* A non-fatal assert. Useful for debugging. */
247 #define radv_assert(x) ({ \
248 if (unlikely(!(x))) \
249 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
252 #define radv_assert(x)
255 #define stub_return(v) \
257 radv_finishme("stub %s", __func__); \
263 radv_finishme("stub %s", __func__); \
267 void *radv_lookup_entrypoint_unchecked(const char *name
);
268 void *radv_lookup_entrypoint_checked(const char *name
,
269 uint32_t core_version
,
270 const struct radv_instance_extension_table
*instance
,
271 const struct radv_device_extension_table
*device
);
273 struct radv_physical_device
{
274 VK_LOADER_DATA _loader_data
;
276 struct radv_instance
* instance
;
278 struct radeon_winsys
*ws
;
279 struct radeon_info rad_info
;
281 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
282 uint8_t driver_uuid
[VK_UUID_SIZE
];
283 uint8_t device_uuid
[VK_UUID_SIZE
];
284 uint8_t cache_uuid
[VK_UUID_SIZE
];
287 struct wsi_device wsi_device
;
289 bool has_rbplus
; /* if RB+ register exist */
290 bool rbplus_allowed
; /* if RB+ is allowed */
291 bool has_clear_state
;
292 bool cpdma_prefetch_writes_memory
;
293 bool has_scissor_bug
;
295 bool has_out_of_order_rast
;
296 bool out_of_order_rast_allowed
;
298 /* This is the drivers on-disk cache used as a fallback as opposed to
299 * the pipeline cache defined by apps.
301 struct disk_cache
* disk_cache
;
303 VkPhysicalDeviceMemoryProperties memory_properties
;
304 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
306 struct radv_device_extension_table supported_extensions
;
309 struct radv_instance
{
310 VK_LOADER_DATA _loader_data
;
312 VkAllocationCallbacks alloc
;
315 int physicalDeviceCount
;
316 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
318 uint64_t debug_flags
;
319 uint64_t perftest_flags
;
321 struct vk_debug_report_instance debug_report_callbacks
;
323 struct radv_instance_extension_table enabled_extensions
;
326 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
327 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
329 bool radv_instance_extension_supported(const char *name
);
330 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
331 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
336 struct radv_pipeline_cache
{
337 struct radv_device
* device
;
338 pthread_mutex_t mutex
;
342 uint32_t kernel_count
;
343 struct cache_entry
** hash_table
;
346 VkAllocationCallbacks alloc
;
349 struct radv_pipeline_key
{
350 uint32_t instance_rate_inputs
;
351 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
352 unsigned tess_input_vertices
;
356 uint8_t log2_ps_iter_samples
;
357 uint8_t log2_num_samples
;
358 uint32_t multisample
: 1;
359 uint32_t has_multiview_view_index
: 1;
363 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
364 struct radv_device
*device
);
366 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
368 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
369 const void *data
, size_t size
);
371 struct radv_shader_variant
;
374 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
375 struct radv_pipeline_cache
*cache
,
376 const unsigned char *sha1
,
377 struct radv_shader_variant
**variants
);
380 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
381 struct radv_pipeline_cache
*cache
,
382 const unsigned char *sha1
,
383 struct radv_shader_variant
**variants
,
384 const void *const *codes
,
385 const unsigned *code_sizes
);
387 enum radv_blit_ds_layout
{
388 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
389 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
390 RADV_BLIT_DS_LAYOUT_COUNT
,
393 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
395 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
398 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
400 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
403 enum radv_meta_dst_layout
{
404 RADV_META_DST_LAYOUT_GENERAL
,
405 RADV_META_DST_LAYOUT_OPTIMAL
,
406 RADV_META_DST_LAYOUT_COUNT
,
409 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
411 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
414 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
416 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
419 struct radv_meta_state
{
420 VkAllocationCallbacks alloc
;
422 struct radv_pipeline_cache cache
;
425 * Use array element `i` for images with `2^i` samples.
428 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
429 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
431 VkRenderPass depthstencil_rp
;
432 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
433 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
434 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
435 } clear
[1 + MAX_SAMPLES_LOG2
];
437 VkPipelineLayout clear_color_p_layout
;
438 VkPipelineLayout clear_depth_p_layout
;
440 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
442 /** Pipeline that blits from a 1D image. */
443 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
445 /** Pipeline that blits from a 2D image. */
446 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
448 /** Pipeline that blits from a 3D image. */
449 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
451 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
452 VkPipeline depth_only_1d_pipeline
;
453 VkPipeline depth_only_2d_pipeline
;
454 VkPipeline depth_only_3d_pipeline
;
456 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
457 VkPipeline stencil_only_1d_pipeline
;
458 VkPipeline stencil_only_2d_pipeline
;
459 VkPipeline stencil_only_3d_pipeline
;
460 VkPipelineLayout pipeline_layout
;
461 VkDescriptorSetLayout ds_layout
;
465 VkRenderPass render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
467 VkPipelineLayout p_layouts
[3];
468 VkDescriptorSetLayout ds_layouts
[3];
469 VkPipeline pipelines
[3][NUM_META_FS_KEYS
];
471 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
472 VkPipeline depth_only_pipeline
[3];
474 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
475 VkPipeline stencil_only_pipeline
[3];
479 VkPipelineLayout img_p_layout
;
480 VkDescriptorSetLayout img_ds_layout
;
482 VkPipeline pipeline_3d
;
485 VkPipelineLayout img_p_layout
;
486 VkDescriptorSetLayout img_ds_layout
;
488 VkPipeline pipeline_3d
;
491 VkPipelineLayout img_p_layout
;
492 VkDescriptorSetLayout img_ds_layout
;
494 VkPipeline pipeline_3d
;
497 VkPipelineLayout img_p_layout
;
498 VkDescriptorSetLayout img_ds_layout
;
500 VkPipeline pipeline_3d
;
504 VkPipelineLayout p_layout
;
505 VkPipeline pipeline
[NUM_META_FS_KEYS
];
506 VkRenderPass pass
[NUM_META_FS_KEYS
];
510 VkDescriptorSetLayout ds_layout
;
511 VkPipelineLayout p_layout
;
514 VkPipeline i_pipeline
;
515 VkPipeline srgb_pipeline
;
516 } rc
[MAX_SAMPLES_LOG2
];
520 VkDescriptorSetLayout ds_layout
;
521 VkPipelineLayout p_layout
;
524 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
525 VkPipeline pipeline
[NUM_META_FS_KEYS
];
526 } rc
[MAX_SAMPLES_LOG2
];
530 VkPipelineLayout p_layout
;
531 VkPipeline decompress_pipeline
;
532 VkPipeline resummarize_pipeline
;
534 } depth_decomp
[1 + MAX_SAMPLES_LOG2
];
537 VkPipelineLayout p_layout
;
538 VkPipeline cmask_eliminate_pipeline
;
539 VkPipeline fmask_decompress_pipeline
;
540 VkPipeline dcc_decompress_pipeline
;
543 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
544 VkPipelineLayout dcc_decompress_compute_p_layout
;
545 VkPipeline dcc_decompress_compute_pipeline
;
549 VkPipelineLayout fill_p_layout
;
550 VkPipelineLayout copy_p_layout
;
551 VkDescriptorSetLayout fill_ds_layout
;
552 VkDescriptorSetLayout copy_ds_layout
;
553 VkPipeline fill_pipeline
;
554 VkPipeline copy_pipeline
;
558 VkDescriptorSetLayout ds_layout
;
559 VkPipelineLayout p_layout
;
560 VkPipeline occlusion_query_pipeline
;
561 VkPipeline pipeline_statistics_query_pipeline
;
566 #define RADV_QUEUE_GENERAL 0
567 #define RADV_QUEUE_COMPUTE 1
568 #define RADV_QUEUE_TRANSFER 2
570 #define RADV_MAX_QUEUE_FAMILIES 3
572 enum ring_type
radv_queue_family_to_ring(int f
);
575 VK_LOADER_DATA _loader_data
;
576 struct radv_device
* device
;
577 struct radeon_winsys_ctx
*hw_ctx
;
578 enum radeon_ctx_priority priority
;
579 uint32_t queue_family_index
;
581 VkDeviceQueueCreateFlags flags
;
583 uint32_t scratch_size
;
584 uint32_t compute_scratch_size
;
585 uint32_t esgs_ring_size
;
586 uint32_t gsvs_ring_size
;
588 bool has_sample_positions
;
590 struct radeon_winsys_bo
*scratch_bo
;
591 struct radeon_winsys_bo
*descriptor_bo
;
592 struct radeon_winsys_bo
*compute_scratch_bo
;
593 struct radeon_winsys_bo
*esgs_ring_bo
;
594 struct radeon_winsys_bo
*gsvs_ring_bo
;
595 struct radeon_winsys_bo
*tess_rings_bo
;
596 struct radeon_winsys_cs
*initial_preamble_cs
;
597 struct radeon_winsys_cs
*initial_full_flush_preamble_cs
;
598 struct radeon_winsys_cs
*continue_preamble_cs
;
602 VK_LOADER_DATA _loader_data
;
604 VkAllocationCallbacks alloc
;
606 struct radv_instance
* instance
;
607 struct radeon_winsys
*ws
;
609 struct radv_meta_state meta_state
;
611 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
612 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
613 struct radeon_winsys_cs
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
615 bool always_use_syncobj
;
616 bool llvm_supports_spill
;
617 bool has_distributed_tess
;
620 uint32_t tess_offchip_block_dw_size
;
621 uint32_t scratch_waves
;
622 uint32_t dispatch_initiator
;
624 uint32_t gs_table_depth
;
626 /* MSAA sample locations.
627 * The first index is the sample index.
628 * The second index is the coordinate: X, Y. */
629 float sample_locations_1x
[1][2];
630 float sample_locations_2x
[2][2];
631 float sample_locations_4x
[4][2];
632 float sample_locations_8x
[8][2];
633 float sample_locations_16x
[16][2];
636 uint32_t gfx_init_size_dw
;
637 struct radeon_winsys_bo
*gfx_init
;
639 struct radeon_winsys_bo
*trace_bo
;
640 uint32_t *trace_id_ptr
;
642 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
643 bool keep_shader_info
;
645 struct radv_physical_device
*physical_device
;
647 /* Backup in-memory cache to be used if the app doesn't provide one */
648 struct radv_pipeline_cache
* mem_cache
;
651 * use different counters so MSAA MRTs get consecutive surface indices,
652 * even if MASK is allocated in between.
654 uint32_t image_mrt_offset_counter
;
655 uint32_t fmask_mrt_offset_counter
;
656 struct list_head shader_slabs
;
657 mtx_t shader_slab_mutex
;
659 /* For detecting VM faults reported by dmesg. */
660 uint64_t dmesg_timestamp
;
662 struct radv_device_extension_table enabled_extensions
;
665 struct radv_device_memory
{
666 struct radeon_winsys_bo
*bo
;
667 /* for dedicated allocations */
668 struct radv_image
*image
;
669 struct radv_buffer
*buffer
;
671 VkDeviceSize map_size
;
677 struct radv_descriptor_range
{
682 struct radv_descriptor_set
{
683 const struct radv_descriptor_set_layout
*layout
;
686 struct radeon_winsys_bo
*bo
;
688 uint32_t *mapped_ptr
;
689 struct radv_descriptor_range
*dynamic_descriptors
;
691 struct radeon_winsys_bo
*descriptors
[0];
694 struct radv_push_descriptor_set
696 struct radv_descriptor_set set
;
700 struct radv_descriptor_pool_entry
{
703 struct radv_descriptor_set
*set
;
706 struct radv_descriptor_pool
{
707 struct radeon_winsys_bo
*bo
;
709 uint64_t current_offset
;
712 uint8_t *host_memory_base
;
713 uint8_t *host_memory_ptr
;
714 uint8_t *host_memory_end
;
716 uint32_t entry_count
;
717 uint32_t max_entry_count
;
718 struct radv_descriptor_pool_entry entries
[0];
721 struct radv_descriptor_update_template_entry
{
722 VkDescriptorType descriptor_type
;
724 /* The number of descriptors to update */
725 uint32_t descriptor_count
;
727 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
730 /* In dwords. Not valid/used for dynamic descriptors */
733 uint32_t buffer_offset
;
735 /* Only valid for combined image samplers and samplers */
736 uint16_t has_sampler
;
742 /* For push descriptors */
743 const uint32_t *immutable_samplers
;
746 struct radv_descriptor_update_template
{
747 uint32_t entry_count
;
748 VkPipelineBindPoint bind_point
;
749 struct radv_descriptor_update_template_entry entry
[0];
755 VkBufferUsageFlags usage
;
756 VkBufferCreateFlags flags
;
759 struct radeon_winsys_bo
* bo
;
765 enum radv_dynamic_state_bits
{
766 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
767 RADV_DYNAMIC_SCISSOR
= 1 << 1,
768 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
769 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
770 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
771 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
772 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
773 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
774 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
775 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
776 RADV_DYNAMIC_ALL
= (1 << 10) - 1,
779 enum radv_cmd_dirty_bits
{
780 /* Keep the dynamic state dirty bits in sync with
781 * enum radv_dynamic_state_bits */
782 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
783 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
784 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
785 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
786 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
787 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
788 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
789 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
790 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
791 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
792 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 10) - 1,
793 RADV_CMD_DIRTY_PIPELINE
= 1 << 10,
794 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 11,
795 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 12,
796 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 13,
799 enum radv_cmd_flush_bits
{
800 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
801 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
802 RADV_CMD_FLAG_INV_SMEM_L1
= 1 << 1,
803 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
804 RADV_CMD_FLAG_INV_VMEM_L1
= 1 << 2,
805 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
806 RADV_CMD_FLAG_INV_GLOBAL_L2
= 1 << 3,
807 /* Same as above, but only writes back and doesn't invalidate */
808 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
= 1 << 4,
809 /* Framebuffer caches */
810 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
811 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
812 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
813 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
814 /* Engine synchronization. */
815 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
816 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
817 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
818 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
820 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
821 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
822 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
823 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
826 struct radv_vertex_binding
{
827 struct radv_buffer
* buffer
;
831 struct radv_viewport_state
{
833 VkViewport viewports
[MAX_VIEWPORTS
];
836 struct radv_scissor_state
{
838 VkRect2D scissors
[MAX_SCISSORS
];
841 struct radv_discard_rectangle_state
{
843 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
846 struct radv_dynamic_state
{
848 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
849 * Defines the set of saved dynamic state.
853 struct radv_viewport_state viewport
;
855 struct radv_scissor_state scissor
;
865 float blend_constants
[4];
875 } stencil_compare_mask
;
880 } stencil_write_mask
;
887 struct radv_discard_rectangle_state discard_rectangle
;
890 extern const struct radv_dynamic_state default_dynamic_state
;
893 radv_get_debug_option_name(int id
);
896 radv_get_perftest_option_name(int id
);
899 * Attachment state when recording a renderpass instance.
901 * The clear value is valid only if there exists a pending clear.
903 struct radv_attachment_state
{
904 VkImageAspectFlags pending_clear_aspects
;
905 uint32_t cleared_views
;
906 VkClearValue clear_value
;
907 VkImageLayout current_layout
;
910 struct radv_descriptor_state
{
911 struct radv_descriptor_set
*sets
[MAX_SETS
];
914 struct radv_push_descriptor_set push_set
;
918 struct radv_cmd_state
{
919 /* Vertex descriptors */
926 uint32_t prefetch_L2_mask
;
928 struct radv_pipeline
* pipeline
;
929 struct radv_pipeline
* emitted_pipeline
;
930 struct radv_pipeline
* compute_pipeline
;
931 struct radv_pipeline
* emitted_compute_pipeline
;
932 struct radv_framebuffer
* framebuffer
;
933 struct radv_render_pass
* pass
;
934 const struct radv_subpass
* subpass
;
935 struct radv_dynamic_state dynamic
;
936 struct radv_attachment_state
* attachments
;
937 VkRect2D render_area
;
940 struct radv_buffer
*index_buffer
;
941 uint64_t index_offset
;
943 uint32_t max_index_count
;
945 int32_t last_index_type
;
947 int32_t last_primitive_reset_en
;
948 uint32_t last_primitive_reset_index
;
949 enum radv_cmd_flush_bits flush_bits
;
950 unsigned active_occlusion_queries
;
951 bool perfect_occlusion_queries_enabled
;
954 uint32_t last_ia_multi_vgt_param
;
956 uint32_t last_num_instances
;
957 uint32_t last_first_instance
;
958 uint32_t last_vertex_offset
;
961 struct radv_cmd_pool
{
962 VkAllocationCallbacks alloc
;
963 struct list_head cmd_buffers
;
964 struct list_head free_cmd_buffers
;
965 uint32_t queue_family_index
;
968 struct radv_cmd_buffer_upload
{
972 struct radeon_winsys_bo
*upload_bo
;
973 struct list_head list
;
976 enum radv_cmd_buffer_status
{
977 RADV_CMD_BUFFER_STATUS_INVALID
,
978 RADV_CMD_BUFFER_STATUS_INITIAL
,
979 RADV_CMD_BUFFER_STATUS_RECORDING
,
980 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
981 RADV_CMD_BUFFER_STATUS_PENDING
,
984 struct radv_cmd_buffer
{
985 VK_LOADER_DATA _loader_data
;
987 struct radv_device
* device
;
989 struct radv_cmd_pool
* pool
;
990 struct list_head pool_link
;
992 VkCommandBufferUsageFlags usage_flags
;
993 VkCommandBufferLevel level
;
994 enum radv_cmd_buffer_status status
;
995 struct radeon_winsys_cs
*cs
;
996 struct radv_cmd_state state
;
997 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
998 uint32_t queue_family_index
;
1000 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1001 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
1002 VkShaderStageFlags push_constant_stages
;
1003 struct radv_descriptor_set meta_push_descriptors
;
1005 struct radv_descriptor_state descriptors
[VK_PIPELINE_BIND_POINT_RANGE_SIZE
];
1007 struct radv_cmd_buffer_upload upload
;
1009 uint32_t scratch_size_needed
;
1010 uint32_t compute_scratch_size_needed
;
1011 uint32_t esgs_ring_size_needed
;
1012 uint32_t gsvs_ring_size_needed
;
1013 bool tess_rings_needed
;
1014 bool sample_positions_needed
;
1016 VkResult record_result
;
1018 int ring_offsets_idx
; /* just used for verification */
1019 uint32_t gfx9_fence_offset
;
1020 struct radeon_winsys_bo
*gfx9_fence_bo
;
1021 uint32_t gfx9_fence_idx
;
1024 * Whether a query pool has been resetted and we have to flush caches.
1026 bool pending_reset_query
;
1031 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1033 void si_init_compute(struct radv_cmd_buffer
*cmd_buffer
);
1034 void si_init_config(struct radv_cmd_buffer
*cmd_buffer
);
1036 void cik_create_gfx_config(struct radv_device
*device
);
1038 void si_write_viewport(struct radeon_winsys_cs
*cs
, int first_vp
,
1039 int count
, const VkViewport
*viewports
);
1040 void si_write_scissors(struct radeon_winsys_cs
*cs
, int first
,
1041 int count
, const VkRect2D
*scissors
,
1042 const VkViewport
*viewports
, bool can_use_guardband
);
1043 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1044 bool instanced_draw
, bool indirect_draw
,
1045 uint32_t draw_vertex_count
);
1046 void si_cs_emit_write_event_eop(struct radeon_winsys_cs
*cs
,
1048 enum chip_class chip_class
,
1050 unsigned event
, unsigned event_flags
,
1054 uint32_t new_fence
);
1056 void si_emit_wait_fence(struct radeon_winsys_cs
*cs
,
1058 uint64_t va
, uint32_t ref
,
1060 void si_cs_emit_cache_flush(struct radeon_winsys_cs
*cs
,
1061 enum chip_class chip_class
,
1062 uint32_t *fence_ptr
, uint64_t va
,
1064 enum radv_cmd_flush_bits flush_bits
);
1065 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1066 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
);
1067 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1068 uint64_t src_va
, uint64_t dest_va
,
1070 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1072 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1073 uint64_t size
, unsigned value
);
1074 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1076 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1079 unsigned *out_offset
,
1082 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1083 const struct radv_subpass
*subpass
,
1086 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1087 unsigned size
, unsigned alignmnet
,
1088 const void *data
, unsigned *out_offset
);
1090 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1091 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1092 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1093 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1094 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
1095 unsigned radv_cayman_get_maxdist(int log_samples
);
1096 void radv_device_init_msaa(struct radv_device
*device
);
1097 void radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1098 struct radv_image
*image
,
1099 VkClearDepthStencilValue ds_clear_value
,
1100 VkImageAspectFlags aspects
);
1101 void radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
1102 struct radv_image
*image
,
1104 uint32_t color_values
[2]);
1105 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
1106 struct radv_image
*image
,
1108 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1109 struct radeon_winsys_bo
*bo
,
1110 uint64_t offset
, uint64_t size
, uint32_t value
);
1111 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1112 bool radv_get_memory_fd(struct radv_device
*device
,
1113 struct radv_device_memory
*memory
,
1116 static inline struct radv_descriptor_state
*
1117 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1118 VkPipelineBindPoint bind_point
)
1120 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1121 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1122 return &cmd_buffer
->descriptors
[bind_point
];
1126 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1128 * Limitations: Can't call normal dispatch functions without binding or rebinding
1129 * the compute pipeline.
1131 void radv_unaligned_dispatch(
1132 struct radv_cmd_buffer
*cmd_buffer
,
1138 struct radeon_winsys_bo
*bo
;
1142 struct radv_shader_module
;
1144 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1145 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1146 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1148 radv_hash_shaders(unsigned char *hash
,
1149 const VkPipelineShaderStageCreateInfo
**stages
,
1150 const struct radv_pipeline_layout
*layout
,
1151 const struct radv_pipeline_key
*key
,
1154 static inline gl_shader_stage
1155 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1157 assert(__builtin_popcount(vk_stage
) == 1);
1158 return ffs(vk_stage
) - 1;
1161 static inline VkShaderStageFlagBits
1162 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1164 return (1 << mesa_stage
);
1167 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1169 #define radv_foreach_stage(stage, stage_bits) \
1170 for (gl_shader_stage stage, \
1171 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1172 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1173 __tmp &= ~(1 << (stage)))
1175 unsigned radv_format_meta_fs_key(VkFormat format
);
1177 struct radv_multisample_state
{
1179 uint32_t pa_sc_line_cntl
;
1180 uint32_t pa_sc_mode_cntl_0
;
1181 uint32_t pa_sc_mode_cntl_1
;
1182 uint32_t pa_sc_aa_config
;
1183 uint32_t pa_sc_aa_mask
[2];
1184 unsigned num_samples
;
1187 struct radv_prim_vertex_count
{
1192 struct radv_vertex_elements_info
{
1193 uint32_t rsrc_word3
[MAX_VERTEX_ATTRIBS
];
1194 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1195 uint32_t binding
[MAX_VERTEX_ATTRIBS
];
1196 uint32_t offset
[MAX_VERTEX_ATTRIBS
];
1200 struct radv_ia_multi_vgt_param_helpers
{
1202 bool partial_es_wave
;
1203 uint8_t primgroup_size
;
1204 bool wd_switch_on_eop
;
1205 bool ia_switch_on_eoi
;
1206 bool partial_vs_wave
;
1209 #define SI_GS_PER_ES 128
1211 struct radv_pipeline
{
1212 struct radv_device
* device
;
1213 struct radv_dynamic_state dynamic_state
;
1215 struct radv_pipeline_layout
* layout
;
1217 bool need_indirect_descriptor_sets
;
1218 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1219 struct radv_shader_variant
*gs_copy_shader
;
1220 VkShaderStageFlags active_stages
;
1222 struct radeon_winsys_cs cs
;
1224 struct radv_vertex_elements_info vertex_elements
;
1226 uint32_t binding_stride
[MAX_VBS
];
1228 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1231 struct radv_multisample_state ms
;
1232 uint32_t spi_baryc_cntl
;
1233 bool prim_restart_enable
;
1234 unsigned esgs_ring_size
;
1235 unsigned gsvs_ring_size
;
1236 uint32_t vtx_base_sgpr
;
1237 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1238 uint8_t vtx_emit_num
;
1239 struct radv_prim_vertex_count prim_vertex_count
;
1240 bool can_use_guardband
;
1241 uint32_t needed_dynamic_state
;
1242 bool disable_out_of_order_rast_for_occlusion
;
1244 /* Used for rbplus */
1245 uint32_t col_format
;
1246 uint32_t cb_target_mask
;
1251 unsigned scratch_bytes_per_wave
;
1254 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1256 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1259 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1261 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1264 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1265 gl_shader_stage stage
,
1268 struct radv_shader_variant
*radv_get_vertex_shader(struct radv_pipeline
*pipeline
);
1270 struct radv_graphics_pipeline_create_info
{
1272 bool db_depth_clear
;
1273 bool db_stencil_clear
;
1274 bool db_depth_disable_expclear
;
1275 bool db_stencil_disable_expclear
;
1276 bool db_flush_depth_inplace
;
1277 bool db_flush_stencil_inplace
;
1278 bool db_resummarize
;
1279 uint32_t custom_blend_mode
;
1283 radv_graphics_pipeline_create(VkDevice device
,
1284 VkPipelineCache cache
,
1285 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1286 const struct radv_graphics_pipeline_create_info
*extra
,
1287 const VkAllocationCallbacks
*alloc
,
1288 VkPipeline
*pPipeline
);
1290 struct vk_format_description
;
1291 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1292 int first_non_void
);
1293 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1294 int first_non_void
);
1295 uint32_t radv_translate_colorformat(VkFormat format
);
1296 uint32_t radv_translate_color_numformat(VkFormat format
,
1297 const struct vk_format_description
*desc
,
1298 int first_non_void
);
1299 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1300 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1301 uint32_t radv_translate_dbformat(VkFormat format
);
1302 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1303 const struct vk_format_description
*desc
,
1304 int first_non_void
);
1305 uint32_t radv_translate_tex_numformat(VkFormat format
,
1306 const struct vk_format_description
*desc
,
1307 int first_non_void
);
1308 bool radv_format_pack_clear_color(VkFormat format
,
1309 uint32_t clear_vals
[2],
1310 VkClearColorValue
*value
);
1311 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1312 bool radv_dcc_formats_compatible(VkFormat format1
,
1315 struct radv_fmask_info
{
1319 unsigned pitch_in_pixels
;
1320 unsigned bank_height
;
1321 unsigned slice_tile_max
;
1322 unsigned tile_mode_index
;
1323 unsigned tile_swizzle
;
1326 struct radv_cmask_info
{
1330 unsigned slice_tile_max
;
1335 /* The original VkFormat provided by the client. This may not match any
1336 * of the actual surface formats.
1339 VkImageAspectFlags aspects
;
1340 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1341 struct ac_surf_info info
;
1342 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1343 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1348 unsigned queue_family_mask
;
1352 /* Set when bound */
1353 struct radeon_winsys_bo
*bo
;
1354 VkDeviceSize offset
;
1355 uint64_t dcc_offset
;
1356 uint64_t htile_offset
;
1357 bool tc_compatible_htile
;
1358 struct radeon_surf surface
;
1360 struct radv_fmask_info fmask
;
1361 struct radv_cmask_info cmask
;
1362 uint64_t clear_value_offset
;
1363 uint64_t dcc_pred_offset
;
1365 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1366 VkDeviceMemory owned_memory
;
1369 /* Whether the image has a htile that is known consistent with the contents of
1371 bool radv_layout_has_htile(const struct radv_image
*image
,
1372 VkImageLayout layout
,
1373 unsigned queue_mask
);
1375 /* Whether the image has a htile that is known consistent with the contents of
1376 * the image and is allowed to be in compressed form.
1378 * If this is false reads that don't use the htile should be able to return
1381 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1382 VkImageLayout layout
,
1383 unsigned queue_mask
);
1385 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1386 VkImageLayout layout
,
1387 unsigned queue_mask
);
1389 bool radv_layout_dcc_compressed(const struct radv_image
*image
,
1390 VkImageLayout layout
,
1391 unsigned queue_mask
);
1394 * Return whether the image has CMASK metadata for color surfaces.
1397 radv_image_has_cmask(const struct radv_image
*image
)
1399 return image
->cmask
.size
;
1403 * Return whether the image has FMASK metadata for color surfaces.
1406 radv_image_has_fmask(const struct radv_image
*image
)
1408 return image
->fmask
.size
;
1412 * Return whether the image has DCC metadata for color surfaces.
1415 radv_image_has_dcc(const struct radv_image
*image
)
1417 return image
->surface
.dcc_size
;
1421 * Return whether DCC metadata is enabled for a level.
1424 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1426 return radv_image_has_dcc(image
) &&
1427 level
< image
->surface
.num_dcc_levels
;
1431 * Return whether the image has HTILE metadata for depth surfaces.
1434 radv_image_has_htile(const struct radv_image
*image
)
1436 return image
->surface
.htile_size
;
1440 * Return whether HTILE metadata is enabled for a level.
1443 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1445 return radv_image_has_htile(image
) && level
== 0;
1449 * Return whether the image is TC-compatible HTILE.
1452 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1454 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1457 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1459 static inline uint32_t
1460 radv_get_layerCount(const struct radv_image
*image
,
1461 const VkImageSubresourceRange
*range
)
1463 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1464 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1467 static inline uint32_t
1468 radv_get_levelCount(const struct radv_image
*image
,
1469 const VkImageSubresourceRange
*range
)
1471 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1472 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1475 struct radeon_bo_metadata
;
1477 radv_init_metadata(struct radv_device
*device
,
1478 struct radv_image
*image
,
1479 struct radeon_bo_metadata
*metadata
);
1481 struct radv_image_view
{
1482 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1483 struct radeon_winsys_bo
*bo
;
1485 VkImageViewType type
;
1486 VkImageAspectFlags aspect_mask
;
1488 uint32_t base_layer
;
1489 uint32_t layer_count
;
1491 uint32_t level_count
;
1492 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1494 uint32_t descriptor
[16];
1496 /* Descriptor for use as a storage image as opposed to a sampled image.
1497 * This has a few differences for cube maps (e.g. type).
1499 uint32_t storage_descriptor
[16];
1502 struct radv_image_create_info
{
1503 const VkImageCreateInfo
*vk_info
;
1505 bool no_metadata_planes
;
1508 VkResult
radv_image_create(VkDevice _device
,
1509 const struct radv_image_create_info
*info
,
1510 const VkAllocationCallbacks
* alloc
,
1514 radv_image_from_gralloc(VkDevice device_h
,
1515 const VkImageCreateInfo
*base_info
,
1516 const VkNativeBufferANDROID
*gralloc_info
,
1517 const VkAllocationCallbacks
*alloc
,
1518 VkImage
*out_image_h
);
1520 void radv_image_view_init(struct radv_image_view
*view
,
1521 struct radv_device
*device
,
1522 const VkImageViewCreateInfo
* pCreateInfo
);
1524 struct radv_buffer_view
{
1525 struct radeon_winsys_bo
*bo
;
1527 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1530 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1531 struct radv_device
*device
,
1532 const VkBufferViewCreateInfo
* pCreateInfo
);
1534 static inline struct VkExtent3D
1535 radv_sanitize_image_extent(const VkImageType imageType
,
1536 const struct VkExtent3D imageExtent
)
1538 switch (imageType
) {
1539 case VK_IMAGE_TYPE_1D
:
1540 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1541 case VK_IMAGE_TYPE_2D
:
1542 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1543 case VK_IMAGE_TYPE_3D
:
1546 unreachable("invalid image type");
1550 static inline struct VkOffset3D
1551 radv_sanitize_image_offset(const VkImageType imageType
,
1552 const struct VkOffset3D imageOffset
)
1554 switch (imageType
) {
1555 case VK_IMAGE_TYPE_1D
:
1556 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1557 case VK_IMAGE_TYPE_2D
:
1558 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1559 case VK_IMAGE_TYPE_3D
:
1562 unreachable("invalid image type");
1567 radv_image_extent_compare(const struct radv_image
*image
,
1568 const VkExtent3D
*extent
)
1570 if (extent
->width
!= image
->info
.width
||
1571 extent
->height
!= image
->info
.height
||
1572 extent
->depth
!= image
->info
.depth
)
1577 struct radv_sampler
{
1581 struct radv_color_buffer_info
{
1582 uint64_t cb_color_base
;
1583 uint64_t cb_color_cmask
;
1584 uint64_t cb_color_fmask
;
1585 uint64_t cb_dcc_base
;
1586 uint32_t cb_color_pitch
;
1587 uint32_t cb_color_slice
;
1588 uint32_t cb_color_view
;
1589 uint32_t cb_color_info
;
1590 uint32_t cb_color_attrib
;
1591 uint32_t cb_color_attrib2
;
1592 uint32_t cb_dcc_control
;
1593 uint32_t cb_color_cmask_slice
;
1594 uint32_t cb_color_fmask_slice
;
1597 struct radv_ds_buffer_info
{
1598 uint64_t db_z_read_base
;
1599 uint64_t db_stencil_read_base
;
1600 uint64_t db_z_write_base
;
1601 uint64_t db_stencil_write_base
;
1602 uint64_t db_htile_data_base
;
1603 uint32_t db_depth_info
;
1605 uint32_t db_stencil_info
;
1606 uint32_t db_depth_view
;
1607 uint32_t db_depth_size
;
1608 uint32_t db_depth_slice
;
1609 uint32_t db_htile_surface
;
1610 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1611 uint32_t db_z_info2
;
1612 uint32_t db_stencil_info2
;
1616 struct radv_attachment_info
{
1618 struct radv_color_buffer_info cb
;
1619 struct radv_ds_buffer_info ds
;
1621 struct radv_image_view
*attachment
;
1624 struct radv_framebuffer
{
1629 uint32_t attachment_count
;
1630 struct radv_attachment_info attachments
[0];
1633 struct radv_subpass_barrier
{
1634 VkPipelineStageFlags src_stage_mask
;
1635 VkAccessFlags src_access_mask
;
1636 VkAccessFlags dst_access_mask
;
1639 struct radv_subpass
{
1640 uint32_t input_count
;
1641 uint32_t color_count
;
1642 VkAttachmentReference
* input_attachments
;
1643 VkAttachmentReference
* color_attachments
;
1644 VkAttachmentReference
* resolve_attachments
;
1645 VkAttachmentReference depth_stencil_attachment
;
1647 /** Subpass has at least one resolve attachment */
1650 struct radv_subpass_barrier start_barrier
;
1653 VkSampleCountFlagBits max_sample_count
;
1656 struct radv_render_pass_attachment
{
1659 VkAttachmentLoadOp load_op
;
1660 VkAttachmentLoadOp stencil_load_op
;
1661 VkImageLayout initial_layout
;
1662 VkImageLayout final_layout
;
1666 struct radv_render_pass
{
1667 uint32_t attachment_count
;
1668 uint32_t subpass_count
;
1669 VkAttachmentReference
* subpass_attachments
;
1670 struct radv_render_pass_attachment
* attachments
;
1671 struct radv_subpass_barrier end_barrier
;
1672 struct radv_subpass subpasses
[0];
1675 VkResult
radv_device_init_meta(struct radv_device
*device
);
1676 void radv_device_finish_meta(struct radv_device
*device
);
1678 struct radv_query_pool
{
1679 struct radeon_winsys_bo
*bo
;
1681 uint32_t availability_offset
;
1685 uint32_t pipeline_stats_mask
;
1688 struct radv_semaphore
{
1689 /* use a winsys sem for non-exportable */
1690 struct radeon_winsys_sem
*sem
;
1692 uint32_t temp_syncobj
;
1695 VkResult
radv_alloc_sem_info(struct radv_winsys_sem_info
*sem_info
,
1697 const VkSemaphore
*wait_sems
,
1698 int num_signal_sems
,
1699 const VkSemaphore
*signal_sems
,
1701 void radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
);
1703 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1704 VkPipelineBindPoint bind_point
,
1705 struct radv_descriptor_set
*set
,
1709 radv_update_descriptor_sets(struct radv_device
*device
,
1710 struct radv_cmd_buffer
*cmd_buffer
,
1711 VkDescriptorSet overrideSet
,
1712 uint32_t descriptorWriteCount
,
1713 const VkWriteDescriptorSet
*pDescriptorWrites
,
1714 uint32_t descriptorCopyCount
,
1715 const VkCopyDescriptorSet
*pDescriptorCopies
);
1718 radv_update_descriptor_set_with_template(struct radv_device
*device
,
1719 struct radv_cmd_buffer
*cmd_buffer
,
1720 struct radv_descriptor_set
*set
,
1721 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
1724 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1725 VkPipelineBindPoint pipelineBindPoint
,
1726 VkPipelineLayout _layout
,
1728 uint32_t descriptorWriteCount
,
1729 const VkWriteDescriptorSet
*pDescriptorWrites
);
1731 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
1732 struct radv_image
*image
, uint32_t value
);
1735 struct radeon_winsys_fence
*fence
;
1740 uint32_t temp_syncobj
;
1743 /* radv_nir_to_llvm.c */
1744 struct radv_shader_variant_info
;
1745 struct radv_nir_compiler_options
;
1747 void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm
,
1748 struct nir_shader
*geom_shader
,
1749 struct ac_shader_binary
*binary
,
1750 struct ac_shader_config
*config
,
1751 struct radv_shader_variant_info
*shader_info
,
1752 const struct radv_nir_compiler_options
*option
);
1754 void radv_compile_nir_shader(LLVMTargetMachineRef tm
,
1755 struct ac_shader_binary
*binary
,
1756 struct ac_shader_config
*config
,
1757 struct radv_shader_variant_info
*shader_info
,
1758 struct nir_shader
*const *nir
,
1760 const struct radv_nir_compiler_options
*options
);
1762 /* radv_shader_info.h */
1763 struct radv_shader_info
;
1765 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
1766 const struct radv_nir_compiler_options
*options
,
1767 struct radv_shader_info
*info
);
1769 struct radeon_winsys_sem
;
1771 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1773 static inline struct __radv_type * \
1774 __radv_type ## _from_handle(__VkType _handle) \
1776 return (struct __radv_type *) _handle; \
1779 static inline __VkType \
1780 __radv_type ## _to_handle(struct __radv_type *_obj) \
1782 return (__VkType) _obj; \
1785 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1787 static inline struct __radv_type * \
1788 __radv_type ## _from_handle(__VkType _handle) \
1790 return (struct __radv_type *)(uintptr_t) _handle; \
1793 static inline __VkType \
1794 __radv_type ## _to_handle(struct __radv_type *_obj) \
1796 return (__VkType)(uintptr_t) _obj; \
1799 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1800 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1802 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
1803 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
1804 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
1805 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
1806 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
1808 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
1809 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
1810 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
1811 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
1812 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
1813 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
1814 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
1815 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
1816 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
1817 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
1818 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
1819 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
1820 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
1821 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
1822 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
1823 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
1824 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
1825 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
1826 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
1827 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
1828 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
1830 #endif /* RADV_PRIVATE_H */