2 * Copyrigh 2016 Red Hat Inc.
4 * Copyright © 2015 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
32 #include "nir/nir_builder.h"
33 #include "radv_meta.h"
34 #include "radv_private.h"
38 #define TIMESTAMP_NOT_READY UINT64_MAX
40 static const int pipelinestat_block_size
= 11 * 8;
41 static const unsigned pipeline_statistics_indices
[] = {7, 6, 3, 4, 5, 2, 1, 0, 8, 9, 10};
44 radv_get_pipeline_statistics_index(const VkQueryPipelineStatisticFlagBits flag
)
46 int offset
= ffs(flag
) - 1;
47 assert(offset
< ARRAY_SIZE(pipeline_statistics_indices
));
48 return pipeline_statistics_indices
[offset
];
51 static nir_ssa_def
*nir_test_flag(nir_builder
*b
, nir_ssa_def
*flags
, uint32_t flag
)
53 return nir_i2b(b
, nir_iand(b
, flags
, nir_imm_int(b
, flag
)));
56 static void radv_break_on_count(nir_builder
*b
, nir_variable
*var
, nir_ssa_def
*count
)
58 nir_ssa_def
*counter
= nir_load_var(b
, var
);
60 nir_if
*if_stmt
= nir_if_create(b
->shader
);
61 if_stmt
->condition
= nir_src_for_ssa(nir_uge(b
, counter
, count
));
62 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
64 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
66 nir_jump_instr
*instr
= nir_jump_instr_create(b
->shader
, nir_jump_break
);
67 nir_builder_instr_insert(b
, &instr
->instr
);
69 b
->cursor
= nir_after_cf_node(&if_stmt
->cf_node
);
70 counter
= nir_iadd(b
, counter
, nir_imm_int(b
, 1));
71 nir_store_var(b
, var
, counter
, 0x1);
74 static struct nir_ssa_def
*
75 radv_load_push_int(nir_builder
*b
, unsigned offset
, const char *name
)
77 nir_intrinsic_instr
*flags
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_push_constant
);
78 nir_intrinsic_set_base(flags
, 0);
79 nir_intrinsic_set_range(flags
, 16);
80 flags
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, offset
));
81 flags
->num_components
= 1;
82 nir_ssa_dest_init(&flags
->instr
, &flags
->dest
, 1, 32, name
);
83 nir_builder_instr_insert(b
, &flags
->instr
);
84 return &flags
->dest
.ssa
;
88 radv_store_availability(nir_builder
*b
, nir_ssa_def
*flags
, nir_ssa_def
*dst_buf
,
89 nir_ssa_def
*offset
, nir_ssa_def
*value32
)
91 nir_ssa_def
*result_is_64bit
= nir_test_flag(b
, flags
, VK_QUERY_RESULT_64_BIT
);
92 nir_if
*availability_if
= nir_if_create(b
->shader
);
93 availability_if
->condition
= nir_src_for_ssa(nir_test_flag(b
, flags
, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
));
94 nir_cf_node_insert(b
->cursor
, &availability_if
->cf_node
);
96 b
->cursor
= nir_after_cf_list(&availability_if
->then_list
);
98 nir_if
*store_64bit_if
= nir_if_create(b
->shader
);
99 store_64bit_if
->condition
= nir_src_for_ssa(result_is_64bit
);
100 nir_cf_node_insert(b
->cursor
, &store_64bit_if
->cf_node
);
102 b
->cursor
= nir_after_cf_list(&store_64bit_if
->then_list
);
104 nir_intrinsic_instr
*store
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_ssbo
);
105 store
->src
[0] = nir_src_for_ssa(nir_vec2(b
, value32
, nir_imm_int(b
, 0)));
106 store
->src
[1] = nir_src_for_ssa(dst_buf
);
107 store
->src
[2] = nir_src_for_ssa(offset
);
108 nir_intrinsic_set_write_mask(store
, 0x3);
109 nir_intrinsic_set_align(store
, 8, 0);
110 store
->num_components
= 2;
111 nir_builder_instr_insert(b
, &store
->instr
);
113 b
->cursor
= nir_after_cf_list(&store_64bit_if
->else_list
);
115 store
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_ssbo
);
116 store
->src
[0] = nir_src_for_ssa(value32
);
117 store
->src
[1] = nir_src_for_ssa(dst_buf
);
118 store
->src
[2] = nir_src_for_ssa(offset
);
119 nir_intrinsic_set_write_mask(store
, 0x1);
120 nir_intrinsic_set_align(store
, 4, 0);
121 store
->num_components
= 1;
122 nir_builder_instr_insert(b
, &store
->instr
);
124 b
->cursor
= nir_after_cf_node(&store_64bit_if
->cf_node
);
126 b
->cursor
= nir_after_cf_node(&availability_if
->cf_node
);
130 build_occlusion_query_shader(struct radv_device
*device
) {
131 /* the shader this builds is roughly
135 * uint32_t dst_stride;
138 * uint32_t src_stride = 16 * db_count;
140 * location(binding = 0) buffer dst_buf;
141 * location(binding = 1) buffer src_buf;
144 * uint64_t result = 0;
145 * uint64_t src_offset = src_stride * global_id.x;
146 * uint64_t dst_offset = dst_stride * global_id.x;
147 * bool available = true;
148 * for (int i = 0; i < db_count; ++i) {
149 * if (enabled_rb_mask & (1 << i)) {
150 * uint64_t start = src_buf[src_offset + 16 * i];
151 * uint64_t end = src_buf[src_offset + 16 * i + 8];
152 * if ((start & (1ull << 63)) && (end & (1ull << 63)))
153 * result += end - start;
158 * uint32_t elem_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;
159 * if ((flags & VK_QUERY_RESULT_PARTIAL_BIT) || available) {
160 * if (flags & VK_QUERY_RESULT_64_BIT)
161 * dst_buf[dst_offset] = result;
163 * dst_buf[dst_offset] = (uint32_t)result.
165 * if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
166 * dst_buf[dst_offset + elem_size] = available;
171 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_COMPUTE
, NULL
);
172 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "occlusion_query");
173 b
.shader
->info
.cs
.local_size
[0] = 64;
174 b
.shader
->info
.cs
.local_size
[1] = 1;
175 b
.shader
->info
.cs
.local_size
[2] = 1;
177 nir_variable
*result
= nir_local_variable_create(b
.impl
, glsl_uint64_t_type(), "result");
178 nir_variable
*outer_counter
= nir_local_variable_create(b
.impl
, glsl_int_type(), "outer_counter");
179 nir_variable
*start
= nir_local_variable_create(b
.impl
, glsl_uint64_t_type(), "start");
180 nir_variable
*end
= nir_local_variable_create(b
.impl
, glsl_uint64_t_type(), "end");
181 nir_variable
*available
= nir_local_variable_create(b
.impl
, glsl_bool_type(), "available");
182 unsigned enabled_rb_mask
= device
->physical_device
->rad_info
.enabled_rb_mask
;
183 unsigned db_count
= device
->physical_device
->rad_info
.num_render_backends
;
185 nir_ssa_def
*flags
= radv_load_push_int(&b
, 0, "flags");
187 nir_intrinsic_instr
*dst_buf
= nir_intrinsic_instr_create(b
.shader
,
188 nir_intrinsic_vulkan_resource_index
);
189 dst_buf
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
190 dst_buf
->num_components
= 1;
191 nir_intrinsic_set_desc_set(dst_buf
, 0);
192 nir_intrinsic_set_binding(dst_buf
, 0);
193 nir_ssa_dest_init(&dst_buf
->instr
, &dst_buf
->dest
, dst_buf
->num_components
, 32, NULL
);
194 nir_builder_instr_insert(&b
, &dst_buf
->instr
);
196 nir_intrinsic_instr
*src_buf
= nir_intrinsic_instr_create(b
.shader
,
197 nir_intrinsic_vulkan_resource_index
);
198 src_buf
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
199 src_buf
->num_components
= 1;
200 nir_intrinsic_set_desc_set(src_buf
, 0);
201 nir_intrinsic_set_binding(src_buf
, 1);
202 nir_ssa_dest_init(&src_buf
->instr
, &src_buf
->dest
, src_buf
->num_components
, 32, NULL
);
203 nir_builder_instr_insert(&b
, &src_buf
->instr
);
205 nir_ssa_def
*invoc_id
= nir_load_local_invocation_id(&b
);
206 nir_ssa_def
*wg_id
= nir_load_work_group_id(&b
);
207 nir_ssa_def
*block_size
= nir_imm_ivec4(&b
,
208 b
.shader
->info
.cs
.local_size
[0],
209 b
.shader
->info
.cs
.local_size
[1],
210 b
.shader
->info
.cs
.local_size
[2], 0);
211 nir_ssa_def
*global_id
= nir_iadd(&b
, nir_imul(&b
, wg_id
, block_size
), invoc_id
);
212 global_id
= nir_channel(&b
, global_id
, 0); // We only care about x here.
214 nir_ssa_def
*input_stride
= nir_imm_int(&b
, db_count
* 16);
215 nir_ssa_def
*input_base
= nir_imul(&b
, input_stride
, global_id
);
216 nir_ssa_def
*output_stride
= radv_load_push_int(&b
, 4, "output_stride");
217 nir_ssa_def
*output_base
= nir_imul(&b
, output_stride
, global_id
);
220 nir_store_var(&b
, result
, nir_imm_int64(&b
, 0), 0x1);
221 nir_store_var(&b
, outer_counter
, nir_imm_int(&b
, 0), 0x1);
222 nir_store_var(&b
, available
, nir_imm_true(&b
), 0x1);
224 nir_loop
*outer_loop
= nir_loop_create(b
.shader
);
225 nir_builder_cf_insert(&b
, &outer_loop
->cf_node
);
226 b
.cursor
= nir_after_cf_list(&outer_loop
->body
);
228 nir_ssa_def
*current_outer_count
= nir_load_var(&b
, outer_counter
);
229 radv_break_on_count(&b
, outer_counter
, nir_imm_int(&b
, db_count
));
231 nir_ssa_def
*enabled_cond
=
232 nir_iand(&b
, nir_imm_int(&b
, enabled_rb_mask
),
233 nir_ishl(&b
, nir_imm_int(&b
, 1), current_outer_count
));
235 nir_if
*enabled_if
= nir_if_create(b
.shader
);
236 enabled_if
->condition
= nir_src_for_ssa(nir_i2b(&b
, enabled_cond
));
237 nir_cf_node_insert(b
.cursor
, &enabled_if
->cf_node
);
239 b
.cursor
= nir_after_cf_list(&enabled_if
->then_list
);
241 nir_ssa_def
*load_offset
= nir_imul(&b
, current_outer_count
, nir_imm_int(&b
, 16));
242 load_offset
= nir_iadd(&b
, input_base
, load_offset
);
244 nir_intrinsic_instr
*load
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ssbo
);
245 load
->src
[0] = nir_src_for_ssa(&src_buf
->dest
.ssa
);
246 load
->src
[1] = nir_src_for_ssa(load_offset
);
247 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 2, 64, NULL
);
248 load
->num_components
= 2;
249 nir_intrinsic_set_align(load
, 16, 0);
250 nir_builder_instr_insert(&b
, &load
->instr
);
252 nir_store_var(&b
, start
, nir_channel(&b
, &load
->dest
.ssa
, 0), 0x1);
253 nir_store_var(&b
, end
, nir_channel(&b
, &load
->dest
.ssa
, 1), 0x1);
255 nir_ssa_def
*start_done
= nir_ilt(&b
, nir_load_var(&b
, start
), nir_imm_int64(&b
, 0));
256 nir_ssa_def
*end_done
= nir_ilt(&b
, nir_load_var(&b
, end
), nir_imm_int64(&b
, 0));
258 nir_if
*update_if
= nir_if_create(b
.shader
);
259 update_if
->condition
= nir_src_for_ssa(nir_iand(&b
, start_done
, end_done
));
260 nir_cf_node_insert(b
.cursor
, &update_if
->cf_node
);
262 b
.cursor
= nir_after_cf_list(&update_if
->then_list
);
264 nir_store_var(&b
, result
,
265 nir_iadd(&b
, nir_load_var(&b
, result
),
266 nir_isub(&b
, nir_load_var(&b
, end
),
267 nir_load_var(&b
, start
))), 0x1);
269 b
.cursor
= nir_after_cf_list(&update_if
->else_list
);
271 nir_store_var(&b
, available
, nir_imm_false(&b
), 0x1);
273 b
.cursor
= nir_after_cf_node(&outer_loop
->cf_node
);
275 /* Store the result if complete or if partial results have been requested. */
277 nir_ssa_def
*result_is_64bit
= nir_test_flag(&b
, flags
, VK_QUERY_RESULT_64_BIT
);
278 nir_ssa_def
*result_size
= nir_bcsel(&b
, result_is_64bit
, nir_imm_int(&b
, 8), nir_imm_int(&b
, 4));
280 nir_if
*store_if
= nir_if_create(b
.shader
);
281 store_if
->condition
= nir_src_for_ssa(nir_ior(&b
, nir_test_flag(&b
, flags
, VK_QUERY_RESULT_PARTIAL_BIT
), nir_load_var(&b
, available
)));
282 nir_cf_node_insert(b
.cursor
, &store_if
->cf_node
);
284 b
.cursor
= nir_after_cf_list(&store_if
->then_list
);
286 nir_if
*store_64bit_if
= nir_if_create(b
.shader
);
287 store_64bit_if
->condition
= nir_src_for_ssa(result_is_64bit
);
288 nir_cf_node_insert(b
.cursor
, &store_64bit_if
->cf_node
);
290 b
.cursor
= nir_after_cf_list(&store_64bit_if
->then_list
);
292 nir_intrinsic_instr
*store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
293 store
->src
[0] = nir_src_for_ssa(nir_load_var(&b
, result
));
294 store
->src
[1] = nir_src_for_ssa(&dst_buf
->dest
.ssa
);
295 store
->src
[2] = nir_src_for_ssa(output_base
);
296 nir_intrinsic_set_write_mask(store
, 0x1);
297 nir_intrinsic_set_align(store
, 8, 0);
298 store
->num_components
= 1;
299 nir_builder_instr_insert(&b
, &store
->instr
);
301 b
.cursor
= nir_after_cf_list(&store_64bit_if
->else_list
);
303 store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
304 store
->src
[0] = nir_src_for_ssa(nir_u2u32(&b
, nir_load_var(&b
, result
)));
305 store
->src
[1] = nir_src_for_ssa(&dst_buf
->dest
.ssa
);
306 store
->src
[2] = nir_src_for_ssa(output_base
);
307 nir_intrinsic_set_write_mask(store
, 0x1);
308 nir_intrinsic_set_align(store
, 4, 0);
309 store
->num_components
= 1;
310 nir_builder_instr_insert(&b
, &store
->instr
);
312 b
.cursor
= nir_after_cf_node(&store_if
->cf_node
);
314 radv_store_availability(&b
, flags
, &dst_buf
->dest
.ssa
,
315 nir_iadd(&b
, result_size
, output_base
),
316 nir_b2i32(&b
, nir_load_var(&b
, available
)));
322 build_pipeline_statistics_query_shader(struct radv_device
*device
) {
323 /* the shader this builds is roughly
327 * uint32_t dst_stride;
328 * uint32_t stats_mask;
329 * uint32_t avail_offset;
332 * uint32_t src_stride = pipelinestat_block_size * 2;
334 * location(binding = 0) buffer dst_buf;
335 * location(binding = 1) buffer src_buf;
338 * uint64_t src_offset = src_stride * global_id.x;
339 * uint64_t dst_base = dst_stride * global_id.x;
340 * uint64_t dst_offset = dst_base;
341 * uint32_t elem_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;
342 * uint32_t elem_count = stats_mask >> 16;
343 * uint32_t available32 = src_buf[avail_offset + 4 * global_id.x];
344 * if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
345 * dst_buf[dst_offset + elem_count * elem_size] = available32;
347 * if ((bool)available32) {
348 * // repeat 11 times:
349 * if (stats_mask & (1 << 0)) {
350 * uint64_t start = src_buf[src_offset + 8 * indices[0]];
351 * uint64_t end = src_buf[src_offset + 8 * indices[0] + pipelinestat_block_size];
352 * uint64_t result = end - start;
353 * if (flags & VK_QUERY_RESULT_64_BIT)
354 * dst_buf[dst_offset] = result;
356 * dst_buf[dst_offset] = (uint32_t)result.
357 * dst_offset += elem_size;
359 * } else if (flags & VK_QUERY_RESULT_PARTIAL_BIT) {
360 * // Set everything to 0 as we don't know what is valid.
361 * for (int i = 0; i < elem_count; ++i)
362 * dst_buf[dst_base + elem_size * i] = 0;
367 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_COMPUTE
, NULL
);
368 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "pipeline_statistics_query");
369 b
.shader
->info
.cs
.local_size
[0] = 64;
370 b
.shader
->info
.cs
.local_size
[1] = 1;
371 b
.shader
->info
.cs
.local_size
[2] = 1;
373 nir_variable
*output_offset
= nir_local_variable_create(b
.impl
, glsl_int_type(), "output_offset");
375 nir_ssa_def
*flags
= radv_load_push_int(&b
, 0, "flags");
376 nir_ssa_def
*stats_mask
= radv_load_push_int(&b
, 8, "stats_mask");
377 nir_ssa_def
*avail_offset
= radv_load_push_int(&b
, 12, "avail_offset");
379 nir_intrinsic_instr
*dst_buf
= nir_intrinsic_instr_create(b
.shader
,
380 nir_intrinsic_vulkan_resource_index
);
381 dst_buf
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
382 dst_buf
->num_components
= 1;;
383 nir_intrinsic_set_desc_set(dst_buf
, 0);
384 nir_intrinsic_set_binding(dst_buf
, 0);
385 nir_ssa_dest_init(&dst_buf
->instr
, &dst_buf
->dest
, dst_buf
->num_components
, 32, NULL
);
386 nir_builder_instr_insert(&b
, &dst_buf
->instr
);
388 nir_intrinsic_instr
*src_buf
= nir_intrinsic_instr_create(b
.shader
,
389 nir_intrinsic_vulkan_resource_index
);
390 src_buf
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
391 src_buf
->num_components
= 1;
392 nir_intrinsic_set_desc_set(src_buf
, 0);
393 nir_intrinsic_set_binding(src_buf
, 1);
394 nir_ssa_dest_init(&src_buf
->instr
, &src_buf
->dest
, src_buf
->num_components
, 32, NULL
);
395 nir_builder_instr_insert(&b
, &src_buf
->instr
);
397 nir_ssa_def
*invoc_id
= nir_load_local_invocation_id(&b
);
398 nir_ssa_def
*wg_id
= nir_load_work_group_id(&b
);
399 nir_ssa_def
*block_size
= nir_imm_ivec4(&b
,
400 b
.shader
->info
.cs
.local_size
[0],
401 b
.shader
->info
.cs
.local_size
[1],
402 b
.shader
->info
.cs
.local_size
[2], 0);
403 nir_ssa_def
*global_id
= nir_iadd(&b
, nir_imul(&b
, wg_id
, block_size
), invoc_id
);
404 global_id
= nir_channel(&b
, global_id
, 0); // We only care about x here.
406 nir_ssa_def
*input_stride
= nir_imm_int(&b
, pipelinestat_block_size
* 2);
407 nir_ssa_def
*input_base
= nir_imul(&b
, input_stride
, global_id
);
408 nir_ssa_def
*output_stride
= radv_load_push_int(&b
, 4, "output_stride");
409 nir_ssa_def
*output_base
= nir_imul(&b
, output_stride
, global_id
);
412 avail_offset
= nir_iadd(&b
, avail_offset
,
413 nir_imul(&b
, global_id
, nir_imm_int(&b
, 4)));
415 nir_intrinsic_instr
*load
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ssbo
);
416 load
->src
[0] = nir_src_for_ssa(&src_buf
->dest
.ssa
);
417 load
->src
[1] = nir_src_for_ssa(avail_offset
);
418 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 1, 32, NULL
);
419 load
->num_components
= 1;
420 nir_intrinsic_set_align(load
, 4, 0);
421 nir_builder_instr_insert(&b
, &load
->instr
);
422 nir_ssa_def
*available32
= &load
->dest
.ssa
;
424 nir_ssa_def
*result_is_64bit
= nir_test_flag(&b
, flags
, VK_QUERY_RESULT_64_BIT
);
425 nir_ssa_def
*elem_size
= nir_bcsel(&b
, result_is_64bit
, nir_imm_int(&b
, 8), nir_imm_int(&b
, 4));
426 nir_ssa_def
*elem_count
= nir_ushr(&b
, stats_mask
, nir_imm_int(&b
, 16));
428 radv_store_availability(&b
, flags
, &dst_buf
->dest
.ssa
,
429 nir_iadd(&b
, output_base
, nir_imul(&b
, elem_count
, elem_size
)),
432 nir_if
*available_if
= nir_if_create(b
.shader
);
433 available_if
->condition
= nir_src_for_ssa(nir_i2b(&b
, available32
));
434 nir_cf_node_insert(b
.cursor
, &available_if
->cf_node
);
436 b
.cursor
= nir_after_cf_list(&available_if
->then_list
);
438 nir_store_var(&b
, output_offset
, output_base
, 0x1);
439 for (int i
= 0; i
< 11; ++i
) {
440 nir_if
*store_if
= nir_if_create(b
.shader
);
441 store_if
->condition
= nir_src_for_ssa(nir_test_flag(&b
, stats_mask
, 1u << i
));
442 nir_cf_node_insert(b
.cursor
, &store_if
->cf_node
);
444 b
.cursor
= nir_after_cf_list(&store_if
->then_list
);
446 load
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ssbo
);
447 load
->src
[0] = nir_src_for_ssa(&src_buf
->dest
.ssa
);
448 load
->src
[1] = nir_src_for_ssa(nir_iadd(&b
, input_base
,
449 nir_imm_int(&b
, pipeline_statistics_indices
[i
] * 8)));
450 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 1, 64, NULL
);
451 load
->num_components
= 1;
452 nir_intrinsic_set_align(load
, 8, 0);
453 nir_builder_instr_insert(&b
, &load
->instr
);
454 nir_ssa_def
*start
= &load
->dest
.ssa
;
456 load
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ssbo
);
457 load
->src
[0] = nir_src_for_ssa(&src_buf
->dest
.ssa
);
458 load
->src
[1] = nir_src_for_ssa(nir_iadd(&b
, input_base
,
459 nir_imm_int(&b
, pipeline_statistics_indices
[i
] * 8 + pipelinestat_block_size
)));
460 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 1, 64, NULL
);
461 load
->num_components
= 1;
462 nir_intrinsic_set_align(load
, 8, 0);
463 nir_builder_instr_insert(&b
, &load
->instr
);
464 nir_ssa_def
*end
= &load
->dest
.ssa
;
466 nir_ssa_def
*result
= nir_isub(&b
, end
, start
);
469 nir_if
*store_64bit_if
= nir_if_create(b
.shader
);
470 store_64bit_if
->condition
= nir_src_for_ssa(result_is_64bit
);
471 nir_cf_node_insert(b
.cursor
, &store_64bit_if
->cf_node
);
473 b
.cursor
= nir_after_cf_list(&store_64bit_if
->then_list
);
475 nir_intrinsic_instr
*store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
476 store
->src
[0] = nir_src_for_ssa(result
);
477 store
->src
[1] = nir_src_for_ssa(&dst_buf
->dest
.ssa
);
478 store
->src
[2] = nir_src_for_ssa(nir_load_var(&b
, output_offset
));
479 nir_intrinsic_set_write_mask(store
, 0x1);
480 nir_intrinsic_set_align(store
, 8, 0);
481 store
->num_components
= 1;
482 nir_builder_instr_insert(&b
, &store
->instr
);
484 b
.cursor
= nir_after_cf_list(&store_64bit_if
->else_list
);
486 store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
487 store
->src
[0] = nir_src_for_ssa(nir_u2u32(&b
, result
));
488 store
->src
[1] = nir_src_for_ssa(&dst_buf
->dest
.ssa
);
489 store
->src
[2] = nir_src_for_ssa(nir_load_var(&b
, output_offset
));
490 nir_intrinsic_set_write_mask(store
, 0x1);
491 nir_intrinsic_set_align(store
, 4, 0);
492 store
->num_components
= 1;
493 nir_builder_instr_insert(&b
, &store
->instr
);
495 b
.cursor
= nir_after_cf_node(&store_64bit_if
->cf_node
);
497 nir_store_var(&b
, output_offset
,
498 nir_iadd(&b
, nir_load_var(&b
, output_offset
),
501 b
.cursor
= nir_after_cf_node(&store_if
->cf_node
);
504 b
.cursor
= nir_after_cf_list(&available_if
->else_list
);
506 available_if
= nir_if_create(b
.shader
);
507 available_if
->condition
= nir_src_for_ssa(nir_test_flag(&b
, flags
, VK_QUERY_RESULT_PARTIAL_BIT
));
508 nir_cf_node_insert(b
.cursor
, &available_if
->cf_node
);
510 b
.cursor
= nir_after_cf_list(&available_if
->then_list
);
512 /* Stores zeros in all outputs. */
514 nir_variable
*counter
= nir_local_variable_create(b
.impl
, glsl_int_type(), "counter");
515 nir_store_var(&b
, counter
, nir_imm_int(&b
, 0), 0x1);
517 nir_loop
*loop
= nir_loop_create(b
.shader
);
518 nir_builder_cf_insert(&b
, &loop
->cf_node
);
519 b
.cursor
= nir_after_cf_list(&loop
->body
);
521 nir_ssa_def
*current_counter
= nir_load_var(&b
, counter
);
522 radv_break_on_count(&b
, counter
, elem_count
);
524 nir_ssa_def
*output_elem
= nir_iadd(&b
, output_base
,
525 nir_imul(&b
, elem_size
, current_counter
));
527 nir_if
*store_64bit_if
= nir_if_create(b
.shader
);
528 store_64bit_if
->condition
= nir_src_for_ssa(result_is_64bit
);
529 nir_cf_node_insert(b
.cursor
, &store_64bit_if
->cf_node
);
531 b
.cursor
= nir_after_cf_list(&store_64bit_if
->then_list
);
533 nir_intrinsic_instr
*store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
534 store
->src
[0] = nir_src_for_ssa(nir_imm_int64(&b
, 0));
535 store
->src
[1] = nir_src_for_ssa(&dst_buf
->dest
.ssa
);
536 store
->src
[2] = nir_src_for_ssa(output_elem
);
537 nir_intrinsic_set_write_mask(store
, 0x1);
538 nir_intrinsic_set_align(store
, 8, 0);
539 store
->num_components
= 1;
540 nir_builder_instr_insert(&b
, &store
->instr
);
542 b
.cursor
= nir_after_cf_list(&store_64bit_if
->else_list
);
544 store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
545 store
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
546 store
->src
[1] = nir_src_for_ssa(&dst_buf
->dest
.ssa
);
547 store
->src
[2] = nir_src_for_ssa(output_elem
);
548 nir_intrinsic_set_write_mask(store
, 0x1);
549 nir_intrinsic_set_align(store
, 4, 0);
550 store
->num_components
= 1;
551 nir_builder_instr_insert(&b
, &store
->instr
);
553 b
.cursor
= nir_after_cf_node(&loop
->cf_node
);
558 build_tfb_query_shader(struct radv_device
*device
)
560 /* the shader this builds is roughly
562 * uint32_t src_stride = 32;
564 * location(binding = 0) buffer dst_buf;
565 * location(binding = 1) buffer src_buf;
568 * uint64_t result[2] = {};
569 * bool available = false;
570 * uint64_t src_offset = src_stride * global_id.x;
571 * uint64_t dst_offset = dst_stride * global_id.x;
572 * uint64_t *src_data = src_buf[src_offset];
573 * uint32_t avail = (src_data[0] >> 32) &
574 * (src_data[1] >> 32) &
575 * (src_data[2] >> 32) &
576 * (src_data[3] >> 32);
577 * if (avail & 0x80000000) {
578 * result[0] = src_data[3] - src_data[1];
579 * result[1] = src_data[2] - src_data[0];
582 * uint32_t result_size = flags & VK_QUERY_RESULT_64_BIT ? 16 : 8;
583 * if ((flags & VK_QUERY_RESULT_PARTIAL_BIT) || available) {
584 * if (flags & VK_QUERY_RESULT_64_BIT) {
585 * dst_buf[dst_offset] = result;
587 * dst_buf[dst_offset] = (uint32_t)result;
590 * if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
591 * dst_buf[dst_offset + result_size] = available;
596 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_COMPUTE
, NULL
);
597 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "tfb_query");
598 b
.shader
->info
.cs
.local_size
[0] = 64;
599 b
.shader
->info
.cs
.local_size
[1] = 1;
600 b
.shader
->info
.cs
.local_size
[2] = 1;
602 /* Create and initialize local variables. */
603 nir_variable
*result
=
604 nir_local_variable_create(b
.impl
,
605 glsl_vector_type(GLSL_TYPE_UINT64
, 2),
607 nir_variable
*available
=
608 nir_local_variable_create(b
.impl
, glsl_bool_type(), "available");
610 nir_store_var(&b
, result
,
611 nir_vec2(&b
, nir_imm_int64(&b
, 0),
612 nir_imm_int64(&b
, 0)), 0x3);
613 nir_store_var(&b
, available
, nir_imm_false(&b
), 0x1);
615 nir_ssa_def
*flags
= radv_load_push_int(&b
, 0, "flags");
617 /* Load resources. */
618 nir_intrinsic_instr
*dst_buf
= nir_intrinsic_instr_create(b
.shader
,
619 nir_intrinsic_vulkan_resource_index
);
620 dst_buf
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
621 dst_buf
->num_components
= 1;
622 nir_intrinsic_set_desc_set(dst_buf
, 0);
623 nir_intrinsic_set_binding(dst_buf
, 0);
624 nir_ssa_dest_init(&dst_buf
->instr
, &dst_buf
->dest
, dst_buf
->num_components
, 32, NULL
);
625 nir_builder_instr_insert(&b
, &dst_buf
->instr
);
627 nir_intrinsic_instr
*src_buf
= nir_intrinsic_instr_create(b
.shader
,
628 nir_intrinsic_vulkan_resource_index
);
629 src_buf
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
630 src_buf
->num_components
= 1;
631 nir_intrinsic_set_desc_set(src_buf
, 0);
632 nir_intrinsic_set_binding(src_buf
, 1);
633 nir_ssa_dest_init(&src_buf
->instr
, &src_buf
->dest
, src_buf
->num_components
, 32, NULL
);
634 nir_builder_instr_insert(&b
, &src_buf
->instr
);
636 /* Compute global ID. */
637 nir_ssa_def
*invoc_id
= nir_load_local_invocation_id(&b
);
638 nir_ssa_def
*wg_id
= nir_load_work_group_id(&b
);
639 nir_ssa_def
*block_size
= nir_imm_ivec4(&b
,
640 b
.shader
->info
.cs
.local_size
[0],
641 b
.shader
->info
.cs
.local_size
[1],
642 b
.shader
->info
.cs
.local_size
[2], 0);
643 nir_ssa_def
*global_id
= nir_iadd(&b
, nir_imul(&b
, wg_id
, block_size
), invoc_id
);
644 global_id
= nir_channel(&b
, global_id
, 0); // We only care about x here.
646 /* Compute src/dst strides. */
647 nir_ssa_def
*input_stride
= nir_imm_int(&b
, 32);
648 nir_ssa_def
*input_base
= nir_imul(&b
, input_stride
, global_id
);
649 nir_ssa_def
*output_stride
= radv_load_push_int(&b
, 4, "output_stride");
650 nir_ssa_def
*output_base
= nir_imul(&b
, output_stride
, global_id
);
652 /* Load data from the query pool. */
653 nir_intrinsic_instr
*load1
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ssbo
);
654 load1
->src
[0] = nir_src_for_ssa(&src_buf
->dest
.ssa
);
655 load1
->src
[1] = nir_src_for_ssa(input_base
);
656 nir_ssa_dest_init(&load1
->instr
, &load1
->dest
, 4, 32, NULL
);
657 load1
->num_components
= 4;
658 nir_intrinsic_set_align(load1
, 32, 0);
659 nir_builder_instr_insert(&b
, &load1
->instr
);
661 nir_intrinsic_instr
*load2
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ssbo
);
662 load2
->src
[0] = nir_src_for_ssa(&src_buf
->dest
.ssa
);
663 load2
->src
[1] = nir_src_for_ssa(nir_iadd(&b
, input_base
, nir_imm_int(&b
, 16)));
664 nir_ssa_dest_init(&load2
->instr
, &load2
->dest
, 4, 32, NULL
);
665 load2
->num_components
= 4;
666 nir_intrinsic_set_align(load2
, 16, 0);
667 nir_builder_instr_insert(&b
, &load2
->instr
);
669 /* Check if result is available. */
670 nir_ssa_def
*avails
[2];
671 avails
[0] = nir_iand(&b
, nir_channel(&b
, &load1
->dest
.ssa
, 1),
672 nir_channel(&b
, &load1
->dest
.ssa
, 3));
673 avails
[1] = nir_iand(&b
, nir_channel(&b
, &load2
->dest
.ssa
, 1),
674 nir_channel(&b
, &load2
->dest
.ssa
, 3));
675 nir_ssa_def
*result_is_available
=
676 nir_i2b(&b
, nir_iand(&b
, nir_iand(&b
, avails
[0], avails
[1]),
677 nir_imm_int(&b
, 0x80000000)));
679 /* Only compute result if available. */
680 nir_if
*available_if
= nir_if_create(b
.shader
);
681 available_if
->condition
= nir_src_for_ssa(result_is_available
);
682 nir_cf_node_insert(b
.cursor
, &available_if
->cf_node
);
684 b
.cursor
= nir_after_cf_list(&available_if
->then_list
);
687 nir_ssa_def
*packed64
[4];
688 packed64
[0] = nir_pack_64_2x32(&b
, nir_vec2(&b
,
689 nir_channel(&b
, &load1
->dest
.ssa
, 0),
690 nir_channel(&b
, &load1
->dest
.ssa
, 1)));
691 packed64
[1] = nir_pack_64_2x32(&b
, nir_vec2(&b
,
692 nir_channel(&b
, &load1
->dest
.ssa
, 2),
693 nir_channel(&b
, &load1
->dest
.ssa
, 3)));
694 packed64
[2] = nir_pack_64_2x32(&b
, nir_vec2(&b
,
695 nir_channel(&b
, &load2
->dest
.ssa
, 0),
696 nir_channel(&b
, &load2
->dest
.ssa
, 1)));
697 packed64
[3] = nir_pack_64_2x32(&b
, nir_vec2(&b
,
698 nir_channel(&b
, &load2
->dest
.ssa
, 2),
699 nir_channel(&b
, &load2
->dest
.ssa
, 3)));
701 /* Compute result. */
702 nir_ssa_def
*num_primitive_written
=
703 nir_isub(&b
, packed64
[3], packed64
[1]);
704 nir_ssa_def
*primitive_storage_needed
=
705 nir_isub(&b
, packed64
[2], packed64
[0]);
707 nir_store_var(&b
, result
,
708 nir_vec2(&b
, num_primitive_written
,
709 primitive_storage_needed
), 0x3);
710 nir_store_var(&b
, available
, nir_imm_true(&b
), 0x1);
712 b
.cursor
= nir_after_cf_node(&available_if
->cf_node
);
714 /* Determine if result is 64 or 32 bit. */
715 nir_ssa_def
*result_is_64bit
=
716 nir_test_flag(&b
, flags
, VK_QUERY_RESULT_64_BIT
);
717 nir_ssa_def
*result_size
=
718 nir_bcsel(&b
, result_is_64bit
, nir_imm_int(&b
, 16),
721 /* Store the result if complete or partial results have been requested. */
722 nir_if
*store_if
= nir_if_create(b
.shader
);
723 store_if
->condition
=
724 nir_src_for_ssa(nir_ior(&b
, nir_test_flag(&b
, flags
, VK_QUERY_RESULT_PARTIAL_BIT
),
725 nir_load_var(&b
, available
)));
726 nir_cf_node_insert(b
.cursor
, &store_if
->cf_node
);
728 b
.cursor
= nir_after_cf_list(&store_if
->then_list
);
731 nir_if
*store_64bit_if
= nir_if_create(b
.shader
);
732 store_64bit_if
->condition
= nir_src_for_ssa(result_is_64bit
);
733 nir_cf_node_insert(b
.cursor
, &store_64bit_if
->cf_node
);
735 b
.cursor
= nir_after_cf_list(&store_64bit_if
->then_list
);
737 nir_intrinsic_instr
*store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
738 store
->src
[0] = nir_src_for_ssa(nir_load_var(&b
, result
));
739 store
->src
[1] = nir_src_for_ssa(&dst_buf
->dest
.ssa
);
740 store
->src
[2] = nir_src_for_ssa(output_base
);
741 nir_intrinsic_set_write_mask(store
, 0x3);
742 nir_intrinsic_set_align(store
, 8, 0);
743 store
->num_components
= 2;
744 nir_builder_instr_insert(&b
, &store
->instr
);
746 b
.cursor
= nir_after_cf_list(&store_64bit_if
->else_list
);
748 store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
749 store
->src
[0] = nir_src_for_ssa(nir_u2u32(&b
, nir_load_var(&b
, result
)));
750 store
->src
[1] = nir_src_for_ssa(&dst_buf
->dest
.ssa
);
751 store
->src
[2] = nir_src_for_ssa(output_base
);
752 nir_intrinsic_set_write_mask(store
, 0x3);
753 nir_intrinsic_set_align(store
, 4, 0);
754 store
->num_components
= 2;
755 nir_builder_instr_insert(&b
, &store
->instr
);
757 b
.cursor
= nir_after_cf_node(&store_64bit_if
->cf_node
);
759 b
.cursor
= nir_after_cf_node(&store_if
->cf_node
);
761 radv_store_availability(&b
, flags
, &dst_buf
->dest
.ssa
,
762 nir_iadd(&b
, result_size
, output_base
),
763 nir_b2i32(&b
, nir_load_var(&b
, available
)));
769 build_timestamp_query_shader(struct radv_device
*device
)
771 /* the shader this builds is roughly
773 * uint32_t src_stride = 8;
775 * location(binding = 0) buffer dst_buf;
776 * location(binding = 1) buffer src_buf;
779 * uint64_t result = 0;
780 * bool available = false;
781 * uint64_t src_offset = src_stride * global_id.x;
782 * uint64_t dst_offset = dst_stride * global_id.x;
783 * uint64_t timestamp = src_buf[src_offset];
784 * if (timestamp != TIMESTAMP_NOT_READY) {
785 * result = timestamp;
788 * uint32_t result_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;
789 * if ((flags & VK_QUERY_RESULT_PARTIAL_BIT) || available) {
790 * if (flags & VK_QUERY_RESULT_64_BIT) {
791 * dst_buf[dst_offset] = result;
793 * dst_buf[dst_offset] = (uint32_t)result;
796 * if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
797 * dst_buf[dst_offset + result_size] = available;
802 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_COMPUTE
, NULL
);
803 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "timestamp_query");
804 b
.shader
->info
.cs
.local_size
[0] = 64;
805 b
.shader
->info
.cs
.local_size
[1] = 1;
806 b
.shader
->info
.cs
.local_size
[2] = 1;
808 /* Create and initialize local variables. */
809 nir_variable
*result
=
810 nir_local_variable_create(b
.impl
, glsl_uint64_t_type(), "result");
811 nir_variable
*available
=
812 nir_local_variable_create(b
.impl
, glsl_bool_type(), "available");
814 nir_store_var(&b
, result
, nir_imm_int64(&b
, 0), 0x1);
815 nir_store_var(&b
, available
, nir_imm_false(&b
), 0x1);
817 nir_ssa_def
*flags
= radv_load_push_int(&b
, 0, "flags");
819 /* Load resources. */
820 nir_intrinsic_instr
*dst_buf
= nir_intrinsic_instr_create(b
.shader
,
821 nir_intrinsic_vulkan_resource_index
);
822 dst_buf
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
823 dst_buf
->num_components
= 1;
824 nir_intrinsic_set_desc_set(dst_buf
, 0);
825 nir_intrinsic_set_binding(dst_buf
, 0);
826 nir_ssa_dest_init(&dst_buf
->instr
, &dst_buf
->dest
, dst_buf
->num_components
, 32, NULL
);
827 nir_builder_instr_insert(&b
, &dst_buf
->instr
);
829 nir_intrinsic_instr
*src_buf
= nir_intrinsic_instr_create(b
.shader
,
830 nir_intrinsic_vulkan_resource_index
);
831 src_buf
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
832 src_buf
->num_components
= 1;
833 nir_intrinsic_set_desc_set(src_buf
, 0);
834 nir_intrinsic_set_binding(src_buf
, 1);
835 nir_ssa_dest_init(&src_buf
->instr
, &src_buf
->dest
, src_buf
->num_components
, 32, NULL
);
836 nir_builder_instr_insert(&b
, &src_buf
->instr
);
838 /* Compute global ID. */
839 nir_ssa_def
*invoc_id
= nir_load_local_invocation_id(&b
);
840 nir_ssa_def
*wg_id
= nir_load_work_group_id(&b
);
841 nir_ssa_def
*block_size
= nir_imm_ivec4(&b
,
842 b
.shader
->info
.cs
.local_size
[0],
843 b
.shader
->info
.cs
.local_size
[1],
844 b
.shader
->info
.cs
.local_size
[2], 0);
845 nir_ssa_def
*global_id
= nir_iadd(&b
, nir_imul(&b
, wg_id
, block_size
), invoc_id
);
846 global_id
= nir_channel(&b
, global_id
, 0); // We only care about x here.
848 /* Compute src/dst strides. */
849 nir_ssa_def
*input_stride
= nir_imm_int(&b
, 8);
850 nir_ssa_def
*input_base
= nir_imul(&b
, input_stride
, global_id
);
851 nir_ssa_def
*output_stride
= radv_load_push_int(&b
, 4, "output_stride");
852 nir_ssa_def
*output_base
= nir_imul(&b
, output_stride
, global_id
);
854 /* Load data from the query pool. */
855 nir_intrinsic_instr
*load
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ssbo
);
856 load
->src
[0] = nir_src_for_ssa(&src_buf
->dest
.ssa
);
857 load
->src
[1] = nir_src_for_ssa(input_base
);
858 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 2, 32, NULL
);
859 load
->num_components
= 2;
860 nir_intrinsic_set_align(load
, 8, 0);
861 nir_builder_instr_insert(&b
, &load
->instr
);
863 /* Pack the timestamp. */
864 nir_ssa_def
*timestamp
;
865 timestamp
= nir_pack_64_2x32(&b
, nir_vec2(&b
,
866 nir_channel(&b
, &load
->dest
.ssa
, 0),
867 nir_channel(&b
, &load
->dest
.ssa
, 1)));
869 /* Check if result is available. */
870 nir_ssa_def
*result_is_available
=
871 nir_i2b(&b
, nir_ine(&b
, timestamp
,
872 nir_imm_int64(&b
, TIMESTAMP_NOT_READY
)));
874 /* Only store result if available. */
875 nir_if
*available_if
= nir_if_create(b
.shader
);
876 available_if
->condition
= nir_src_for_ssa(result_is_available
);
877 nir_cf_node_insert(b
.cursor
, &available_if
->cf_node
);
879 b
.cursor
= nir_after_cf_list(&available_if
->then_list
);
881 nir_store_var(&b
, result
, timestamp
, 0x1);
882 nir_store_var(&b
, available
, nir_imm_true(&b
), 0x1);
884 b
.cursor
= nir_after_cf_node(&available_if
->cf_node
);
886 /* Determine if result is 64 or 32 bit. */
887 nir_ssa_def
*result_is_64bit
=
888 nir_test_flag(&b
, flags
, VK_QUERY_RESULT_64_BIT
);
889 nir_ssa_def
*result_size
=
890 nir_bcsel(&b
, result_is_64bit
, nir_imm_int(&b
, 8),
893 /* Store the result if complete or partial results have been requested. */
894 nir_if
*store_if
= nir_if_create(b
.shader
);
895 store_if
->condition
=
896 nir_src_for_ssa(nir_ior(&b
, nir_test_flag(&b
, flags
, VK_QUERY_RESULT_PARTIAL_BIT
),
897 nir_load_var(&b
, available
)));
898 nir_cf_node_insert(b
.cursor
, &store_if
->cf_node
);
900 b
.cursor
= nir_after_cf_list(&store_if
->then_list
);
903 nir_if
*store_64bit_if
= nir_if_create(b
.shader
);
904 store_64bit_if
->condition
= nir_src_for_ssa(result_is_64bit
);
905 nir_cf_node_insert(b
.cursor
, &store_64bit_if
->cf_node
);
907 b
.cursor
= nir_after_cf_list(&store_64bit_if
->then_list
);
909 nir_intrinsic_instr
*store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
910 store
->src
[0] = nir_src_for_ssa(nir_load_var(&b
, result
));
911 store
->src
[1] = nir_src_for_ssa(&dst_buf
->dest
.ssa
);
912 store
->src
[2] = nir_src_for_ssa(output_base
);
913 nir_intrinsic_set_write_mask(store
, 0x1);
914 nir_intrinsic_set_align(store
, 8, 0);
915 store
->num_components
= 1;
916 nir_builder_instr_insert(&b
, &store
->instr
);
918 b
.cursor
= nir_after_cf_list(&store_64bit_if
->else_list
);
920 store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
921 store
->src
[0] = nir_src_for_ssa(nir_u2u32(&b
, nir_load_var(&b
, result
)));
922 store
->src
[1] = nir_src_for_ssa(&dst_buf
->dest
.ssa
);
923 store
->src
[2] = nir_src_for_ssa(output_base
);
924 nir_intrinsic_set_write_mask(store
, 0x1);
925 nir_intrinsic_set_align(store
, 4, 0);
926 store
->num_components
= 1;
927 nir_builder_instr_insert(&b
, &store
->instr
);
929 b
.cursor
= nir_after_cf_node(&store_64bit_if
->cf_node
);
931 b
.cursor
= nir_after_cf_node(&store_if
->cf_node
);
933 radv_store_availability(&b
, flags
, &dst_buf
->dest
.ssa
,
934 nir_iadd(&b
, result_size
, output_base
),
935 nir_b2i32(&b
, nir_load_var(&b
, available
)));
940 static VkResult
radv_device_init_meta_query_state_internal(struct radv_device
*device
)
943 struct radv_shader_module occlusion_cs
= { .nir
= NULL
};
944 struct radv_shader_module pipeline_statistics_cs
= { .nir
= NULL
};
945 struct radv_shader_module tfb_cs
= { .nir
= NULL
};
946 struct radv_shader_module timestamp_cs
= { .nir
= NULL
};
948 mtx_lock(&device
->meta_state
.mtx
);
949 if (device
->meta_state
.query
.pipeline_statistics_query_pipeline
) {
950 mtx_unlock(&device
->meta_state
.mtx
);
953 occlusion_cs
.nir
= build_occlusion_query_shader(device
);
954 pipeline_statistics_cs
.nir
= build_pipeline_statistics_query_shader(device
);
955 tfb_cs
.nir
= build_tfb_query_shader(device
);
956 timestamp_cs
.nir
= build_timestamp_query_shader(device
);
958 VkDescriptorSetLayoutCreateInfo occlusion_ds_create_info
= {
959 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
960 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
962 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
965 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
,
966 .descriptorCount
= 1,
967 .stageFlags
= VK_SHADER_STAGE_COMPUTE_BIT
,
968 .pImmutableSamplers
= NULL
972 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
,
973 .descriptorCount
= 1,
974 .stageFlags
= VK_SHADER_STAGE_COMPUTE_BIT
,
975 .pImmutableSamplers
= NULL
980 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
981 &occlusion_ds_create_info
,
982 &device
->meta_state
.alloc
,
983 &device
->meta_state
.query
.ds_layout
);
984 if (result
!= VK_SUCCESS
)
987 VkPipelineLayoutCreateInfo occlusion_pl_create_info
= {
988 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
990 .pSetLayouts
= &device
->meta_state
.query
.ds_layout
,
991 .pushConstantRangeCount
= 1,
992 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_COMPUTE_BIT
, 0, 16},
995 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
996 &occlusion_pl_create_info
,
997 &device
->meta_state
.alloc
,
998 &device
->meta_state
.query
.p_layout
);
999 if (result
!= VK_SUCCESS
)
1002 VkPipelineShaderStageCreateInfo occlusion_pipeline_shader_stage
= {
1003 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1004 .stage
= VK_SHADER_STAGE_COMPUTE_BIT
,
1005 .module
= radv_shader_module_to_handle(&occlusion_cs
),
1007 .pSpecializationInfo
= NULL
,
1010 VkComputePipelineCreateInfo occlusion_vk_pipeline_info
= {
1011 .sType
= VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
,
1012 .stage
= occlusion_pipeline_shader_stage
,
1014 .layout
= device
->meta_state
.query
.p_layout
,
1017 result
= radv_CreateComputePipelines(radv_device_to_handle(device
),
1018 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1019 1, &occlusion_vk_pipeline_info
, NULL
,
1020 &device
->meta_state
.query
.occlusion_query_pipeline
);
1021 if (result
!= VK_SUCCESS
)
1024 VkPipelineShaderStageCreateInfo pipeline_statistics_pipeline_shader_stage
= {
1025 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1026 .stage
= VK_SHADER_STAGE_COMPUTE_BIT
,
1027 .module
= radv_shader_module_to_handle(&pipeline_statistics_cs
),
1029 .pSpecializationInfo
= NULL
,
1032 VkComputePipelineCreateInfo pipeline_statistics_vk_pipeline_info
= {
1033 .sType
= VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
,
1034 .stage
= pipeline_statistics_pipeline_shader_stage
,
1036 .layout
= device
->meta_state
.query
.p_layout
,
1039 result
= radv_CreateComputePipelines(radv_device_to_handle(device
),
1040 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1041 1, &pipeline_statistics_vk_pipeline_info
, NULL
,
1042 &device
->meta_state
.query
.pipeline_statistics_query_pipeline
);
1043 if (result
!= VK_SUCCESS
)
1046 VkPipelineShaderStageCreateInfo tfb_pipeline_shader_stage
= {
1047 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1048 .stage
= VK_SHADER_STAGE_COMPUTE_BIT
,
1049 .module
= radv_shader_module_to_handle(&tfb_cs
),
1051 .pSpecializationInfo
= NULL
,
1054 VkComputePipelineCreateInfo tfb_pipeline_info
= {
1055 .sType
= VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
,
1056 .stage
= tfb_pipeline_shader_stage
,
1058 .layout
= device
->meta_state
.query
.p_layout
,
1061 result
= radv_CreateComputePipelines(radv_device_to_handle(device
),
1062 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1063 1, &tfb_pipeline_info
, NULL
,
1064 &device
->meta_state
.query
.tfb_query_pipeline
);
1065 if (result
!= VK_SUCCESS
)
1068 VkPipelineShaderStageCreateInfo timestamp_pipeline_shader_stage
= {
1069 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1070 .stage
= VK_SHADER_STAGE_COMPUTE_BIT
,
1071 .module
= radv_shader_module_to_handle(×tamp_cs
),
1073 .pSpecializationInfo
= NULL
,
1076 VkComputePipelineCreateInfo timestamp_pipeline_info
= {
1077 .sType
= VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
,
1078 .stage
= timestamp_pipeline_shader_stage
,
1080 .layout
= device
->meta_state
.query
.p_layout
,
1083 result
= radv_CreateComputePipelines(radv_device_to_handle(device
),
1084 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1085 1, ×tamp_pipeline_info
, NULL
,
1086 &device
->meta_state
.query
.timestamp_query_pipeline
);
1089 if (result
!= VK_SUCCESS
)
1090 radv_device_finish_meta_query_state(device
);
1091 ralloc_free(occlusion_cs
.nir
);
1092 ralloc_free(pipeline_statistics_cs
.nir
);
1093 ralloc_free(tfb_cs
.nir
);
1094 ralloc_free(timestamp_cs
.nir
);
1095 mtx_unlock(&device
->meta_state
.mtx
);
1099 VkResult
radv_device_init_meta_query_state(struct radv_device
*device
, bool on_demand
)
1104 return radv_device_init_meta_query_state_internal(device
);
1107 void radv_device_finish_meta_query_state(struct radv_device
*device
)
1109 if (device
->meta_state
.query
.tfb_query_pipeline
)
1110 radv_DestroyPipeline(radv_device_to_handle(device
),
1111 device
->meta_state
.query
.tfb_query_pipeline
,
1112 &device
->meta_state
.alloc
);
1114 if (device
->meta_state
.query
.pipeline_statistics_query_pipeline
)
1115 radv_DestroyPipeline(radv_device_to_handle(device
),
1116 device
->meta_state
.query
.pipeline_statistics_query_pipeline
,
1117 &device
->meta_state
.alloc
);
1119 if (device
->meta_state
.query
.occlusion_query_pipeline
)
1120 radv_DestroyPipeline(radv_device_to_handle(device
),
1121 device
->meta_state
.query
.occlusion_query_pipeline
,
1122 &device
->meta_state
.alloc
);
1124 if (device
->meta_state
.query
.timestamp_query_pipeline
)
1125 radv_DestroyPipeline(radv_device_to_handle(device
),
1126 device
->meta_state
.query
.timestamp_query_pipeline
,
1127 &device
->meta_state
.alloc
);
1129 if (device
->meta_state
.query
.p_layout
)
1130 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
1131 device
->meta_state
.query
.p_layout
,
1132 &device
->meta_state
.alloc
);
1134 if (device
->meta_state
.query
.ds_layout
)
1135 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
1136 device
->meta_state
.query
.ds_layout
,
1137 &device
->meta_state
.alloc
);
1140 static void radv_query_shader(struct radv_cmd_buffer
*cmd_buffer
,
1141 VkPipeline
*pipeline
,
1142 struct radeon_winsys_bo
*src_bo
,
1143 struct radeon_winsys_bo
*dst_bo
,
1144 uint64_t src_offset
, uint64_t dst_offset
,
1145 uint32_t src_stride
, uint32_t dst_stride
,
1146 uint32_t count
, uint32_t flags
,
1147 uint32_t pipeline_stats_mask
, uint32_t avail_offset
)
1149 struct radv_device
*device
= cmd_buffer
->device
;
1150 struct radv_meta_saved_state saved_state
;
1151 bool old_predicating
;
1154 VkResult ret
= radv_device_init_meta_query_state_internal(device
);
1155 if (ret
!= VK_SUCCESS
) {
1156 cmd_buffer
->record_result
= ret
;
1161 radv_meta_save(&saved_state
, cmd_buffer
,
1162 RADV_META_SAVE_COMPUTE_PIPELINE
|
1163 RADV_META_SAVE_CONSTANTS
|
1164 RADV_META_SAVE_DESCRIPTORS
);
1166 /* VK_EXT_conditional_rendering says that copy commands should not be
1167 * affected by conditional rendering.
1169 old_predicating
= cmd_buffer
->state
.predicating
;
1170 cmd_buffer
->state
.predicating
= false;
1172 struct radv_buffer dst_buffer
= {
1174 .offset
= dst_offset
,
1175 .size
= dst_stride
* count
1178 struct radv_buffer src_buffer
= {
1180 .offset
= src_offset
,
1181 .size
= MAX2(src_stride
* count
, avail_offset
+ 4 * count
- src_offset
)
1184 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
1185 VK_PIPELINE_BIND_POINT_COMPUTE
, *pipeline
);
1187 radv_meta_push_descriptor_set(cmd_buffer
,
1188 VK_PIPELINE_BIND_POINT_COMPUTE
,
1189 device
->meta_state
.query
.p_layout
,
1191 2, /* descriptorWriteCount */
1192 (VkWriteDescriptorSet
[]) {
1194 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
1196 .dstArrayElement
= 0,
1197 .descriptorCount
= 1,
1198 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
,
1199 .pBufferInfo
= &(VkDescriptorBufferInfo
) {
1200 .buffer
= radv_buffer_to_handle(&dst_buffer
),
1202 .range
= VK_WHOLE_SIZE
1206 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
1208 .dstArrayElement
= 0,
1209 .descriptorCount
= 1,
1210 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
,
1211 .pBufferInfo
= &(VkDescriptorBufferInfo
) {
1212 .buffer
= radv_buffer_to_handle(&src_buffer
),
1214 .range
= VK_WHOLE_SIZE
1219 /* Encode the number of elements for easy access by the shader. */
1220 pipeline_stats_mask
&= 0x7ff;
1221 pipeline_stats_mask
|= util_bitcount(pipeline_stats_mask
) << 16;
1223 avail_offset
-= src_offset
;
1227 uint32_t dst_stride
;
1228 uint32_t pipeline_stats_mask
;
1229 uint32_t avail_offset
;
1230 } push_constants
= {
1233 pipeline_stats_mask
,
1237 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
1238 device
->meta_state
.query
.p_layout
,
1239 VK_SHADER_STAGE_COMPUTE_BIT
, 0, sizeof(push_constants
),
1242 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_INV_L2
|
1243 RADV_CMD_FLAG_INV_VCACHE
;
1245 if (flags
& VK_QUERY_RESULT_WAIT_BIT
)
1246 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
;
1248 radv_unaligned_dispatch(cmd_buffer
, count
, 1, 1);
1250 /* Restore conditional rendering. */
1251 cmd_buffer
->state
.predicating
= old_predicating
;
1253 radv_meta_restore(&saved_state
, cmd_buffer
);
1257 radv_query_pool_needs_gds(struct radv_device
*device
,
1258 struct radv_query_pool
*pool
)
1260 /* The number of primitives generated by geometry shader invocations is
1261 * only counted by the hardware if GS uses the legacy path. When NGG GS
1262 * is used, the hardware can't know the number of generated primitives
1263 * and we have to it manually inside the shader. To achieve that, the
1264 * driver does a plain GDS atomic to accumulate that value.
1265 * TODO: fix use of NGG GS and non-NGG GS inside the same begin/end
1268 return device
->physical_device
->use_ngg_gs
&&
1269 (pool
->pipeline_stats_mask
& VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT
);
1272 VkResult
radv_CreateQueryPool(
1274 const VkQueryPoolCreateInfo
* pCreateInfo
,
1275 const VkAllocationCallbacks
* pAllocator
,
1276 VkQueryPool
* pQueryPool
)
1278 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1279 struct radv_query_pool
*pool
= vk_alloc2(&device
->vk
.alloc
, pAllocator
,
1281 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1284 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1286 vk_object_base_init(&device
->vk
, &pool
->base
,
1287 VK_OBJECT_TYPE_QUERY_POOL
);
1289 switch(pCreateInfo
->queryType
) {
1290 case VK_QUERY_TYPE_OCCLUSION
:
1291 pool
->stride
= 16 * device
->physical_device
->rad_info
.num_render_backends
;
1293 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
1294 pool
->stride
= pipelinestat_block_size
* 2;
1296 case VK_QUERY_TYPE_TIMESTAMP
:
1299 case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT
:
1303 unreachable("creating unhandled query type");
1306 pool
->type
= pCreateInfo
->queryType
;
1307 pool
->pipeline_stats_mask
= pCreateInfo
->pipelineStatistics
;
1308 pool
->availability_offset
= pool
->stride
* pCreateInfo
->queryCount
;
1309 pool
->size
= pool
->availability_offset
;
1310 if (pCreateInfo
->queryType
== VK_QUERY_TYPE_PIPELINE_STATISTICS
)
1311 pool
->size
+= 4 * pCreateInfo
->queryCount
;
1313 pool
->bo
= device
->ws
->buffer_create(device
->ws
, pool
->size
,
1314 64, RADEON_DOMAIN_GTT
, RADEON_FLAG_NO_INTERPROCESS_SHARING
,
1315 RADV_BO_PRIORITY_QUERY_POOL
);
1318 vk_free2(&device
->vk
.alloc
, pAllocator
, pool
);
1319 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1322 pool
->ptr
= device
->ws
->buffer_map(pool
->bo
);
1325 device
->ws
->buffer_destroy(pool
->bo
);
1326 vk_free2(&device
->vk
.alloc
, pAllocator
, pool
);
1327 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1330 *pQueryPool
= radv_query_pool_to_handle(pool
);
1334 void radv_DestroyQueryPool(
1337 const VkAllocationCallbacks
* pAllocator
)
1339 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1340 RADV_FROM_HANDLE(radv_query_pool
, pool
, _pool
);
1345 device
->ws
->buffer_destroy(pool
->bo
);
1347 vk_object_base_finish(&pool
->base
);
1348 vk_free2(&device
->vk
.alloc
, pAllocator
, pool
);
1351 VkResult
radv_GetQueryPoolResults(
1353 VkQueryPool queryPool
,
1354 uint32_t firstQuery
,
1355 uint32_t queryCount
,
1358 VkDeviceSize stride
,
1359 VkQueryResultFlags flags
)
1361 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1362 RADV_FROM_HANDLE(radv_query_pool
, pool
, queryPool
);
1364 VkResult result
= VK_SUCCESS
;
1366 for(unsigned i
= 0; i
< queryCount
; ++i
, data
+= stride
) {
1368 unsigned query
= firstQuery
+ i
;
1369 char *src
= pool
->ptr
+ query
* pool
->stride
;
1372 switch (pool
->type
) {
1373 case VK_QUERY_TYPE_TIMESTAMP
: {
1374 volatile uint64_t const *src64
= (volatile uint64_t const *)src
;
1375 available
= *src64
!= TIMESTAMP_NOT_READY
;
1377 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
1378 while (*src64
== TIMESTAMP_NOT_READY
)
1383 if (!available
&& !(flags
& VK_QUERY_RESULT_PARTIAL_BIT
))
1384 result
= VK_NOT_READY
;
1386 if (flags
& VK_QUERY_RESULT_64_BIT
) {
1387 if (available
|| (flags
& VK_QUERY_RESULT_PARTIAL_BIT
))
1388 *(uint64_t*)dest
= *src64
;
1391 if (available
|| (flags
& VK_QUERY_RESULT_PARTIAL_BIT
))
1392 *(uint32_t*)dest
= *(volatile uint32_t*)src
;
1397 case VK_QUERY_TYPE_OCCLUSION
: {
1398 volatile uint64_t const *src64
= (volatile uint64_t const *)src
;
1399 uint32_t db_count
= device
->physical_device
->rad_info
.num_render_backends
;
1400 uint32_t enabled_rb_mask
= device
->physical_device
->rad_info
.enabled_rb_mask
;
1401 uint64_t sample_count
= 0;
1404 for (int i
= 0; i
< db_count
; ++i
) {
1405 uint64_t start
, end
;
1407 if (!(enabled_rb_mask
& (1 << i
)))
1411 start
= src64
[2 * i
];
1412 end
= src64
[2 * i
+ 1];
1413 } while ((!(start
& (1ull << 63)) || !(end
& (1ull << 63))) && (flags
& VK_QUERY_RESULT_WAIT_BIT
));
1415 if (!(start
& (1ull << 63)) || !(end
& (1ull << 63)))
1418 sample_count
+= end
- start
;
1422 if (!available
&& !(flags
& VK_QUERY_RESULT_PARTIAL_BIT
))
1423 result
= VK_NOT_READY
;
1425 if (flags
& VK_QUERY_RESULT_64_BIT
) {
1426 if (available
|| (flags
& VK_QUERY_RESULT_PARTIAL_BIT
))
1427 *(uint64_t*)dest
= sample_count
;
1430 if (available
|| (flags
& VK_QUERY_RESULT_PARTIAL_BIT
))
1431 *(uint32_t*)dest
= sample_count
;
1436 case VK_QUERY_TYPE_PIPELINE_STATISTICS
: {
1437 if (flags
& VK_QUERY_RESULT_WAIT_BIT
)
1438 while(!*(volatile uint32_t*)(pool
->ptr
+ pool
->availability_offset
+ 4 * query
))
1440 available
= *(volatile uint32_t*)(pool
->ptr
+ pool
->availability_offset
+ 4 * query
);
1442 if (!available
&& !(flags
& VK_QUERY_RESULT_PARTIAL_BIT
))
1443 result
= VK_NOT_READY
;
1445 const volatile uint64_t *start
= (uint64_t*)src
;
1446 const volatile uint64_t *stop
= (uint64_t*)(src
+ pipelinestat_block_size
);
1447 if (flags
& VK_QUERY_RESULT_64_BIT
) {
1448 uint64_t *dst
= (uint64_t*)dest
;
1449 dest
+= util_bitcount(pool
->pipeline_stats_mask
) * 8;
1450 for(int i
= 0; i
< 11; ++i
) {
1451 if(pool
->pipeline_stats_mask
& (1u << i
)) {
1452 if (available
|| (flags
& VK_QUERY_RESULT_PARTIAL_BIT
))
1453 *dst
= stop
[pipeline_statistics_indices
[i
]] -
1454 start
[pipeline_statistics_indices
[i
]];
1460 uint32_t *dst
= (uint32_t*)dest
;
1461 dest
+= util_bitcount(pool
->pipeline_stats_mask
) * 4;
1462 for(int i
= 0; i
< 11; ++i
) {
1463 if(pool
->pipeline_stats_mask
& (1u << i
)) {
1464 if (available
|| (flags
& VK_QUERY_RESULT_PARTIAL_BIT
))
1465 *dst
= stop
[pipeline_statistics_indices
[i
]] -
1466 start
[pipeline_statistics_indices
[i
]];
1473 case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT
: {
1474 volatile uint64_t const *src64
= (volatile uint64_t const *)src
;
1475 uint64_t num_primitives_written
;
1476 uint64_t primitive_storage_needed
;
1478 /* SAMPLE_STREAMOUTSTATS stores this structure:
1480 * u64 NumPrimitivesWritten;
1481 * u64 PrimitiveStorageNeeded;
1485 for (int j
= 0; j
< 4; j
++) {
1486 if (!(src64
[j
] & 0x8000000000000000UL
))
1490 if (!available
&& !(flags
& VK_QUERY_RESULT_PARTIAL_BIT
))
1491 result
= VK_NOT_READY
;
1493 num_primitives_written
= src64
[3] - src64
[1];
1494 primitive_storage_needed
= src64
[2] - src64
[0];
1496 if (flags
& VK_QUERY_RESULT_64_BIT
) {
1497 if (available
|| (flags
& VK_QUERY_RESULT_PARTIAL_BIT
))
1498 *(uint64_t *)dest
= num_primitives_written
;
1500 if (available
|| (flags
& VK_QUERY_RESULT_PARTIAL_BIT
))
1501 *(uint64_t *)dest
= primitive_storage_needed
;
1504 if (available
|| (flags
& VK_QUERY_RESULT_PARTIAL_BIT
))
1505 *(uint32_t *)dest
= num_primitives_written
;
1507 if (available
|| (flags
& VK_QUERY_RESULT_PARTIAL_BIT
))
1508 *(uint32_t *)dest
= primitive_storage_needed
;
1514 unreachable("trying to get results of unhandled query type");
1517 if (flags
& VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
) {
1518 if (flags
& VK_QUERY_RESULT_64_BIT
) {
1519 *(uint64_t*)dest
= available
;
1521 *(uint32_t*)dest
= available
;
1529 static void emit_query_flush(struct radv_cmd_buffer
*cmd_buffer
,
1530 struct radv_query_pool
*pool
)
1532 if (cmd_buffer
->pending_reset_query
) {
1533 if (pool
->size
>= RADV_BUFFER_OPS_CS_THRESHOLD
) {
1534 /* Only need to flush caches if the query pool size is
1535 * large enough to be resetted using the compute shader
1536 * path. Small pools don't need any cache flushes
1537 * because we use a CP dma clear.
1539 si_emit_cache_flush(cmd_buffer
);
1544 void radv_CmdCopyQueryPoolResults(
1545 VkCommandBuffer commandBuffer
,
1546 VkQueryPool queryPool
,
1547 uint32_t firstQuery
,
1548 uint32_t queryCount
,
1550 VkDeviceSize dstOffset
,
1551 VkDeviceSize stride
,
1552 VkQueryResultFlags flags
)
1554 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1555 RADV_FROM_HANDLE(radv_query_pool
, pool
, queryPool
);
1556 RADV_FROM_HANDLE(radv_buffer
, dst_buffer
, dstBuffer
);
1557 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1558 uint64_t va
= radv_buffer_get_va(pool
->bo
);
1559 uint64_t dest_va
= radv_buffer_get_va(dst_buffer
->bo
);
1560 dest_va
+= dst_buffer
->offset
+ dstOffset
;
1562 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, pool
->bo
);
1563 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, dst_buffer
->bo
);
1565 /* From the Vulkan spec 1.1.108:
1567 * "vkCmdCopyQueryPoolResults is guaranteed to see the effect of
1568 * previous uses of vkCmdResetQueryPool in the same queue, without any
1569 * additional synchronization."
1571 * So, we have to flush the caches if the compute shader path was used.
1573 emit_query_flush(cmd_buffer
, pool
);
1575 switch (pool
->type
) {
1576 case VK_QUERY_TYPE_OCCLUSION
:
1577 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
1578 for(unsigned i
= 0; i
< queryCount
; ++i
, dest_va
+= stride
) {
1579 unsigned query
= firstQuery
+ i
;
1580 uint64_t src_va
= va
+ query
* pool
->stride
+ pool
->stride
- 4;
1582 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
1584 /* Waits on the upper word of the last DB entry */
1585 radv_cp_wait_mem(cs
, WAIT_REG_MEM_GREATER_OR_EQUAL
,
1586 src_va
, 0x80000000, 0xffffffff);
1589 radv_query_shader(cmd_buffer
, &cmd_buffer
->device
->meta_state
.query
.occlusion_query_pipeline
,
1590 pool
->bo
, dst_buffer
->bo
, firstQuery
* pool
->stride
,
1591 dst_buffer
->offset
+ dstOffset
,
1592 pool
->stride
, stride
,
1593 queryCount
, flags
, 0, 0);
1595 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
1596 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
1597 for(unsigned i
= 0; i
< queryCount
; ++i
, dest_va
+= stride
) {
1598 unsigned query
= firstQuery
+ i
;
1600 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
1602 uint64_t avail_va
= va
+ pool
->availability_offset
+ 4 * query
;
1604 /* This waits on the ME. All copies below are done on the ME */
1605 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
,
1606 avail_va
, 1, 0xffffffff);
1609 radv_query_shader(cmd_buffer
, &cmd_buffer
->device
->meta_state
.query
.pipeline_statistics_query_pipeline
,
1610 pool
->bo
, dst_buffer
->bo
, firstQuery
* pool
->stride
,
1611 dst_buffer
->offset
+ dstOffset
,
1612 pool
->stride
, stride
, queryCount
, flags
,
1613 pool
->pipeline_stats_mask
,
1614 pool
->availability_offset
+ 4 * firstQuery
);
1616 case VK_QUERY_TYPE_TIMESTAMP
:
1617 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
1618 for(unsigned i
= 0; i
< queryCount
; ++i
, dest_va
+= stride
) {
1619 unsigned query
= firstQuery
+ i
;
1620 uint64_t local_src_va
= va
+ query
* pool
->stride
;
1622 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
1624 /* Wait on the high 32 bits of the timestamp in
1625 * case the low part is 0xffffffff.
1627 radv_cp_wait_mem(cs
, WAIT_REG_MEM_NOT_EQUAL
,
1629 TIMESTAMP_NOT_READY
>> 32,
1634 radv_query_shader(cmd_buffer
, &cmd_buffer
->device
->meta_state
.query
.timestamp_query_pipeline
,
1635 pool
->bo
, dst_buffer
->bo
,
1636 firstQuery
* pool
->stride
,
1637 dst_buffer
->offset
+ dstOffset
,
1638 pool
->stride
, stride
,
1639 queryCount
, flags
, 0, 0);
1641 case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT
:
1642 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
1643 for(unsigned i
= 0; i
< queryCount
; i
++) {
1644 unsigned query
= firstQuery
+ i
;
1645 uint64_t src_va
= va
+ query
* pool
->stride
;
1647 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7 * 4);
1649 /* Wait on the upper word of all results. */
1650 for (unsigned j
= 0; j
< 4; j
++, src_va
+= 8) {
1651 radv_cp_wait_mem(cs
, WAIT_REG_MEM_GREATER_OR_EQUAL
,
1652 src_va
+ 4, 0x80000000,
1658 radv_query_shader(cmd_buffer
, &cmd_buffer
->device
->meta_state
.query
.tfb_query_pipeline
,
1659 pool
->bo
, dst_buffer
->bo
,
1660 firstQuery
* pool
->stride
,
1661 dst_buffer
->offset
+ dstOffset
,
1662 pool
->stride
, stride
,
1663 queryCount
, flags
, 0, 0);
1666 unreachable("trying to get results of unhandled query type");
1671 void radv_CmdResetQueryPool(
1672 VkCommandBuffer commandBuffer
,
1673 VkQueryPool queryPool
,
1674 uint32_t firstQuery
,
1675 uint32_t queryCount
)
1677 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1678 RADV_FROM_HANDLE(radv_query_pool
, pool
, queryPool
);
1679 uint32_t value
= pool
->type
== VK_QUERY_TYPE_TIMESTAMP
1680 ? (uint32_t)TIMESTAMP_NOT_READY
: 0;
1681 uint32_t flush_bits
= 0;
1683 /* Make sure to sync all previous work if the given command buffer has
1684 * pending active queries. Otherwise the GPU might write queries data
1685 * after the reset operation.
1687 cmd_buffer
->state
.flush_bits
|= cmd_buffer
->active_query_flush_bits
;
1689 flush_bits
|= radv_fill_buffer(cmd_buffer
, pool
->bo
,
1690 firstQuery
* pool
->stride
,
1691 queryCount
* pool
->stride
, value
);
1693 if (pool
->type
== VK_QUERY_TYPE_PIPELINE_STATISTICS
) {
1694 flush_bits
|= radv_fill_buffer(cmd_buffer
, pool
->bo
,
1695 pool
->availability_offset
+ firstQuery
* 4,
1700 /* Only need to flush caches for the compute shader path. */
1701 cmd_buffer
->pending_reset_query
= true;
1702 cmd_buffer
->state
.flush_bits
|= flush_bits
;
1706 void radv_ResetQueryPool(
1708 VkQueryPool queryPool
,
1709 uint32_t firstQuery
,
1710 uint32_t queryCount
)
1712 RADV_FROM_HANDLE(radv_query_pool
, pool
, queryPool
);
1714 uint32_t value
= pool
->type
== VK_QUERY_TYPE_TIMESTAMP
1715 ? (uint32_t)TIMESTAMP_NOT_READY
: 0;
1716 uint32_t *data
= (uint32_t*)(pool
->ptr
+ firstQuery
* pool
->stride
);
1717 uint32_t *data_end
= (uint32_t*)(pool
->ptr
+ (firstQuery
+ queryCount
) * pool
->stride
);
1719 for(uint32_t *p
= data
; p
!= data_end
; ++p
)
1722 if (pool
->type
== VK_QUERY_TYPE_PIPELINE_STATISTICS
) {
1723 memset(pool
->ptr
+ pool
->availability_offset
+ firstQuery
* 4,
1728 static unsigned event_type_for_stream(unsigned stream
)
1732 case 0: return V_028A90_SAMPLE_STREAMOUTSTATS
;
1733 case 1: return V_028A90_SAMPLE_STREAMOUTSTATS1
;
1734 case 2: return V_028A90_SAMPLE_STREAMOUTSTATS2
;
1735 case 3: return V_028A90_SAMPLE_STREAMOUTSTATS3
;
1739 static void emit_begin_query(struct radv_cmd_buffer
*cmd_buffer
,
1740 struct radv_query_pool
*pool
,
1742 VkQueryType query_type
,
1743 VkQueryControlFlags flags
,
1746 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1747 switch (query_type
) {
1748 case VK_QUERY_TYPE_OCCLUSION
:
1749 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
1751 ++cmd_buffer
->state
.active_occlusion_queries
;
1752 if (cmd_buffer
->state
.active_occlusion_queries
== 1) {
1753 if (flags
& VK_QUERY_CONTROL_PRECISE_BIT
) {
1754 /* This is the first occlusion query, enable
1755 * the hint if the precision bit is set.
1757 cmd_buffer
->state
.perfect_occlusion_queries_enabled
= true;
1760 radv_set_db_count_control(cmd_buffer
);
1762 if ((flags
& VK_QUERY_CONTROL_PRECISE_BIT
) &&
1763 !cmd_buffer
->state
.perfect_occlusion_queries_enabled
) {
1764 /* This is not the first query, but this one
1765 * needs to enable precision, DB_COUNT_CONTROL
1766 * has to be updated accordingly.
1768 cmd_buffer
->state
.perfect_occlusion_queries_enabled
= true;
1770 radv_set_db_count_control(cmd_buffer
);
1774 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
1775 radeon_emit(cs
, EVENT_TYPE(V_028A90_ZPASS_DONE
) | EVENT_INDEX(1));
1776 radeon_emit(cs
, va
);
1777 radeon_emit(cs
, va
>> 32);
1779 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
1780 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4);
1782 ++cmd_buffer
->state
.active_pipeline_queries
;
1783 if (cmd_buffer
->state
.active_pipeline_queries
== 1) {
1784 cmd_buffer
->state
.flush_bits
&= ~RADV_CMD_FLAG_STOP_PIPELINE_STATS
;
1785 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_START_PIPELINE_STATS
;
1788 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
1789 radeon_emit(cs
, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT
) | EVENT_INDEX(2));
1790 radeon_emit(cs
, va
);
1791 radeon_emit(cs
, va
>> 32);
1793 if (radv_query_pool_needs_gds(cmd_buffer
->device
, pool
)) {
1794 int idx
= radv_get_pipeline_statistics_index(VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT
);
1796 /* Make sure GDS is idle before copying the value. */
1797 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
1798 RADV_CMD_FLAG_INV_L2
;
1799 si_emit_cache_flush(cmd_buffer
);
1803 si_cs_emit_write_event_eop(cs
,
1804 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
1805 radv_cmd_buffer_uses_mec(cmd_buffer
),
1806 V_028A90_PS_DONE
, 0,
1809 va
, EOP_DATA_GDS(0, 1), 0);
1811 /* Record that the command buffer needs GDS. */
1812 cmd_buffer
->gds_needed
= true;
1814 cmd_buffer
->state
.active_pipeline_gds_queries
++;
1817 case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT
:
1818 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4);
1820 assert(index
< MAX_SO_STREAMS
);
1822 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
1823 radeon_emit(cs
, EVENT_TYPE(event_type_for_stream(index
)) | EVENT_INDEX(3));
1824 radeon_emit(cs
, va
);
1825 radeon_emit(cs
, va
>> 32);
1828 unreachable("beginning unhandled query type");
1833 static void emit_end_query(struct radv_cmd_buffer
*cmd_buffer
,
1834 struct radv_query_pool
*pool
,
1835 uint64_t va
, uint64_t avail_va
,
1836 VkQueryType query_type
, uint32_t index
)
1838 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1839 switch (query_type
) {
1840 case VK_QUERY_TYPE_OCCLUSION
:
1841 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 14);
1843 cmd_buffer
->state
.active_occlusion_queries
--;
1844 if (cmd_buffer
->state
.active_occlusion_queries
== 0) {
1845 radv_set_db_count_control(cmd_buffer
);
1847 /* Reset the perfect occlusion queries hint now that no
1848 * queries are active.
1850 cmd_buffer
->state
.perfect_occlusion_queries_enabled
= false;
1853 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
1854 radeon_emit(cs
, EVENT_TYPE(V_028A90_ZPASS_DONE
) | EVENT_INDEX(1));
1855 radeon_emit(cs
, va
+ 8);
1856 radeon_emit(cs
, (va
+ 8) >> 32);
1859 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
1860 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 16);
1862 cmd_buffer
->state
.active_pipeline_queries
--;
1863 if (cmd_buffer
->state
.active_pipeline_queries
== 0) {
1864 cmd_buffer
->state
.flush_bits
&= ~RADV_CMD_FLAG_START_PIPELINE_STATS
;
1865 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_STOP_PIPELINE_STATS
;
1867 va
+= pipelinestat_block_size
;
1869 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
1870 radeon_emit(cs
, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT
) | EVENT_INDEX(2));
1871 radeon_emit(cs
, va
);
1872 radeon_emit(cs
, va
>> 32);
1874 si_cs_emit_write_event_eop(cs
,
1875 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
1876 radv_cmd_buffer_uses_mec(cmd_buffer
),
1877 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
1879 EOP_DATA_SEL_VALUE_32BIT
,
1881 cmd_buffer
->gfx9_eop_bug_va
);
1883 if (radv_query_pool_needs_gds(cmd_buffer
->device
, pool
)) {
1884 int idx
= radv_get_pipeline_statistics_index(VK_QUERY_PIPELINE_STATISTIC_GEOMETRY_SHADER_PRIMITIVES_BIT
);
1886 /* Make sure GDS is idle before copying the value. */
1887 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
1888 RADV_CMD_FLAG_INV_L2
;
1889 si_emit_cache_flush(cmd_buffer
);
1893 si_cs_emit_write_event_eop(cs
,
1894 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
1895 radv_cmd_buffer_uses_mec(cmd_buffer
),
1896 V_028A90_PS_DONE
, 0,
1899 va
, EOP_DATA_GDS(0, 1), 0);
1901 cmd_buffer
->state
.active_pipeline_gds_queries
--;
1904 case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT
:
1905 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4);
1907 assert(index
< MAX_SO_STREAMS
);
1909 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
1910 radeon_emit(cs
, EVENT_TYPE(event_type_for_stream(index
)) | EVENT_INDEX(3));
1911 radeon_emit(cs
, (va
+ 16));
1912 radeon_emit(cs
, (va
+ 16) >> 32);
1915 unreachable("ending unhandled query type");
1918 cmd_buffer
->active_query_flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
1919 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
1920 RADV_CMD_FLAG_INV_L2
|
1921 RADV_CMD_FLAG_INV_VCACHE
;
1922 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1923 cmd_buffer
->active_query_flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
1924 RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
1928 void radv_CmdBeginQueryIndexedEXT(
1929 VkCommandBuffer commandBuffer
,
1930 VkQueryPool queryPool
,
1932 VkQueryControlFlags flags
,
1935 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1936 RADV_FROM_HANDLE(radv_query_pool
, pool
, queryPool
);
1937 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1938 uint64_t va
= radv_buffer_get_va(pool
->bo
);
1940 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, pool
->bo
);
1942 emit_query_flush(cmd_buffer
, pool
);
1944 va
+= pool
->stride
* query
;
1946 emit_begin_query(cmd_buffer
, pool
, va
, pool
->type
, flags
, index
);
1949 void radv_CmdBeginQuery(
1950 VkCommandBuffer commandBuffer
,
1951 VkQueryPool queryPool
,
1953 VkQueryControlFlags flags
)
1955 radv_CmdBeginQueryIndexedEXT(commandBuffer
, queryPool
, query
, flags
, 0);
1958 void radv_CmdEndQueryIndexedEXT(
1959 VkCommandBuffer commandBuffer
,
1960 VkQueryPool queryPool
,
1964 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1965 RADV_FROM_HANDLE(radv_query_pool
, pool
, queryPool
);
1966 uint64_t va
= radv_buffer_get_va(pool
->bo
);
1967 uint64_t avail_va
= va
+ pool
->availability_offset
+ 4 * query
;
1968 va
+= pool
->stride
* query
;
1970 /* Do not need to add the pool BO to the list because the query must
1971 * currently be active, which means the BO is already in the list.
1973 emit_end_query(cmd_buffer
, pool
, va
, avail_va
, pool
->type
, index
);
1976 * For multiview we have to emit a query for each bit in the mask,
1977 * however the first query we emit will get the totals for all the
1978 * operations, so we don't want to get a real value in the other
1979 * queries. This emits a fake begin/end sequence so the waiting
1980 * code gets a completed query value and doesn't hang, but the
1983 if (cmd_buffer
->state
.subpass
&& cmd_buffer
->state
.subpass
->view_mask
) {
1984 uint64_t avail_va
= va
+ pool
->availability_offset
+ 4 * query
;
1987 for (unsigned i
= 1; i
< util_bitcount(cmd_buffer
->state
.subpass
->view_mask
); i
++) {
1990 emit_begin_query(cmd_buffer
, pool
, va
, pool
->type
, 0, 0);
1991 emit_end_query(cmd_buffer
, pool
, va
, avail_va
, pool
->type
, 0);
1996 void radv_CmdEndQuery(
1997 VkCommandBuffer commandBuffer
,
1998 VkQueryPool queryPool
,
2001 radv_CmdEndQueryIndexedEXT(commandBuffer
, queryPool
, query
, 0);
2004 void radv_CmdWriteTimestamp(
2005 VkCommandBuffer commandBuffer
,
2006 VkPipelineStageFlagBits pipelineStage
,
2007 VkQueryPool queryPool
,
2010 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2011 RADV_FROM_HANDLE(radv_query_pool
, pool
, queryPool
);
2012 bool mec
= radv_cmd_buffer_uses_mec(cmd_buffer
);
2013 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
2014 uint64_t va
= radv_buffer_get_va(pool
->bo
);
2015 uint64_t query_va
= va
+ pool
->stride
* query
;
2017 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, pool
->bo
);
2019 emit_query_flush(cmd_buffer
, pool
);
2021 int num_queries
= 1;
2022 if (cmd_buffer
->state
.subpass
&& cmd_buffer
->state
.subpass
->view_mask
)
2023 num_queries
= util_bitcount(cmd_buffer
->state
.subpass
->view_mask
);
2025 ASSERTED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 28 * num_queries
);
2027 for (unsigned i
= 0; i
< num_queries
; i
++) {
2028 switch(pipelineStage
) {
2029 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
:
2030 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
2031 radeon_emit(cs
, COPY_DATA_COUNT_SEL
| COPY_DATA_WR_CONFIRM
|
2032 COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP
) |
2033 COPY_DATA_DST_SEL(V_370_MEM
));
2036 radeon_emit(cs
, query_va
);
2037 radeon_emit(cs
, query_va
>> 32);
2040 si_cs_emit_write_event_eop(cs
,
2041 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
2043 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
2045 EOP_DATA_SEL_TIMESTAMP
,
2047 cmd_buffer
->gfx9_eop_bug_va
);
2050 query_va
+= pool
->stride
;
2053 cmd_buffer
->active_query_flush_bits
|= RADV_CMD_FLAG_PS_PARTIAL_FLUSH
|
2054 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
2055 RADV_CMD_FLAG_INV_L2
|
2056 RADV_CMD_FLAG_INV_VCACHE
;
2057 if (cmd_buffer
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2058 cmd_buffer
->active_query_flush_bits
|= RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
2059 RADV_CMD_FLAG_FLUSH_AND_INV_DB
;
2062 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);