2 * Copyrigh 2016 Red Hat Inc.
4 * Copyright © 2015 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
32 #include "nir/nir_builder.h"
33 #include "radv_meta.h"
34 #include "radv_private.h"
38 #define TIMESTAMP_NOT_READY UINT64_MAX
40 static const int pipelinestat_block_size
= 11 * 8;
41 static const unsigned pipeline_statistics_indices
[] = {7, 6, 3, 4, 5, 2, 1, 0, 8, 9, 10};
43 static unsigned get_max_db(struct radv_device
*device
)
45 unsigned num_db
= device
->physical_device
->rad_info
.num_render_backends
;
46 MAYBE_UNUSED
unsigned rb_mask
= device
->physical_device
->rad_info
.enabled_rb_mask
;
48 /* Otherwise we need to change the query reset procedure */
49 assert(rb_mask
== ((1ull << num_db
) - 1));
55 static nir_ssa_def
*nir_test_flag(nir_builder
*b
, nir_ssa_def
*flags
, uint32_t flag
)
57 return nir_i2b(b
, nir_iand(b
, flags
, nir_imm_int(b
, flag
)));
60 static void radv_break_on_count(nir_builder
*b
, nir_variable
*var
, nir_ssa_def
*count
)
62 nir_ssa_def
*counter
= nir_load_var(b
, var
);
64 nir_if
*if_stmt
= nir_if_create(b
->shader
);
65 if_stmt
->condition
= nir_src_for_ssa(nir_uge(b
, counter
, count
));
66 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
68 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
70 nir_jump_instr
*instr
= nir_jump_instr_create(b
->shader
, nir_jump_break
);
71 nir_builder_instr_insert(b
, &instr
->instr
);
73 b
->cursor
= nir_after_cf_node(&if_stmt
->cf_node
);
74 counter
= nir_iadd(b
, counter
, nir_imm_int(b
, 1));
75 nir_store_var(b
, var
, counter
, 0x1);
78 static struct nir_ssa_def
*
79 radv_load_push_int(nir_builder
*b
, unsigned offset
, const char *name
)
81 nir_intrinsic_instr
*flags
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_push_constant
);
82 nir_intrinsic_set_base(flags
, 0);
83 nir_intrinsic_set_range(flags
, 16);
84 flags
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, offset
));
85 flags
->num_components
= 1;
86 nir_ssa_dest_init(&flags
->instr
, &flags
->dest
, 1, 32, name
);
87 nir_builder_instr_insert(b
, &flags
->instr
);
88 return &flags
->dest
.ssa
;
92 build_occlusion_query_shader(struct radv_device
*device
) {
93 /* the shader this builds is roughly
97 * uint32_t dst_stride;
100 * uint32_t src_stride = 16 * db_count;
102 * location(binding = 0) buffer dst_buf;
103 * location(binding = 1) buffer src_buf;
106 * uint64_t result = 0;
107 * uint64_t src_offset = src_stride * global_id.x;
108 * uint64_t dst_offset = dst_stride * global_id.x;
109 * bool available = true;
110 * for (int i = 0; i < db_count; ++i) {
111 * uint64_t start = src_buf[src_offset + 16 * i];
112 * uint64_t end = src_buf[src_offset + 16 * i + 8];
113 * if ((start & (1ull << 63)) && (end & (1ull << 63)))
114 * result += end - start;
118 * uint32_t elem_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;
119 * if ((flags & VK_QUERY_RESULT_PARTIAL_BIT) || available) {
120 * if (flags & VK_QUERY_RESULT_64_BIT)
121 * dst_buf[dst_offset] = result;
123 * dst_buf[dst_offset] = (uint32_t)result.
125 * if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
126 * dst_buf[dst_offset + elem_size] = available;
131 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_COMPUTE
, NULL
);
132 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "occlusion_query");
133 b
.shader
->info
.cs
.local_size
[0] = 64;
134 b
.shader
->info
.cs
.local_size
[1] = 1;
135 b
.shader
->info
.cs
.local_size
[2] = 1;
137 nir_variable
*result
= nir_local_variable_create(b
.impl
, glsl_uint64_t_type(), "result");
138 nir_variable
*outer_counter
= nir_local_variable_create(b
.impl
, glsl_int_type(), "outer_counter");
139 nir_variable
*start
= nir_local_variable_create(b
.impl
, glsl_uint64_t_type(), "start");
140 nir_variable
*end
= nir_local_variable_create(b
.impl
, glsl_uint64_t_type(), "end");
141 nir_variable
*available
= nir_local_variable_create(b
.impl
, glsl_bool_type(), "available");
142 unsigned db_count
= get_max_db(device
);
144 nir_ssa_def
*flags
= radv_load_push_int(&b
, 0, "flags");
146 nir_intrinsic_instr
*dst_buf
= nir_intrinsic_instr_create(b
.shader
,
147 nir_intrinsic_vulkan_resource_index
);
148 dst_buf
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
149 nir_intrinsic_set_desc_set(dst_buf
, 0);
150 nir_intrinsic_set_binding(dst_buf
, 0);
151 nir_ssa_dest_init(&dst_buf
->instr
, &dst_buf
->dest
, 1, 32, NULL
);
152 nir_builder_instr_insert(&b
, &dst_buf
->instr
);
154 nir_intrinsic_instr
*src_buf
= nir_intrinsic_instr_create(b
.shader
,
155 nir_intrinsic_vulkan_resource_index
);
156 src_buf
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
157 nir_intrinsic_set_desc_set(src_buf
, 0);
158 nir_intrinsic_set_binding(src_buf
, 1);
159 nir_ssa_dest_init(&src_buf
->instr
, &src_buf
->dest
, 1, 32, NULL
);
160 nir_builder_instr_insert(&b
, &src_buf
->instr
);
162 nir_ssa_def
*invoc_id
= nir_load_local_invocation_id(&b
);
163 nir_ssa_def
*wg_id
= nir_load_work_group_id(&b
);
164 nir_ssa_def
*block_size
= nir_imm_ivec4(&b
,
165 b
.shader
->info
.cs
.local_size
[0],
166 b
.shader
->info
.cs
.local_size
[1],
167 b
.shader
->info
.cs
.local_size
[2], 0);
168 nir_ssa_def
*global_id
= nir_iadd(&b
, nir_imul(&b
, wg_id
, block_size
), invoc_id
);
169 global_id
= nir_channel(&b
, global_id
, 0); // We only care about x here.
171 nir_ssa_def
*input_stride
= nir_imm_int(&b
, db_count
* 16);
172 nir_ssa_def
*input_base
= nir_imul(&b
, input_stride
, global_id
);
173 nir_ssa_def
*output_stride
= radv_load_push_int(&b
, 4, "output_stride");
174 nir_ssa_def
*output_base
= nir_imul(&b
, output_stride
, global_id
);
177 nir_store_var(&b
, result
, nir_imm_int64(&b
, 0), 0x1);
178 nir_store_var(&b
, outer_counter
, nir_imm_int(&b
, 0), 0x1);
179 nir_store_var(&b
, available
, nir_imm_true(&b
), 0x1);
181 nir_loop
*outer_loop
= nir_loop_create(b
.shader
);
182 nir_builder_cf_insert(&b
, &outer_loop
->cf_node
);
183 b
.cursor
= nir_after_cf_list(&outer_loop
->body
);
185 nir_ssa_def
*current_outer_count
= nir_load_var(&b
, outer_counter
);
186 radv_break_on_count(&b
, outer_counter
, nir_imm_int(&b
, db_count
));
188 nir_ssa_def
*load_offset
= nir_imul(&b
, current_outer_count
, nir_imm_int(&b
, 16));
189 load_offset
= nir_iadd(&b
, input_base
, load_offset
);
191 nir_intrinsic_instr
*load
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ssbo
);
192 load
->src
[0] = nir_src_for_ssa(&src_buf
->dest
.ssa
);
193 load
->src
[1] = nir_src_for_ssa(load_offset
);
194 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 2, 64, NULL
);
195 load
->num_components
= 2;
196 nir_builder_instr_insert(&b
, &load
->instr
);
198 nir_store_var(&b
, start
, nir_channel(&b
, &load
->dest
.ssa
, 0), 0x1);
199 nir_store_var(&b
, end
, nir_channel(&b
, &load
->dest
.ssa
, 1), 0x1);
201 nir_ssa_def
*start_done
= nir_ilt(&b
, nir_load_var(&b
, start
), nir_imm_int64(&b
, 0));
202 nir_ssa_def
*end_done
= nir_ilt(&b
, nir_load_var(&b
, end
), nir_imm_int64(&b
, 0));
204 nir_if
*update_if
= nir_if_create(b
.shader
);
205 update_if
->condition
= nir_src_for_ssa(nir_iand(&b
, start_done
, end_done
));
206 nir_cf_node_insert(b
.cursor
, &update_if
->cf_node
);
208 b
.cursor
= nir_after_cf_list(&update_if
->then_list
);
210 nir_store_var(&b
, result
,
211 nir_iadd(&b
, nir_load_var(&b
, result
),
212 nir_isub(&b
, nir_load_var(&b
, end
),
213 nir_load_var(&b
, start
))), 0x1);
215 b
.cursor
= nir_after_cf_list(&update_if
->else_list
);
217 nir_store_var(&b
, available
, nir_imm_false(&b
), 0x1);
219 b
.cursor
= nir_after_cf_node(&outer_loop
->cf_node
);
221 /* Store the result if complete or if partial results have been requested. */
223 nir_ssa_def
*result_is_64bit
= nir_test_flag(&b
, flags
, VK_QUERY_RESULT_64_BIT
);
224 nir_ssa_def
*result_size
= nir_bcsel(&b
, result_is_64bit
, nir_imm_int(&b
, 8), nir_imm_int(&b
, 4));
226 nir_if
*store_if
= nir_if_create(b
.shader
);
227 store_if
->condition
= nir_src_for_ssa(nir_ior(&b
, nir_test_flag(&b
, flags
, VK_QUERY_RESULT_PARTIAL_BIT
), nir_load_var(&b
, available
)));
228 nir_cf_node_insert(b
.cursor
, &store_if
->cf_node
);
230 b
.cursor
= nir_after_cf_list(&store_if
->then_list
);
232 nir_if
*store_64bit_if
= nir_if_create(b
.shader
);
233 store_64bit_if
->condition
= nir_src_for_ssa(result_is_64bit
);
234 nir_cf_node_insert(b
.cursor
, &store_64bit_if
->cf_node
);
236 b
.cursor
= nir_after_cf_list(&store_64bit_if
->then_list
);
238 nir_intrinsic_instr
*store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
239 store
->src
[0] = nir_src_for_ssa(nir_load_var(&b
, result
));
240 store
->src
[1] = nir_src_for_ssa(&dst_buf
->dest
.ssa
);
241 store
->src
[2] = nir_src_for_ssa(output_base
);
242 nir_intrinsic_set_write_mask(store
, 0x1);
243 store
->num_components
= 1;
244 nir_builder_instr_insert(&b
, &store
->instr
);
246 b
.cursor
= nir_after_cf_list(&store_64bit_if
->else_list
);
248 store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
249 store
->src
[0] = nir_src_for_ssa(nir_u2u32(&b
, nir_load_var(&b
, result
)));
250 store
->src
[1] = nir_src_for_ssa(&dst_buf
->dest
.ssa
);
251 store
->src
[2] = nir_src_for_ssa(output_base
);
252 nir_intrinsic_set_write_mask(store
, 0x1);
253 store
->num_components
= 1;
254 nir_builder_instr_insert(&b
, &store
->instr
);
256 b
.cursor
= nir_after_cf_node(&store_if
->cf_node
);
258 /* Store the availability bit if requested. */
260 nir_if
*availability_if
= nir_if_create(b
.shader
);
261 availability_if
->condition
= nir_src_for_ssa(nir_test_flag(&b
, flags
, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
));
262 nir_cf_node_insert(b
.cursor
, &availability_if
->cf_node
);
264 b
.cursor
= nir_after_cf_list(&availability_if
->then_list
);
266 store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
267 store
->src
[0] = nir_src_for_ssa(nir_b2i32(&b
, nir_load_var(&b
, available
)));
268 store
->src
[1] = nir_src_for_ssa(&dst_buf
->dest
.ssa
);
269 store
->src
[2] = nir_src_for_ssa(nir_iadd(&b
, result_size
, output_base
));
270 nir_intrinsic_set_write_mask(store
, 0x1);
271 store
->num_components
= 1;
272 nir_builder_instr_insert(&b
, &store
->instr
);
278 build_pipeline_statistics_query_shader(struct radv_device
*device
) {
279 /* the shader this builds is roughly
283 * uint32_t dst_stride;
284 * uint32_t stats_mask;
285 * uint32_t avail_offset;
288 * uint32_t src_stride = pipelinestat_block_size * 2;
290 * location(binding = 0) buffer dst_buf;
291 * location(binding = 1) buffer src_buf;
294 * uint64_t src_offset = src_stride * global_id.x;
295 * uint64_t dst_base = dst_stride * global_id.x;
296 * uint64_t dst_offset = dst_base;
297 * uint32_t elem_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;
298 * uint32_t elem_count = stats_mask >> 16;
299 * uint32_t available32 = src_buf[avail_offset + 4 * global_id.x];
300 * if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
301 * dst_buf[dst_offset + elem_count * elem_size] = available32;
303 * if ((bool)available32) {
304 * // repeat 11 times:
305 * if (stats_mask & (1 << 0)) {
306 * uint64_t start = src_buf[src_offset + 8 * indices[0]];
307 * uint64_t end = src_buf[src_offset + 8 * indices[0] + pipelinestat_block_size];
308 * uint64_t result = end - start;
309 * if (flags & VK_QUERY_RESULT_64_BIT)
310 * dst_buf[dst_offset] = result;
312 * dst_buf[dst_offset] = (uint32_t)result.
313 * dst_offset += elem_size;
315 * } else if (flags & VK_QUERY_RESULT_PARTIAL_BIT) {
316 * // Set everything to 0 as we don't know what is valid.
317 * for (int i = 0; i < elem_count; ++i)
318 * dst_buf[dst_base + elem_size * i] = 0;
323 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_COMPUTE
, NULL
);
324 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "pipeline_statistics_query");
325 b
.shader
->info
.cs
.local_size
[0] = 64;
326 b
.shader
->info
.cs
.local_size
[1] = 1;
327 b
.shader
->info
.cs
.local_size
[2] = 1;
329 nir_variable
*output_offset
= nir_local_variable_create(b
.impl
, glsl_int_type(), "output_offset");
331 nir_ssa_def
*flags
= radv_load_push_int(&b
, 0, "flags");
332 nir_ssa_def
*stats_mask
= radv_load_push_int(&b
, 8, "stats_mask");
333 nir_ssa_def
*avail_offset
= radv_load_push_int(&b
, 12, "avail_offset");
335 nir_intrinsic_instr
*dst_buf
= nir_intrinsic_instr_create(b
.shader
,
336 nir_intrinsic_vulkan_resource_index
);
337 dst_buf
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
338 nir_intrinsic_set_desc_set(dst_buf
, 0);
339 nir_intrinsic_set_binding(dst_buf
, 0);
340 nir_ssa_dest_init(&dst_buf
->instr
, &dst_buf
->dest
, 1, 32, NULL
);
341 nir_builder_instr_insert(&b
, &dst_buf
->instr
);
343 nir_intrinsic_instr
*src_buf
= nir_intrinsic_instr_create(b
.shader
,
344 nir_intrinsic_vulkan_resource_index
);
345 src_buf
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
346 nir_intrinsic_set_desc_set(src_buf
, 0);
347 nir_intrinsic_set_binding(src_buf
, 1);
348 nir_ssa_dest_init(&src_buf
->instr
, &src_buf
->dest
, 1, 32, NULL
);
349 nir_builder_instr_insert(&b
, &src_buf
->instr
);
351 nir_ssa_def
*invoc_id
= nir_load_local_invocation_id(&b
);
352 nir_ssa_def
*wg_id
= nir_load_work_group_id(&b
);
353 nir_ssa_def
*block_size
= nir_imm_ivec4(&b
,
354 b
.shader
->info
.cs
.local_size
[0],
355 b
.shader
->info
.cs
.local_size
[1],
356 b
.shader
->info
.cs
.local_size
[2], 0);
357 nir_ssa_def
*global_id
= nir_iadd(&b
, nir_imul(&b
, wg_id
, block_size
), invoc_id
);
358 global_id
= nir_channel(&b
, global_id
, 0); // We only care about x here.
360 nir_ssa_def
*input_stride
= nir_imm_int(&b
, pipelinestat_block_size
* 2);
361 nir_ssa_def
*input_base
= nir_imul(&b
, input_stride
, global_id
);
362 nir_ssa_def
*output_stride
= radv_load_push_int(&b
, 4, "output_stride");
363 nir_ssa_def
*output_base
= nir_imul(&b
, output_stride
, global_id
);
366 avail_offset
= nir_iadd(&b
, avail_offset
,
367 nir_imul(&b
, global_id
, nir_imm_int(&b
, 4)));
369 nir_intrinsic_instr
*load
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ssbo
);
370 load
->src
[0] = nir_src_for_ssa(&src_buf
->dest
.ssa
);
371 load
->src
[1] = nir_src_for_ssa(avail_offset
);
372 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 1, 32, NULL
);
373 load
->num_components
= 1;
374 nir_builder_instr_insert(&b
, &load
->instr
);
375 nir_ssa_def
*available32
= &load
->dest
.ssa
;
377 nir_ssa_def
*result_is_64bit
= nir_test_flag(&b
, flags
, VK_QUERY_RESULT_64_BIT
);
378 nir_ssa_def
*elem_size
= nir_bcsel(&b
, result_is_64bit
, nir_imm_int(&b
, 8), nir_imm_int(&b
, 4));
379 nir_ssa_def
*elem_count
= nir_ushr(&b
, stats_mask
, nir_imm_int(&b
, 16));
381 /* Store the availability bit if requested. */
383 nir_if
*availability_if
= nir_if_create(b
.shader
);
384 availability_if
->condition
= nir_src_for_ssa(nir_test_flag(&b
, flags
, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
));
385 nir_cf_node_insert(b
.cursor
, &availability_if
->cf_node
);
387 b
.cursor
= nir_after_cf_list(&availability_if
->then_list
);
389 nir_intrinsic_instr
*store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
390 store
->src
[0] = nir_src_for_ssa(available32
);
391 store
->src
[1] = nir_src_for_ssa(&dst_buf
->dest
.ssa
);
392 store
->src
[2] = nir_src_for_ssa(nir_iadd(&b
, output_base
, nir_imul(&b
, elem_count
, elem_size
)));
393 nir_intrinsic_set_write_mask(store
, 0x1);
394 store
->num_components
= 1;
395 nir_builder_instr_insert(&b
, &store
->instr
);
397 b
.cursor
= nir_after_cf_node(&availability_if
->cf_node
);
399 nir_if
*available_if
= nir_if_create(b
.shader
);
400 available_if
->condition
= nir_src_for_ssa(nir_i2b(&b
, available32
));
401 nir_cf_node_insert(b
.cursor
, &available_if
->cf_node
);
403 b
.cursor
= nir_after_cf_list(&available_if
->then_list
);
405 nir_store_var(&b
, output_offset
, output_base
, 0x1);
406 for (int i
= 0; i
< 11; ++i
) {
407 nir_if
*store_if
= nir_if_create(b
.shader
);
408 store_if
->condition
= nir_src_for_ssa(nir_test_flag(&b
, stats_mask
, 1u << i
));
409 nir_cf_node_insert(b
.cursor
, &store_if
->cf_node
);
411 b
.cursor
= nir_after_cf_list(&store_if
->then_list
);
413 load
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ssbo
);
414 load
->src
[0] = nir_src_for_ssa(&src_buf
->dest
.ssa
);
415 load
->src
[1] = nir_src_for_ssa(nir_iadd(&b
, input_base
,
416 nir_imm_int(&b
, pipeline_statistics_indices
[i
] * 8)));
417 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 1, 64, NULL
);
418 load
->num_components
= 1;
419 nir_builder_instr_insert(&b
, &load
->instr
);
420 nir_ssa_def
*start
= &load
->dest
.ssa
;
422 load
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ssbo
);
423 load
->src
[0] = nir_src_for_ssa(&src_buf
->dest
.ssa
);
424 load
->src
[1] = nir_src_for_ssa(nir_iadd(&b
, input_base
,
425 nir_imm_int(&b
, pipeline_statistics_indices
[i
] * 8 + pipelinestat_block_size
)));
426 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 1, 64, NULL
);
427 load
->num_components
= 1;
428 nir_builder_instr_insert(&b
, &load
->instr
);
429 nir_ssa_def
*end
= &load
->dest
.ssa
;
431 nir_ssa_def
*result
= nir_isub(&b
, end
, start
);
434 nir_if
*store_64bit_if
= nir_if_create(b
.shader
);
435 store_64bit_if
->condition
= nir_src_for_ssa(result_is_64bit
);
436 nir_cf_node_insert(b
.cursor
, &store_64bit_if
->cf_node
);
438 b
.cursor
= nir_after_cf_list(&store_64bit_if
->then_list
);
440 nir_intrinsic_instr
*store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
441 store
->src
[0] = nir_src_for_ssa(result
);
442 store
->src
[1] = nir_src_for_ssa(&dst_buf
->dest
.ssa
);
443 store
->src
[2] = nir_src_for_ssa(nir_load_var(&b
, output_offset
));
444 nir_intrinsic_set_write_mask(store
, 0x1);
445 store
->num_components
= 1;
446 nir_builder_instr_insert(&b
, &store
->instr
);
448 b
.cursor
= nir_after_cf_list(&store_64bit_if
->else_list
);
450 store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
451 store
->src
[0] = nir_src_for_ssa(nir_u2u32(&b
, result
));
452 store
->src
[1] = nir_src_for_ssa(&dst_buf
->dest
.ssa
);
453 store
->src
[2] = nir_src_for_ssa(nir_load_var(&b
, output_offset
));
454 nir_intrinsic_set_write_mask(store
, 0x1);
455 store
->num_components
= 1;
456 nir_builder_instr_insert(&b
, &store
->instr
);
458 b
.cursor
= nir_after_cf_node(&store_64bit_if
->cf_node
);
460 nir_store_var(&b
, output_offset
,
461 nir_iadd(&b
, nir_load_var(&b
, output_offset
),
464 b
.cursor
= nir_after_cf_node(&store_if
->cf_node
);
467 b
.cursor
= nir_after_cf_list(&available_if
->else_list
);
469 available_if
= nir_if_create(b
.shader
);
470 available_if
->condition
= nir_src_for_ssa(nir_test_flag(&b
, flags
, VK_QUERY_RESULT_PARTIAL_BIT
));
471 nir_cf_node_insert(b
.cursor
, &available_if
->cf_node
);
473 b
.cursor
= nir_after_cf_list(&available_if
->then_list
);
475 /* Stores zeros in all outputs. */
477 nir_variable
*counter
= nir_local_variable_create(b
.impl
, glsl_int_type(), "counter");
478 nir_store_var(&b
, counter
, nir_imm_int(&b
, 0), 0x1);
480 nir_loop
*loop
= nir_loop_create(b
.shader
);
481 nir_builder_cf_insert(&b
, &loop
->cf_node
);
482 b
.cursor
= nir_after_cf_list(&loop
->body
);
484 nir_ssa_def
*current_counter
= nir_load_var(&b
, counter
);
485 radv_break_on_count(&b
, counter
, elem_count
);
487 nir_ssa_def
*output_elem
= nir_iadd(&b
, output_base
,
488 nir_imul(&b
, elem_size
, current_counter
));
490 nir_if
*store_64bit_if
= nir_if_create(b
.shader
);
491 store_64bit_if
->condition
= nir_src_for_ssa(result_is_64bit
);
492 nir_cf_node_insert(b
.cursor
, &store_64bit_if
->cf_node
);
494 b
.cursor
= nir_after_cf_list(&store_64bit_if
->then_list
);
496 store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
497 store
->src
[0] = nir_src_for_ssa(nir_imm_int64(&b
, 0));
498 store
->src
[1] = nir_src_for_ssa(&dst_buf
->dest
.ssa
);
499 store
->src
[2] = nir_src_for_ssa(output_elem
);
500 nir_intrinsic_set_write_mask(store
, 0x1);
501 store
->num_components
= 1;
502 nir_builder_instr_insert(&b
, &store
->instr
);
504 b
.cursor
= nir_after_cf_list(&store_64bit_if
->else_list
);
506 store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
507 store
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
508 store
->src
[1] = nir_src_for_ssa(&dst_buf
->dest
.ssa
);
509 store
->src
[2] = nir_src_for_ssa(output_elem
);
510 nir_intrinsic_set_write_mask(store
, 0x1);
511 store
->num_components
= 1;
512 nir_builder_instr_insert(&b
, &store
->instr
);
514 b
.cursor
= nir_after_cf_node(&loop
->cf_node
);
519 build_tfb_query_shader(struct radv_device
*device
)
521 /* the shader this builds is roughly
523 * uint32_t src_stride = 32;
525 * location(binding = 0) buffer dst_buf;
526 * location(binding = 1) buffer src_buf;
529 * uint64_t result[2] = {};
530 * bool available = false;
531 * uint64_t src_offset = src_stride * global_id.x;
532 * uint64_t dst_offset = dst_stride * global_id.x;
533 * uint64_t *src_data = src_buf[src_offset];
534 * uint32_t avail = (src_data[0] >> 32) &
535 * (src_data[1] >> 32) &
536 * (src_data[2] >> 32) &
537 * (src_data[3] >> 32);
538 * if (avail & 0x80000000) {
539 * result[0] = src_data[3] - src_data[1];
540 * result[1] = src_data[2] - src_data[0];
543 * uint32_t result_size = flags & VK_QUERY_RESULT_64_BIT ? 16 : 8;
544 * if ((flags & VK_QUERY_RESULT_PARTIAL_BIT) || available) {
545 * if (flags & VK_QUERY_RESULT_64_BIT) {
546 * dst_buf[dst_offset] = result;
548 * dst_buf[dst_offset] = (uint32_t)result;
551 * if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
552 * dst_buf[dst_offset + result_size] = available;
557 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_COMPUTE
, NULL
);
558 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "tfb_query");
559 b
.shader
->info
.cs
.local_size
[0] = 64;
560 b
.shader
->info
.cs
.local_size
[1] = 1;
561 b
.shader
->info
.cs
.local_size
[2] = 1;
563 /* Create and initialize local variables. */
564 nir_variable
*result
=
565 nir_local_variable_create(b
.impl
,
566 glsl_vector_type(GLSL_TYPE_UINT64
, 2),
568 nir_variable
*available
=
569 nir_local_variable_create(b
.impl
, glsl_bool_type(), "available");
571 nir_store_var(&b
, result
,
572 nir_vec2(&b
, nir_imm_int64(&b
, 0),
573 nir_imm_int64(&b
, 0)), 0x3);
574 nir_store_var(&b
, available
, nir_imm_false(&b
), 0x1);
576 nir_ssa_def
*flags
= radv_load_push_int(&b
, 0, "flags");
578 /* Load resources. */
579 nir_intrinsic_instr
*dst_buf
= nir_intrinsic_instr_create(b
.shader
,
580 nir_intrinsic_vulkan_resource_index
);
581 dst_buf
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
582 nir_intrinsic_set_desc_set(dst_buf
, 0);
583 nir_intrinsic_set_binding(dst_buf
, 0);
584 nir_ssa_dest_init(&dst_buf
->instr
, &dst_buf
->dest
, 1, 32, NULL
);
585 nir_builder_instr_insert(&b
, &dst_buf
->instr
);
587 nir_intrinsic_instr
*src_buf
= nir_intrinsic_instr_create(b
.shader
,
588 nir_intrinsic_vulkan_resource_index
);
589 src_buf
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
590 nir_intrinsic_set_desc_set(src_buf
, 0);
591 nir_intrinsic_set_binding(src_buf
, 1);
592 nir_ssa_dest_init(&src_buf
->instr
, &src_buf
->dest
, 1, 32, NULL
);
593 nir_builder_instr_insert(&b
, &src_buf
->instr
);
595 /* Compute global ID. */
596 nir_ssa_def
*invoc_id
= nir_load_local_invocation_id(&b
);
597 nir_ssa_def
*wg_id
= nir_load_work_group_id(&b
);
598 nir_ssa_def
*block_size
= nir_imm_ivec4(&b
,
599 b
.shader
->info
.cs
.local_size
[0],
600 b
.shader
->info
.cs
.local_size
[1],
601 b
.shader
->info
.cs
.local_size
[2], 0);
602 nir_ssa_def
*global_id
= nir_iadd(&b
, nir_imul(&b
, wg_id
, block_size
), invoc_id
);
603 global_id
= nir_channel(&b
, global_id
, 0); // We only care about x here.
605 /* Compute src/dst strides. */
606 nir_ssa_def
*input_stride
= nir_imm_int(&b
, 32);
607 nir_ssa_def
*input_base
= nir_imul(&b
, input_stride
, global_id
);
608 nir_ssa_def
*output_stride
= radv_load_push_int(&b
, 4, "output_stride");
609 nir_ssa_def
*output_base
= nir_imul(&b
, output_stride
, global_id
);
611 /* Load data from the query pool. */
612 nir_intrinsic_instr
*load1
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ssbo
);
613 load1
->src
[0] = nir_src_for_ssa(&src_buf
->dest
.ssa
);
614 load1
->src
[1] = nir_src_for_ssa(input_base
);
615 nir_ssa_dest_init(&load1
->instr
, &load1
->dest
, 4, 32, NULL
);
616 load1
->num_components
= 4;
617 nir_builder_instr_insert(&b
, &load1
->instr
);
619 nir_intrinsic_instr
*load2
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_ssbo
);
620 load2
->src
[0] = nir_src_for_ssa(&src_buf
->dest
.ssa
);
621 load2
->src
[1] = nir_src_for_ssa(nir_iadd(&b
, input_base
, nir_imm_int(&b
, 16)));
622 nir_ssa_dest_init(&load2
->instr
, &load2
->dest
, 4, 32, NULL
);
623 load2
->num_components
= 4;
624 nir_builder_instr_insert(&b
, &load2
->instr
);
626 /* Check if result is available. */
627 nir_ssa_def
*avails
[2];
628 avails
[0] = nir_iand(&b
, nir_channel(&b
, &load1
->dest
.ssa
, 1),
629 nir_channel(&b
, &load1
->dest
.ssa
, 3));
630 avails
[1] = nir_iand(&b
, nir_channel(&b
, &load2
->dest
.ssa
, 1),
631 nir_channel(&b
, &load2
->dest
.ssa
, 3));
632 nir_ssa_def
*result_is_available
=
633 nir_i2b(&b
, nir_iand(&b
, nir_iand(&b
, avails
[0], avails
[1]),
634 nir_imm_int(&b
, 0x80000000)));
636 /* Only compute result if available. */
637 nir_if
*available_if
= nir_if_create(b
.shader
);
638 available_if
->condition
= nir_src_for_ssa(result_is_available
);
639 nir_cf_node_insert(b
.cursor
, &available_if
->cf_node
);
641 b
.cursor
= nir_after_cf_list(&available_if
->then_list
);
644 nir_ssa_def
*packed64
[4];
645 packed64
[0] = nir_pack_64_2x32(&b
, nir_vec2(&b
,
646 nir_channel(&b
, &load1
->dest
.ssa
, 0),
647 nir_channel(&b
, &load1
->dest
.ssa
, 1)));
648 packed64
[1] = nir_pack_64_2x32(&b
, nir_vec2(&b
,
649 nir_channel(&b
, &load1
->dest
.ssa
, 2),
650 nir_channel(&b
, &load1
->dest
.ssa
, 3)));
651 packed64
[2] = nir_pack_64_2x32(&b
, nir_vec2(&b
,
652 nir_channel(&b
, &load2
->dest
.ssa
, 0),
653 nir_channel(&b
, &load2
->dest
.ssa
, 1)));
654 packed64
[3] = nir_pack_64_2x32(&b
, nir_vec2(&b
,
655 nir_channel(&b
, &load2
->dest
.ssa
, 2),
656 nir_channel(&b
, &load2
->dest
.ssa
, 3)));
658 /* Compute result. */
659 nir_ssa_def
*num_primitive_written
=
660 nir_isub(&b
, packed64
[3], packed64
[1]);
661 nir_ssa_def
*primitive_storage_needed
=
662 nir_isub(&b
, packed64
[2], packed64
[0]);
664 nir_store_var(&b
, result
,
665 nir_vec2(&b
, num_primitive_written
,
666 primitive_storage_needed
), 0x3);
667 nir_store_var(&b
, available
, nir_imm_true(&b
), 0x1);
669 b
.cursor
= nir_after_cf_node(&available_if
->cf_node
);
671 /* Determine if result is 64 or 32 bit. */
672 nir_ssa_def
*result_is_64bit
=
673 nir_test_flag(&b
, flags
, VK_QUERY_RESULT_64_BIT
);
674 nir_ssa_def
*result_size
=
675 nir_bcsel(&b
, result_is_64bit
, nir_imm_int(&b
, 16),
678 /* Store the result if complete or partial results have been requested. */
679 nir_if
*store_if
= nir_if_create(b
.shader
);
680 store_if
->condition
=
681 nir_src_for_ssa(nir_ior(&b
, nir_test_flag(&b
, flags
, VK_QUERY_RESULT_PARTIAL_BIT
),
682 nir_load_var(&b
, available
)));
683 nir_cf_node_insert(b
.cursor
, &store_if
->cf_node
);
685 b
.cursor
= nir_after_cf_list(&store_if
->then_list
);
688 nir_if
*store_64bit_if
= nir_if_create(b
.shader
);
689 store_64bit_if
->condition
= nir_src_for_ssa(result_is_64bit
);
690 nir_cf_node_insert(b
.cursor
, &store_64bit_if
->cf_node
);
692 b
.cursor
= nir_after_cf_list(&store_64bit_if
->then_list
);
694 nir_intrinsic_instr
*store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
695 store
->src
[0] = nir_src_for_ssa(nir_load_var(&b
, result
));
696 store
->src
[1] = nir_src_for_ssa(&dst_buf
->dest
.ssa
);
697 store
->src
[2] = nir_src_for_ssa(output_base
);
698 nir_intrinsic_set_write_mask(store
, 0x3);
699 store
->num_components
= 2;
700 nir_builder_instr_insert(&b
, &store
->instr
);
702 b
.cursor
= nir_after_cf_list(&store_64bit_if
->else_list
);
704 store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
705 store
->src
[0] = nir_src_for_ssa(nir_u2u32(&b
, nir_load_var(&b
, result
)));
706 store
->src
[1] = nir_src_for_ssa(&dst_buf
->dest
.ssa
);
707 store
->src
[2] = nir_src_for_ssa(output_base
);
708 nir_intrinsic_set_write_mask(store
, 0x3);
709 store
->num_components
= 2;
710 nir_builder_instr_insert(&b
, &store
->instr
);
712 b
.cursor
= nir_after_cf_node(&store_64bit_if
->cf_node
);
714 b
.cursor
= nir_after_cf_node(&store_if
->cf_node
);
716 /* Store the availability bit if requested. */
717 nir_if
*availability_if
= nir_if_create(b
.shader
);
718 availability_if
->condition
=
719 nir_src_for_ssa(nir_test_flag(&b
, flags
, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
));
720 nir_cf_node_insert(b
.cursor
, &availability_if
->cf_node
);
722 b
.cursor
= nir_after_cf_list(&availability_if
->then_list
);
724 store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_store_ssbo
);
725 store
->src
[0] = nir_src_for_ssa(nir_b2i32(&b
, nir_load_var(&b
, available
)));
726 store
->src
[1] = nir_src_for_ssa(&dst_buf
->dest
.ssa
);
727 store
->src
[2] = nir_src_for_ssa(nir_iadd(&b
, result_size
, output_base
));
728 nir_intrinsic_set_write_mask(store
, 0x1);
729 store
->num_components
= 1;
730 nir_builder_instr_insert(&b
, &store
->instr
);
732 b
.cursor
= nir_after_cf_node(&availability_if
->cf_node
);
737 static VkResult
radv_device_init_meta_query_state_internal(struct radv_device
*device
)
740 struct radv_shader_module occlusion_cs
= { .nir
= NULL
};
741 struct radv_shader_module pipeline_statistics_cs
= { .nir
= NULL
};
742 struct radv_shader_module tfb_cs
= { .nir
= NULL
};
744 mtx_lock(&device
->meta_state
.mtx
);
745 if (device
->meta_state
.query
.pipeline_statistics_query_pipeline
) {
746 mtx_unlock(&device
->meta_state
.mtx
);
749 occlusion_cs
.nir
= build_occlusion_query_shader(device
);
750 pipeline_statistics_cs
.nir
= build_pipeline_statistics_query_shader(device
);
751 tfb_cs
.nir
= build_tfb_query_shader(device
);
753 VkDescriptorSetLayoutCreateInfo occlusion_ds_create_info
= {
754 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
755 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
757 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
760 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
,
761 .descriptorCount
= 1,
762 .stageFlags
= VK_SHADER_STAGE_COMPUTE_BIT
,
763 .pImmutableSamplers
= NULL
767 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
,
768 .descriptorCount
= 1,
769 .stageFlags
= VK_SHADER_STAGE_COMPUTE_BIT
,
770 .pImmutableSamplers
= NULL
775 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
776 &occlusion_ds_create_info
,
777 &device
->meta_state
.alloc
,
778 &device
->meta_state
.query
.ds_layout
);
779 if (result
!= VK_SUCCESS
)
782 VkPipelineLayoutCreateInfo occlusion_pl_create_info
= {
783 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
785 .pSetLayouts
= &device
->meta_state
.query
.ds_layout
,
786 .pushConstantRangeCount
= 1,
787 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_COMPUTE_BIT
, 0, 16},
790 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
791 &occlusion_pl_create_info
,
792 &device
->meta_state
.alloc
,
793 &device
->meta_state
.query
.p_layout
);
794 if (result
!= VK_SUCCESS
)
797 VkPipelineShaderStageCreateInfo occlusion_pipeline_shader_stage
= {
798 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
799 .stage
= VK_SHADER_STAGE_COMPUTE_BIT
,
800 .module
= radv_shader_module_to_handle(&occlusion_cs
),
802 .pSpecializationInfo
= NULL
,
805 VkComputePipelineCreateInfo occlusion_vk_pipeline_info
= {
806 .sType
= VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
,
807 .stage
= occlusion_pipeline_shader_stage
,
809 .layout
= device
->meta_state
.query
.p_layout
,
812 result
= radv_CreateComputePipelines(radv_device_to_handle(device
),
813 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
814 1, &occlusion_vk_pipeline_info
, NULL
,
815 &device
->meta_state
.query
.occlusion_query_pipeline
);
816 if (result
!= VK_SUCCESS
)
819 VkPipelineShaderStageCreateInfo pipeline_statistics_pipeline_shader_stage
= {
820 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
821 .stage
= VK_SHADER_STAGE_COMPUTE_BIT
,
822 .module
= radv_shader_module_to_handle(&pipeline_statistics_cs
),
824 .pSpecializationInfo
= NULL
,
827 VkComputePipelineCreateInfo pipeline_statistics_vk_pipeline_info
= {
828 .sType
= VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
,
829 .stage
= pipeline_statistics_pipeline_shader_stage
,
831 .layout
= device
->meta_state
.query
.p_layout
,
834 result
= radv_CreateComputePipelines(radv_device_to_handle(device
),
835 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
836 1, &pipeline_statistics_vk_pipeline_info
, NULL
,
837 &device
->meta_state
.query
.pipeline_statistics_query_pipeline
);
838 if (result
!= VK_SUCCESS
)
841 VkPipelineShaderStageCreateInfo tfb_pipeline_shader_stage
= {
842 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
843 .stage
= VK_SHADER_STAGE_COMPUTE_BIT
,
844 .module
= radv_shader_module_to_handle(&tfb_cs
),
846 .pSpecializationInfo
= NULL
,
849 VkComputePipelineCreateInfo tfb_pipeline_info
= {
850 .sType
= VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
,
851 .stage
= tfb_pipeline_shader_stage
,
853 .layout
= device
->meta_state
.query
.p_layout
,
856 result
= radv_CreateComputePipelines(radv_device_to_handle(device
),
857 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
858 1, &tfb_pipeline_info
, NULL
,
859 &device
->meta_state
.query
.tfb_query_pipeline
);
861 if (result
!= VK_SUCCESS
)
862 radv_device_finish_meta_query_state(device
);
863 ralloc_free(occlusion_cs
.nir
);
864 ralloc_free(pipeline_statistics_cs
.nir
);
865 ralloc_free(tfb_cs
.nir
);
866 mtx_unlock(&device
->meta_state
.mtx
);
870 VkResult
radv_device_init_meta_query_state(struct radv_device
*device
, bool on_demand
)
875 return radv_device_init_meta_query_state_internal(device
);
878 void radv_device_finish_meta_query_state(struct radv_device
*device
)
880 if (device
->meta_state
.query
.tfb_query_pipeline
)
881 radv_DestroyPipeline(radv_device_to_handle(device
),
882 device
->meta_state
.query
.tfb_query_pipeline
,
883 &device
->meta_state
.alloc
);
885 if (device
->meta_state
.query
.pipeline_statistics_query_pipeline
)
886 radv_DestroyPipeline(radv_device_to_handle(device
),
887 device
->meta_state
.query
.pipeline_statistics_query_pipeline
,
888 &device
->meta_state
.alloc
);
890 if (device
->meta_state
.query
.occlusion_query_pipeline
)
891 radv_DestroyPipeline(radv_device_to_handle(device
),
892 device
->meta_state
.query
.occlusion_query_pipeline
,
893 &device
->meta_state
.alloc
);
895 if (device
->meta_state
.query
.p_layout
)
896 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
897 device
->meta_state
.query
.p_layout
,
898 &device
->meta_state
.alloc
);
900 if (device
->meta_state
.query
.ds_layout
)
901 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
902 device
->meta_state
.query
.ds_layout
,
903 &device
->meta_state
.alloc
);
906 static void radv_query_shader(struct radv_cmd_buffer
*cmd_buffer
,
907 VkPipeline
*pipeline
,
908 struct radeon_winsys_bo
*src_bo
,
909 struct radeon_winsys_bo
*dst_bo
,
910 uint64_t src_offset
, uint64_t dst_offset
,
911 uint32_t src_stride
, uint32_t dst_stride
,
912 uint32_t count
, uint32_t flags
,
913 uint32_t pipeline_stats_mask
, uint32_t avail_offset
)
915 struct radv_device
*device
= cmd_buffer
->device
;
916 struct radv_meta_saved_state saved_state
;
917 bool old_predicating
;
920 VkResult ret
= radv_device_init_meta_query_state_internal(device
);
921 if (ret
!= VK_SUCCESS
) {
922 cmd_buffer
->record_result
= ret
;
927 radv_meta_save(&saved_state
, cmd_buffer
,
928 RADV_META_SAVE_COMPUTE_PIPELINE
|
929 RADV_META_SAVE_CONSTANTS
|
930 RADV_META_SAVE_DESCRIPTORS
);
932 /* VK_EXT_conditional_rendering says that copy commands should not be
933 * affected by conditional rendering.
935 old_predicating
= cmd_buffer
->state
.predicating
;
936 cmd_buffer
->state
.predicating
= false;
938 struct radv_buffer dst_buffer
= {
940 .offset
= dst_offset
,
941 .size
= dst_stride
* count
944 struct radv_buffer src_buffer
= {
946 .offset
= src_offset
,
947 .size
= MAX2(src_stride
* count
, avail_offset
+ 4 * count
- src_offset
)
950 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
951 VK_PIPELINE_BIND_POINT_COMPUTE
, *pipeline
);
953 radv_meta_push_descriptor_set(cmd_buffer
,
954 VK_PIPELINE_BIND_POINT_COMPUTE
,
955 device
->meta_state
.query
.p_layout
,
957 2, /* descriptorWriteCount */
958 (VkWriteDescriptorSet
[]) {
960 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
962 .dstArrayElement
= 0,
963 .descriptorCount
= 1,
964 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
,
965 .pBufferInfo
= &(VkDescriptorBufferInfo
) {
966 .buffer
= radv_buffer_to_handle(&dst_buffer
),
968 .range
= VK_WHOLE_SIZE
972 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
974 .dstArrayElement
= 0,
975 .descriptorCount
= 1,
976 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
,
977 .pBufferInfo
= &(VkDescriptorBufferInfo
) {
978 .buffer
= radv_buffer_to_handle(&src_buffer
),
980 .range
= VK_WHOLE_SIZE
985 /* Encode the number of elements for easy access by the shader. */
986 pipeline_stats_mask
&= 0x7ff;
987 pipeline_stats_mask
|= util_bitcount(pipeline_stats_mask
) << 16;
989 avail_offset
-= src_offset
;
994 uint32_t pipeline_stats_mask
;
995 uint32_t avail_offset
;
1003 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
1004 device
->meta_state
.query
.p_layout
,
1005 VK_SHADER_STAGE_COMPUTE_BIT
, 0, sizeof(push_constants
),
1008 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_INV_GLOBAL_L2
|
1009 RADV_CMD_FLAG_INV_VMEM_L1
;
1011 if (flags
& VK_QUERY_RESULT_WAIT_BIT
)
1012 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
;
1014 radv_unaligned_dispatch(cmd_buffer
, count
, 1, 1);
1016 /* Restore conditional rendering. */
1017 cmd_buffer
->state
.predicating
= old_predicating
;
1019 radv_meta_restore(&saved_state
, cmd_buffer
);
1022 VkResult
radv_CreateQueryPool(
1024 const VkQueryPoolCreateInfo
* pCreateInfo
,
1025 const VkAllocationCallbacks
* pAllocator
,
1026 VkQueryPool
* pQueryPool
)
1028 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1029 struct radv_query_pool
*pool
= vk_alloc2(&device
->alloc
, pAllocator
,
1031 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1032 uint32_t initial_value
= pCreateInfo
->queryType
== VK_QUERY_TYPE_TIMESTAMP
1033 ? TIMESTAMP_NOT_READY
: 0;
1036 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1039 switch(pCreateInfo
->queryType
) {
1040 case VK_QUERY_TYPE_OCCLUSION
:
1041 pool
->stride
= 16 * get_max_db(device
);
1043 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
1044 pool
->stride
= pipelinestat_block_size
* 2;
1046 case VK_QUERY_TYPE_TIMESTAMP
:
1049 case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT
:
1053 unreachable("creating unhandled query type");
1056 pool
->type
= pCreateInfo
->queryType
;
1057 pool
->pipeline_stats_mask
= pCreateInfo
->pipelineStatistics
;
1058 pool
->availability_offset
= pool
->stride
* pCreateInfo
->queryCount
;
1059 pool
->size
= pool
->availability_offset
;
1060 if (pCreateInfo
->queryType
== VK_QUERY_TYPE_PIPELINE_STATISTICS
)
1061 pool
->size
+= 4 * pCreateInfo
->queryCount
;
1063 pool
->bo
= device
->ws
->buffer_create(device
->ws
, pool
->size
,
1064 64, RADEON_DOMAIN_GTT
, RADEON_FLAG_NO_INTERPROCESS_SHARING
);
1067 vk_free2(&device
->alloc
, pAllocator
, pool
);
1068 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1071 pool
->ptr
= device
->ws
->buffer_map(pool
->bo
);
1074 device
->ws
->buffer_destroy(pool
->bo
);
1075 vk_free2(&device
->alloc
, pAllocator
, pool
);
1076 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1078 memset(pool
->ptr
, initial_value
, pool
->size
);
1080 *pQueryPool
= radv_query_pool_to_handle(pool
);
1084 void radv_DestroyQueryPool(
1087 const VkAllocationCallbacks
* pAllocator
)
1089 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1090 RADV_FROM_HANDLE(radv_query_pool
, pool
, _pool
);
1095 device
->ws
->buffer_destroy(pool
->bo
);
1096 vk_free2(&device
->alloc
, pAllocator
, pool
);
1099 VkResult
radv_GetQueryPoolResults(
1101 VkQueryPool queryPool
,
1102 uint32_t firstQuery
,
1103 uint32_t queryCount
,
1106 VkDeviceSize stride
,
1107 VkQueryResultFlags flags
)
1109 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1110 RADV_FROM_HANDLE(radv_query_pool
, pool
, queryPool
);
1112 VkResult result
= VK_SUCCESS
;
1114 for(unsigned i
= 0; i
< queryCount
; ++i
, data
+= stride
) {
1116 unsigned query
= firstQuery
+ i
;
1117 char *src
= pool
->ptr
+ query
* pool
->stride
;
1120 if (pool
->type
== VK_QUERY_TYPE_PIPELINE_STATISTICS
) {
1121 if (flags
& VK_QUERY_RESULT_WAIT_BIT
)
1122 while(!*(volatile uint32_t*)(pool
->ptr
+ pool
->availability_offset
+ 4 * query
))
1124 available
= *(uint32_t*)(pool
->ptr
+ pool
->availability_offset
+ 4 * query
);
1127 switch (pool
->type
) {
1128 case VK_QUERY_TYPE_TIMESTAMP
: {
1129 available
= *(uint64_t *)src
!= TIMESTAMP_NOT_READY
;
1131 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
1132 while (*(volatile uint64_t *)src
== TIMESTAMP_NOT_READY
)
1134 available
= *(uint64_t *)src
!= TIMESTAMP_NOT_READY
;
1137 if (!available
&& !(flags
& VK_QUERY_RESULT_PARTIAL_BIT
)) {
1138 result
= VK_NOT_READY
;
1143 if (flags
& VK_QUERY_RESULT_64_BIT
) {
1144 *(uint64_t*)dest
= *(uint64_t*)src
;
1147 *(uint32_t*)dest
= *(uint32_t*)src
;
1152 case VK_QUERY_TYPE_OCCLUSION
: {
1153 volatile uint64_t const *src64
= (volatile uint64_t const *)src
;
1154 uint64_t sample_count
= 0;
1155 int db_count
= get_max_db(device
);
1158 for (int i
= 0; i
< db_count
; ++i
) {
1159 uint64_t start
, end
;
1161 start
= src64
[2 * i
];
1162 end
= src64
[2 * i
+ 1];
1163 } while ((!(start
& (1ull << 63)) || !(end
& (1ull << 63))) && (flags
& VK_QUERY_RESULT_WAIT_BIT
));
1165 if (!(start
& (1ull << 63)) || !(end
& (1ull << 63)))
1168 sample_count
+= end
- start
;
1172 if (!available
&& !(flags
& VK_QUERY_RESULT_PARTIAL_BIT
)) {
1173 result
= VK_NOT_READY
;
1178 if (flags
& VK_QUERY_RESULT_64_BIT
) {
1179 *(uint64_t*)dest
= sample_count
;
1182 *(uint32_t*)dest
= sample_count
;
1187 case VK_QUERY_TYPE_PIPELINE_STATISTICS
: {
1188 if (!available
&& !(flags
& VK_QUERY_RESULT_PARTIAL_BIT
)) {
1189 result
= VK_NOT_READY
;
1194 const uint64_t *start
= (uint64_t*)src
;
1195 const uint64_t *stop
= (uint64_t*)(src
+ pipelinestat_block_size
);
1196 if (flags
& VK_QUERY_RESULT_64_BIT
) {
1197 uint64_t *dst
= (uint64_t*)dest
;
1198 dest
+= util_bitcount(pool
->pipeline_stats_mask
) * 8;
1199 for(int i
= 0; i
< 11; ++i
)
1200 if(pool
->pipeline_stats_mask
& (1u << i
))
1201 *dst
++ = stop
[pipeline_statistics_indices
[i
]] -
1202 start
[pipeline_statistics_indices
[i
]];
1205 uint32_t *dst
= (uint32_t*)dest
;
1206 dest
+= util_bitcount(pool
->pipeline_stats_mask
) * 4;
1207 for(int i
= 0; i
< 11; ++i
)
1208 if(pool
->pipeline_stats_mask
& (1u << i
))
1209 *dst
++ = stop
[pipeline_statistics_indices
[i
]] -
1210 start
[pipeline_statistics_indices
[i
]];
1214 case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT
: {
1215 volatile uint64_t const *src64
= (volatile uint64_t const *)src
;
1216 uint64_t num_primitives_written
;
1217 uint64_t primitive_storage_needed
;
1219 /* SAMPLE_STREAMOUTSTATS stores this structure:
1221 * u64 NumPrimitivesWritten;
1222 * u64 PrimitiveStorageNeeded;
1226 for (int j
= 0; j
< 4; j
++) {
1227 if (!(src64
[j
] & 0x8000000000000000UL
))
1231 if (!available
&& !(flags
& VK_QUERY_RESULT_PARTIAL_BIT
)) {
1232 result
= VK_NOT_READY
;
1236 num_primitives_written
= src64
[3] - src64
[1];
1237 primitive_storage_needed
= src64
[2] - src64
[0];
1239 if (flags
& VK_QUERY_RESULT_64_BIT
) {
1240 *(uint64_t *)dest
= num_primitives_written
;
1242 *(uint64_t *)dest
= primitive_storage_needed
;
1245 *(uint32_t *)dest
= num_primitives_written
;
1247 *(uint32_t *)dest
= primitive_storage_needed
;
1253 unreachable("trying to get results of unhandled query type");
1256 if (flags
& VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
) {
1257 if (flags
& VK_QUERY_RESULT_64_BIT
) {
1258 *(uint64_t*)dest
= available
;
1260 *(uint32_t*)dest
= available
;
1268 void radv_CmdCopyQueryPoolResults(
1269 VkCommandBuffer commandBuffer
,
1270 VkQueryPool queryPool
,
1271 uint32_t firstQuery
,
1272 uint32_t queryCount
,
1274 VkDeviceSize dstOffset
,
1275 VkDeviceSize stride
,
1276 VkQueryResultFlags flags
)
1278 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1279 RADV_FROM_HANDLE(radv_query_pool
, pool
, queryPool
);
1280 RADV_FROM_HANDLE(radv_buffer
, dst_buffer
, dstBuffer
);
1281 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1282 unsigned elem_size
= (flags
& VK_QUERY_RESULT_64_BIT
) ? 8 : 4;
1283 uint64_t va
= radv_buffer_get_va(pool
->bo
);
1284 uint64_t dest_va
= radv_buffer_get_va(dst_buffer
->bo
);
1285 dest_va
+= dst_buffer
->offset
+ dstOffset
;
1287 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, pool
->bo
);
1288 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cmd_buffer
->cs
, dst_buffer
->bo
);
1290 switch (pool
->type
) {
1291 case VK_QUERY_TYPE_OCCLUSION
:
1292 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
1293 for(unsigned i
= 0; i
< queryCount
; ++i
, dest_va
+= stride
) {
1294 unsigned query
= firstQuery
+ i
;
1295 uint64_t src_va
= va
+ query
* pool
->stride
+ pool
->stride
- 4;
1297 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
1299 /* Waits on the upper word of the last DB entry */
1300 radv_cp_wait_mem(cs
, WAIT_REG_MEM_GREATER_OR_EQUAL
,
1301 src_va
, 0x80000000, 0xffffffff);
1304 radv_query_shader(cmd_buffer
, &cmd_buffer
->device
->meta_state
.query
.occlusion_query_pipeline
,
1305 pool
->bo
, dst_buffer
->bo
, firstQuery
* pool
->stride
,
1306 dst_buffer
->offset
+ dstOffset
,
1307 pool
->stride
, stride
,
1308 queryCount
, flags
, 0, 0);
1310 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
1311 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
1312 for(unsigned i
= 0; i
< queryCount
; ++i
, dest_va
+= stride
) {
1313 unsigned query
= firstQuery
+ i
;
1315 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
1317 uint64_t avail_va
= va
+ pool
->availability_offset
+ 4 * query
;
1319 /* This waits on the ME. All copies below are done on the ME */
1320 radv_cp_wait_mem(cs
, WAIT_REG_MEM_EQUAL
,
1321 avail_va
, 1, 0xffffffff);
1324 radv_query_shader(cmd_buffer
, &cmd_buffer
->device
->meta_state
.query
.pipeline_statistics_query_pipeline
,
1325 pool
->bo
, dst_buffer
->bo
, firstQuery
* pool
->stride
,
1326 dst_buffer
->offset
+ dstOffset
,
1327 pool
->stride
, stride
, queryCount
, flags
,
1328 pool
->pipeline_stats_mask
,
1329 pool
->availability_offset
+ 4 * firstQuery
);
1331 case VK_QUERY_TYPE_TIMESTAMP
:
1332 for(unsigned i
= 0; i
< queryCount
; ++i
, dest_va
+= stride
) {
1333 unsigned query
= firstQuery
+ i
;
1334 uint64_t local_src_va
= va
+ query
* pool
->stride
;
1336 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 19);
1339 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
1340 /* Wait on the high 32 bits of the timestamp in
1341 * case the low part is 0xffffffff.
1343 radv_cp_wait_mem(cs
, WAIT_REG_MEM_NOT_EQUAL
,
1345 TIMESTAMP_NOT_READY
>> 32,
1348 if (flags
& VK_QUERY_RESULT_WITH_AVAILABILITY_BIT
) {
1349 uint64_t avail_dest_va
= dest_va
+ elem_size
;
1351 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1352 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1353 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM_GRBM
));
1354 radeon_emit(cs
, local_src_va
);
1355 radeon_emit(cs
, local_src_va
>> 32);
1356 radeon_emit(cs
, avail_dest_va
);
1357 radeon_emit(cs
, avail_dest_va
>> 32);
1360 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1361 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM
) |
1362 COPY_DATA_DST_SEL(COPY_DATA_DST_MEM_GRBM
) |
1363 ((flags
& VK_QUERY_RESULT_64_BIT
) ? COPY_DATA_COUNT_SEL
: 0));
1364 radeon_emit(cs
, local_src_va
);
1365 radeon_emit(cs
, local_src_va
>> 32);
1366 radeon_emit(cs
, dest_va
);
1367 radeon_emit(cs
, dest_va
>> 32);
1370 assert(cs
->cdw
<= cdw_max
);
1373 case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT
:
1374 if (flags
& VK_QUERY_RESULT_WAIT_BIT
) {
1375 for(unsigned i
= 0; i
< queryCount
; i
++) {
1376 unsigned query
= firstQuery
+ i
;
1377 uint64_t src_va
= va
+ query
* pool
->stride
;
1379 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7 * 4);
1381 /* Wait on the upper word of all results. */
1382 for (unsigned j
= 0; j
< 4; j
++, src_va
+= 8) {
1383 radv_cp_wait_mem(cs
, WAIT_REG_MEM_GREATER_OR_EQUAL
,
1384 src_va
+ 4, 0x80000000,
1390 radv_query_shader(cmd_buffer
, &cmd_buffer
->device
->meta_state
.query
.tfb_query_pipeline
,
1391 pool
->bo
, dst_buffer
->bo
,
1392 firstQuery
* pool
->stride
,
1393 dst_buffer
->offset
+ dstOffset
,
1394 pool
->stride
, stride
,
1395 queryCount
, flags
, 0, 0);
1398 unreachable("trying to get results of unhandled query type");
1403 void radv_CmdResetQueryPool(
1404 VkCommandBuffer commandBuffer
,
1405 VkQueryPool queryPool
,
1406 uint32_t firstQuery
,
1407 uint32_t queryCount
)
1409 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1410 RADV_FROM_HANDLE(radv_query_pool
, pool
, queryPool
);
1411 uint32_t value
= pool
->type
== VK_QUERY_TYPE_TIMESTAMP
1412 ? TIMESTAMP_NOT_READY
: 0;
1413 uint32_t flush_bits
= 0;
1415 flush_bits
|= radv_fill_buffer(cmd_buffer
, pool
->bo
,
1416 firstQuery
* pool
->stride
,
1417 queryCount
* pool
->stride
, value
);
1419 if (pool
->type
== VK_QUERY_TYPE_PIPELINE_STATISTICS
) {
1420 flush_bits
|= radv_fill_buffer(cmd_buffer
, pool
->bo
,
1421 pool
->availability_offset
+ firstQuery
* 4,
1426 /* Only need to flush caches for the compute shader path. */
1427 cmd_buffer
->pending_reset_query
= true;
1428 cmd_buffer
->state
.flush_bits
|= flush_bits
;
1432 static unsigned event_type_for_stream(unsigned stream
)
1436 case 0: return V_028A90_SAMPLE_STREAMOUTSTATS
;
1437 case 1: return V_028A90_SAMPLE_STREAMOUTSTATS1
;
1438 case 2: return V_028A90_SAMPLE_STREAMOUTSTATS2
;
1439 case 3: return V_028A90_SAMPLE_STREAMOUTSTATS3
;
1443 static void emit_query_flush(struct radv_cmd_buffer
*cmd_buffer
,
1444 struct radv_query_pool
*pool
)
1446 if (cmd_buffer
->pending_reset_query
) {
1447 if (pool
->size
>= RADV_BUFFER_OPS_CS_THRESHOLD
) {
1448 /* Only need to flush caches if the query pool size is
1449 * large enough to be resetted using the compute shader
1450 * path. Small pools don't need any cache flushes
1451 * because we use a CP dma clear.
1453 si_emit_cache_flush(cmd_buffer
);
1458 static void emit_begin_query(struct radv_cmd_buffer
*cmd_buffer
,
1460 VkQueryType query_type
,
1461 VkQueryControlFlags flags
,
1464 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1465 switch (query_type
) {
1466 case VK_QUERY_TYPE_OCCLUSION
:
1467 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 7);
1469 ++cmd_buffer
->state
.active_occlusion_queries
;
1470 if (cmd_buffer
->state
.active_occlusion_queries
== 1) {
1471 if (flags
& VK_QUERY_CONTROL_PRECISE_BIT
) {
1472 /* This is the first occlusion query, enable
1473 * the hint if the precision bit is set.
1475 cmd_buffer
->state
.perfect_occlusion_queries_enabled
= true;
1478 radv_set_db_count_control(cmd_buffer
);
1480 if ((flags
& VK_QUERY_CONTROL_PRECISE_BIT
) &&
1481 !cmd_buffer
->state
.perfect_occlusion_queries_enabled
) {
1482 /* This is not the first query, but this one
1483 * needs to enable precision, DB_COUNT_CONTROL
1484 * has to be updated accordingly.
1486 cmd_buffer
->state
.perfect_occlusion_queries_enabled
= true;
1488 radv_set_db_count_control(cmd_buffer
);
1492 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
1493 radeon_emit(cs
, EVENT_TYPE(V_028A90_ZPASS_DONE
) | EVENT_INDEX(1));
1494 radeon_emit(cs
, va
);
1495 radeon_emit(cs
, va
>> 32);
1497 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
1498 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4);
1500 ++cmd_buffer
->state
.active_pipeline_queries
;
1501 if (cmd_buffer
->state
.active_pipeline_queries
== 1) {
1502 cmd_buffer
->state
.flush_bits
&= ~RADV_CMD_FLAG_STOP_PIPELINE_STATS
;
1503 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_START_PIPELINE_STATS
;
1506 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
1507 radeon_emit(cs
, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT
) | EVENT_INDEX(2));
1508 radeon_emit(cs
, va
);
1509 radeon_emit(cs
, va
>> 32);
1511 case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT
:
1512 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4);
1514 assert(index
< MAX_SO_STREAMS
);
1516 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
1517 radeon_emit(cs
, EVENT_TYPE(event_type_for_stream(index
)) | EVENT_INDEX(3));
1518 radeon_emit(cs
, va
);
1519 radeon_emit(cs
, va
>> 32);
1522 unreachable("beginning unhandled query type");
1527 static void emit_end_query(struct radv_cmd_buffer
*cmd_buffer
,
1528 uint64_t va
, uint64_t avail_va
,
1529 VkQueryType query_type
, uint32_t index
)
1531 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1532 switch (query_type
) {
1533 case VK_QUERY_TYPE_OCCLUSION
:
1534 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 14);
1536 cmd_buffer
->state
.active_occlusion_queries
--;
1537 if (cmd_buffer
->state
.active_occlusion_queries
== 0) {
1538 radv_set_db_count_control(cmd_buffer
);
1540 /* Reset the perfect occlusion queries hint now that no
1541 * queries are active.
1543 cmd_buffer
->state
.perfect_occlusion_queries_enabled
= false;
1546 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
1547 radeon_emit(cs
, EVENT_TYPE(V_028A90_ZPASS_DONE
) | EVENT_INDEX(1));
1548 radeon_emit(cs
, va
+ 8);
1549 radeon_emit(cs
, (va
+ 8) >> 32);
1552 case VK_QUERY_TYPE_PIPELINE_STATISTICS
:
1553 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 16);
1555 cmd_buffer
->state
.active_pipeline_queries
--;
1556 if (cmd_buffer
->state
.active_pipeline_queries
== 0) {
1557 cmd_buffer
->state
.flush_bits
&= ~RADV_CMD_FLAG_START_PIPELINE_STATS
;
1558 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_STOP_PIPELINE_STATS
;
1560 va
+= pipelinestat_block_size
;
1562 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
1563 radeon_emit(cs
, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT
) | EVENT_INDEX(2));
1564 radeon_emit(cs
, va
);
1565 radeon_emit(cs
, va
>> 32);
1567 si_cs_emit_write_event_eop(cs
,
1568 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
1569 radv_cmd_buffer_uses_mec(cmd_buffer
),
1570 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
1571 EOP_DATA_SEL_VALUE_32BIT
,
1573 cmd_buffer
->gfx9_eop_bug_va
);
1575 case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT
:
1576 radeon_check_space(cmd_buffer
->device
->ws
, cs
, 4);
1578 assert(index
< MAX_SO_STREAMS
);
1580 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
1581 radeon_emit(cs
, EVENT_TYPE(event_type_for_stream(index
)) | EVENT_INDEX(3));
1582 radeon_emit(cs
, (va
+ 16));
1583 radeon_emit(cs
, (va
+ 16) >> 32);
1586 unreachable("ending unhandled query type");
1590 void radv_CmdBeginQueryIndexedEXT(
1591 VkCommandBuffer commandBuffer
,
1592 VkQueryPool queryPool
,
1594 VkQueryControlFlags flags
,
1597 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1598 RADV_FROM_HANDLE(radv_query_pool
, pool
, queryPool
);
1599 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1600 uint64_t va
= radv_buffer_get_va(pool
->bo
);
1602 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, pool
->bo
);
1604 emit_query_flush(cmd_buffer
, pool
);
1606 va
+= pool
->stride
* query
;
1608 emit_begin_query(cmd_buffer
, va
, pool
->type
, flags
, index
);
1611 void radv_CmdBeginQuery(
1612 VkCommandBuffer commandBuffer
,
1613 VkQueryPool queryPool
,
1615 VkQueryControlFlags flags
)
1617 radv_CmdBeginQueryIndexedEXT(commandBuffer
, queryPool
, query
, flags
, 0);
1620 void radv_CmdEndQueryIndexedEXT(
1621 VkCommandBuffer commandBuffer
,
1622 VkQueryPool queryPool
,
1626 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1627 RADV_FROM_HANDLE(radv_query_pool
, pool
, queryPool
);
1628 uint64_t va
= radv_buffer_get_va(pool
->bo
);
1629 uint64_t avail_va
= va
+ pool
->availability_offset
+ 4 * query
;
1630 va
+= pool
->stride
* query
;
1632 /* Do not need to add the pool BO to the list because the query must
1633 * currently be active, which means the BO is already in the list.
1635 emit_end_query(cmd_buffer
, va
, avail_va
, pool
->type
, index
);
1638 * For multiview we have to emit a query for each bit in the mask,
1639 * however the first query we emit will get the totals for all the
1640 * operations, so we don't want to get a real value in the other
1641 * queries. This emits a fake begin/end sequence so the waiting
1642 * code gets a completed query value and doesn't hang, but the
1645 if (cmd_buffer
->state
.subpass
&& cmd_buffer
->state
.subpass
->view_mask
) {
1646 uint64_t avail_va
= va
+ pool
->availability_offset
+ 4 * query
;
1649 for (unsigned i
= 1; i
< util_bitcount(cmd_buffer
->state
.subpass
->view_mask
); i
++) {
1652 emit_begin_query(cmd_buffer
, va
, pool
->type
, 0, 0);
1653 emit_end_query(cmd_buffer
, va
, avail_va
, pool
->type
, 0);
1658 void radv_CmdEndQuery(
1659 VkCommandBuffer commandBuffer
,
1660 VkQueryPool queryPool
,
1663 radv_CmdEndQueryIndexedEXT(commandBuffer
, queryPool
, query
, 0);
1666 void radv_CmdWriteTimestamp(
1667 VkCommandBuffer commandBuffer
,
1668 VkPipelineStageFlagBits pipelineStage
,
1669 VkQueryPool queryPool
,
1672 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1673 RADV_FROM_HANDLE(radv_query_pool
, pool
, queryPool
);
1674 bool mec
= radv_cmd_buffer_uses_mec(cmd_buffer
);
1675 struct radeon_cmdbuf
*cs
= cmd_buffer
->cs
;
1676 uint64_t va
= radv_buffer_get_va(pool
->bo
);
1677 uint64_t query_va
= va
+ pool
->stride
* query
;
1679 radv_cs_add_buffer(cmd_buffer
->device
->ws
, cs
, pool
->bo
);
1681 emit_query_flush(cmd_buffer
, pool
);
1683 int num_queries
= 1;
1684 if (cmd_buffer
->state
.subpass
&& cmd_buffer
->state
.subpass
->view_mask
)
1685 num_queries
= util_bitcount(cmd_buffer
->state
.subpass
->view_mask
);
1687 MAYBE_UNUSED
unsigned cdw_max
= radeon_check_space(cmd_buffer
->device
->ws
, cs
, 28 * num_queries
);
1689 for (unsigned i
= 0; i
< num_queries
; i
++) {
1690 switch(pipelineStage
) {
1691 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
:
1692 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
1693 radeon_emit(cs
, COPY_DATA_COUNT_SEL
| COPY_DATA_WR_CONFIRM
|
1694 COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP
) |
1695 COPY_DATA_DST_SEL(V_370_MEM
));
1698 radeon_emit(cs
, query_va
);
1699 radeon_emit(cs
, query_va
>> 32);
1702 si_cs_emit_write_event_eop(cs
,
1703 cmd_buffer
->device
->physical_device
->rad_info
.chip_class
,
1705 V_028A90_BOTTOM_OF_PIPE_TS
, 0,
1706 EOP_DATA_SEL_TIMESTAMP
,
1708 cmd_buffer
->gfx9_eop_bug_va
);
1711 query_va
+= pool
->stride
;
1713 assert(cmd_buffer
->cs
->cdw
<= cdw_max
);