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radv: add radv_secure_compile_type enum
[mesa.git] / src / amd / vulkan / radv_query.c
1 /*
2 * Copyrigh 2016 Red Hat Inc.
3 * Based on anv:
4 * Copyright © 2015 Intel Corporation
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25
26 #include <assert.h>
27 #include <stdbool.h>
28 #include <string.h>
29 #include <unistd.h>
30 #include <fcntl.h>
31
32 #include "nir/nir_builder.h"
33 #include "radv_meta.h"
34 #include "radv_private.h"
35 #include "radv_cs.h"
36 #include "sid.h"
37
38 #define TIMESTAMP_NOT_READY UINT64_MAX
39
40 static const int pipelinestat_block_size = 11 * 8;
41 static const unsigned pipeline_statistics_indices[] = {7, 6, 3, 4, 5, 2, 1, 0, 8, 9, 10};
42
43 static nir_ssa_def *nir_test_flag(nir_builder *b, nir_ssa_def *flags, uint32_t flag)
44 {
45 return nir_i2b(b, nir_iand(b, flags, nir_imm_int(b, flag)));
46 }
47
48 static void radv_break_on_count(nir_builder *b, nir_variable *var, nir_ssa_def *count)
49 {
50 nir_ssa_def *counter = nir_load_var(b, var);
51
52 nir_if *if_stmt = nir_if_create(b->shader);
53 if_stmt->condition = nir_src_for_ssa(nir_uge(b, counter, count));
54 nir_cf_node_insert(b->cursor, &if_stmt->cf_node);
55
56 b->cursor = nir_after_cf_list(&if_stmt->then_list);
57
58 nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_break);
59 nir_builder_instr_insert(b, &instr->instr);
60
61 b->cursor = nir_after_cf_node(&if_stmt->cf_node);
62 counter = nir_iadd(b, counter, nir_imm_int(b, 1));
63 nir_store_var(b, var, counter, 0x1);
64 }
65
66 static struct nir_ssa_def *
67 radv_load_push_int(nir_builder *b, unsigned offset, const char *name)
68 {
69 nir_intrinsic_instr *flags = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
70 nir_intrinsic_set_base(flags, 0);
71 nir_intrinsic_set_range(flags, 16);
72 flags->src[0] = nir_src_for_ssa(nir_imm_int(b, offset));
73 flags->num_components = 1;
74 nir_ssa_dest_init(&flags->instr, &flags->dest, 1, 32, name);
75 nir_builder_instr_insert(b, &flags->instr);
76 return &flags->dest.ssa;
77 }
78
79 static nir_shader *
80 build_occlusion_query_shader(struct radv_device *device) {
81 /* the shader this builds is roughly
82 *
83 * push constants {
84 * uint32_t flags;
85 * uint32_t dst_stride;
86 * };
87 *
88 * uint32_t src_stride = 16 * db_count;
89 *
90 * location(binding = 0) buffer dst_buf;
91 * location(binding = 1) buffer src_buf;
92 *
93 * void main() {
94 * uint64_t result = 0;
95 * uint64_t src_offset = src_stride * global_id.x;
96 * uint64_t dst_offset = dst_stride * global_id.x;
97 * bool available = true;
98 * for (int i = 0; i < db_count; ++i) {
99 * if (enabled_rb_mask & (1 << i)) {
100 * uint64_t start = src_buf[src_offset + 16 * i];
101 * uint64_t end = src_buf[src_offset + 16 * i + 8];
102 * if ((start & (1ull << 63)) && (end & (1ull << 63)))
103 * result += end - start;
104 * else
105 * available = false;
106 * }
107 * }
108 * uint32_t elem_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;
109 * if ((flags & VK_QUERY_RESULT_PARTIAL_BIT) || available) {
110 * if (flags & VK_QUERY_RESULT_64_BIT)
111 * dst_buf[dst_offset] = result;
112 * else
113 * dst_buf[dst_offset] = (uint32_t)result.
114 * }
115 * if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
116 * dst_buf[dst_offset + elem_size] = available;
117 * }
118 * }
119 */
120 nir_builder b;
121 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
122 b.shader->info.name = ralloc_strdup(b.shader, "occlusion_query");
123 b.shader->info.cs.local_size[0] = 64;
124 b.shader->info.cs.local_size[1] = 1;
125 b.shader->info.cs.local_size[2] = 1;
126
127 nir_variable *result = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "result");
128 nir_variable *outer_counter = nir_local_variable_create(b.impl, glsl_int_type(), "outer_counter");
129 nir_variable *start = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "start");
130 nir_variable *end = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "end");
131 nir_variable *available = nir_local_variable_create(b.impl, glsl_bool_type(), "available");
132 unsigned enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask;
133 unsigned db_count = device->physical_device->rad_info.num_render_backends;
134
135 nir_ssa_def *flags = radv_load_push_int(&b, 0, "flags");
136
137 nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
138 nir_intrinsic_vulkan_resource_index);
139 dst_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
140 dst_buf->num_components = 1;
141 nir_intrinsic_set_desc_set(dst_buf, 0);
142 nir_intrinsic_set_binding(dst_buf, 0);
143 nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, dst_buf->num_components, 32, NULL);
144 nir_builder_instr_insert(&b, &dst_buf->instr);
145
146 nir_intrinsic_instr *src_buf = nir_intrinsic_instr_create(b.shader,
147 nir_intrinsic_vulkan_resource_index);
148 src_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
149 src_buf->num_components = 1;
150 nir_intrinsic_set_desc_set(src_buf, 0);
151 nir_intrinsic_set_binding(src_buf, 1);
152 nir_ssa_dest_init(&src_buf->instr, &src_buf->dest, src_buf->num_components, 32, NULL);
153 nir_builder_instr_insert(&b, &src_buf->instr);
154
155 nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
156 nir_ssa_def *wg_id = nir_load_work_group_id(&b);
157 nir_ssa_def *block_size = nir_imm_ivec4(&b,
158 b.shader->info.cs.local_size[0],
159 b.shader->info.cs.local_size[1],
160 b.shader->info.cs.local_size[2], 0);
161 nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
162 global_id = nir_channel(&b, global_id, 0); // We only care about x here.
163
164 nir_ssa_def *input_stride = nir_imm_int(&b, db_count * 16);
165 nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id);
166 nir_ssa_def *output_stride = radv_load_push_int(&b, 4, "output_stride");
167 nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id);
168
169
170 nir_store_var(&b, result, nir_imm_int64(&b, 0), 0x1);
171 nir_store_var(&b, outer_counter, nir_imm_int(&b, 0), 0x1);
172 nir_store_var(&b, available, nir_imm_true(&b), 0x1);
173
174 nir_loop *outer_loop = nir_loop_create(b.shader);
175 nir_builder_cf_insert(&b, &outer_loop->cf_node);
176 b.cursor = nir_after_cf_list(&outer_loop->body);
177
178 nir_ssa_def *current_outer_count = nir_load_var(&b, outer_counter);
179 radv_break_on_count(&b, outer_counter, nir_imm_int(&b, db_count));
180
181 nir_ssa_def *enabled_cond =
182 nir_iand(&b, nir_imm_int(&b, enabled_rb_mask),
183 nir_ishl(&b, nir_imm_int(&b, 1), current_outer_count));
184
185 nir_if *enabled_if = nir_if_create(b.shader);
186 enabled_if->condition = nir_src_for_ssa(nir_i2b(&b, enabled_cond));
187 nir_cf_node_insert(b.cursor, &enabled_if->cf_node);
188
189 b.cursor = nir_after_cf_list(&enabled_if->then_list);
190
191 nir_ssa_def *load_offset = nir_imul(&b, current_outer_count, nir_imm_int(&b, 16));
192 load_offset = nir_iadd(&b, input_base, load_offset);
193
194 nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
195 load->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
196 load->src[1] = nir_src_for_ssa(load_offset);
197 nir_ssa_dest_init(&load->instr, &load->dest, 2, 64, NULL);
198 load->num_components = 2;
199 nir_builder_instr_insert(&b, &load->instr);
200
201 nir_store_var(&b, start, nir_channel(&b, &load->dest.ssa, 0), 0x1);
202 nir_store_var(&b, end, nir_channel(&b, &load->dest.ssa, 1), 0x1);
203
204 nir_ssa_def *start_done = nir_ilt(&b, nir_load_var(&b, start), nir_imm_int64(&b, 0));
205 nir_ssa_def *end_done = nir_ilt(&b, nir_load_var(&b, end), nir_imm_int64(&b, 0));
206
207 nir_if *update_if = nir_if_create(b.shader);
208 update_if->condition = nir_src_for_ssa(nir_iand(&b, start_done, end_done));
209 nir_cf_node_insert(b.cursor, &update_if->cf_node);
210
211 b.cursor = nir_after_cf_list(&update_if->then_list);
212
213 nir_store_var(&b, result,
214 nir_iadd(&b, nir_load_var(&b, result),
215 nir_isub(&b, nir_load_var(&b, end),
216 nir_load_var(&b, start))), 0x1);
217
218 b.cursor = nir_after_cf_list(&update_if->else_list);
219
220 nir_store_var(&b, available, nir_imm_false(&b), 0x1);
221
222 b.cursor = nir_after_cf_node(&outer_loop->cf_node);
223
224 /* Store the result if complete or if partial results have been requested. */
225
226 nir_ssa_def *result_is_64bit = nir_test_flag(&b, flags, VK_QUERY_RESULT_64_BIT);
227 nir_ssa_def *result_size = nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 8), nir_imm_int(&b, 4));
228
229 nir_if *store_if = nir_if_create(b.shader);
230 store_if->condition = nir_src_for_ssa(nir_ior(&b, nir_test_flag(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT), nir_load_var(&b, available)));
231 nir_cf_node_insert(b.cursor, &store_if->cf_node);
232
233 b.cursor = nir_after_cf_list(&store_if->then_list);
234
235 nir_if *store_64bit_if = nir_if_create(b.shader);
236 store_64bit_if->condition = nir_src_for_ssa(result_is_64bit);
237 nir_cf_node_insert(b.cursor, &store_64bit_if->cf_node);
238
239 b.cursor = nir_after_cf_list(&store_64bit_if->then_list);
240
241 nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
242 store->src[0] = nir_src_for_ssa(nir_load_var(&b, result));
243 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
244 store->src[2] = nir_src_for_ssa(output_base);
245 nir_intrinsic_set_write_mask(store, 0x1);
246 store->num_components = 1;
247 nir_builder_instr_insert(&b, &store->instr);
248
249 b.cursor = nir_after_cf_list(&store_64bit_if->else_list);
250
251 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
252 store->src[0] = nir_src_for_ssa(nir_u2u32(&b, nir_load_var(&b, result)));
253 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
254 store->src[2] = nir_src_for_ssa(output_base);
255 nir_intrinsic_set_write_mask(store, 0x1);
256 store->num_components = 1;
257 nir_builder_instr_insert(&b, &store->instr);
258
259 b.cursor = nir_after_cf_node(&store_if->cf_node);
260
261 /* Store the availability bit if requested. */
262
263 nir_if *availability_if = nir_if_create(b.shader);
264 availability_if->condition = nir_src_for_ssa(nir_test_flag(&b, flags, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT));
265 nir_cf_node_insert(b.cursor, &availability_if->cf_node);
266
267 b.cursor = nir_after_cf_list(&availability_if->then_list);
268
269 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
270 store->src[0] = nir_src_for_ssa(nir_b2i32(&b, nir_load_var(&b, available)));
271 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
272 store->src[2] = nir_src_for_ssa(nir_iadd(&b, result_size, output_base));
273 nir_intrinsic_set_write_mask(store, 0x1);
274 store->num_components = 1;
275 nir_builder_instr_insert(&b, &store->instr);
276
277 return b.shader;
278 }
279
280 static nir_shader *
281 build_pipeline_statistics_query_shader(struct radv_device *device) {
282 /* the shader this builds is roughly
283 *
284 * push constants {
285 * uint32_t flags;
286 * uint32_t dst_stride;
287 * uint32_t stats_mask;
288 * uint32_t avail_offset;
289 * };
290 *
291 * uint32_t src_stride = pipelinestat_block_size * 2;
292 *
293 * location(binding = 0) buffer dst_buf;
294 * location(binding = 1) buffer src_buf;
295 *
296 * void main() {
297 * uint64_t src_offset = src_stride * global_id.x;
298 * uint64_t dst_base = dst_stride * global_id.x;
299 * uint64_t dst_offset = dst_base;
300 * uint32_t elem_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;
301 * uint32_t elem_count = stats_mask >> 16;
302 * uint32_t available32 = src_buf[avail_offset + 4 * global_id.x];
303 * if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
304 * dst_buf[dst_offset + elem_count * elem_size] = available32;
305 * }
306 * if ((bool)available32) {
307 * // repeat 11 times:
308 * if (stats_mask & (1 << 0)) {
309 * uint64_t start = src_buf[src_offset + 8 * indices[0]];
310 * uint64_t end = src_buf[src_offset + 8 * indices[0] + pipelinestat_block_size];
311 * uint64_t result = end - start;
312 * if (flags & VK_QUERY_RESULT_64_BIT)
313 * dst_buf[dst_offset] = result;
314 * else
315 * dst_buf[dst_offset] = (uint32_t)result.
316 * dst_offset += elem_size;
317 * }
318 * } else if (flags & VK_QUERY_RESULT_PARTIAL_BIT) {
319 * // Set everything to 0 as we don't know what is valid.
320 * for (int i = 0; i < elem_count; ++i)
321 * dst_buf[dst_base + elem_size * i] = 0;
322 * }
323 * }
324 */
325 nir_builder b;
326 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
327 b.shader->info.name = ralloc_strdup(b.shader, "pipeline_statistics_query");
328 b.shader->info.cs.local_size[0] = 64;
329 b.shader->info.cs.local_size[1] = 1;
330 b.shader->info.cs.local_size[2] = 1;
331
332 nir_variable *output_offset = nir_local_variable_create(b.impl, glsl_int_type(), "output_offset");
333
334 nir_ssa_def *flags = radv_load_push_int(&b, 0, "flags");
335 nir_ssa_def *stats_mask = radv_load_push_int(&b, 8, "stats_mask");
336 nir_ssa_def *avail_offset = radv_load_push_int(&b, 12, "avail_offset");
337
338 nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
339 nir_intrinsic_vulkan_resource_index);
340 dst_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
341 dst_buf->num_components = 1;;
342 nir_intrinsic_set_desc_set(dst_buf, 0);
343 nir_intrinsic_set_binding(dst_buf, 0);
344 nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, dst_buf->num_components, 32, NULL);
345 nir_builder_instr_insert(&b, &dst_buf->instr);
346
347 nir_intrinsic_instr *src_buf = nir_intrinsic_instr_create(b.shader,
348 nir_intrinsic_vulkan_resource_index);
349 src_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
350 src_buf->num_components = 1;
351 nir_intrinsic_set_desc_set(src_buf, 0);
352 nir_intrinsic_set_binding(src_buf, 1);
353 nir_ssa_dest_init(&src_buf->instr, &src_buf->dest, src_buf->num_components, 32, NULL);
354 nir_builder_instr_insert(&b, &src_buf->instr);
355
356 nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
357 nir_ssa_def *wg_id = nir_load_work_group_id(&b);
358 nir_ssa_def *block_size = nir_imm_ivec4(&b,
359 b.shader->info.cs.local_size[0],
360 b.shader->info.cs.local_size[1],
361 b.shader->info.cs.local_size[2], 0);
362 nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
363 global_id = nir_channel(&b, global_id, 0); // We only care about x here.
364
365 nir_ssa_def *input_stride = nir_imm_int(&b, pipelinestat_block_size * 2);
366 nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id);
367 nir_ssa_def *output_stride = radv_load_push_int(&b, 4, "output_stride");
368 nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id);
369
370
371 avail_offset = nir_iadd(&b, avail_offset,
372 nir_imul(&b, global_id, nir_imm_int(&b, 4)));
373
374 nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
375 load->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
376 load->src[1] = nir_src_for_ssa(avail_offset);
377 nir_ssa_dest_init(&load->instr, &load->dest, 1, 32, NULL);
378 load->num_components = 1;
379 nir_builder_instr_insert(&b, &load->instr);
380 nir_ssa_def *available32 = &load->dest.ssa;
381
382 nir_ssa_def *result_is_64bit = nir_test_flag(&b, flags, VK_QUERY_RESULT_64_BIT);
383 nir_ssa_def *elem_size = nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 8), nir_imm_int(&b, 4));
384 nir_ssa_def *elem_count = nir_ushr(&b, stats_mask, nir_imm_int(&b, 16));
385
386 /* Store the availability bit if requested. */
387
388 nir_if *availability_if = nir_if_create(b.shader);
389 availability_if->condition = nir_src_for_ssa(nir_test_flag(&b, flags, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT));
390 nir_cf_node_insert(b.cursor, &availability_if->cf_node);
391
392 b.cursor = nir_after_cf_list(&availability_if->then_list);
393
394 nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
395 store->src[0] = nir_src_for_ssa(available32);
396 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
397 store->src[2] = nir_src_for_ssa(nir_iadd(&b, output_base, nir_imul(&b, elem_count, elem_size)));
398 nir_intrinsic_set_write_mask(store, 0x1);
399 store->num_components = 1;
400 nir_builder_instr_insert(&b, &store->instr);
401
402 b.cursor = nir_after_cf_node(&availability_if->cf_node);
403
404 nir_if *available_if = nir_if_create(b.shader);
405 available_if->condition = nir_src_for_ssa(nir_i2b(&b, available32));
406 nir_cf_node_insert(b.cursor, &available_if->cf_node);
407
408 b.cursor = nir_after_cf_list(&available_if->then_list);
409
410 nir_store_var(&b, output_offset, output_base, 0x1);
411 for (int i = 0; i < 11; ++i) {
412 nir_if *store_if = nir_if_create(b.shader);
413 store_if->condition = nir_src_for_ssa(nir_test_flag(&b, stats_mask, 1u << i));
414 nir_cf_node_insert(b.cursor, &store_if->cf_node);
415
416 b.cursor = nir_after_cf_list(&store_if->then_list);
417
418 load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
419 load->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
420 load->src[1] = nir_src_for_ssa(nir_iadd(&b, input_base,
421 nir_imm_int(&b, pipeline_statistics_indices[i] * 8)));
422 nir_ssa_dest_init(&load->instr, &load->dest, 1, 64, NULL);
423 load->num_components = 1;
424 nir_builder_instr_insert(&b, &load->instr);
425 nir_ssa_def *start = &load->dest.ssa;
426
427 load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
428 load->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
429 load->src[1] = nir_src_for_ssa(nir_iadd(&b, input_base,
430 nir_imm_int(&b, pipeline_statistics_indices[i] * 8 + pipelinestat_block_size)));
431 nir_ssa_dest_init(&load->instr, &load->dest, 1, 64, NULL);
432 load->num_components = 1;
433 nir_builder_instr_insert(&b, &load->instr);
434 nir_ssa_def *end = &load->dest.ssa;
435
436 nir_ssa_def *result = nir_isub(&b, end, start);
437
438 /* Store result */
439 nir_if *store_64bit_if = nir_if_create(b.shader);
440 store_64bit_if->condition = nir_src_for_ssa(result_is_64bit);
441 nir_cf_node_insert(b.cursor, &store_64bit_if->cf_node);
442
443 b.cursor = nir_after_cf_list(&store_64bit_if->then_list);
444
445 nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
446 store->src[0] = nir_src_for_ssa(result);
447 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
448 store->src[2] = nir_src_for_ssa(nir_load_var(&b, output_offset));
449 nir_intrinsic_set_write_mask(store, 0x1);
450 store->num_components = 1;
451 nir_builder_instr_insert(&b, &store->instr);
452
453 b.cursor = nir_after_cf_list(&store_64bit_if->else_list);
454
455 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
456 store->src[0] = nir_src_for_ssa(nir_u2u32(&b, result));
457 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
458 store->src[2] = nir_src_for_ssa(nir_load_var(&b, output_offset));
459 nir_intrinsic_set_write_mask(store, 0x1);
460 store->num_components = 1;
461 nir_builder_instr_insert(&b, &store->instr);
462
463 b.cursor = nir_after_cf_node(&store_64bit_if->cf_node);
464
465 nir_store_var(&b, output_offset,
466 nir_iadd(&b, nir_load_var(&b, output_offset),
467 elem_size), 0x1);
468
469 b.cursor = nir_after_cf_node(&store_if->cf_node);
470 }
471
472 b.cursor = nir_after_cf_list(&available_if->else_list);
473
474 available_if = nir_if_create(b.shader);
475 available_if->condition = nir_src_for_ssa(nir_test_flag(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT));
476 nir_cf_node_insert(b.cursor, &available_if->cf_node);
477
478 b.cursor = nir_after_cf_list(&available_if->then_list);
479
480 /* Stores zeros in all outputs. */
481
482 nir_variable *counter = nir_local_variable_create(b.impl, glsl_int_type(), "counter");
483 nir_store_var(&b, counter, nir_imm_int(&b, 0), 0x1);
484
485 nir_loop *loop = nir_loop_create(b.shader);
486 nir_builder_cf_insert(&b, &loop->cf_node);
487 b.cursor = nir_after_cf_list(&loop->body);
488
489 nir_ssa_def *current_counter = nir_load_var(&b, counter);
490 radv_break_on_count(&b, counter, elem_count);
491
492 nir_ssa_def *output_elem = nir_iadd(&b, output_base,
493 nir_imul(&b, elem_size, current_counter));
494
495 nir_if *store_64bit_if = nir_if_create(b.shader);
496 store_64bit_if->condition = nir_src_for_ssa(result_is_64bit);
497 nir_cf_node_insert(b.cursor, &store_64bit_if->cf_node);
498
499 b.cursor = nir_after_cf_list(&store_64bit_if->then_list);
500
501 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
502 store->src[0] = nir_src_for_ssa(nir_imm_int64(&b, 0));
503 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
504 store->src[2] = nir_src_for_ssa(output_elem);
505 nir_intrinsic_set_write_mask(store, 0x1);
506 store->num_components = 1;
507 nir_builder_instr_insert(&b, &store->instr);
508
509 b.cursor = nir_after_cf_list(&store_64bit_if->else_list);
510
511 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
512 store->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
513 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
514 store->src[2] = nir_src_for_ssa(output_elem);
515 nir_intrinsic_set_write_mask(store, 0x1);
516 store->num_components = 1;
517 nir_builder_instr_insert(&b, &store->instr);
518
519 b.cursor = nir_after_cf_node(&loop->cf_node);
520 return b.shader;
521 }
522
523 static nir_shader *
524 build_tfb_query_shader(struct radv_device *device)
525 {
526 /* the shader this builds is roughly
527 *
528 * uint32_t src_stride = 32;
529 *
530 * location(binding = 0) buffer dst_buf;
531 * location(binding = 1) buffer src_buf;
532 *
533 * void main() {
534 * uint64_t result[2] = {};
535 * bool available = false;
536 * uint64_t src_offset = src_stride * global_id.x;
537 * uint64_t dst_offset = dst_stride * global_id.x;
538 * uint64_t *src_data = src_buf[src_offset];
539 * uint32_t avail = (src_data[0] >> 32) &
540 * (src_data[1] >> 32) &
541 * (src_data[2] >> 32) &
542 * (src_data[3] >> 32);
543 * if (avail & 0x80000000) {
544 * result[0] = src_data[3] - src_data[1];
545 * result[1] = src_data[2] - src_data[0];
546 * available = true;
547 * }
548 * uint32_t result_size = flags & VK_QUERY_RESULT_64_BIT ? 16 : 8;
549 * if ((flags & VK_QUERY_RESULT_PARTIAL_BIT) || available) {
550 * if (flags & VK_QUERY_RESULT_64_BIT) {
551 * dst_buf[dst_offset] = result;
552 * } else {
553 * dst_buf[dst_offset] = (uint32_t)result;
554 * }
555 * }
556 * if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
557 * dst_buf[dst_offset + result_size] = available;
558 * }
559 * }
560 */
561 nir_builder b;
562 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
563 b.shader->info.name = ralloc_strdup(b.shader, "tfb_query");
564 b.shader->info.cs.local_size[0] = 64;
565 b.shader->info.cs.local_size[1] = 1;
566 b.shader->info.cs.local_size[2] = 1;
567
568 /* Create and initialize local variables. */
569 nir_variable *result =
570 nir_local_variable_create(b.impl,
571 glsl_vector_type(GLSL_TYPE_UINT64, 2),
572 "result");
573 nir_variable *available =
574 nir_local_variable_create(b.impl, glsl_bool_type(), "available");
575
576 nir_store_var(&b, result,
577 nir_vec2(&b, nir_imm_int64(&b, 0),
578 nir_imm_int64(&b, 0)), 0x3);
579 nir_store_var(&b, available, nir_imm_false(&b), 0x1);
580
581 nir_ssa_def *flags = radv_load_push_int(&b, 0, "flags");
582
583 /* Load resources. */
584 nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
585 nir_intrinsic_vulkan_resource_index);
586 dst_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
587 dst_buf->num_components = 1;
588 nir_intrinsic_set_desc_set(dst_buf, 0);
589 nir_intrinsic_set_binding(dst_buf, 0);
590 nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, dst_buf->num_components, 32, NULL);
591 nir_builder_instr_insert(&b, &dst_buf->instr);
592
593 nir_intrinsic_instr *src_buf = nir_intrinsic_instr_create(b.shader,
594 nir_intrinsic_vulkan_resource_index);
595 src_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
596 src_buf->num_components = 1;
597 nir_intrinsic_set_desc_set(src_buf, 0);
598 nir_intrinsic_set_binding(src_buf, 1);
599 nir_ssa_dest_init(&src_buf->instr, &src_buf->dest, src_buf->num_components, 32, NULL);
600 nir_builder_instr_insert(&b, &src_buf->instr);
601
602 /* Compute global ID. */
603 nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
604 nir_ssa_def *wg_id = nir_load_work_group_id(&b);
605 nir_ssa_def *block_size = nir_imm_ivec4(&b,
606 b.shader->info.cs.local_size[0],
607 b.shader->info.cs.local_size[1],
608 b.shader->info.cs.local_size[2], 0);
609 nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
610 global_id = nir_channel(&b, global_id, 0); // We only care about x here.
611
612 /* Compute src/dst strides. */
613 nir_ssa_def *input_stride = nir_imm_int(&b, 32);
614 nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id);
615 nir_ssa_def *output_stride = radv_load_push_int(&b, 4, "output_stride");
616 nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id);
617
618 /* Load data from the query pool. */
619 nir_intrinsic_instr *load1 = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
620 load1->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
621 load1->src[1] = nir_src_for_ssa(input_base);
622 nir_ssa_dest_init(&load1->instr, &load1->dest, 4, 32, NULL);
623 load1->num_components = 4;
624 nir_builder_instr_insert(&b, &load1->instr);
625
626 nir_intrinsic_instr *load2 = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
627 load2->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
628 load2->src[1] = nir_src_for_ssa(nir_iadd(&b, input_base, nir_imm_int(&b, 16)));
629 nir_ssa_dest_init(&load2->instr, &load2->dest, 4, 32, NULL);
630 load2->num_components = 4;
631 nir_builder_instr_insert(&b, &load2->instr);
632
633 /* Check if result is available. */
634 nir_ssa_def *avails[2];
635 avails[0] = nir_iand(&b, nir_channel(&b, &load1->dest.ssa, 1),
636 nir_channel(&b, &load1->dest.ssa, 3));
637 avails[1] = nir_iand(&b, nir_channel(&b, &load2->dest.ssa, 1),
638 nir_channel(&b, &load2->dest.ssa, 3));
639 nir_ssa_def *result_is_available =
640 nir_i2b(&b, nir_iand(&b, nir_iand(&b, avails[0], avails[1]),
641 nir_imm_int(&b, 0x80000000)));
642
643 /* Only compute result if available. */
644 nir_if *available_if = nir_if_create(b.shader);
645 available_if->condition = nir_src_for_ssa(result_is_available);
646 nir_cf_node_insert(b.cursor, &available_if->cf_node);
647
648 b.cursor = nir_after_cf_list(&available_if->then_list);
649
650 /* Pack values. */
651 nir_ssa_def *packed64[4];
652 packed64[0] = nir_pack_64_2x32(&b, nir_vec2(&b,
653 nir_channel(&b, &load1->dest.ssa, 0),
654 nir_channel(&b, &load1->dest.ssa, 1)));
655 packed64[1] = nir_pack_64_2x32(&b, nir_vec2(&b,
656 nir_channel(&b, &load1->dest.ssa, 2),
657 nir_channel(&b, &load1->dest.ssa, 3)));
658 packed64[2] = nir_pack_64_2x32(&b, nir_vec2(&b,
659 nir_channel(&b, &load2->dest.ssa, 0),
660 nir_channel(&b, &load2->dest.ssa, 1)));
661 packed64[3] = nir_pack_64_2x32(&b, nir_vec2(&b,
662 nir_channel(&b, &load2->dest.ssa, 2),
663 nir_channel(&b, &load2->dest.ssa, 3)));
664
665 /* Compute result. */
666 nir_ssa_def *num_primitive_written =
667 nir_isub(&b, packed64[3], packed64[1]);
668 nir_ssa_def *primitive_storage_needed =
669 nir_isub(&b, packed64[2], packed64[0]);
670
671 nir_store_var(&b, result,
672 nir_vec2(&b, num_primitive_written,
673 primitive_storage_needed), 0x3);
674 nir_store_var(&b, available, nir_imm_true(&b), 0x1);
675
676 b.cursor = nir_after_cf_node(&available_if->cf_node);
677
678 /* Determine if result is 64 or 32 bit. */
679 nir_ssa_def *result_is_64bit =
680 nir_test_flag(&b, flags, VK_QUERY_RESULT_64_BIT);
681 nir_ssa_def *result_size =
682 nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 16),
683 nir_imm_int(&b, 8));
684
685 /* Store the result if complete or partial results have been requested. */
686 nir_if *store_if = nir_if_create(b.shader);
687 store_if->condition =
688 nir_src_for_ssa(nir_ior(&b, nir_test_flag(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT),
689 nir_load_var(&b, available)));
690 nir_cf_node_insert(b.cursor, &store_if->cf_node);
691
692 b.cursor = nir_after_cf_list(&store_if->then_list);
693
694 /* Store result. */
695 nir_if *store_64bit_if = nir_if_create(b.shader);
696 store_64bit_if->condition = nir_src_for_ssa(result_is_64bit);
697 nir_cf_node_insert(b.cursor, &store_64bit_if->cf_node);
698
699 b.cursor = nir_after_cf_list(&store_64bit_if->then_list);
700
701 nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
702 store->src[0] = nir_src_for_ssa(nir_load_var(&b, result));
703 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
704 store->src[2] = nir_src_for_ssa(output_base);
705 nir_intrinsic_set_write_mask(store, 0x3);
706 store->num_components = 2;
707 nir_builder_instr_insert(&b, &store->instr);
708
709 b.cursor = nir_after_cf_list(&store_64bit_if->else_list);
710
711 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
712 store->src[0] = nir_src_for_ssa(nir_u2u32(&b, nir_load_var(&b, result)));
713 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
714 store->src[2] = nir_src_for_ssa(output_base);
715 nir_intrinsic_set_write_mask(store, 0x3);
716 store->num_components = 2;
717 nir_builder_instr_insert(&b, &store->instr);
718
719 b.cursor = nir_after_cf_node(&store_64bit_if->cf_node);
720
721 b.cursor = nir_after_cf_node(&store_if->cf_node);
722
723 /* Store the availability bit if requested. */
724 nir_if *availability_if = nir_if_create(b.shader);
725 availability_if->condition =
726 nir_src_for_ssa(nir_test_flag(&b, flags, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT));
727 nir_cf_node_insert(b.cursor, &availability_if->cf_node);
728
729 b.cursor = nir_after_cf_list(&availability_if->then_list);
730
731 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
732 store->src[0] = nir_src_for_ssa(nir_b2i32(&b, nir_load_var(&b, available)));
733 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
734 store->src[2] = nir_src_for_ssa(nir_iadd(&b, result_size, output_base));
735 nir_intrinsic_set_write_mask(store, 0x1);
736 store->num_components = 1;
737 nir_builder_instr_insert(&b, &store->instr);
738
739 b.cursor = nir_after_cf_node(&availability_if->cf_node);
740
741 return b.shader;
742 }
743
744 static nir_shader *
745 build_timestamp_query_shader(struct radv_device *device)
746 {
747 /* the shader this builds is roughly
748 *
749 * uint32_t src_stride = 8;
750 *
751 * location(binding = 0) buffer dst_buf;
752 * location(binding = 1) buffer src_buf;
753 *
754 * void main() {
755 * uint64_t result = 0;
756 * bool available = false;
757 * uint64_t src_offset = src_stride * global_id.x;
758 * uint64_t dst_offset = dst_stride * global_id.x;
759 * uint64_t timestamp = src_buf[src_offset];
760 * if (timestamp != TIMESTAMP_NOT_READY) {
761 * result = timestamp;
762 * available = true;
763 * }
764 * uint32_t result_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;
765 * if ((flags & VK_QUERY_RESULT_PARTIAL_BIT) || available) {
766 * if (flags & VK_QUERY_RESULT_64_BIT) {
767 * dst_buf[dst_offset] = result;
768 * } else {
769 * dst_buf[dst_offset] = (uint32_t)result;
770 * }
771 * }
772 * if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
773 * dst_buf[dst_offset + result_size] = available;
774 * }
775 * }
776 */
777 nir_builder b;
778 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
779 b.shader->info.name = ralloc_strdup(b.shader, "timestamp_query");
780 b.shader->info.cs.local_size[0] = 64;
781 b.shader->info.cs.local_size[1] = 1;
782 b.shader->info.cs.local_size[2] = 1;
783
784 /* Create and initialize local variables. */
785 nir_variable *result =
786 nir_local_variable_create(b.impl, glsl_uint64_t_type(), "result");
787 nir_variable *available =
788 nir_local_variable_create(b.impl, glsl_bool_type(), "available");
789
790 nir_store_var(&b, result, nir_imm_int64(&b, 0), 0x1);
791 nir_store_var(&b, available, nir_imm_false(&b), 0x1);
792
793 nir_ssa_def *flags = radv_load_push_int(&b, 0, "flags");
794
795 /* Load resources. */
796 nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
797 nir_intrinsic_vulkan_resource_index);
798 dst_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
799 dst_buf->num_components = 1;
800 nir_intrinsic_set_desc_set(dst_buf, 0);
801 nir_intrinsic_set_binding(dst_buf, 0);
802 nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, dst_buf->num_components, 32, NULL);
803 nir_builder_instr_insert(&b, &dst_buf->instr);
804
805 nir_intrinsic_instr *src_buf = nir_intrinsic_instr_create(b.shader,
806 nir_intrinsic_vulkan_resource_index);
807 src_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
808 src_buf->num_components = 1;
809 nir_intrinsic_set_desc_set(src_buf, 0);
810 nir_intrinsic_set_binding(src_buf, 1);
811 nir_ssa_dest_init(&src_buf->instr, &src_buf->dest, src_buf->num_components, 32, NULL);
812 nir_builder_instr_insert(&b, &src_buf->instr);
813
814 /* Compute global ID. */
815 nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b);
816 nir_ssa_def *wg_id = nir_load_work_group_id(&b);
817 nir_ssa_def *block_size = nir_imm_ivec4(&b,
818 b.shader->info.cs.local_size[0],
819 b.shader->info.cs.local_size[1],
820 b.shader->info.cs.local_size[2], 0);
821 nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
822 global_id = nir_channel(&b, global_id, 0); // We only care about x here.
823
824 /* Compute src/dst strides. */
825 nir_ssa_def *input_stride = nir_imm_int(&b, 8);
826 nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id);
827 nir_ssa_def *output_stride = radv_load_push_int(&b, 4, "output_stride");
828 nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id);
829
830 /* Load data from the query pool. */
831 nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
832 load->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
833 load->src[1] = nir_src_for_ssa(input_base);
834 nir_ssa_dest_init(&load->instr, &load->dest, 2, 32, NULL);
835 load->num_components = 2;
836 nir_builder_instr_insert(&b, &load->instr);
837
838 /* Pack the timestamp. */
839 nir_ssa_def *timestamp;
840 timestamp = nir_pack_64_2x32(&b, nir_vec2(&b,
841 nir_channel(&b, &load->dest.ssa, 0),
842 nir_channel(&b, &load->dest.ssa, 1)));
843
844 /* Check if result is available. */
845 nir_ssa_def *result_is_available =
846 nir_i2b(&b, nir_ine(&b, timestamp,
847 nir_imm_int64(&b, TIMESTAMP_NOT_READY)));
848
849 /* Only store result if available. */
850 nir_if *available_if = nir_if_create(b.shader);
851 available_if->condition = nir_src_for_ssa(result_is_available);
852 nir_cf_node_insert(b.cursor, &available_if->cf_node);
853
854 b.cursor = nir_after_cf_list(&available_if->then_list);
855
856 nir_store_var(&b, result, timestamp, 0x1);
857 nir_store_var(&b, available, nir_imm_true(&b), 0x1);
858
859 b.cursor = nir_after_cf_node(&available_if->cf_node);
860
861 /* Determine if result is 64 or 32 bit. */
862 nir_ssa_def *result_is_64bit =
863 nir_test_flag(&b, flags, VK_QUERY_RESULT_64_BIT);
864 nir_ssa_def *result_size =
865 nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 8),
866 nir_imm_int(&b, 4));
867
868 /* Store the result if complete or partial results have been requested. */
869 nir_if *store_if = nir_if_create(b.shader);
870 store_if->condition =
871 nir_src_for_ssa(nir_ior(&b, nir_test_flag(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT),
872 nir_load_var(&b, available)));
873 nir_cf_node_insert(b.cursor, &store_if->cf_node);
874
875 b.cursor = nir_after_cf_list(&store_if->then_list);
876
877 /* Store result. */
878 nir_if *store_64bit_if = nir_if_create(b.shader);
879 store_64bit_if->condition = nir_src_for_ssa(result_is_64bit);
880 nir_cf_node_insert(b.cursor, &store_64bit_if->cf_node);
881
882 b.cursor = nir_after_cf_list(&store_64bit_if->then_list);
883
884 nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
885 store->src[0] = nir_src_for_ssa(nir_load_var(&b, result));
886 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
887 store->src[2] = nir_src_for_ssa(output_base);
888 nir_intrinsic_set_write_mask(store, 0x1);
889 store->num_components = 1;
890 nir_builder_instr_insert(&b, &store->instr);
891
892 b.cursor = nir_after_cf_list(&store_64bit_if->else_list);
893
894 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
895 store->src[0] = nir_src_for_ssa(nir_u2u32(&b, nir_load_var(&b, result)));
896 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
897 store->src[2] = nir_src_for_ssa(output_base);
898 nir_intrinsic_set_write_mask(store, 0x1);
899 store->num_components = 1;
900 nir_builder_instr_insert(&b, &store->instr);
901
902 b.cursor = nir_after_cf_node(&store_64bit_if->cf_node);
903
904 b.cursor = nir_after_cf_node(&store_if->cf_node);
905
906 /* Store the availability bit if requested. */
907 nir_if *availability_if = nir_if_create(b.shader);
908 availability_if->condition =
909 nir_src_for_ssa(nir_test_flag(&b, flags, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT));
910 nir_cf_node_insert(b.cursor, &availability_if->cf_node);
911
912 b.cursor = nir_after_cf_list(&availability_if->then_list);
913
914 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
915 store->src[0] = nir_src_for_ssa(nir_b2i32(&b, nir_load_var(&b, available)));
916 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
917 store->src[2] = nir_src_for_ssa(nir_iadd(&b, result_size, output_base));
918 nir_intrinsic_set_write_mask(store, 0x1);
919 store->num_components = 1;
920 nir_builder_instr_insert(&b, &store->instr);
921
922 b.cursor = nir_after_cf_node(&availability_if->cf_node);
923
924 return b.shader;
925 }
926
927 static VkResult radv_device_init_meta_query_state_internal(struct radv_device *device)
928 {
929 VkResult result;
930 struct radv_shader_module occlusion_cs = { .nir = NULL };
931 struct radv_shader_module pipeline_statistics_cs = { .nir = NULL };
932 struct radv_shader_module tfb_cs = { .nir = NULL };
933 struct radv_shader_module timestamp_cs = { .nir = NULL };
934
935 mtx_lock(&device->meta_state.mtx);
936 if (device->meta_state.query.pipeline_statistics_query_pipeline) {
937 mtx_unlock(&device->meta_state.mtx);
938 return VK_SUCCESS;
939 }
940 occlusion_cs.nir = build_occlusion_query_shader(device);
941 pipeline_statistics_cs.nir = build_pipeline_statistics_query_shader(device);
942 tfb_cs.nir = build_tfb_query_shader(device);
943 timestamp_cs.nir = build_timestamp_query_shader(device);
944
945 VkDescriptorSetLayoutCreateInfo occlusion_ds_create_info = {
946 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
947 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
948 .bindingCount = 2,
949 .pBindings = (VkDescriptorSetLayoutBinding[]) {
950 {
951 .binding = 0,
952 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
953 .descriptorCount = 1,
954 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
955 .pImmutableSamplers = NULL
956 },
957 {
958 .binding = 1,
959 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
960 .descriptorCount = 1,
961 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
962 .pImmutableSamplers = NULL
963 },
964 }
965 };
966
967 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
968 &occlusion_ds_create_info,
969 &device->meta_state.alloc,
970 &device->meta_state.query.ds_layout);
971 if (result != VK_SUCCESS)
972 goto fail;
973
974 VkPipelineLayoutCreateInfo occlusion_pl_create_info = {
975 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
976 .setLayoutCount = 1,
977 .pSetLayouts = &device->meta_state.query.ds_layout,
978 .pushConstantRangeCount = 1,
979 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
980 };
981
982 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
983 &occlusion_pl_create_info,
984 &device->meta_state.alloc,
985 &device->meta_state.query.p_layout);
986 if (result != VK_SUCCESS)
987 goto fail;
988
989 VkPipelineShaderStageCreateInfo occlusion_pipeline_shader_stage = {
990 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
991 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
992 .module = radv_shader_module_to_handle(&occlusion_cs),
993 .pName = "main",
994 .pSpecializationInfo = NULL,
995 };
996
997 VkComputePipelineCreateInfo occlusion_vk_pipeline_info = {
998 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
999 .stage = occlusion_pipeline_shader_stage,
1000 .flags = 0,
1001 .layout = device->meta_state.query.p_layout,
1002 };
1003
1004 result = radv_CreateComputePipelines(radv_device_to_handle(device),
1005 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1006 1, &occlusion_vk_pipeline_info, NULL,
1007 &device->meta_state.query.occlusion_query_pipeline);
1008 if (result != VK_SUCCESS)
1009 goto fail;
1010
1011 VkPipelineShaderStageCreateInfo pipeline_statistics_pipeline_shader_stage = {
1012 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1013 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
1014 .module = radv_shader_module_to_handle(&pipeline_statistics_cs),
1015 .pName = "main",
1016 .pSpecializationInfo = NULL,
1017 };
1018
1019 VkComputePipelineCreateInfo pipeline_statistics_vk_pipeline_info = {
1020 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
1021 .stage = pipeline_statistics_pipeline_shader_stage,
1022 .flags = 0,
1023 .layout = device->meta_state.query.p_layout,
1024 };
1025
1026 result = radv_CreateComputePipelines(radv_device_to_handle(device),
1027 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1028 1, &pipeline_statistics_vk_pipeline_info, NULL,
1029 &device->meta_state.query.pipeline_statistics_query_pipeline);
1030 if (result != VK_SUCCESS)
1031 goto fail;
1032
1033 VkPipelineShaderStageCreateInfo tfb_pipeline_shader_stage = {
1034 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1035 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
1036 .module = radv_shader_module_to_handle(&tfb_cs),
1037 .pName = "main",
1038 .pSpecializationInfo = NULL,
1039 };
1040
1041 VkComputePipelineCreateInfo tfb_pipeline_info = {
1042 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
1043 .stage = tfb_pipeline_shader_stage,
1044 .flags = 0,
1045 .layout = device->meta_state.query.p_layout,
1046 };
1047
1048 result = radv_CreateComputePipelines(radv_device_to_handle(device),
1049 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1050 1, &tfb_pipeline_info, NULL,
1051 &device->meta_state.query.tfb_query_pipeline);
1052 if (result != VK_SUCCESS)
1053 goto fail;
1054
1055 VkPipelineShaderStageCreateInfo timestamp_pipeline_shader_stage = {
1056 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1057 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
1058 .module = radv_shader_module_to_handle(&timestamp_cs),
1059 .pName = "main",
1060 .pSpecializationInfo = NULL,
1061 };
1062
1063 VkComputePipelineCreateInfo timestamp_pipeline_info = {
1064 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
1065 .stage = timestamp_pipeline_shader_stage,
1066 .flags = 0,
1067 .layout = device->meta_state.query.p_layout,
1068 };
1069
1070 result = radv_CreateComputePipelines(radv_device_to_handle(device),
1071 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1072 1, &timestamp_pipeline_info, NULL,
1073 &device->meta_state.query.timestamp_query_pipeline);
1074
1075 fail:
1076 if (result != VK_SUCCESS)
1077 radv_device_finish_meta_query_state(device);
1078 ralloc_free(occlusion_cs.nir);
1079 ralloc_free(pipeline_statistics_cs.nir);
1080 ralloc_free(tfb_cs.nir);
1081 ralloc_free(timestamp_cs.nir);
1082 mtx_unlock(&device->meta_state.mtx);
1083 return result;
1084 }
1085
1086 VkResult radv_device_init_meta_query_state(struct radv_device *device, bool on_demand)
1087 {
1088 if (on_demand)
1089 return VK_SUCCESS;
1090
1091 return radv_device_init_meta_query_state_internal(device);
1092 }
1093
1094 void radv_device_finish_meta_query_state(struct radv_device *device)
1095 {
1096 if (device->meta_state.query.tfb_query_pipeline)
1097 radv_DestroyPipeline(radv_device_to_handle(device),
1098 device->meta_state.query.tfb_query_pipeline,
1099 &device->meta_state.alloc);
1100
1101 if (device->meta_state.query.pipeline_statistics_query_pipeline)
1102 radv_DestroyPipeline(radv_device_to_handle(device),
1103 device->meta_state.query.pipeline_statistics_query_pipeline,
1104 &device->meta_state.alloc);
1105
1106 if (device->meta_state.query.occlusion_query_pipeline)
1107 radv_DestroyPipeline(radv_device_to_handle(device),
1108 device->meta_state.query.occlusion_query_pipeline,
1109 &device->meta_state.alloc);
1110
1111 if (device->meta_state.query.timestamp_query_pipeline)
1112 radv_DestroyPipeline(radv_device_to_handle(device),
1113 device->meta_state.query.timestamp_query_pipeline,
1114 &device->meta_state.alloc);
1115
1116 if (device->meta_state.query.p_layout)
1117 radv_DestroyPipelineLayout(radv_device_to_handle(device),
1118 device->meta_state.query.p_layout,
1119 &device->meta_state.alloc);
1120
1121 if (device->meta_state.query.ds_layout)
1122 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
1123 device->meta_state.query.ds_layout,
1124 &device->meta_state.alloc);
1125 }
1126
1127 static void radv_query_shader(struct radv_cmd_buffer *cmd_buffer,
1128 VkPipeline *pipeline,
1129 struct radeon_winsys_bo *src_bo,
1130 struct radeon_winsys_bo *dst_bo,
1131 uint64_t src_offset, uint64_t dst_offset,
1132 uint32_t src_stride, uint32_t dst_stride,
1133 uint32_t count, uint32_t flags,
1134 uint32_t pipeline_stats_mask, uint32_t avail_offset)
1135 {
1136 struct radv_device *device = cmd_buffer->device;
1137 struct radv_meta_saved_state saved_state;
1138 bool old_predicating;
1139
1140 if (!*pipeline) {
1141 VkResult ret = radv_device_init_meta_query_state_internal(device);
1142 if (ret != VK_SUCCESS) {
1143 cmd_buffer->record_result = ret;
1144 return;
1145 }
1146 }
1147
1148 radv_meta_save(&saved_state, cmd_buffer,
1149 RADV_META_SAVE_COMPUTE_PIPELINE |
1150 RADV_META_SAVE_CONSTANTS |
1151 RADV_META_SAVE_DESCRIPTORS);
1152
1153 /* VK_EXT_conditional_rendering says that copy commands should not be
1154 * affected by conditional rendering.
1155 */
1156 old_predicating = cmd_buffer->state.predicating;
1157 cmd_buffer->state.predicating = false;
1158
1159 struct radv_buffer dst_buffer = {
1160 .bo = dst_bo,
1161 .offset = dst_offset,
1162 .size = dst_stride * count
1163 };
1164
1165 struct radv_buffer src_buffer = {
1166 .bo = src_bo,
1167 .offset = src_offset,
1168 .size = MAX2(src_stride * count, avail_offset + 4 * count - src_offset)
1169 };
1170
1171 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
1172 VK_PIPELINE_BIND_POINT_COMPUTE, *pipeline);
1173
1174 radv_meta_push_descriptor_set(cmd_buffer,
1175 VK_PIPELINE_BIND_POINT_COMPUTE,
1176 device->meta_state.query.p_layout,
1177 0, /* set */
1178 2, /* descriptorWriteCount */
1179 (VkWriteDescriptorSet[]) {
1180 {
1181 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
1182 .dstBinding = 0,
1183 .dstArrayElement = 0,
1184 .descriptorCount = 1,
1185 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
1186 .pBufferInfo = &(VkDescriptorBufferInfo) {
1187 .buffer = radv_buffer_to_handle(&dst_buffer),
1188 .offset = 0,
1189 .range = VK_WHOLE_SIZE
1190 }
1191 },
1192 {
1193 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
1194 .dstBinding = 1,
1195 .dstArrayElement = 0,
1196 .descriptorCount = 1,
1197 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
1198 .pBufferInfo = &(VkDescriptorBufferInfo) {
1199 .buffer = radv_buffer_to_handle(&src_buffer),
1200 .offset = 0,
1201 .range = VK_WHOLE_SIZE
1202 }
1203 }
1204 });
1205
1206 /* Encode the number of elements for easy access by the shader. */
1207 pipeline_stats_mask &= 0x7ff;
1208 pipeline_stats_mask |= util_bitcount(pipeline_stats_mask) << 16;
1209
1210 avail_offset -= src_offset;
1211
1212 struct {
1213 uint32_t flags;
1214 uint32_t dst_stride;
1215 uint32_t pipeline_stats_mask;
1216 uint32_t avail_offset;
1217 } push_constants = {
1218 flags,
1219 dst_stride,
1220 pipeline_stats_mask,
1221 avail_offset
1222 };
1223
1224 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
1225 device->meta_state.query.p_layout,
1226 VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(push_constants),
1227 &push_constants);
1228
1229 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_L2 |
1230 RADV_CMD_FLAG_INV_VCACHE;
1231
1232 if (flags & VK_QUERY_RESULT_WAIT_BIT)
1233 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER;
1234
1235 radv_unaligned_dispatch(cmd_buffer, count, 1, 1);
1236
1237 /* Restore conditional rendering. */
1238 cmd_buffer->state.predicating = old_predicating;
1239
1240 radv_meta_restore(&saved_state, cmd_buffer);
1241 }
1242
1243 VkResult radv_CreateQueryPool(
1244 VkDevice _device,
1245 const VkQueryPoolCreateInfo* pCreateInfo,
1246 const VkAllocationCallbacks* pAllocator,
1247 VkQueryPool* pQueryPool)
1248 {
1249 RADV_FROM_HANDLE(radv_device, device, _device);
1250 struct radv_query_pool *pool = vk_alloc2(&device->alloc, pAllocator,
1251 sizeof(*pool), 8,
1252 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1253
1254 if (!pool)
1255 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1256
1257
1258 switch(pCreateInfo->queryType) {
1259 case VK_QUERY_TYPE_OCCLUSION:
1260 pool->stride = 16 * device->physical_device->rad_info.num_render_backends;
1261 break;
1262 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
1263 pool->stride = pipelinestat_block_size * 2;
1264 break;
1265 case VK_QUERY_TYPE_TIMESTAMP:
1266 pool->stride = 8;
1267 break;
1268 case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT:
1269 pool->stride = 32;
1270 break;
1271 default:
1272 unreachable("creating unhandled query type");
1273 }
1274
1275 pool->type = pCreateInfo->queryType;
1276 pool->pipeline_stats_mask = pCreateInfo->pipelineStatistics;
1277 pool->availability_offset = pool->stride * pCreateInfo->queryCount;
1278 pool->size = pool->availability_offset;
1279 if (pCreateInfo->queryType == VK_QUERY_TYPE_PIPELINE_STATISTICS)
1280 pool->size += 4 * pCreateInfo->queryCount;
1281
1282 pool->bo = device->ws->buffer_create(device->ws, pool->size,
1283 64, RADEON_DOMAIN_GTT, RADEON_FLAG_NO_INTERPROCESS_SHARING,
1284 RADV_BO_PRIORITY_QUERY_POOL);
1285
1286 if (!pool->bo) {
1287 vk_free2(&device->alloc, pAllocator, pool);
1288 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
1289 }
1290
1291 pool->ptr = device->ws->buffer_map(pool->bo);
1292
1293 if (!pool->ptr) {
1294 device->ws->buffer_destroy(pool->bo);
1295 vk_free2(&device->alloc, pAllocator, pool);
1296 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
1297 }
1298
1299 *pQueryPool = radv_query_pool_to_handle(pool);
1300 return VK_SUCCESS;
1301 }
1302
1303 void radv_DestroyQueryPool(
1304 VkDevice _device,
1305 VkQueryPool _pool,
1306 const VkAllocationCallbacks* pAllocator)
1307 {
1308 RADV_FROM_HANDLE(radv_device, device, _device);
1309 RADV_FROM_HANDLE(radv_query_pool, pool, _pool);
1310
1311 if (!pool)
1312 return;
1313
1314 device->ws->buffer_destroy(pool->bo);
1315 vk_free2(&device->alloc, pAllocator, pool);
1316 }
1317
1318 VkResult radv_GetQueryPoolResults(
1319 VkDevice _device,
1320 VkQueryPool queryPool,
1321 uint32_t firstQuery,
1322 uint32_t queryCount,
1323 size_t dataSize,
1324 void* pData,
1325 VkDeviceSize stride,
1326 VkQueryResultFlags flags)
1327 {
1328 RADV_FROM_HANDLE(radv_device, device, _device);
1329 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
1330 char *data = pData;
1331 VkResult result = VK_SUCCESS;
1332
1333 for(unsigned i = 0; i < queryCount; ++i, data += stride) {
1334 char *dest = data;
1335 unsigned query = firstQuery + i;
1336 char *src = pool->ptr + query * pool->stride;
1337 uint32_t available;
1338
1339 switch (pool->type) {
1340 case VK_QUERY_TYPE_TIMESTAMP: {
1341 volatile uint64_t const *src64 = (volatile uint64_t const *)src;
1342 available = *src64 != TIMESTAMP_NOT_READY;
1343
1344 if (flags & VK_QUERY_RESULT_WAIT_BIT) {
1345 while (*src64 == TIMESTAMP_NOT_READY)
1346 ;
1347 available = true;
1348 }
1349
1350 if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT))
1351 result = VK_NOT_READY;
1352
1353 if (flags & VK_QUERY_RESULT_64_BIT) {
1354 if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))
1355 *(uint64_t*)dest = *src64;
1356 dest += 8;
1357 } else {
1358 if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))
1359 *(uint32_t*)dest = *(volatile uint32_t*)src;
1360 dest += 4;
1361 }
1362 break;
1363 }
1364 case VK_QUERY_TYPE_OCCLUSION: {
1365 volatile uint64_t const *src64 = (volatile uint64_t const *)src;
1366 uint32_t db_count = device->physical_device->rad_info.num_render_backends;
1367 uint32_t enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask;
1368 uint64_t sample_count = 0;
1369 available = 1;
1370
1371 for (int i = 0; i < db_count; ++i) {
1372 uint64_t start, end;
1373
1374 if (!(enabled_rb_mask & (1 << i)))
1375 continue;
1376
1377 do {
1378 start = src64[2 * i];
1379 end = src64[2 * i + 1];
1380 } while ((!(start & (1ull << 63)) || !(end & (1ull << 63))) && (flags & VK_QUERY_RESULT_WAIT_BIT));
1381
1382 if (!(start & (1ull << 63)) || !(end & (1ull << 63)))
1383 available = 0;
1384 else {
1385 sample_count += end - start;
1386 }
1387 }
1388
1389 if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT))
1390 result = VK_NOT_READY;
1391
1392 if (flags & VK_QUERY_RESULT_64_BIT) {
1393 if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))
1394 *(uint64_t*)dest = sample_count;
1395 dest += 8;
1396 } else {
1397 if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))
1398 *(uint32_t*)dest = sample_count;
1399 dest += 4;
1400 }
1401 break;
1402 }
1403 case VK_QUERY_TYPE_PIPELINE_STATISTICS: {
1404 if (flags & VK_QUERY_RESULT_WAIT_BIT)
1405 while(!*(volatile uint32_t*)(pool->ptr + pool->availability_offset + 4 * query))
1406 ;
1407 available = *(volatile uint32_t*)(pool->ptr + pool->availability_offset + 4 * query);
1408
1409 if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT))
1410 result = VK_NOT_READY;
1411
1412 const volatile uint64_t *start = (uint64_t*)src;
1413 const volatile uint64_t *stop = (uint64_t*)(src + pipelinestat_block_size);
1414 if (flags & VK_QUERY_RESULT_64_BIT) {
1415 uint64_t *dst = (uint64_t*)dest;
1416 dest += util_bitcount(pool->pipeline_stats_mask) * 8;
1417 for(int i = 0; i < 11; ++i) {
1418 if(pool->pipeline_stats_mask & (1u << i)) {
1419 if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))
1420 *dst = stop[pipeline_statistics_indices[i]] -
1421 start[pipeline_statistics_indices[i]];
1422 dst++;
1423 }
1424 }
1425
1426 } else {
1427 uint32_t *dst = (uint32_t*)dest;
1428 dest += util_bitcount(pool->pipeline_stats_mask) * 4;
1429 for(int i = 0; i < 11; ++i) {
1430 if(pool->pipeline_stats_mask & (1u << i)) {
1431 if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))
1432 *dst = stop[pipeline_statistics_indices[i]] -
1433 start[pipeline_statistics_indices[i]];
1434 dst++;
1435 }
1436 }
1437 }
1438 break;
1439 }
1440 case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT: {
1441 volatile uint64_t const *src64 = (volatile uint64_t const *)src;
1442 uint64_t num_primitives_written;
1443 uint64_t primitive_storage_needed;
1444
1445 /* SAMPLE_STREAMOUTSTATS stores this structure:
1446 * {
1447 * u64 NumPrimitivesWritten;
1448 * u64 PrimitiveStorageNeeded;
1449 * }
1450 */
1451 available = 1;
1452 for (int j = 0; j < 4; j++) {
1453 if (!(src64[j] & 0x8000000000000000UL))
1454 available = 0;
1455 }
1456
1457 if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT))
1458 result = VK_NOT_READY;
1459
1460 num_primitives_written = src64[3] - src64[1];
1461 primitive_storage_needed = src64[2] - src64[0];
1462
1463 if (flags & VK_QUERY_RESULT_64_BIT) {
1464 if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))
1465 *(uint64_t *)dest = num_primitives_written;
1466 dest += 8;
1467 if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))
1468 *(uint64_t *)dest = primitive_storage_needed;
1469 dest += 8;
1470 } else {
1471 if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))
1472 *(uint32_t *)dest = num_primitives_written;
1473 dest += 4;
1474 if (available || (flags & VK_QUERY_RESULT_PARTIAL_BIT))
1475 *(uint32_t *)dest = primitive_storage_needed;
1476 dest += 4;
1477 }
1478 break;
1479 }
1480 default:
1481 unreachable("trying to get results of unhandled query type");
1482 }
1483
1484 if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
1485 if (flags & VK_QUERY_RESULT_64_BIT) {
1486 *(uint64_t*)dest = available;
1487 } else {
1488 *(uint32_t*)dest = available;
1489 }
1490 }
1491 }
1492
1493 return result;
1494 }
1495
1496 static void emit_query_flush(struct radv_cmd_buffer *cmd_buffer,
1497 struct radv_query_pool *pool)
1498 {
1499 if (cmd_buffer->pending_reset_query) {
1500 if (pool->size >= RADV_BUFFER_OPS_CS_THRESHOLD) {
1501 /* Only need to flush caches if the query pool size is
1502 * large enough to be resetted using the compute shader
1503 * path. Small pools don't need any cache flushes
1504 * because we use a CP dma clear.
1505 */
1506 si_emit_cache_flush(cmd_buffer);
1507 }
1508 }
1509 }
1510
1511 void radv_CmdCopyQueryPoolResults(
1512 VkCommandBuffer commandBuffer,
1513 VkQueryPool queryPool,
1514 uint32_t firstQuery,
1515 uint32_t queryCount,
1516 VkBuffer dstBuffer,
1517 VkDeviceSize dstOffset,
1518 VkDeviceSize stride,
1519 VkQueryResultFlags flags)
1520 {
1521 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1522 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
1523 RADV_FROM_HANDLE(radv_buffer, dst_buffer, dstBuffer);
1524 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1525 uint64_t va = radv_buffer_get_va(pool->bo);
1526 uint64_t dest_va = radv_buffer_get_va(dst_buffer->bo);
1527 dest_va += dst_buffer->offset + dstOffset;
1528
1529 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, pool->bo);
1530 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_buffer->bo);
1531
1532 /* From the Vulkan spec 1.1.108:
1533 *
1534 * "vkCmdCopyQueryPoolResults is guaranteed to see the effect of
1535 * previous uses of vkCmdResetQueryPool in the same queue, without any
1536 * additional synchronization."
1537 *
1538 * So, we have to flush the caches if the compute shader path was used.
1539 */
1540 emit_query_flush(cmd_buffer, pool);
1541
1542 switch (pool->type) {
1543 case VK_QUERY_TYPE_OCCLUSION:
1544 if (flags & VK_QUERY_RESULT_WAIT_BIT) {
1545 for(unsigned i = 0; i < queryCount; ++i, dest_va += stride) {
1546 unsigned query = firstQuery + i;
1547 uint64_t src_va = va + query * pool->stride + pool->stride - 4;
1548
1549 radeon_check_space(cmd_buffer->device->ws, cs, 7);
1550
1551 /* Waits on the upper word of the last DB entry */
1552 radv_cp_wait_mem(cs, WAIT_REG_MEM_GREATER_OR_EQUAL,
1553 src_va, 0x80000000, 0xffffffff);
1554 }
1555 }
1556 radv_query_shader(cmd_buffer, &cmd_buffer->device->meta_state.query.occlusion_query_pipeline,
1557 pool->bo, dst_buffer->bo, firstQuery * pool->stride,
1558 dst_buffer->offset + dstOffset,
1559 pool->stride, stride,
1560 queryCount, flags, 0, 0);
1561 break;
1562 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
1563 if (flags & VK_QUERY_RESULT_WAIT_BIT) {
1564 for(unsigned i = 0; i < queryCount; ++i, dest_va += stride) {
1565 unsigned query = firstQuery + i;
1566
1567 radeon_check_space(cmd_buffer->device->ws, cs, 7);
1568
1569 uint64_t avail_va = va + pool->availability_offset + 4 * query;
1570
1571 /* This waits on the ME. All copies below are done on the ME */
1572 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL,
1573 avail_va, 1, 0xffffffff);
1574 }
1575 }
1576 radv_query_shader(cmd_buffer, &cmd_buffer->device->meta_state.query.pipeline_statistics_query_pipeline,
1577 pool->bo, dst_buffer->bo, firstQuery * pool->stride,
1578 dst_buffer->offset + dstOffset,
1579 pool->stride, stride, queryCount, flags,
1580 pool->pipeline_stats_mask,
1581 pool->availability_offset + 4 * firstQuery);
1582 break;
1583 case VK_QUERY_TYPE_TIMESTAMP:
1584 if (flags & VK_QUERY_RESULT_WAIT_BIT) {
1585 for(unsigned i = 0; i < queryCount; ++i, dest_va += stride) {
1586 unsigned query = firstQuery + i;
1587 uint64_t local_src_va = va + query * pool->stride;
1588
1589 radeon_check_space(cmd_buffer->device->ws, cs, 7);
1590
1591 /* Wait on the high 32 bits of the timestamp in
1592 * case the low part is 0xffffffff.
1593 */
1594 radv_cp_wait_mem(cs, WAIT_REG_MEM_NOT_EQUAL,
1595 local_src_va + 4,
1596 TIMESTAMP_NOT_READY >> 32,
1597 0xffffffff);
1598 }
1599 }
1600
1601 radv_query_shader(cmd_buffer, &cmd_buffer->device->meta_state.query.timestamp_query_pipeline,
1602 pool->bo, dst_buffer->bo,
1603 firstQuery * pool->stride,
1604 dst_buffer->offset + dstOffset,
1605 pool->stride, stride,
1606 queryCount, flags, 0, 0);
1607 break;
1608 case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT:
1609 if (flags & VK_QUERY_RESULT_WAIT_BIT) {
1610 for(unsigned i = 0; i < queryCount; i++) {
1611 unsigned query = firstQuery + i;
1612 uint64_t src_va = va + query * pool->stride;
1613
1614 radeon_check_space(cmd_buffer->device->ws, cs, 7 * 4);
1615
1616 /* Wait on the upper word of all results. */
1617 for (unsigned j = 0; j < 4; j++, src_va += 8) {
1618 radv_cp_wait_mem(cs, WAIT_REG_MEM_GREATER_OR_EQUAL,
1619 src_va + 4, 0x80000000,
1620 0xffffffff);
1621 }
1622 }
1623 }
1624
1625 radv_query_shader(cmd_buffer, &cmd_buffer->device->meta_state.query.tfb_query_pipeline,
1626 pool->bo, dst_buffer->bo,
1627 firstQuery * pool->stride,
1628 dst_buffer->offset + dstOffset,
1629 pool->stride, stride,
1630 queryCount, flags, 0, 0);
1631 break;
1632 default:
1633 unreachable("trying to get results of unhandled query type");
1634 }
1635
1636 }
1637
1638 void radv_CmdResetQueryPool(
1639 VkCommandBuffer commandBuffer,
1640 VkQueryPool queryPool,
1641 uint32_t firstQuery,
1642 uint32_t queryCount)
1643 {
1644 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1645 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
1646 uint32_t value = pool->type == VK_QUERY_TYPE_TIMESTAMP
1647 ? TIMESTAMP_NOT_READY : 0;
1648 uint32_t flush_bits = 0;
1649
1650 /* Make sure to sync all previous work if the given command buffer has
1651 * pending active queries. Otherwise the GPU might write queries data
1652 * after the reset operation.
1653 */
1654 cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
1655
1656 flush_bits |= radv_fill_buffer(cmd_buffer, pool->bo,
1657 firstQuery * pool->stride,
1658 queryCount * pool->stride, value);
1659
1660 if (pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS) {
1661 flush_bits |= radv_fill_buffer(cmd_buffer, pool->bo,
1662 pool->availability_offset + firstQuery * 4,
1663 queryCount * 4, 0);
1664 }
1665
1666 if (flush_bits) {
1667 /* Only need to flush caches for the compute shader path. */
1668 cmd_buffer->pending_reset_query = true;
1669 cmd_buffer->state.flush_bits |= flush_bits;
1670 }
1671 }
1672
1673 void radv_ResetQueryPoolEXT(
1674 VkDevice _device,
1675 VkQueryPool queryPool,
1676 uint32_t firstQuery,
1677 uint32_t queryCount)
1678 {
1679 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
1680
1681 uint32_t value = pool->type == VK_QUERY_TYPE_TIMESTAMP
1682 ? TIMESTAMP_NOT_READY : 0;
1683 uint32_t *data = (uint32_t*)(pool->ptr + firstQuery * pool->stride);
1684 uint32_t *data_end = (uint32_t*)(pool->ptr + (firstQuery + queryCount) * pool->stride);
1685
1686 for(uint32_t *p = data; p != data_end; ++p)
1687 *p = value;
1688
1689 if (pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS) {
1690 memset(pool->ptr + pool->availability_offset + firstQuery * 4,
1691 0, queryCount * 4);
1692 }
1693 }
1694
1695 static unsigned event_type_for_stream(unsigned stream)
1696 {
1697 switch (stream) {
1698 default:
1699 case 0: return V_028A90_SAMPLE_STREAMOUTSTATS;
1700 case 1: return V_028A90_SAMPLE_STREAMOUTSTATS1;
1701 case 2: return V_028A90_SAMPLE_STREAMOUTSTATS2;
1702 case 3: return V_028A90_SAMPLE_STREAMOUTSTATS3;
1703 }
1704 }
1705
1706 static void emit_begin_query(struct radv_cmd_buffer *cmd_buffer,
1707 uint64_t va,
1708 VkQueryType query_type,
1709 VkQueryControlFlags flags,
1710 uint32_t index)
1711 {
1712 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1713 switch (query_type) {
1714 case VK_QUERY_TYPE_OCCLUSION:
1715 radeon_check_space(cmd_buffer->device->ws, cs, 7);
1716
1717 ++cmd_buffer->state.active_occlusion_queries;
1718 if (cmd_buffer->state.active_occlusion_queries == 1) {
1719 if (flags & VK_QUERY_CONTROL_PRECISE_BIT) {
1720 /* This is the first occlusion query, enable
1721 * the hint if the precision bit is set.
1722 */
1723 cmd_buffer->state.perfect_occlusion_queries_enabled = true;
1724 }
1725
1726 radv_set_db_count_control(cmd_buffer);
1727 } else {
1728 if ((flags & VK_QUERY_CONTROL_PRECISE_BIT) &&
1729 !cmd_buffer->state.perfect_occlusion_queries_enabled) {
1730 /* This is not the first query, but this one
1731 * needs to enable precision, DB_COUNT_CONTROL
1732 * has to be updated accordingly.
1733 */
1734 cmd_buffer->state.perfect_occlusion_queries_enabled = true;
1735
1736 radv_set_db_count_control(cmd_buffer);
1737 }
1738 }
1739
1740 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1741 radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
1742 radeon_emit(cs, va);
1743 radeon_emit(cs, va >> 32);
1744 break;
1745 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
1746 radeon_check_space(cmd_buffer->device->ws, cs, 4);
1747
1748 ++cmd_buffer->state.active_pipeline_queries;
1749 if (cmd_buffer->state.active_pipeline_queries == 1) {
1750 cmd_buffer->state.flush_bits &= ~RADV_CMD_FLAG_STOP_PIPELINE_STATS;
1751 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_START_PIPELINE_STATS;
1752 }
1753
1754 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1755 radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
1756 radeon_emit(cs, va);
1757 radeon_emit(cs, va >> 32);
1758 break;
1759 case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT:
1760 radeon_check_space(cmd_buffer->device->ws, cs, 4);
1761
1762 assert(index < MAX_SO_STREAMS);
1763
1764 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1765 radeon_emit(cs, EVENT_TYPE(event_type_for_stream(index)) | EVENT_INDEX(3));
1766 radeon_emit(cs, va);
1767 radeon_emit(cs, va >> 32);
1768 break;
1769 default:
1770 unreachable("beginning unhandled query type");
1771 }
1772
1773 }
1774
1775 static void emit_end_query(struct radv_cmd_buffer *cmd_buffer,
1776 uint64_t va, uint64_t avail_va,
1777 VkQueryType query_type, uint32_t index)
1778 {
1779 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1780 switch (query_type) {
1781 case VK_QUERY_TYPE_OCCLUSION:
1782 radeon_check_space(cmd_buffer->device->ws, cs, 14);
1783
1784 cmd_buffer->state.active_occlusion_queries--;
1785 if (cmd_buffer->state.active_occlusion_queries == 0) {
1786 radv_set_db_count_control(cmd_buffer);
1787
1788 /* Reset the perfect occlusion queries hint now that no
1789 * queries are active.
1790 */
1791 cmd_buffer->state.perfect_occlusion_queries_enabled = false;
1792 }
1793
1794 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1795 radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
1796 radeon_emit(cs, va + 8);
1797 radeon_emit(cs, (va + 8) >> 32);
1798
1799 break;
1800 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
1801 radeon_check_space(cmd_buffer->device->ws, cs, 16);
1802
1803 cmd_buffer->state.active_pipeline_queries--;
1804 if (cmd_buffer->state.active_pipeline_queries == 0) {
1805 cmd_buffer->state.flush_bits &= ~RADV_CMD_FLAG_START_PIPELINE_STATS;
1806 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_STOP_PIPELINE_STATS;
1807 }
1808 va += pipelinestat_block_size;
1809
1810 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1811 radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
1812 radeon_emit(cs, va);
1813 radeon_emit(cs, va >> 32);
1814
1815 si_cs_emit_write_event_eop(cs,
1816 cmd_buffer->device->physical_device->rad_info.chip_class,
1817 radv_cmd_buffer_uses_mec(cmd_buffer),
1818 V_028A90_BOTTOM_OF_PIPE_TS, 0,
1819 EOP_DST_SEL_MEM,
1820 EOP_DATA_SEL_VALUE_32BIT,
1821 avail_va, 1,
1822 cmd_buffer->gfx9_eop_bug_va);
1823 break;
1824 case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT:
1825 radeon_check_space(cmd_buffer->device->ws, cs, 4);
1826
1827 assert(index < MAX_SO_STREAMS);
1828
1829 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1830 radeon_emit(cs, EVENT_TYPE(event_type_for_stream(index)) | EVENT_INDEX(3));
1831 radeon_emit(cs, (va + 16));
1832 radeon_emit(cs, (va + 16) >> 32);
1833 break;
1834 default:
1835 unreachable("ending unhandled query type");
1836 }
1837
1838 cmd_buffer->active_query_flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1839 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1840 RADV_CMD_FLAG_INV_L2 |
1841 RADV_CMD_FLAG_INV_VCACHE;
1842 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1843 cmd_buffer->active_query_flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1844 RADV_CMD_FLAG_FLUSH_AND_INV_DB;
1845 }
1846 }
1847
1848 void radv_CmdBeginQueryIndexedEXT(
1849 VkCommandBuffer commandBuffer,
1850 VkQueryPool queryPool,
1851 uint32_t query,
1852 VkQueryControlFlags flags,
1853 uint32_t index)
1854 {
1855 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1856 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
1857 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1858 uint64_t va = radv_buffer_get_va(pool->bo);
1859
1860 radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo);
1861
1862 emit_query_flush(cmd_buffer, pool);
1863
1864 va += pool->stride * query;
1865
1866 emit_begin_query(cmd_buffer, va, pool->type, flags, index);
1867 }
1868
1869 void radv_CmdBeginQuery(
1870 VkCommandBuffer commandBuffer,
1871 VkQueryPool queryPool,
1872 uint32_t query,
1873 VkQueryControlFlags flags)
1874 {
1875 radv_CmdBeginQueryIndexedEXT(commandBuffer, queryPool, query, flags, 0);
1876 }
1877
1878 void radv_CmdEndQueryIndexedEXT(
1879 VkCommandBuffer commandBuffer,
1880 VkQueryPool queryPool,
1881 uint32_t query,
1882 uint32_t index)
1883 {
1884 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1885 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
1886 uint64_t va = radv_buffer_get_va(pool->bo);
1887 uint64_t avail_va = va + pool->availability_offset + 4 * query;
1888 va += pool->stride * query;
1889
1890 /* Do not need to add the pool BO to the list because the query must
1891 * currently be active, which means the BO is already in the list.
1892 */
1893 emit_end_query(cmd_buffer, va, avail_va, pool->type, index);
1894
1895 /*
1896 * For multiview we have to emit a query for each bit in the mask,
1897 * however the first query we emit will get the totals for all the
1898 * operations, so we don't want to get a real value in the other
1899 * queries. This emits a fake begin/end sequence so the waiting
1900 * code gets a completed query value and doesn't hang, but the
1901 * query returns 0.
1902 */
1903 if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
1904 uint64_t avail_va = va + pool->availability_offset + 4 * query;
1905
1906
1907 for (unsigned i = 1; i < util_bitcount(cmd_buffer->state.subpass->view_mask); i++) {
1908 va += pool->stride;
1909 avail_va += 4;
1910 emit_begin_query(cmd_buffer, va, pool->type, 0, 0);
1911 emit_end_query(cmd_buffer, va, avail_va, pool->type, 0);
1912 }
1913 }
1914 }
1915
1916 void radv_CmdEndQuery(
1917 VkCommandBuffer commandBuffer,
1918 VkQueryPool queryPool,
1919 uint32_t query)
1920 {
1921 radv_CmdEndQueryIndexedEXT(commandBuffer, queryPool, query, 0);
1922 }
1923
1924 void radv_CmdWriteTimestamp(
1925 VkCommandBuffer commandBuffer,
1926 VkPipelineStageFlagBits pipelineStage,
1927 VkQueryPool queryPool,
1928 uint32_t query)
1929 {
1930 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1931 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
1932 bool mec = radv_cmd_buffer_uses_mec(cmd_buffer);
1933 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1934 uint64_t va = radv_buffer_get_va(pool->bo);
1935 uint64_t query_va = va + pool->stride * query;
1936
1937 radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo);
1938
1939 emit_query_flush(cmd_buffer, pool);
1940
1941 int num_queries = 1;
1942 if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask)
1943 num_queries = util_bitcount(cmd_buffer->state.subpass->view_mask);
1944
1945 ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 28 * num_queries);
1946
1947 for (unsigned i = 0; i < num_queries; i++) {
1948 switch(pipelineStage) {
1949 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:
1950 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1951 radeon_emit(cs, COPY_DATA_COUNT_SEL | COPY_DATA_WR_CONFIRM |
1952 COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
1953 COPY_DATA_DST_SEL(V_370_MEM));
1954 radeon_emit(cs, 0);
1955 radeon_emit(cs, 0);
1956 radeon_emit(cs, query_va);
1957 radeon_emit(cs, query_va >> 32);
1958 break;
1959 default:
1960 si_cs_emit_write_event_eop(cs,
1961 cmd_buffer->device->physical_device->rad_info.chip_class,
1962 mec,
1963 V_028A90_BOTTOM_OF_PIPE_TS, 0,
1964 EOP_DST_SEL_MEM,
1965 EOP_DATA_SEL_TIMESTAMP,
1966 query_va, 0,
1967 cmd_buffer->gfx9_eop_bug_va);
1968 break;
1969 }
1970 query_va += pool->stride;
1971 }
1972
1973 cmd_buffer->active_query_flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1974 RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1975 RADV_CMD_FLAG_INV_L2 |
1976 RADV_CMD_FLAG_INV_VCACHE;
1977 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1978 cmd_buffer->active_query_flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1979 RADV_CMD_FLAG_FLUSH_AND_INV_DB;
1980 }
1981
1982 assert(cmd_buffer->cs->cdw <= cdw_max);
1983 }