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[mesa.git] / src / amd / vulkan / radv_query.c
1 /*
2 * Copyrigh 2016 Red Hat Inc.
3 * Based on anv:
4 * Copyright © 2015 Intel Corporation
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25
26 #include <assert.h>
27 #include <stdbool.h>
28 #include <string.h>
29 #include <unistd.h>
30 #include <fcntl.h>
31
32 #include "nir/nir_builder.h"
33 #include "radv_meta.h"
34 #include "radv_private.h"
35 #include "radv_cs.h"
36 #include "sid.h"
37
38
39 static const int pipelinestat_block_size = 11 * 8;
40 static const unsigned pipeline_statistics_indices[] = {7, 6, 3, 4, 5, 2, 1, 0, 8, 9, 10};
41
42 static unsigned get_max_db(struct radv_device *device)
43 {
44 unsigned num_db = device->physical_device->rad_info.num_render_backends;
45 MAYBE_UNUSED unsigned rb_mask = device->physical_device->rad_info.enabled_rb_mask;
46
47 if (device->physical_device->rad_info.chip_class == SI)
48 num_db = 8;
49 else
50 num_db = MAX2(8, num_db);
51
52 /* Otherwise we need to change the query reset procedure */
53 assert(rb_mask == ((1ull << num_db) - 1));
54
55 return num_db;
56 }
57
58 static void radv_break_on_count(nir_builder *b, nir_variable *var, nir_ssa_def *count)
59 {
60 nir_ssa_def *counter = nir_load_var(b, var);
61
62 nir_if *if_stmt = nir_if_create(b->shader);
63 if_stmt->condition = nir_src_for_ssa(nir_uge(b, counter, count));
64 nir_cf_node_insert(b->cursor, &if_stmt->cf_node);
65
66 b->cursor = nir_after_cf_list(&if_stmt->then_list);
67
68 nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_break);
69 nir_builder_instr_insert(b, &instr->instr);
70
71 b->cursor = nir_after_cf_node(&if_stmt->cf_node);
72 counter = nir_iadd(b, counter, nir_imm_int(b, 1));
73 nir_store_var(b, var, counter, 0x1);
74 }
75
76 static struct nir_ssa_def *
77 radv_load_push_int(nir_builder *b, unsigned offset, const char *name)
78 {
79 nir_intrinsic_instr *flags = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
80 nir_intrinsic_set_base(flags, 0);
81 nir_intrinsic_set_range(flags, 16);
82 flags->src[0] = nir_src_for_ssa(nir_imm_int(b, offset));
83 flags->num_components = 1;
84 nir_ssa_dest_init(&flags->instr, &flags->dest, 1, 32, name);
85 nir_builder_instr_insert(b, &flags->instr);
86 return &flags->dest.ssa;
87 }
88
89 static nir_shader *
90 build_occlusion_query_shader(struct radv_device *device) {
91 /* the shader this builds is roughly
92 *
93 * push constants {
94 * uint32_t flags;
95 * uint32_t dst_stride;
96 * };
97 *
98 * uint32_t src_stride = 16 * db_count;
99 *
100 * location(binding = 0) buffer dst_buf;
101 * location(binding = 1) buffer src_buf;
102 *
103 * void main() {
104 * uint64_t result = 0;
105 * uint64_t src_offset = src_stride * global_id.x;
106 * uint64_t dst_offset = dst_stride * global_id.x;
107 * bool available = true;
108 * for (int i = 0; i < db_count; ++i) {
109 * uint64_t start = src_buf[src_offset + 16 * i];
110 * uint64_t end = src_buf[src_offset + 16 * i + 8];
111 * if ((start & (1ull << 63)) && (end & (1ull << 63)))
112 * result += end - start;
113 * else
114 * available = false;
115 * }
116 * uint32_t elem_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;
117 * if ((flags & VK_QUERY_RESULT_PARTIAL_BIT) || available) {
118 * if (flags & VK_QUERY_RESULT_64_BIT)
119 * dst_buf[dst_offset] = result;
120 * else
121 * dst_buf[dst_offset] = (uint32_t)result.
122 * }
123 * if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
124 * dst_buf[dst_offset + elem_size] = available;
125 * }
126 * }
127 */
128 nir_builder b;
129 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
130 b.shader->info->name = ralloc_strdup(b.shader, "occlusion_query");
131 b.shader->info->cs.local_size[0] = 64;
132 b.shader->info->cs.local_size[1] = 1;
133 b.shader->info->cs.local_size[2] = 1;
134
135 nir_variable *result = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "result");
136 nir_variable *outer_counter = nir_local_variable_create(b.impl, glsl_int_type(), "outer_counter");
137 nir_variable *start = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "start");
138 nir_variable *end = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "end");
139 nir_variable *available = nir_local_variable_create(b.impl, glsl_int_type(), "available");
140 unsigned db_count = get_max_db(device);
141
142 nir_ssa_def *flags = radv_load_push_int(&b, 0, "flags");
143
144 nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
145 nir_intrinsic_vulkan_resource_index);
146 dst_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
147 nir_intrinsic_set_desc_set(dst_buf, 0);
148 nir_intrinsic_set_binding(dst_buf, 0);
149 nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, 1, 32, NULL);
150 nir_builder_instr_insert(&b, &dst_buf->instr);
151
152 nir_intrinsic_instr *src_buf = nir_intrinsic_instr_create(b.shader,
153 nir_intrinsic_vulkan_resource_index);
154 src_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
155 nir_intrinsic_set_desc_set(src_buf, 0);
156 nir_intrinsic_set_binding(src_buf, 1);
157 nir_ssa_dest_init(&src_buf->instr, &src_buf->dest, 1, 32, NULL);
158 nir_builder_instr_insert(&b, &src_buf->instr);
159
160 nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
161 nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
162 nir_ssa_def *block_size = nir_imm_ivec4(&b,
163 b.shader->info->cs.local_size[0],
164 b.shader->info->cs.local_size[1],
165 b.shader->info->cs.local_size[2], 0);
166 nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
167 global_id = nir_channel(&b, global_id, 0); // We only care about x here.
168
169 nir_ssa_def *input_stride = nir_imm_int(&b, db_count * 16);
170 nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id);
171 nir_ssa_def *output_stride = radv_load_push_int(&b, 4, "output_stride");
172 nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id);
173
174
175 nir_store_var(&b, result, nir_imm_int64(&b, 0), 0x1);
176 nir_store_var(&b, outer_counter, nir_imm_int(&b, 0), 0x1);
177 nir_store_var(&b, available, nir_imm_int(&b, 1), 0x1);
178
179 nir_loop *outer_loop = nir_loop_create(b.shader);
180 nir_builder_cf_insert(&b, &outer_loop->cf_node);
181 b.cursor = nir_after_cf_list(&outer_loop->body);
182
183 nir_ssa_def *current_outer_count = nir_load_var(&b, outer_counter);
184 radv_break_on_count(&b, outer_counter, nir_imm_int(&b, db_count));
185
186 nir_ssa_def *load_offset = nir_imul(&b, current_outer_count, nir_imm_int(&b, 16));
187 load_offset = nir_iadd(&b, input_base, load_offset);
188
189 nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
190 load->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
191 load->src[1] = nir_src_for_ssa(load_offset);
192 nir_ssa_dest_init(&load->instr, &load->dest, 2, 64, NULL);
193 load->num_components = 2;
194 nir_builder_instr_insert(&b, &load->instr);
195
196 const unsigned swizzle0[] = {0,0,0,0};
197 const unsigned swizzle1[] = {1,1,1,1};
198 nir_store_var(&b, start, nir_swizzle(&b, &load->dest.ssa, swizzle0, 1, false), 0x1);
199 nir_store_var(&b, end, nir_swizzle(&b, &load->dest.ssa, swizzle1, 1, false), 0x1);
200
201 nir_ssa_def *start_done = nir_ilt(&b, nir_load_var(&b, start), nir_imm_int64(&b, 0));
202 nir_ssa_def *end_done = nir_ilt(&b, nir_load_var(&b, end), nir_imm_int64(&b, 0));
203
204 nir_if *update_if = nir_if_create(b.shader);
205 update_if->condition = nir_src_for_ssa(nir_iand(&b, start_done, end_done));
206 nir_cf_node_insert(b.cursor, &update_if->cf_node);
207
208 b.cursor = nir_after_cf_list(&update_if->then_list);
209
210 nir_store_var(&b, result,
211 nir_iadd(&b, nir_load_var(&b, result),
212 nir_isub(&b, nir_load_var(&b, end),
213 nir_load_var(&b, start))), 0x1);
214
215 b.cursor = nir_after_cf_list(&update_if->else_list);
216
217 nir_store_var(&b, available, nir_imm_int(&b, 0), 0x1);
218
219 b.cursor = nir_after_cf_node(&outer_loop->cf_node);
220
221 /* Store the result if complete or if partial results have been requested. */
222
223 nir_ssa_def *result_is_64bit = nir_iand(&b, flags,
224 nir_imm_int(&b, VK_QUERY_RESULT_64_BIT));
225 nir_ssa_def *result_size = nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 8), nir_imm_int(&b, 4));
226
227 nir_if *store_if = nir_if_create(b.shader);
228 store_if->condition = nir_src_for_ssa(nir_ior(&b, nir_iand(&b, flags, nir_imm_int(&b, VK_QUERY_RESULT_PARTIAL_BIT)), nir_load_var(&b, available)));
229 nir_cf_node_insert(b.cursor, &store_if->cf_node);
230
231 b.cursor = nir_after_cf_list(&store_if->then_list);
232
233 nir_if *store_64bit_if = nir_if_create(b.shader);
234 store_64bit_if->condition = nir_src_for_ssa(result_is_64bit);
235 nir_cf_node_insert(b.cursor, &store_64bit_if->cf_node);
236
237 b.cursor = nir_after_cf_list(&store_64bit_if->then_list);
238
239 nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
240 store->src[0] = nir_src_for_ssa(nir_load_var(&b, result));
241 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
242 store->src[2] = nir_src_for_ssa(output_base);
243 nir_intrinsic_set_write_mask(store, 0x1);
244 store->num_components = 1;
245 nir_builder_instr_insert(&b, &store->instr);
246
247 b.cursor = nir_after_cf_list(&store_64bit_if->else_list);
248
249 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
250 store->src[0] = nir_src_for_ssa(nir_u2u32(&b, nir_load_var(&b, result)));
251 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
252 store->src[2] = nir_src_for_ssa(output_base);
253 nir_intrinsic_set_write_mask(store, 0x1);
254 store->num_components = 1;
255 nir_builder_instr_insert(&b, &store->instr);
256
257 b.cursor = nir_after_cf_node(&store_if->cf_node);
258
259 /* Store the availability bit if requested. */
260
261 nir_if *availability_if = nir_if_create(b.shader);
262 availability_if->condition = nir_src_for_ssa(nir_iand(&b, flags, nir_imm_int(&b, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT)));
263 nir_cf_node_insert(b.cursor, &availability_if->cf_node);
264
265 b.cursor = nir_after_cf_list(&availability_if->then_list);
266
267 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
268 store->src[0] = nir_src_for_ssa(nir_load_var(&b, available));
269 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
270 store->src[2] = nir_src_for_ssa(nir_iadd(&b, result_size, output_base));
271 nir_intrinsic_set_write_mask(store, 0x1);
272 store->num_components = 1;
273 nir_builder_instr_insert(&b, &store->instr);
274
275 return b.shader;
276 }
277
278 static nir_shader *
279 build_pipeline_statistics_query_shader(struct radv_device *device) {
280 /* the shader this builds is roughly
281 *
282 * push constants {
283 * uint32_t flags;
284 * uint32_t dst_stride;
285 * uint32_t stats_mask;
286 * uint32_t avail_offset;
287 * };
288 *
289 * uint32_t src_stride = pipelinestat_block_size * 2;
290 *
291 * location(binding = 0) buffer dst_buf;
292 * location(binding = 1) buffer src_buf;
293 *
294 * void main() {
295 * uint64_t src_offset = src_stride * global_id.x;
296 * uint64_t dst_base = dst_stride * global_id.x;
297 * uint64_t dst_offset = dst_base;
298 * uint32_t elem_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;
299 * uint32_t elem_count = stats_mask >> 16;
300 * uint32_t available = src_buf[avail_offset + 4 * global_id.x];
301 * if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
302 * dst_buf[dst_offset + elem_count * elem_size] = available;
303 * }
304 * if (available) {
305 * // repeat 11 times:
306 * if (stats_mask & (1 << 0)) {
307 * uint64_t start = src_buf[src_offset + 8 * indices[0]];
308 * uint64_t end = src_buf[src_offset + 8 * indices[0] + pipelinestat_block_size];
309 * uint64_t result = end - start;
310 * if (flags & VK_QUERY_RESULT_64_BIT)
311 * dst_buf[dst_offset] = result;
312 * else
313 * dst_buf[dst_offset] = (uint32_t)result.
314 * dst_offset += elem_size;
315 * }
316 * } else if (flags & VK_QUERY_RESULT_PARTIAL_BIT) {
317 * // Set everything to 0 as we don't know what is valid.
318 * for (int i = 0; i < elem_count; ++i)
319 * dst_buf[dst_base + elem_size * i] = 0;
320 * }
321 * }
322 */
323 nir_builder b;
324 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
325 b.shader->info->name = ralloc_strdup(b.shader, "pipeline_statistics_query");
326 b.shader->info->cs.local_size[0] = 64;
327 b.shader->info->cs.local_size[1] = 1;
328 b.shader->info->cs.local_size[2] = 1;
329
330 nir_variable *output_offset = nir_local_variable_create(b.impl, glsl_int_type(), "output_offset");
331
332 nir_ssa_def *flags = radv_load_push_int(&b, 0, "flags");
333 nir_ssa_def *stats_mask = radv_load_push_int(&b, 8, "stats_mask");
334 nir_ssa_def *avail_offset = radv_load_push_int(&b, 12, "avail_offset");
335
336 nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
337 nir_intrinsic_vulkan_resource_index);
338 dst_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
339 nir_intrinsic_set_desc_set(dst_buf, 0);
340 nir_intrinsic_set_binding(dst_buf, 0);
341 nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, 1, 32, NULL);
342 nir_builder_instr_insert(&b, &dst_buf->instr);
343
344 nir_intrinsic_instr *src_buf = nir_intrinsic_instr_create(b.shader,
345 nir_intrinsic_vulkan_resource_index);
346 src_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
347 nir_intrinsic_set_desc_set(src_buf, 0);
348 nir_intrinsic_set_binding(src_buf, 1);
349 nir_ssa_dest_init(&src_buf->instr, &src_buf->dest, 1, 32, NULL);
350 nir_builder_instr_insert(&b, &src_buf->instr);
351
352 nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
353 nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
354 nir_ssa_def *block_size = nir_imm_ivec4(&b,
355 b.shader->info->cs.local_size[0],
356 b.shader->info->cs.local_size[1],
357 b.shader->info->cs.local_size[2], 0);
358 nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
359 global_id = nir_channel(&b, global_id, 0); // We only care about x here.
360
361 nir_ssa_def *input_stride = nir_imm_int(&b, pipelinestat_block_size * 2);
362 nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id);
363 nir_ssa_def *output_stride = radv_load_push_int(&b, 4, "output_stride");
364 nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id);
365
366
367 avail_offset = nir_iadd(&b, avail_offset,
368 nir_imul(&b, global_id, nir_imm_int(&b, 4)));
369
370 nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
371 load->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
372 load->src[1] = nir_src_for_ssa(avail_offset);
373 nir_ssa_dest_init(&load->instr, &load->dest, 1, 32, NULL);
374 load->num_components = 1;
375 nir_builder_instr_insert(&b, &load->instr);
376 nir_ssa_def *available = &load->dest.ssa;
377
378 nir_ssa_def *result_is_64bit = nir_iand(&b, flags,
379 nir_imm_int(&b, VK_QUERY_RESULT_64_BIT));
380 nir_ssa_def *elem_size = nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 8), nir_imm_int(&b, 4));
381 nir_ssa_def *elem_count = nir_ushr(&b, stats_mask, nir_imm_int(&b, 16));
382
383 /* Store the availability bit if requested. */
384
385 nir_if *availability_if = nir_if_create(b.shader);
386 availability_if->condition = nir_src_for_ssa(nir_iand(&b, flags, nir_imm_int(&b, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT)));
387 nir_cf_node_insert(b.cursor, &availability_if->cf_node);
388
389 b.cursor = nir_after_cf_list(&availability_if->then_list);
390
391 nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
392 store->src[0] = nir_src_for_ssa(available);
393 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
394 store->src[2] = nir_src_for_ssa(nir_iadd(&b, output_base, nir_imul(&b, elem_count, elem_size)));
395 nir_intrinsic_set_write_mask(store, 0x1);
396 store->num_components = 1;
397 nir_builder_instr_insert(&b, &store->instr);
398
399 b.cursor = nir_after_cf_node(&availability_if->cf_node);
400
401 nir_if *available_if = nir_if_create(b.shader);
402 available_if->condition = nir_src_for_ssa(available);
403 nir_cf_node_insert(b.cursor, &available_if->cf_node);
404
405 b.cursor = nir_after_cf_list(&available_if->then_list);
406
407 nir_store_var(&b, output_offset, output_base, 0x1);
408 for (int i = 0; i < 11; ++i) {
409 nir_if *store_if = nir_if_create(b.shader);
410 store_if->condition = nir_src_for_ssa(nir_iand(&b, stats_mask, nir_imm_int(&b, 1u << i)));
411 nir_cf_node_insert(b.cursor, &store_if->cf_node);
412
413 b.cursor = nir_after_cf_list(&store_if->then_list);
414
415 load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
416 load->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
417 load->src[1] = nir_src_for_ssa(nir_iadd(&b, input_base,
418 nir_imm_int(&b, pipeline_statistics_indices[i] * 8)));
419 nir_ssa_dest_init(&load->instr, &load->dest, 1, 64, NULL);
420 load->num_components = 1;
421 nir_builder_instr_insert(&b, &load->instr);
422 nir_ssa_def *start = &load->dest.ssa;
423
424 load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
425 load->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
426 load->src[1] = nir_src_for_ssa(nir_iadd(&b, input_base,
427 nir_imm_int(&b, pipeline_statistics_indices[i] * 8 + pipelinestat_block_size)));
428 nir_ssa_dest_init(&load->instr, &load->dest, 1, 64, NULL);
429 load->num_components = 1;
430 nir_builder_instr_insert(&b, &load->instr);
431 nir_ssa_def *end = &load->dest.ssa;
432
433 nir_ssa_def *result = nir_isub(&b, end, start);
434
435 /* Store result */
436 nir_if *store_64bit_if = nir_if_create(b.shader);
437 store_64bit_if->condition = nir_src_for_ssa(result_is_64bit);
438 nir_cf_node_insert(b.cursor, &store_64bit_if->cf_node);
439
440 b.cursor = nir_after_cf_list(&store_64bit_if->then_list);
441
442 nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
443 store->src[0] = nir_src_for_ssa(result);
444 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
445 store->src[2] = nir_src_for_ssa(nir_load_var(&b, output_offset));
446 nir_intrinsic_set_write_mask(store, 0x1);
447 store->num_components = 1;
448 nir_builder_instr_insert(&b, &store->instr);
449
450 b.cursor = nir_after_cf_list(&store_64bit_if->else_list);
451
452 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
453 store->src[0] = nir_src_for_ssa(nir_u2u32(&b, result));
454 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
455 store->src[2] = nir_src_for_ssa(nir_load_var(&b, output_offset));
456 nir_intrinsic_set_write_mask(store, 0x1);
457 store->num_components = 1;
458 nir_builder_instr_insert(&b, &store->instr);
459
460 b.cursor = nir_after_cf_node(&store_64bit_if->cf_node);
461
462 nir_store_var(&b, output_offset,
463 nir_iadd(&b, nir_load_var(&b, output_offset),
464 elem_size), 0x1);
465
466 b.cursor = nir_after_cf_node(&store_if->cf_node);
467 }
468
469 b.cursor = nir_after_cf_list(&available_if->else_list);
470
471 available_if = nir_if_create(b.shader);
472 available_if->condition = nir_src_for_ssa(nir_iand(&b, flags,
473 nir_imm_int(&b, VK_QUERY_RESULT_PARTIAL_BIT)));
474 nir_cf_node_insert(b.cursor, &available_if->cf_node);
475
476 b.cursor = nir_after_cf_list(&available_if->then_list);
477
478 /* Stores zeros in all outputs. */
479
480 nir_variable *counter = nir_local_variable_create(b.impl, glsl_int_type(), "counter");
481 nir_store_var(&b, counter, nir_imm_int(&b, 0), 0x1);
482
483 nir_loop *loop = nir_loop_create(b.shader);
484 nir_builder_cf_insert(&b, &loop->cf_node);
485 b.cursor = nir_after_cf_list(&loop->body);
486
487 nir_ssa_def *current_counter = nir_load_var(&b, counter);
488 radv_break_on_count(&b, counter, elem_count);
489
490 nir_ssa_def *output_elem = nir_iadd(&b, output_base,
491 nir_imul(&b, elem_size, current_counter));
492
493 nir_if *store_64bit_if = nir_if_create(b.shader);
494 store_64bit_if->condition = nir_src_for_ssa(result_is_64bit);
495 nir_cf_node_insert(b.cursor, &store_64bit_if->cf_node);
496
497 b.cursor = nir_after_cf_list(&store_64bit_if->then_list);
498
499 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
500 store->src[0] = nir_src_for_ssa(nir_imm_int64(&b, 0));
501 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
502 store->src[2] = nir_src_for_ssa(output_elem);
503 nir_intrinsic_set_write_mask(store, 0x1);
504 store->num_components = 1;
505 nir_builder_instr_insert(&b, &store->instr);
506
507 b.cursor = nir_after_cf_list(&store_64bit_if->else_list);
508
509 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
510 store->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
511 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
512 store->src[2] = nir_src_for_ssa(output_elem);
513 nir_intrinsic_set_write_mask(store, 0x1);
514 store->num_components = 1;
515 nir_builder_instr_insert(&b, &store->instr);
516
517 b.cursor = nir_after_cf_node(&loop->cf_node);
518 return b.shader;
519 }
520
521 VkResult radv_device_init_meta_query_state(struct radv_device *device)
522 {
523 VkResult result;
524 struct radv_shader_module occlusion_cs = { .nir = NULL };
525 struct radv_shader_module pipeline_statistics_cs = { .nir = NULL };
526
527 zero(device->meta_state.query);
528
529 occlusion_cs.nir = build_occlusion_query_shader(device);
530 pipeline_statistics_cs.nir = build_pipeline_statistics_query_shader(device);
531
532 VkDescriptorSetLayoutCreateInfo occlusion_ds_create_info = {
533 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
534 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
535 .bindingCount = 2,
536 .pBindings = (VkDescriptorSetLayoutBinding[]) {
537 {
538 .binding = 0,
539 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
540 .descriptorCount = 1,
541 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
542 .pImmutableSamplers = NULL
543 },
544 {
545 .binding = 1,
546 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
547 .descriptorCount = 1,
548 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
549 .pImmutableSamplers = NULL
550 },
551 }
552 };
553
554 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
555 &occlusion_ds_create_info,
556 &device->meta_state.alloc,
557 &device->meta_state.query.ds_layout);
558 if (result != VK_SUCCESS)
559 goto fail;
560
561 VkPipelineLayoutCreateInfo occlusion_pl_create_info = {
562 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
563 .setLayoutCount = 1,
564 .pSetLayouts = &device->meta_state.query.ds_layout,
565 .pushConstantRangeCount = 1,
566 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
567 };
568
569 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
570 &occlusion_pl_create_info,
571 &device->meta_state.alloc,
572 &device->meta_state.query.p_layout);
573 if (result != VK_SUCCESS)
574 goto fail;
575
576 VkPipelineShaderStageCreateInfo occlusion_pipeline_shader_stage = {
577 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
578 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
579 .module = radv_shader_module_to_handle(&occlusion_cs),
580 .pName = "main",
581 .pSpecializationInfo = NULL,
582 };
583
584 VkComputePipelineCreateInfo occlusion_vk_pipeline_info = {
585 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
586 .stage = occlusion_pipeline_shader_stage,
587 .flags = 0,
588 .layout = device->meta_state.query.p_layout,
589 };
590
591 result = radv_CreateComputePipelines(radv_device_to_handle(device),
592 radv_pipeline_cache_to_handle(&device->meta_state.cache),
593 1, &occlusion_vk_pipeline_info, NULL,
594 &device->meta_state.query.occlusion_query_pipeline);
595 if (result != VK_SUCCESS)
596 goto fail;
597
598 VkPipelineShaderStageCreateInfo pipeline_statistics_pipeline_shader_stage = {
599 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
600 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
601 .module = radv_shader_module_to_handle(&pipeline_statistics_cs),
602 .pName = "main",
603 .pSpecializationInfo = NULL,
604 };
605
606 VkComputePipelineCreateInfo pipeline_statistics_vk_pipeline_info = {
607 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
608 .stage = pipeline_statistics_pipeline_shader_stage,
609 .flags = 0,
610 .layout = device->meta_state.query.p_layout,
611 };
612
613 result = radv_CreateComputePipelines(radv_device_to_handle(device),
614 radv_pipeline_cache_to_handle(&device->meta_state.cache),
615 1, &pipeline_statistics_vk_pipeline_info, NULL,
616 &device->meta_state.query.pipeline_statistics_query_pipeline);
617 if (result != VK_SUCCESS)
618 goto fail;
619
620 return VK_SUCCESS;
621 fail:
622 radv_device_finish_meta_query_state(device);
623 ralloc_free(occlusion_cs.nir);
624 ralloc_free(pipeline_statistics_cs.nir);
625 return result;
626 }
627
628 void radv_device_finish_meta_query_state(struct radv_device *device)
629 {
630 if (device->meta_state.query.pipeline_statistics_query_pipeline)
631 radv_DestroyPipeline(radv_device_to_handle(device),
632 device->meta_state.query.pipeline_statistics_query_pipeline,
633 &device->meta_state.alloc);
634
635 if (device->meta_state.query.occlusion_query_pipeline)
636 radv_DestroyPipeline(radv_device_to_handle(device),
637 device->meta_state.query.occlusion_query_pipeline,
638 &device->meta_state.alloc);
639
640 if (device->meta_state.query.p_layout)
641 radv_DestroyPipelineLayout(radv_device_to_handle(device),
642 device->meta_state.query.p_layout,
643 &device->meta_state.alloc);
644
645 if (device->meta_state.query.ds_layout)
646 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
647 device->meta_state.query.ds_layout,
648 &device->meta_state.alloc);
649 }
650
651 static void radv_query_shader(struct radv_cmd_buffer *cmd_buffer,
652 VkPipeline pipeline,
653 struct radeon_winsys_bo *src_bo,
654 struct radeon_winsys_bo *dst_bo,
655 uint64_t src_offset, uint64_t dst_offset,
656 uint32_t src_stride, uint32_t dst_stride,
657 uint32_t count, uint32_t flags,
658 uint32_t pipeline_stats_mask, uint32_t avail_offset)
659 {
660 struct radv_device *device = cmd_buffer->device;
661 struct radv_meta_saved_compute_state saved_state;
662
663 radv_meta_save_compute(&saved_state, cmd_buffer, 4);
664
665 struct radv_buffer dst_buffer = {
666 .bo = dst_bo,
667 .offset = dst_offset,
668 .size = dst_stride * count
669 };
670
671 struct radv_buffer src_buffer = {
672 .bo = src_bo,
673 .offset = src_offset,
674 .size = MAX2(src_stride * count, avail_offset + 4 * count - src_offset)
675 };
676
677 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
678 VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
679
680 radv_meta_push_descriptor_set(cmd_buffer,
681 VK_PIPELINE_BIND_POINT_COMPUTE,
682 device->meta_state.query.p_layout,
683 0, /* set */
684 2, /* descriptorWriteCount */
685 (VkWriteDescriptorSet[]) {
686 {
687 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
688 .dstBinding = 0,
689 .dstArrayElement = 0,
690 .descriptorCount = 1,
691 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
692 .pBufferInfo = &(VkDescriptorBufferInfo) {
693 .buffer = radv_buffer_to_handle(&dst_buffer),
694 .offset = 0,
695 .range = VK_WHOLE_SIZE
696 }
697 },
698 {
699 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
700 .dstBinding = 1,
701 .dstArrayElement = 0,
702 .descriptorCount = 1,
703 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
704 .pBufferInfo = &(VkDescriptorBufferInfo) {
705 .buffer = radv_buffer_to_handle(&src_buffer),
706 .offset = 0,
707 .range = VK_WHOLE_SIZE
708 }
709 }
710 });
711
712 /* Encode the number of elements for easy access by the shader. */
713 pipeline_stats_mask &= 0x7ff;
714 pipeline_stats_mask |= util_bitcount(pipeline_stats_mask) << 16;
715
716 avail_offset -= src_offset;
717
718 struct {
719 uint32_t flags;
720 uint32_t dst_stride;
721 uint32_t pipeline_stats_mask;
722 uint32_t avail_offset;
723 } push_constants = {
724 flags,
725 dst_stride,
726 pipeline_stats_mask,
727 avail_offset
728 };
729
730 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
731 device->meta_state.query.p_layout,
732 VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(push_constants),
733 &push_constants);
734
735 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2 |
736 RADV_CMD_FLAG_INV_VMEM_L1;
737
738 if (flags & VK_QUERY_RESULT_WAIT_BIT)
739 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER;
740
741 radv_unaligned_dispatch(cmd_buffer, count, 1, 1);
742
743 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2 |
744 RADV_CMD_FLAG_INV_VMEM_L1 |
745 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
746
747 radv_meta_restore_compute(&saved_state, cmd_buffer, 4);
748 }
749
750 VkResult radv_CreateQueryPool(
751 VkDevice _device,
752 const VkQueryPoolCreateInfo* pCreateInfo,
753 const VkAllocationCallbacks* pAllocator,
754 VkQueryPool* pQueryPool)
755 {
756 RADV_FROM_HANDLE(radv_device, device, _device);
757 uint64_t size;
758 struct radv_query_pool *pool = vk_alloc2(&device->alloc, pAllocator,
759 sizeof(*pool), 8,
760 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
761
762 if (!pool)
763 return VK_ERROR_OUT_OF_HOST_MEMORY;
764
765
766 switch(pCreateInfo->queryType) {
767 case VK_QUERY_TYPE_OCCLUSION:
768 pool->stride = 16 * get_max_db(device);
769 break;
770 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
771 pool->stride = pipelinestat_block_size * 2;
772 break;
773 case VK_QUERY_TYPE_TIMESTAMP:
774 pool->stride = 8;
775 break;
776 default:
777 unreachable("creating unhandled query type");
778 }
779
780 pool->type = pCreateInfo->queryType;
781 pool->pipeline_stats_mask = pCreateInfo->pipelineStatistics;
782 pool->availability_offset = pool->stride * pCreateInfo->queryCount;
783 size = pool->availability_offset;
784 if (pCreateInfo->queryType == VK_QUERY_TYPE_TIMESTAMP ||
785 pCreateInfo->queryType == VK_QUERY_TYPE_PIPELINE_STATISTICS)
786 size += 4 * pCreateInfo->queryCount;
787
788 pool->bo = device->ws->buffer_create(device->ws, size,
789 64, RADEON_DOMAIN_GTT, 0);
790
791 if (!pool->bo) {
792 vk_free2(&device->alloc, pAllocator, pool);
793 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
794 }
795
796 pool->ptr = device->ws->buffer_map(pool->bo);
797
798 if (!pool->ptr) {
799 device->ws->buffer_destroy(pool->bo);
800 vk_free2(&device->alloc, pAllocator, pool);
801 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
802 }
803 memset(pool->ptr, 0, size);
804
805 *pQueryPool = radv_query_pool_to_handle(pool);
806 return VK_SUCCESS;
807 }
808
809 void radv_DestroyQueryPool(
810 VkDevice _device,
811 VkQueryPool _pool,
812 const VkAllocationCallbacks* pAllocator)
813 {
814 RADV_FROM_HANDLE(radv_device, device, _device);
815 RADV_FROM_HANDLE(radv_query_pool, pool, _pool);
816
817 if (!pool)
818 return;
819
820 device->ws->buffer_destroy(pool->bo);
821 vk_free2(&device->alloc, pAllocator, pool);
822 }
823
824 VkResult radv_GetQueryPoolResults(
825 VkDevice _device,
826 VkQueryPool queryPool,
827 uint32_t firstQuery,
828 uint32_t queryCount,
829 size_t dataSize,
830 void* pData,
831 VkDeviceSize stride,
832 VkQueryResultFlags flags)
833 {
834 RADV_FROM_HANDLE(radv_device, device, _device);
835 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
836 char *data = pData;
837 VkResult result = VK_SUCCESS;
838
839 for(unsigned i = 0; i < queryCount; ++i, data += stride) {
840 char *dest = data;
841 unsigned query = firstQuery + i;
842 char *src = pool->ptr + query * pool->stride;
843 uint32_t available;
844
845 if (pool->type != VK_QUERY_TYPE_OCCLUSION) {
846 if (flags & VK_QUERY_RESULT_WAIT_BIT)
847 while(!*(volatile uint32_t*)(pool->ptr + pool->availability_offset + 4 * query))
848 ;
849 available = *(uint32_t*)(pool->ptr + pool->availability_offset + 4 * query);
850 }
851
852 switch (pool->type) {
853 case VK_QUERY_TYPE_TIMESTAMP: {
854 if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT)) {
855 result = VK_NOT_READY;
856 break;
857
858 }
859
860 if (flags & VK_QUERY_RESULT_64_BIT) {
861 *(uint64_t*)dest = *(uint64_t*)src;
862 dest += 8;
863 } else {
864 *(uint32_t*)dest = *(uint32_t*)src;
865 dest += 4;
866 }
867 break;
868 }
869 case VK_QUERY_TYPE_OCCLUSION: {
870 volatile uint64_t const *src64 = (volatile uint64_t const *)src;
871 uint64_t sample_count = 0;
872 int db_count = get_max_db(device);
873 available = 1;
874
875 for (int i = 0; i < db_count; ++i) {
876 uint64_t start, end;
877 do {
878 start = src64[2 * i];
879 end = src64[2 * i + 1];
880 } while ((!(start & (1ull << 63)) || !(end & (1ull << 63))) && (flags & VK_QUERY_RESULT_WAIT_BIT));
881
882 if (!(start & (1ull << 63)) || !(end & (1ull << 63)))
883 available = 0;
884 else {
885 sample_count += end - start;
886 }
887 }
888
889 if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT)) {
890 result = VK_NOT_READY;
891 break;
892
893 }
894
895 if (flags & VK_QUERY_RESULT_64_BIT) {
896 *(uint64_t*)dest = sample_count;
897 dest += 8;
898 } else {
899 *(uint32_t*)dest = sample_count;
900 dest += 4;
901 }
902 break;
903 }
904 case VK_QUERY_TYPE_PIPELINE_STATISTICS: {
905 if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT)) {
906 result = VK_NOT_READY;
907 break;
908
909 }
910
911 const uint64_t *start = (uint64_t*)src;
912 const uint64_t *stop = (uint64_t*)(src + pipelinestat_block_size);
913 if (flags & VK_QUERY_RESULT_64_BIT) {
914 uint64_t *dst = (uint64_t*)dest;
915 dest += util_bitcount(pool->pipeline_stats_mask) * 8;
916 for(int i = 0; i < 11; ++i)
917 if(pool->pipeline_stats_mask & (1u << i))
918 *dst++ = stop[pipeline_statistics_indices[i]] -
919 start[pipeline_statistics_indices[i]];
920
921 } else {
922 uint32_t *dst = (uint32_t*)dest;
923 dest += util_bitcount(pool->pipeline_stats_mask) * 4;
924 for(int i = 0; i < 11; ++i)
925 if(pool->pipeline_stats_mask & (1u << i))
926 *dst++ = stop[pipeline_statistics_indices[i]] -
927 start[pipeline_statistics_indices[i]];
928 }
929 break;
930 }
931 default:
932 unreachable("trying to get results of unhandled query type");
933 }
934
935 if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
936 if (flags & VK_QUERY_RESULT_64_BIT) {
937 *(uint64_t*)dest = available;
938 } else {
939 *(uint32_t*)dest = available;
940 }
941 }
942 }
943
944 return result;
945 }
946
947 void radv_CmdCopyQueryPoolResults(
948 VkCommandBuffer commandBuffer,
949 VkQueryPool queryPool,
950 uint32_t firstQuery,
951 uint32_t queryCount,
952 VkBuffer dstBuffer,
953 VkDeviceSize dstOffset,
954 VkDeviceSize stride,
955 VkQueryResultFlags flags)
956 {
957 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
958 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
959 RADV_FROM_HANDLE(radv_buffer, dst_buffer, dstBuffer);
960 struct radeon_winsys_cs *cs = cmd_buffer->cs;
961 unsigned elem_size = (flags & VK_QUERY_RESULT_64_BIT) ? 8 : 4;
962 uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
963 uint64_t dest_va = cmd_buffer->device->ws->buffer_get_va(dst_buffer->bo);
964 dest_va += dst_buffer->offset + dstOffset;
965
966 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, pool->bo, 8);
967 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, dst_buffer->bo, 8);
968
969 switch (pool->type) {
970 case VK_QUERY_TYPE_OCCLUSION:
971 if (flags & VK_QUERY_RESULT_WAIT_BIT) {
972 for(unsigned i = 0; i < queryCount; ++i, dest_va += stride) {
973 unsigned query = firstQuery + i;
974 uint64_t src_va = va + query * pool->stride + pool->stride - 4;
975
976 /* Waits on the upper word of the last DB entry */
977 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
978 radeon_emit(cs, 5 | WAIT_REG_MEM_MEM_SPACE(1));
979 radeon_emit(cs, src_va);
980 radeon_emit(cs, src_va >> 32);
981 radeon_emit(cs, 0x80000000); /* reference value */
982 radeon_emit(cs, 0xffffffff); /* mask */
983 radeon_emit(cs, 4); /* poll interval */
984 }
985 }
986 radv_query_shader(cmd_buffer, cmd_buffer->device->meta_state.query.occlusion_query_pipeline,
987 pool->bo, dst_buffer->bo, firstQuery * pool->stride,
988 dst_buffer->offset + dstOffset,
989 get_max_db(cmd_buffer->device) * 16, stride,
990 queryCount, flags, 0, 0);
991 break;
992 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
993 if (flags & VK_QUERY_RESULT_WAIT_BIT) {
994 for(unsigned i = 0; i < queryCount; ++i, dest_va += stride) {
995 unsigned query = firstQuery + i;
996
997 radeon_check_space(cmd_buffer->device->ws, cs, 7);
998
999 uint64_t avail_va = va + pool->availability_offset + 4 * query;
1000
1001 /* This waits on the ME. All copies below are done on the ME */
1002 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
1003 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
1004 radeon_emit(cs, avail_va);
1005 radeon_emit(cs, avail_va >> 32);
1006 radeon_emit(cs, 1); /* reference value */
1007 radeon_emit(cs, 0xffffffff); /* mask */
1008 radeon_emit(cs, 4); /* poll interval */
1009 }
1010 }
1011 radv_query_shader(cmd_buffer, cmd_buffer->device->meta_state.query.pipeline_statistics_query_pipeline,
1012 pool->bo, dst_buffer->bo, firstQuery * pool->stride,
1013 dst_buffer->offset + dstOffset,
1014 pipelinestat_block_size * 2, stride, queryCount, flags,
1015 pool->pipeline_stats_mask,
1016 pool->availability_offset + 4 * firstQuery);
1017 break;
1018 case VK_QUERY_TYPE_TIMESTAMP:
1019 for(unsigned i = 0; i < queryCount; ++i, dest_va += stride) {
1020 unsigned query = firstQuery + i;
1021 uint64_t local_src_va = va + query * pool->stride;
1022
1023 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 19);
1024
1025
1026 if (flags & VK_QUERY_RESULT_WAIT_BIT) {
1027 /* TODO, not sure if there is any case where we won't always be ready yet */
1028 uint64_t avail_va = va + pool->availability_offset + 4 * query;
1029
1030 /* This waits on the ME. All copies below are done on the ME */
1031 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
1032 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
1033 radeon_emit(cs, avail_va);
1034 radeon_emit(cs, avail_va >> 32);
1035 radeon_emit(cs, 1); /* reference value */
1036 radeon_emit(cs, 0xffffffff); /* mask */
1037 radeon_emit(cs, 4); /* poll interval */
1038 }
1039 if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
1040 uint64_t avail_va = va + pool->availability_offset + 4 * query;
1041 uint64_t avail_dest_va = dest_va + elem_size;
1042
1043 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1044 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1045 COPY_DATA_DST_SEL(COPY_DATA_MEM));
1046 radeon_emit(cs, avail_va);
1047 radeon_emit(cs, avail_va >> 32);
1048 radeon_emit(cs, avail_dest_va);
1049 radeon_emit(cs, avail_dest_va >> 32);
1050 }
1051
1052 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1053 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1054 COPY_DATA_DST_SEL(COPY_DATA_MEM) |
1055 ((flags & VK_QUERY_RESULT_64_BIT) ? COPY_DATA_COUNT_SEL : 0));
1056 radeon_emit(cs, local_src_va);
1057 radeon_emit(cs, local_src_va >> 32);
1058 radeon_emit(cs, dest_va);
1059 radeon_emit(cs, dest_va >> 32);
1060
1061
1062 assert(cs->cdw <= cdw_max);
1063 }
1064 break;
1065 default:
1066 unreachable("trying to get results of unhandled query type");
1067 }
1068
1069 }
1070
1071 void radv_CmdResetQueryPool(
1072 VkCommandBuffer commandBuffer,
1073 VkQueryPool queryPool,
1074 uint32_t firstQuery,
1075 uint32_t queryCount)
1076 {
1077 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1078 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
1079 uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
1080
1081 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, pool->bo, 8);
1082
1083 si_cp_dma_clear_buffer(cmd_buffer, va + firstQuery * pool->stride,
1084 queryCount * pool->stride, 0);
1085 if (pool->type == VK_QUERY_TYPE_TIMESTAMP ||
1086 pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS)
1087 si_cp_dma_clear_buffer(cmd_buffer, va + pool->availability_offset + firstQuery * 4,
1088 queryCount * 4, 0);
1089 }
1090
1091 void radv_CmdBeginQuery(
1092 VkCommandBuffer commandBuffer,
1093 VkQueryPool queryPool,
1094 uint32_t query,
1095 VkQueryControlFlags flags)
1096 {
1097 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1098 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
1099 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1100 uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
1101 va += pool->stride * query;
1102
1103 cmd_buffer->device->ws->cs_add_buffer(cs, pool->bo, 8);
1104
1105 switch (pool->type) {
1106 case VK_QUERY_TYPE_OCCLUSION:
1107 radeon_check_space(cmd_buffer->device->ws, cs, 7);
1108
1109 ++cmd_buffer->state.active_occlusion_queries;
1110 if (cmd_buffer->state.active_occlusion_queries == 1)
1111 radv_set_db_count_control(cmd_buffer);
1112
1113 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1114 radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
1115 radeon_emit(cs, va);
1116 radeon_emit(cs, va >> 32);
1117 break;
1118 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
1119 radeon_check_space(cmd_buffer->device->ws, cs, 4);
1120
1121 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1122 radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
1123 radeon_emit(cs, va);
1124 radeon_emit(cs, va >> 32);
1125 break;
1126 default:
1127 unreachable("beginning unhandled query type");
1128 }
1129 }
1130
1131
1132 void radv_CmdEndQuery(
1133 VkCommandBuffer commandBuffer,
1134 VkQueryPool queryPool,
1135 uint32_t query)
1136 {
1137 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1138 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
1139 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1140 uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
1141 uint64_t avail_va = va + pool->availability_offset + 4 * query;
1142 va += pool->stride * query;
1143
1144 cmd_buffer->device->ws->cs_add_buffer(cs, pool->bo, 8);
1145
1146 switch (pool->type) {
1147 case VK_QUERY_TYPE_OCCLUSION:
1148 radeon_check_space(cmd_buffer->device->ws, cs, 14);
1149
1150 cmd_buffer->state.active_occlusion_queries--;
1151 if (cmd_buffer->state.active_occlusion_queries == 0)
1152 radv_set_db_count_control(cmd_buffer);
1153
1154 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1155 radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
1156 radeon_emit(cs, va + 8);
1157 radeon_emit(cs, (va + 8) >> 32);
1158
1159 break;
1160 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
1161 radeon_check_space(cmd_buffer->device->ws, cs, 10);
1162
1163 va += pipelinestat_block_size;
1164
1165 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1166 radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
1167 radeon_emit(cs, va);
1168 radeon_emit(cs, va >> 32);
1169
1170 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
1171 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
1172 EVENT_INDEX(5));
1173 radeon_emit(cs, avail_va);
1174 radeon_emit(cs, (avail_va >> 32) | EOP_DATA_SEL(1));
1175 radeon_emit(cs, 1);
1176 radeon_emit(cs, 0);
1177 break;
1178 default:
1179 unreachable("ending unhandled query type");
1180 }
1181 }
1182
1183 void radv_CmdWriteTimestamp(
1184 VkCommandBuffer commandBuffer,
1185 VkPipelineStageFlagBits pipelineStage,
1186 VkQueryPool queryPool,
1187 uint32_t query)
1188 {
1189 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1190 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
1191 bool mec = radv_cmd_buffer_uses_mec(cmd_buffer);
1192 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1193 uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
1194 uint64_t avail_va = va + pool->availability_offset + 4 * query;
1195 uint64_t query_va = va + pool->stride * query;
1196
1197 cmd_buffer->device->ws->cs_add_buffer(cs, pool->bo, 5);
1198
1199 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 14);
1200
1201 switch(pipelineStage) {
1202 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:
1203 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1204 radeon_emit(cs, COPY_DATA_COUNT_SEL | COPY_DATA_WR_CONFIRM |
1205 COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
1206 COPY_DATA_DST_SEL(V_370_MEM_ASYNC));
1207 radeon_emit(cs, 0);
1208 radeon_emit(cs, 0);
1209 radeon_emit(cs, query_va);
1210 radeon_emit(cs, query_va >> 32);
1211
1212 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1213 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1214 S_370_WR_CONFIRM(1) |
1215 S_370_ENGINE_SEL(V_370_ME));
1216 radeon_emit(cs, avail_va);
1217 radeon_emit(cs, avail_va >> 32);
1218 radeon_emit(cs, 1);
1219 break;
1220 default:
1221 if (mec) {
1222 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 5, 0));
1223 radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
1224 radeon_emit(cs, 3 << 29);
1225 radeon_emit(cs, query_va);
1226 radeon_emit(cs, query_va >> 32);
1227 radeon_emit(cs, 0);
1228 radeon_emit(cs, 0);
1229
1230 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 5, 0));
1231 radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
1232 radeon_emit(cs, 1 << 29);
1233 radeon_emit(cs, avail_va);
1234 radeon_emit(cs, avail_va >> 32);
1235 radeon_emit(cs, 1);
1236 radeon_emit(cs, 0);
1237 } else {
1238 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
1239 radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
1240 radeon_emit(cs, query_va);
1241 radeon_emit(cs, (3 << 29) | ((query_va >> 32) & 0xFFFF));
1242 radeon_emit(cs, 0);
1243 radeon_emit(cs, 0);
1244
1245 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
1246 radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
1247 radeon_emit(cs, avail_va);
1248 radeon_emit(cs, (1 << 29) | ((avail_va >> 32) & 0xFFFF));
1249 radeon_emit(cs, 1);
1250 radeon_emit(cs, 0);
1251 }
1252 break;
1253 }
1254
1255 assert(cmd_buffer->cs->cdw <= cdw_max);
1256 }