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radv: fix setting global locations for indirect descriptors
[mesa.git] / src / amd / vulkan / radv_query.c
1 /*
2 * Copyrigh 2016 Red Hat Inc.
3 * Based on anv:
4 * Copyright © 2015 Intel Corporation
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25
26 #include <assert.h>
27 #include <stdbool.h>
28 #include <string.h>
29 #include <unistd.h>
30 #include <fcntl.h>
31
32 #include "nir/nir_builder.h"
33 #include "radv_meta.h"
34 #include "radv_private.h"
35 #include "radv_cs.h"
36 #include "sid.h"
37
38
39 static const int pipelinestat_block_size = 11 * 8;
40 static const unsigned pipeline_statistics_indices[] = {7, 6, 3, 4, 5, 2, 1, 0, 8, 9, 10};
41
42 static unsigned get_max_db(struct radv_device *device)
43 {
44 unsigned num_db = device->physical_device->rad_info.num_render_backends;
45 MAYBE_UNUSED unsigned rb_mask = device->physical_device->rad_info.enabled_rb_mask;
46
47 /* Otherwise we need to change the query reset procedure */
48 assert(rb_mask == ((1ull << num_db) - 1));
49
50 return num_db;
51 }
52
53 static void radv_break_on_count(nir_builder *b, nir_variable *var, nir_ssa_def *count)
54 {
55 nir_ssa_def *counter = nir_load_var(b, var);
56
57 nir_if *if_stmt = nir_if_create(b->shader);
58 if_stmt->condition = nir_src_for_ssa(nir_uge(b, counter, count));
59 nir_cf_node_insert(b->cursor, &if_stmt->cf_node);
60
61 b->cursor = nir_after_cf_list(&if_stmt->then_list);
62
63 nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_break);
64 nir_builder_instr_insert(b, &instr->instr);
65
66 b->cursor = nir_after_cf_node(&if_stmt->cf_node);
67 counter = nir_iadd(b, counter, nir_imm_int(b, 1));
68 nir_store_var(b, var, counter, 0x1);
69 }
70
71 static struct nir_ssa_def *
72 radv_load_push_int(nir_builder *b, unsigned offset, const char *name)
73 {
74 nir_intrinsic_instr *flags = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
75 nir_intrinsic_set_base(flags, 0);
76 nir_intrinsic_set_range(flags, 16);
77 flags->src[0] = nir_src_for_ssa(nir_imm_int(b, offset));
78 flags->num_components = 1;
79 nir_ssa_dest_init(&flags->instr, &flags->dest, 1, 32, name);
80 nir_builder_instr_insert(b, &flags->instr);
81 return &flags->dest.ssa;
82 }
83
84 static nir_shader *
85 build_occlusion_query_shader(struct radv_device *device) {
86 /* the shader this builds is roughly
87 *
88 * push constants {
89 * uint32_t flags;
90 * uint32_t dst_stride;
91 * };
92 *
93 * uint32_t src_stride = 16 * db_count;
94 *
95 * location(binding = 0) buffer dst_buf;
96 * location(binding = 1) buffer src_buf;
97 *
98 * void main() {
99 * uint64_t result = 0;
100 * uint64_t src_offset = src_stride * global_id.x;
101 * uint64_t dst_offset = dst_stride * global_id.x;
102 * bool available = true;
103 * for (int i = 0; i < db_count; ++i) {
104 * uint64_t start = src_buf[src_offset + 16 * i];
105 * uint64_t end = src_buf[src_offset + 16 * i + 8];
106 * if ((start & (1ull << 63)) && (end & (1ull << 63)))
107 * result += end - start;
108 * else
109 * available = false;
110 * }
111 * uint32_t elem_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;
112 * if ((flags & VK_QUERY_RESULT_PARTIAL_BIT) || available) {
113 * if (flags & VK_QUERY_RESULT_64_BIT)
114 * dst_buf[dst_offset] = result;
115 * else
116 * dst_buf[dst_offset] = (uint32_t)result.
117 * }
118 * if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
119 * dst_buf[dst_offset + elem_size] = available;
120 * }
121 * }
122 */
123 nir_builder b;
124 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
125 b.shader->info.name = ralloc_strdup(b.shader, "occlusion_query");
126 b.shader->info.cs.local_size[0] = 64;
127 b.shader->info.cs.local_size[1] = 1;
128 b.shader->info.cs.local_size[2] = 1;
129
130 nir_variable *result = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "result");
131 nir_variable *outer_counter = nir_local_variable_create(b.impl, glsl_int_type(), "outer_counter");
132 nir_variable *start = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "start");
133 nir_variable *end = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "end");
134 nir_variable *available = nir_local_variable_create(b.impl, glsl_int_type(), "available");
135 unsigned db_count = get_max_db(device);
136
137 nir_ssa_def *flags = radv_load_push_int(&b, 0, "flags");
138
139 nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
140 nir_intrinsic_vulkan_resource_index);
141 dst_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
142 nir_intrinsic_set_desc_set(dst_buf, 0);
143 nir_intrinsic_set_binding(dst_buf, 0);
144 nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, 1, 32, NULL);
145 nir_builder_instr_insert(&b, &dst_buf->instr);
146
147 nir_intrinsic_instr *src_buf = nir_intrinsic_instr_create(b.shader,
148 nir_intrinsic_vulkan_resource_index);
149 src_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
150 nir_intrinsic_set_desc_set(src_buf, 0);
151 nir_intrinsic_set_binding(src_buf, 1);
152 nir_ssa_dest_init(&src_buf->instr, &src_buf->dest, 1, 32, NULL);
153 nir_builder_instr_insert(&b, &src_buf->instr);
154
155 nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
156 nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
157 nir_ssa_def *block_size = nir_imm_ivec4(&b,
158 b.shader->info.cs.local_size[0],
159 b.shader->info.cs.local_size[1],
160 b.shader->info.cs.local_size[2], 0);
161 nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
162 global_id = nir_channel(&b, global_id, 0); // We only care about x here.
163
164 nir_ssa_def *input_stride = nir_imm_int(&b, db_count * 16);
165 nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id);
166 nir_ssa_def *output_stride = radv_load_push_int(&b, 4, "output_stride");
167 nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id);
168
169
170 nir_store_var(&b, result, nir_imm_int64(&b, 0), 0x1);
171 nir_store_var(&b, outer_counter, nir_imm_int(&b, 0), 0x1);
172 nir_store_var(&b, available, nir_imm_int(&b, 1), 0x1);
173
174 nir_loop *outer_loop = nir_loop_create(b.shader);
175 nir_builder_cf_insert(&b, &outer_loop->cf_node);
176 b.cursor = nir_after_cf_list(&outer_loop->body);
177
178 nir_ssa_def *current_outer_count = nir_load_var(&b, outer_counter);
179 radv_break_on_count(&b, outer_counter, nir_imm_int(&b, db_count));
180
181 nir_ssa_def *load_offset = nir_imul(&b, current_outer_count, nir_imm_int(&b, 16));
182 load_offset = nir_iadd(&b, input_base, load_offset);
183
184 nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
185 load->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
186 load->src[1] = nir_src_for_ssa(load_offset);
187 nir_ssa_dest_init(&load->instr, &load->dest, 2, 64, NULL);
188 load->num_components = 2;
189 nir_builder_instr_insert(&b, &load->instr);
190
191 nir_store_var(&b, start, nir_channel(&b, &load->dest.ssa, 0), 0x1);
192 nir_store_var(&b, end, nir_channel(&b, &load->dest.ssa, 1), 0x1);
193
194 nir_ssa_def *start_done = nir_ilt(&b, nir_load_var(&b, start), nir_imm_int64(&b, 0));
195 nir_ssa_def *end_done = nir_ilt(&b, nir_load_var(&b, end), nir_imm_int64(&b, 0));
196
197 nir_if *update_if = nir_if_create(b.shader);
198 update_if->condition = nir_src_for_ssa(nir_iand(&b, start_done, end_done));
199 nir_cf_node_insert(b.cursor, &update_if->cf_node);
200
201 b.cursor = nir_after_cf_list(&update_if->then_list);
202
203 nir_store_var(&b, result,
204 nir_iadd(&b, nir_load_var(&b, result),
205 nir_isub(&b, nir_load_var(&b, end),
206 nir_load_var(&b, start))), 0x1);
207
208 b.cursor = nir_after_cf_list(&update_if->else_list);
209
210 nir_store_var(&b, available, nir_imm_int(&b, 0), 0x1);
211
212 b.cursor = nir_after_cf_node(&outer_loop->cf_node);
213
214 /* Store the result if complete or if partial results have been requested. */
215
216 nir_ssa_def *result_is_64bit = nir_iand(&b, flags,
217 nir_imm_int(&b, VK_QUERY_RESULT_64_BIT));
218 nir_ssa_def *result_size = nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 8), nir_imm_int(&b, 4));
219
220 nir_if *store_if = nir_if_create(b.shader);
221 store_if->condition = nir_src_for_ssa(nir_ior(&b, nir_iand(&b, flags, nir_imm_int(&b, VK_QUERY_RESULT_PARTIAL_BIT)), nir_load_var(&b, available)));
222 nir_cf_node_insert(b.cursor, &store_if->cf_node);
223
224 b.cursor = nir_after_cf_list(&store_if->then_list);
225
226 nir_if *store_64bit_if = nir_if_create(b.shader);
227 store_64bit_if->condition = nir_src_for_ssa(result_is_64bit);
228 nir_cf_node_insert(b.cursor, &store_64bit_if->cf_node);
229
230 b.cursor = nir_after_cf_list(&store_64bit_if->then_list);
231
232 nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
233 store->src[0] = nir_src_for_ssa(nir_load_var(&b, result));
234 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
235 store->src[2] = nir_src_for_ssa(output_base);
236 nir_intrinsic_set_write_mask(store, 0x1);
237 store->num_components = 1;
238 nir_builder_instr_insert(&b, &store->instr);
239
240 b.cursor = nir_after_cf_list(&store_64bit_if->else_list);
241
242 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
243 store->src[0] = nir_src_for_ssa(nir_u2u32(&b, nir_load_var(&b, result)));
244 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
245 store->src[2] = nir_src_for_ssa(output_base);
246 nir_intrinsic_set_write_mask(store, 0x1);
247 store->num_components = 1;
248 nir_builder_instr_insert(&b, &store->instr);
249
250 b.cursor = nir_after_cf_node(&store_if->cf_node);
251
252 /* Store the availability bit if requested. */
253
254 nir_if *availability_if = nir_if_create(b.shader);
255 availability_if->condition = nir_src_for_ssa(nir_iand(&b, flags, nir_imm_int(&b, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT)));
256 nir_cf_node_insert(b.cursor, &availability_if->cf_node);
257
258 b.cursor = nir_after_cf_list(&availability_if->then_list);
259
260 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
261 store->src[0] = nir_src_for_ssa(nir_load_var(&b, available));
262 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
263 store->src[2] = nir_src_for_ssa(nir_iadd(&b, result_size, output_base));
264 nir_intrinsic_set_write_mask(store, 0x1);
265 store->num_components = 1;
266 nir_builder_instr_insert(&b, &store->instr);
267
268 return b.shader;
269 }
270
271 static nir_shader *
272 build_pipeline_statistics_query_shader(struct radv_device *device) {
273 /* the shader this builds is roughly
274 *
275 * push constants {
276 * uint32_t flags;
277 * uint32_t dst_stride;
278 * uint32_t stats_mask;
279 * uint32_t avail_offset;
280 * };
281 *
282 * uint32_t src_stride = pipelinestat_block_size * 2;
283 *
284 * location(binding = 0) buffer dst_buf;
285 * location(binding = 1) buffer src_buf;
286 *
287 * void main() {
288 * uint64_t src_offset = src_stride * global_id.x;
289 * uint64_t dst_base = dst_stride * global_id.x;
290 * uint64_t dst_offset = dst_base;
291 * uint32_t elem_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;
292 * uint32_t elem_count = stats_mask >> 16;
293 * uint32_t available = src_buf[avail_offset + 4 * global_id.x];
294 * if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
295 * dst_buf[dst_offset + elem_count * elem_size] = available;
296 * }
297 * if (available) {
298 * // repeat 11 times:
299 * if (stats_mask & (1 << 0)) {
300 * uint64_t start = src_buf[src_offset + 8 * indices[0]];
301 * uint64_t end = src_buf[src_offset + 8 * indices[0] + pipelinestat_block_size];
302 * uint64_t result = end - start;
303 * if (flags & VK_QUERY_RESULT_64_BIT)
304 * dst_buf[dst_offset] = result;
305 * else
306 * dst_buf[dst_offset] = (uint32_t)result.
307 * dst_offset += elem_size;
308 * }
309 * } else if (flags & VK_QUERY_RESULT_PARTIAL_BIT) {
310 * // Set everything to 0 as we don't know what is valid.
311 * for (int i = 0; i < elem_count; ++i)
312 * dst_buf[dst_base + elem_size * i] = 0;
313 * }
314 * }
315 */
316 nir_builder b;
317 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
318 b.shader->info.name = ralloc_strdup(b.shader, "pipeline_statistics_query");
319 b.shader->info.cs.local_size[0] = 64;
320 b.shader->info.cs.local_size[1] = 1;
321 b.shader->info.cs.local_size[2] = 1;
322
323 nir_variable *output_offset = nir_local_variable_create(b.impl, glsl_int_type(), "output_offset");
324
325 nir_ssa_def *flags = radv_load_push_int(&b, 0, "flags");
326 nir_ssa_def *stats_mask = radv_load_push_int(&b, 8, "stats_mask");
327 nir_ssa_def *avail_offset = radv_load_push_int(&b, 12, "avail_offset");
328
329 nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
330 nir_intrinsic_vulkan_resource_index);
331 dst_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
332 nir_intrinsic_set_desc_set(dst_buf, 0);
333 nir_intrinsic_set_binding(dst_buf, 0);
334 nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, 1, 32, NULL);
335 nir_builder_instr_insert(&b, &dst_buf->instr);
336
337 nir_intrinsic_instr *src_buf = nir_intrinsic_instr_create(b.shader,
338 nir_intrinsic_vulkan_resource_index);
339 src_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
340 nir_intrinsic_set_desc_set(src_buf, 0);
341 nir_intrinsic_set_binding(src_buf, 1);
342 nir_ssa_dest_init(&src_buf->instr, &src_buf->dest, 1, 32, NULL);
343 nir_builder_instr_insert(&b, &src_buf->instr);
344
345 nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
346 nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
347 nir_ssa_def *block_size = nir_imm_ivec4(&b,
348 b.shader->info.cs.local_size[0],
349 b.shader->info.cs.local_size[1],
350 b.shader->info.cs.local_size[2], 0);
351 nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
352 global_id = nir_channel(&b, global_id, 0); // We only care about x here.
353
354 nir_ssa_def *input_stride = nir_imm_int(&b, pipelinestat_block_size * 2);
355 nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id);
356 nir_ssa_def *output_stride = radv_load_push_int(&b, 4, "output_stride");
357 nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id);
358
359
360 avail_offset = nir_iadd(&b, avail_offset,
361 nir_imul(&b, global_id, nir_imm_int(&b, 4)));
362
363 nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
364 load->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
365 load->src[1] = nir_src_for_ssa(avail_offset);
366 nir_ssa_dest_init(&load->instr, &load->dest, 1, 32, NULL);
367 load->num_components = 1;
368 nir_builder_instr_insert(&b, &load->instr);
369 nir_ssa_def *available = &load->dest.ssa;
370
371 nir_ssa_def *result_is_64bit = nir_iand(&b, flags,
372 nir_imm_int(&b, VK_QUERY_RESULT_64_BIT));
373 nir_ssa_def *elem_size = nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 8), nir_imm_int(&b, 4));
374 nir_ssa_def *elem_count = nir_ushr(&b, stats_mask, nir_imm_int(&b, 16));
375
376 /* Store the availability bit if requested. */
377
378 nir_if *availability_if = nir_if_create(b.shader);
379 availability_if->condition = nir_src_for_ssa(nir_iand(&b, flags, nir_imm_int(&b, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT)));
380 nir_cf_node_insert(b.cursor, &availability_if->cf_node);
381
382 b.cursor = nir_after_cf_list(&availability_if->then_list);
383
384 nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
385 store->src[0] = nir_src_for_ssa(available);
386 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
387 store->src[2] = nir_src_for_ssa(nir_iadd(&b, output_base, nir_imul(&b, elem_count, elem_size)));
388 nir_intrinsic_set_write_mask(store, 0x1);
389 store->num_components = 1;
390 nir_builder_instr_insert(&b, &store->instr);
391
392 b.cursor = nir_after_cf_node(&availability_if->cf_node);
393
394 nir_if *available_if = nir_if_create(b.shader);
395 available_if->condition = nir_src_for_ssa(available);
396 nir_cf_node_insert(b.cursor, &available_if->cf_node);
397
398 b.cursor = nir_after_cf_list(&available_if->then_list);
399
400 nir_store_var(&b, output_offset, output_base, 0x1);
401 for (int i = 0; i < 11; ++i) {
402 nir_if *store_if = nir_if_create(b.shader);
403 store_if->condition = nir_src_for_ssa(nir_iand(&b, stats_mask, nir_imm_int(&b, 1u << i)));
404 nir_cf_node_insert(b.cursor, &store_if->cf_node);
405
406 b.cursor = nir_after_cf_list(&store_if->then_list);
407
408 load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
409 load->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
410 load->src[1] = nir_src_for_ssa(nir_iadd(&b, input_base,
411 nir_imm_int(&b, pipeline_statistics_indices[i] * 8)));
412 nir_ssa_dest_init(&load->instr, &load->dest, 1, 64, NULL);
413 load->num_components = 1;
414 nir_builder_instr_insert(&b, &load->instr);
415 nir_ssa_def *start = &load->dest.ssa;
416
417 load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
418 load->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
419 load->src[1] = nir_src_for_ssa(nir_iadd(&b, input_base,
420 nir_imm_int(&b, pipeline_statistics_indices[i] * 8 + pipelinestat_block_size)));
421 nir_ssa_dest_init(&load->instr, &load->dest, 1, 64, NULL);
422 load->num_components = 1;
423 nir_builder_instr_insert(&b, &load->instr);
424 nir_ssa_def *end = &load->dest.ssa;
425
426 nir_ssa_def *result = nir_isub(&b, end, start);
427
428 /* Store result */
429 nir_if *store_64bit_if = nir_if_create(b.shader);
430 store_64bit_if->condition = nir_src_for_ssa(result_is_64bit);
431 nir_cf_node_insert(b.cursor, &store_64bit_if->cf_node);
432
433 b.cursor = nir_after_cf_list(&store_64bit_if->then_list);
434
435 nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
436 store->src[0] = nir_src_for_ssa(result);
437 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
438 store->src[2] = nir_src_for_ssa(nir_load_var(&b, output_offset));
439 nir_intrinsic_set_write_mask(store, 0x1);
440 store->num_components = 1;
441 nir_builder_instr_insert(&b, &store->instr);
442
443 b.cursor = nir_after_cf_list(&store_64bit_if->else_list);
444
445 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
446 store->src[0] = nir_src_for_ssa(nir_u2u32(&b, result));
447 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
448 store->src[2] = nir_src_for_ssa(nir_load_var(&b, output_offset));
449 nir_intrinsic_set_write_mask(store, 0x1);
450 store->num_components = 1;
451 nir_builder_instr_insert(&b, &store->instr);
452
453 b.cursor = nir_after_cf_node(&store_64bit_if->cf_node);
454
455 nir_store_var(&b, output_offset,
456 nir_iadd(&b, nir_load_var(&b, output_offset),
457 elem_size), 0x1);
458
459 b.cursor = nir_after_cf_node(&store_if->cf_node);
460 }
461
462 b.cursor = nir_after_cf_list(&available_if->else_list);
463
464 available_if = nir_if_create(b.shader);
465 available_if->condition = nir_src_for_ssa(nir_iand(&b, flags,
466 nir_imm_int(&b, VK_QUERY_RESULT_PARTIAL_BIT)));
467 nir_cf_node_insert(b.cursor, &available_if->cf_node);
468
469 b.cursor = nir_after_cf_list(&available_if->then_list);
470
471 /* Stores zeros in all outputs. */
472
473 nir_variable *counter = nir_local_variable_create(b.impl, glsl_int_type(), "counter");
474 nir_store_var(&b, counter, nir_imm_int(&b, 0), 0x1);
475
476 nir_loop *loop = nir_loop_create(b.shader);
477 nir_builder_cf_insert(&b, &loop->cf_node);
478 b.cursor = nir_after_cf_list(&loop->body);
479
480 nir_ssa_def *current_counter = nir_load_var(&b, counter);
481 radv_break_on_count(&b, counter, elem_count);
482
483 nir_ssa_def *output_elem = nir_iadd(&b, output_base,
484 nir_imul(&b, elem_size, current_counter));
485
486 nir_if *store_64bit_if = nir_if_create(b.shader);
487 store_64bit_if->condition = nir_src_for_ssa(result_is_64bit);
488 nir_cf_node_insert(b.cursor, &store_64bit_if->cf_node);
489
490 b.cursor = nir_after_cf_list(&store_64bit_if->then_list);
491
492 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
493 store->src[0] = nir_src_for_ssa(nir_imm_int64(&b, 0));
494 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
495 store->src[2] = nir_src_for_ssa(output_elem);
496 nir_intrinsic_set_write_mask(store, 0x1);
497 store->num_components = 1;
498 nir_builder_instr_insert(&b, &store->instr);
499
500 b.cursor = nir_after_cf_list(&store_64bit_if->else_list);
501
502 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
503 store->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
504 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
505 store->src[2] = nir_src_for_ssa(output_elem);
506 nir_intrinsic_set_write_mask(store, 0x1);
507 store->num_components = 1;
508 nir_builder_instr_insert(&b, &store->instr);
509
510 b.cursor = nir_after_cf_node(&loop->cf_node);
511 return b.shader;
512 }
513
514 static VkResult radv_device_init_meta_query_state_internal(struct radv_device *device)
515 {
516 VkResult result;
517 struct radv_shader_module occlusion_cs = { .nir = NULL };
518 struct radv_shader_module pipeline_statistics_cs = { .nir = NULL };
519
520 mtx_lock(&device->meta_state.mtx);
521 if (device->meta_state.query.pipeline_statistics_query_pipeline) {
522 mtx_unlock(&device->meta_state.mtx);
523 return VK_SUCCESS;
524 }
525 occlusion_cs.nir = build_occlusion_query_shader(device);
526 pipeline_statistics_cs.nir = build_pipeline_statistics_query_shader(device);
527
528 VkDescriptorSetLayoutCreateInfo occlusion_ds_create_info = {
529 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
530 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
531 .bindingCount = 2,
532 .pBindings = (VkDescriptorSetLayoutBinding[]) {
533 {
534 .binding = 0,
535 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
536 .descriptorCount = 1,
537 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
538 .pImmutableSamplers = NULL
539 },
540 {
541 .binding = 1,
542 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
543 .descriptorCount = 1,
544 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
545 .pImmutableSamplers = NULL
546 },
547 }
548 };
549
550 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
551 &occlusion_ds_create_info,
552 &device->meta_state.alloc,
553 &device->meta_state.query.ds_layout);
554 if (result != VK_SUCCESS)
555 goto fail;
556
557 VkPipelineLayoutCreateInfo occlusion_pl_create_info = {
558 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
559 .setLayoutCount = 1,
560 .pSetLayouts = &device->meta_state.query.ds_layout,
561 .pushConstantRangeCount = 1,
562 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
563 };
564
565 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
566 &occlusion_pl_create_info,
567 &device->meta_state.alloc,
568 &device->meta_state.query.p_layout);
569 if (result != VK_SUCCESS)
570 goto fail;
571
572 VkPipelineShaderStageCreateInfo occlusion_pipeline_shader_stage = {
573 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
574 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
575 .module = radv_shader_module_to_handle(&occlusion_cs),
576 .pName = "main",
577 .pSpecializationInfo = NULL,
578 };
579
580 VkComputePipelineCreateInfo occlusion_vk_pipeline_info = {
581 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
582 .stage = occlusion_pipeline_shader_stage,
583 .flags = 0,
584 .layout = device->meta_state.query.p_layout,
585 };
586
587 result = radv_CreateComputePipelines(radv_device_to_handle(device),
588 radv_pipeline_cache_to_handle(&device->meta_state.cache),
589 1, &occlusion_vk_pipeline_info, NULL,
590 &device->meta_state.query.occlusion_query_pipeline);
591 if (result != VK_SUCCESS)
592 goto fail;
593
594 VkPipelineShaderStageCreateInfo pipeline_statistics_pipeline_shader_stage = {
595 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
596 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
597 .module = radv_shader_module_to_handle(&pipeline_statistics_cs),
598 .pName = "main",
599 .pSpecializationInfo = NULL,
600 };
601
602 VkComputePipelineCreateInfo pipeline_statistics_vk_pipeline_info = {
603 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
604 .stage = pipeline_statistics_pipeline_shader_stage,
605 .flags = 0,
606 .layout = device->meta_state.query.p_layout,
607 };
608
609 result = radv_CreateComputePipelines(radv_device_to_handle(device),
610 radv_pipeline_cache_to_handle(&device->meta_state.cache),
611 1, &pipeline_statistics_vk_pipeline_info, NULL,
612 &device->meta_state.query.pipeline_statistics_query_pipeline);
613
614 fail:
615 if (result != VK_SUCCESS)
616 radv_device_finish_meta_query_state(device);
617 ralloc_free(occlusion_cs.nir);
618 ralloc_free(pipeline_statistics_cs.nir);
619 mtx_unlock(&device->meta_state.mtx);
620 return result;
621 }
622
623 VkResult radv_device_init_meta_query_state(struct radv_device *device, bool on_demand)
624 {
625 if (on_demand)
626 return VK_SUCCESS;
627
628 return radv_device_init_meta_query_state_internal(device);
629 }
630
631 void radv_device_finish_meta_query_state(struct radv_device *device)
632 {
633 if (device->meta_state.query.pipeline_statistics_query_pipeline)
634 radv_DestroyPipeline(radv_device_to_handle(device),
635 device->meta_state.query.pipeline_statistics_query_pipeline,
636 &device->meta_state.alloc);
637
638 if (device->meta_state.query.occlusion_query_pipeline)
639 radv_DestroyPipeline(radv_device_to_handle(device),
640 device->meta_state.query.occlusion_query_pipeline,
641 &device->meta_state.alloc);
642
643 if (device->meta_state.query.p_layout)
644 radv_DestroyPipelineLayout(radv_device_to_handle(device),
645 device->meta_state.query.p_layout,
646 &device->meta_state.alloc);
647
648 if (device->meta_state.query.ds_layout)
649 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
650 device->meta_state.query.ds_layout,
651 &device->meta_state.alloc);
652 }
653
654 static void radv_query_shader(struct radv_cmd_buffer *cmd_buffer,
655 VkPipeline *pipeline,
656 struct radeon_winsys_bo *src_bo,
657 struct radeon_winsys_bo *dst_bo,
658 uint64_t src_offset, uint64_t dst_offset,
659 uint32_t src_stride, uint32_t dst_stride,
660 uint32_t count, uint32_t flags,
661 uint32_t pipeline_stats_mask, uint32_t avail_offset)
662 {
663 struct radv_device *device = cmd_buffer->device;
664 struct radv_meta_saved_state saved_state;
665
666 if (!*pipeline) {
667 VkResult ret = radv_device_init_meta_query_state_internal(device);
668 if (ret != VK_SUCCESS) {
669 cmd_buffer->record_result = ret;
670 return;
671 }
672 }
673
674 radv_meta_save(&saved_state, cmd_buffer,
675 RADV_META_SAVE_COMPUTE_PIPELINE |
676 RADV_META_SAVE_CONSTANTS |
677 RADV_META_SAVE_DESCRIPTORS);
678
679 struct radv_buffer dst_buffer = {
680 .bo = dst_bo,
681 .offset = dst_offset,
682 .size = dst_stride * count
683 };
684
685 struct radv_buffer src_buffer = {
686 .bo = src_bo,
687 .offset = src_offset,
688 .size = MAX2(src_stride * count, avail_offset + 4 * count - src_offset)
689 };
690
691 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
692 VK_PIPELINE_BIND_POINT_COMPUTE, *pipeline);
693
694 radv_meta_push_descriptor_set(cmd_buffer,
695 VK_PIPELINE_BIND_POINT_COMPUTE,
696 device->meta_state.query.p_layout,
697 0, /* set */
698 2, /* descriptorWriteCount */
699 (VkWriteDescriptorSet[]) {
700 {
701 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
702 .dstBinding = 0,
703 .dstArrayElement = 0,
704 .descriptorCount = 1,
705 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
706 .pBufferInfo = &(VkDescriptorBufferInfo) {
707 .buffer = radv_buffer_to_handle(&dst_buffer),
708 .offset = 0,
709 .range = VK_WHOLE_SIZE
710 }
711 },
712 {
713 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
714 .dstBinding = 1,
715 .dstArrayElement = 0,
716 .descriptorCount = 1,
717 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
718 .pBufferInfo = &(VkDescriptorBufferInfo) {
719 .buffer = radv_buffer_to_handle(&src_buffer),
720 .offset = 0,
721 .range = VK_WHOLE_SIZE
722 }
723 }
724 });
725
726 /* Encode the number of elements for easy access by the shader. */
727 pipeline_stats_mask &= 0x7ff;
728 pipeline_stats_mask |= util_bitcount(pipeline_stats_mask) << 16;
729
730 avail_offset -= src_offset;
731
732 struct {
733 uint32_t flags;
734 uint32_t dst_stride;
735 uint32_t pipeline_stats_mask;
736 uint32_t avail_offset;
737 } push_constants = {
738 flags,
739 dst_stride,
740 pipeline_stats_mask,
741 avail_offset
742 };
743
744 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
745 device->meta_state.query.p_layout,
746 VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(push_constants),
747 &push_constants);
748
749 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2 |
750 RADV_CMD_FLAG_INV_VMEM_L1;
751
752 if (flags & VK_QUERY_RESULT_WAIT_BIT)
753 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER;
754
755 radv_unaligned_dispatch(cmd_buffer, count, 1, 1);
756
757 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2 |
758 RADV_CMD_FLAG_INV_VMEM_L1 |
759 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
760
761 radv_meta_restore(&saved_state, cmd_buffer);
762 }
763
764 VkResult radv_CreateQueryPool(
765 VkDevice _device,
766 const VkQueryPoolCreateInfo* pCreateInfo,
767 const VkAllocationCallbacks* pAllocator,
768 VkQueryPool* pQueryPool)
769 {
770 RADV_FROM_HANDLE(radv_device, device, _device);
771 struct radv_query_pool *pool = vk_alloc2(&device->alloc, pAllocator,
772 sizeof(*pool), 8,
773 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
774
775 if (!pool)
776 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
777
778
779 switch(pCreateInfo->queryType) {
780 case VK_QUERY_TYPE_OCCLUSION:
781 pool->stride = 16 * get_max_db(device);
782 break;
783 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
784 pool->stride = pipelinestat_block_size * 2;
785 break;
786 case VK_QUERY_TYPE_TIMESTAMP:
787 pool->stride = 8;
788 break;
789 default:
790 unreachable("creating unhandled query type");
791 }
792
793 pool->type = pCreateInfo->queryType;
794 pool->pipeline_stats_mask = pCreateInfo->pipelineStatistics;
795 pool->availability_offset = pool->stride * pCreateInfo->queryCount;
796 pool->size = pool->availability_offset;
797 if (pCreateInfo->queryType == VK_QUERY_TYPE_TIMESTAMP ||
798 pCreateInfo->queryType == VK_QUERY_TYPE_PIPELINE_STATISTICS)
799 pool->size += 4 * pCreateInfo->queryCount;
800
801 pool->bo = device->ws->buffer_create(device->ws, pool->size,
802 64, RADEON_DOMAIN_GTT, RADEON_FLAG_NO_INTERPROCESS_SHARING);
803
804 if (!pool->bo) {
805 vk_free2(&device->alloc, pAllocator, pool);
806 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
807 }
808
809 pool->ptr = device->ws->buffer_map(pool->bo);
810
811 if (!pool->ptr) {
812 device->ws->buffer_destroy(pool->bo);
813 vk_free2(&device->alloc, pAllocator, pool);
814 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
815 }
816 memset(pool->ptr, 0, pool->size);
817
818 *pQueryPool = radv_query_pool_to_handle(pool);
819 return VK_SUCCESS;
820 }
821
822 void radv_DestroyQueryPool(
823 VkDevice _device,
824 VkQueryPool _pool,
825 const VkAllocationCallbacks* pAllocator)
826 {
827 RADV_FROM_HANDLE(radv_device, device, _device);
828 RADV_FROM_HANDLE(radv_query_pool, pool, _pool);
829
830 if (!pool)
831 return;
832
833 device->ws->buffer_destroy(pool->bo);
834 vk_free2(&device->alloc, pAllocator, pool);
835 }
836
837 VkResult radv_GetQueryPoolResults(
838 VkDevice _device,
839 VkQueryPool queryPool,
840 uint32_t firstQuery,
841 uint32_t queryCount,
842 size_t dataSize,
843 void* pData,
844 VkDeviceSize stride,
845 VkQueryResultFlags flags)
846 {
847 RADV_FROM_HANDLE(radv_device, device, _device);
848 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
849 char *data = pData;
850 VkResult result = VK_SUCCESS;
851
852 for(unsigned i = 0; i < queryCount; ++i, data += stride) {
853 char *dest = data;
854 unsigned query = firstQuery + i;
855 char *src = pool->ptr + query * pool->stride;
856 uint32_t available;
857
858 if (pool->type != VK_QUERY_TYPE_OCCLUSION) {
859 if (flags & VK_QUERY_RESULT_WAIT_BIT)
860 while(!*(volatile uint32_t*)(pool->ptr + pool->availability_offset + 4 * query))
861 ;
862 available = *(uint32_t*)(pool->ptr + pool->availability_offset + 4 * query);
863 }
864
865 switch (pool->type) {
866 case VK_QUERY_TYPE_TIMESTAMP: {
867 if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT)) {
868 result = VK_NOT_READY;
869 break;
870
871 }
872
873 if (flags & VK_QUERY_RESULT_64_BIT) {
874 *(uint64_t*)dest = *(uint64_t*)src;
875 dest += 8;
876 } else {
877 *(uint32_t*)dest = *(uint32_t*)src;
878 dest += 4;
879 }
880 break;
881 }
882 case VK_QUERY_TYPE_OCCLUSION: {
883 volatile uint64_t const *src64 = (volatile uint64_t const *)src;
884 uint64_t sample_count = 0;
885 int db_count = get_max_db(device);
886 available = 1;
887
888 for (int i = 0; i < db_count; ++i) {
889 uint64_t start, end;
890 do {
891 start = src64[2 * i];
892 end = src64[2 * i + 1];
893 } while ((!(start & (1ull << 63)) || !(end & (1ull << 63))) && (flags & VK_QUERY_RESULT_WAIT_BIT));
894
895 if (!(start & (1ull << 63)) || !(end & (1ull << 63)))
896 available = 0;
897 else {
898 sample_count += end - start;
899 }
900 }
901
902 if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT)) {
903 result = VK_NOT_READY;
904 break;
905
906 }
907
908 if (flags & VK_QUERY_RESULT_64_BIT) {
909 *(uint64_t*)dest = sample_count;
910 dest += 8;
911 } else {
912 *(uint32_t*)dest = sample_count;
913 dest += 4;
914 }
915 break;
916 }
917 case VK_QUERY_TYPE_PIPELINE_STATISTICS: {
918 if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT)) {
919 result = VK_NOT_READY;
920 break;
921
922 }
923
924 const uint64_t *start = (uint64_t*)src;
925 const uint64_t *stop = (uint64_t*)(src + pipelinestat_block_size);
926 if (flags & VK_QUERY_RESULT_64_BIT) {
927 uint64_t *dst = (uint64_t*)dest;
928 dest += util_bitcount(pool->pipeline_stats_mask) * 8;
929 for(int i = 0; i < 11; ++i)
930 if(pool->pipeline_stats_mask & (1u << i))
931 *dst++ = stop[pipeline_statistics_indices[i]] -
932 start[pipeline_statistics_indices[i]];
933
934 } else {
935 uint32_t *dst = (uint32_t*)dest;
936 dest += util_bitcount(pool->pipeline_stats_mask) * 4;
937 for(int i = 0; i < 11; ++i)
938 if(pool->pipeline_stats_mask & (1u << i))
939 *dst++ = stop[pipeline_statistics_indices[i]] -
940 start[pipeline_statistics_indices[i]];
941 }
942 break;
943 }
944 default:
945 unreachable("trying to get results of unhandled query type");
946 }
947
948 if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
949 if (flags & VK_QUERY_RESULT_64_BIT) {
950 *(uint64_t*)dest = available;
951 } else {
952 *(uint32_t*)dest = available;
953 }
954 }
955 }
956
957 return result;
958 }
959
960 void radv_CmdCopyQueryPoolResults(
961 VkCommandBuffer commandBuffer,
962 VkQueryPool queryPool,
963 uint32_t firstQuery,
964 uint32_t queryCount,
965 VkBuffer dstBuffer,
966 VkDeviceSize dstOffset,
967 VkDeviceSize stride,
968 VkQueryResultFlags flags)
969 {
970 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
971 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
972 RADV_FROM_HANDLE(radv_buffer, dst_buffer, dstBuffer);
973 struct radeon_cmdbuf *cs = cmd_buffer->cs;
974 unsigned elem_size = (flags & VK_QUERY_RESULT_64_BIT) ? 8 : 4;
975 uint64_t va = radv_buffer_get_va(pool->bo);
976 uint64_t dest_va = radv_buffer_get_va(dst_buffer->bo);
977 dest_va += dst_buffer->offset + dstOffset;
978
979 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, pool->bo);
980 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_buffer->bo);
981
982 switch (pool->type) {
983 case VK_QUERY_TYPE_OCCLUSION:
984 if (flags & VK_QUERY_RESULT_WAIT_BIT) {
985 for(unsigned i = 0; i < queryCount; ++i, dest_va += stride) {
986 unsigned query = firstQuery + i;
987 uint64_t src_va = va + query * pool->stride + pool->stride - 4;
988
989 /* Waits on the upper word of the last DB entry */
990 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
991 radeon_emit(cs, 5 | WAIT_REG_MEM_MEM_SPACE(1));
992 radeon_emit(cs, src_va);
993 radeon_emit(cs, src_va >> 32);
994 radeon_emit(cs, 0x80000000); /* reference value */
995 radeon_emit(cs, 0xffffffff); /* mask */
996 radeon_emit(cs, 4); /* poll interval */
997 }
998 }
999 radv_query_shader(cmd_buffer, &cmd_buffer->device->meta_state.query.occlusion_query_pipeline,
1000 pool->bo, dst_buffer->bo, firstQuery * pool->stride,
1001 dst_buffer->offset + dstOffset,
1002 get_max_db(cmd_buffer->device) * 16, stride,
1003 queryCount, flags, 0, 0);
1004 break;
1005 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
1006 if (flags & VK_QUERY_RESULT_WAIT_BIT) {
1007 for(unsigned i = 0; i < queryCount; ++i, dest_va += stride) {
1008 unsigned query = firstQuery + i;
1009
1010 radeon_check_space(cmd_buffer->device->ws, cs, 7);
1011
1012 uint64_t avail_va = va + pool->availability_offset + 4 * query;
1013
1014 /* This waits on the ME. All copies below are done on the ME */
1015 si_emit_wait_fence(cs, avail_va, 1, 0xffffffff);
1016 }
1017 }
1018 radv_query_shader(cmd_buffer, &cmd_buffer->device->meta_state.query.pipeline_statistics_query_pipeline,
1019 pool->bo, dst_buffer->bo, firstQuery * pool->stride,
1020 dst_buffer->offset + dstOffset,
1021 pipelinestat_block_size * 2, stride, queryCount, flags,
1022 pool->pipeline_stats_mask,
1023 pool->availability_offset + 4 * firstQuery);
1024 break;
1025 case VK_QUERY_TYPE_TIMESTAMP:
1026 for(unsigned i = 0; i < queryCount; ++i, dest_va += stride) {
1027 unsigned query = firstQuery + i;
1028 uint64_t local_src_va = va + query * pool->stride;
1029
1030 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 19);
1031
1032
1033 if (flags & VK_QUERY_RESULT_WAIT_BIT) {
1034 /* TODO, not sure if there is any case where we won't always be ready yet */
1035 uint64_t avail_va = va + pool->availability_offset + 4 * query;
1036
1037 /* This waits on the ME. All copies below are done on the ME */
1038 si_emit_wait_fence(cs, avail_va, 1, 0xffffffff);
1039 }
1040 if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
1041 uint64_t avail_va = va + pool->availability_offset + 4 * query;
1042 uint64_t avail_dest_va = dest_va + elem_size;
1043
1044 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1045 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1046 COPY_DATA_DST_SEL(COPY_DATA_MEM));
1047 radeon_emit(cs, avail_va);
1048 radeon_emit(cs, avail_va >> 32);
1049 radeon_emit(cs, avail_dest_va);
1050 radeon_emit(cs, avail_dest_va >> 32);
1051 }
1052
1053 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1054 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1055 COPY_DATA_DST_SEL(COPY_DATA_MEM) |
1056 ((flags & VK_QUERY_RESULT_64_BIT) ? COPY_DATA_COUNT_SEL : 0));
1057 radeon_emit(cs, local_src_va);
1058 radeon_emit(cs, local_src_va >> 32);
1059 radeon_emit(cs, dest_va);
1060 radeon_emit(cs, dest_va >> 32);
1061
1062
1063 assert(cs->cdw <= cdw_max);
1064 }
1065 break;
1066 default:
1067 unreachable("trying to get results of unhandled query type");
1068 }
1069
1070 }
1071
1072 void radv_CmdResetQueryPool(
1073 VkCommandBuffer commandBuffer,
1074 VkQueryPool queryPool,
1075 uint32_t firstQuery,
1076 uint32_t queryCount)
1077 {
1078 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1079 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
1080 uint32_t flush_bits = 0;
1081
1082 flush_bits |= radv_fill_buffer(cmd_buffer, pool->bo,
1083 firstQuery * pool->stride,
1084 queryCount * pool->stride, 0);
1085
1086 if (pool->type == VK_QUERY_TYPE_TIMESTAMP ||
1087 pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS) {
1088 flush_bits |= radv_fill_buffer(cmd_buffer, pool->bo,
1089 pool->availability_offset + firstQuery * 4,
1090 queryCount * 4, 0);
1091 }
1092
1093 if (flush_bits) {
1094 /* Only need to flush caches for the compute shader path. */
1095 cmd_buffer->pending_reset_query = true;
1096 cmd_buffer->state.flush_bits |= flush_bits;
1097 }
1098 }
1099
1100 static void emit_begin_query(struct radv_cmd_buffer *cmd_buffer,
1101 uint64_t va,
1102 VkQueryType query_type,
1103 VkQueryControlFlags flags)
1104 {
1105 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1106 switch (query_type) {
1107 case VK_QUERY_TYPE_OCCLUSION:
1108 radeon_check_space(cmd_buffer->device->ws, cs, 7);
1109
1110 ++cmd_buffer->state.active_occlusion_queries;
1111 if (cmd_buffer->state.active_occlusion_queries == 1) {
1112 if (flags & VK_QUERY_CONTROL_PRECISE_BIT) {
1113 /* This is the first occlusion query, enable
1114 * the hint if the precision bit is set.
1115 */
1116 cmd_buffer->state.perfect_occlusion_queries_enabled = true;
1117 }
1118
1119 radv_set_db_count_control(cmd_buffer);
1120 } else {
1121 if ((flags & VK_QUERY_CONTROL_PRECISE_BIT) &&
1122 !cmd_buffer->state.perfect_occlusion_queries_enabled) {
1123 /* This is not the first query, but this one
1124 * needs to enable precision, DB_COUNT_CONTROL
1125 * has to be updated accordingly.
1126 */
1127 cmd_buffer->state.perfect_occlusion_queries_enabled = true;
1128
1129 radv_set_db_count_control(cmd_buffer);
1130 }
1131 }
1132
1133 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1134 radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
1135 radeon_emit(cs, va);
1136 radeon_emit(cs, va >> 32);
1137 break;
1138 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
1139 radeon_check_space(cmd_buffer->device->ws, cs, 4);
1140
1141 ++cmd_buffer->state.active_pipeline_queries;
1142 if (cmd_buffer->state.active_pipeline_queries == 1) {
1143 cmd_buffer->state.flush_bits &= ~RADV_CMD_FLAG_STOP_PIPELINE_STATS;
1144 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_START_PIPELINE_STATS;
1145 }
1146
1147 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1148 radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
1149 radeon_emit(cs, va);
1150 radeon_emit(cs, va >> 32);
1151 break;
1152 default:
1153 unreachable("beginning unhandled query type");
1154 }
1155
1156 }
1157
1158 static void emit_end_query(struct radv_cmd_buffer *cmd_buffer,
1159 uint64_t va, uint64_t avail_va,
1160 VkQueryType query_type)
1161 {
1162 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1163 switch (query_type) {
1164 case VK_QUERY_TYPE_OCCLUSION:
1165 radeon_check_space(cmd_buffer->device->ws, cs, 14);
1166
1167 cmd_buffer->state.active_occlusion_queries--;
1168 if (cmd_buffer->state.active_occlusion_queries == 0) {
1169 radv_set_db_count_control(cmd_buffer);
1170
1171 /* Reset the perfect occlusion queries hint now that no
1172 * queries are active.
1173 */
1174 cmd_buffer->state.perfect_occlusion_queries_enabled = false;
1175 }
1176
1177 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1178 radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
1179 radeon_emit(cs, va + 8);
1180 radeon_emit(cs, (va + 8) >> 32);
1181
1182 break;
1183 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
1184 radeon_check_space(cmd_buffer->device->ws, cs, 16);
1185
1186 cmd_buffer->state.active_pipeline_queries--;
1187 if (cmd_buffer->state.active_pipeline_queries == 0) {
1188 cmd_buffer->state.flush_bits &= ~RADV_CMD_FLAG_START_PIPELINE_STATS;
1189 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_STOP_PIPELINE_STATS;
1190 }
1191 va += pipelinestat_block_size;
1192
1193 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1194 radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
1195 radeon_emit(cs, va);
1196 radeon_emit(cs, va >> 32);
1197
1198 si_cs_emit_write_event_eop(cs,
1199 cmd_buffer->device->physical_device->rad_info.chip_class,
1200 radv_cmd_buffer_uses_mec(cmd_buffer),
1201 V_028A90_BOTTOM_OF_PIPE_TS, 0,
1202 EOP_DATA_SEL_VALUE_32BIT,
1203 avail_va, 0, 1,
1204 cmd_buffer->gfx9_eop_bug_va);
1205 break;
1206 default:
1207 unreachable("ending unhandled query type");
1208 }
1209 }
1210
1211 void radv_CmdBeginQuery(
1212 VkCommandBuffer commandBuffer,
1213 VkQueryPool queryPool,
1214 uint32_t query,
1215 VkQueryControlFlags flags)
1216 {
1217 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1218 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
1219 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1220 uint64_t va = radv_buffer_get_va(pool->bo);
1221
1222 radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo);
1223
1224 if (cmd_buffer->pending_reset_query) {
1225 if (pool->size >= RADV_BUFFER_OPS_CS_THRESHOLD) {
1226 /* Only need to flush caches if the query pool size is
1227 * large enough to be resetted using the compute shader
1228 * path. Small pools don't need any cache flushes
1229 * because we use a CP dma clear.
1230 */
1231 si_emit_cache_flush(cmd_buffer);
1232 cmd_buffer->pending_reset_query = false;
1233 }
1234 }
1235
1236 va += pool->stride * query;
1237
1238 emit_begin_query(cmd_buffer, va, pool->type, flags);
1239 }
1240
1241
1242 void radv_CmdEndQuery(
1243 VkCommandBuffer commandBuffer,
1244 VkQueryPool queryPool,
1245 uint32_t query)
1246 {
1247 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1248 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
1249 uint64_t va = radv_buffer_get_va(pool->bo);
1250 uint64_t avail_va = va + pool->availability_offset + 4 * query;
1251 va += pool->stride * query;
1252
1253 /* Do not need to add the pool BO to the list because the query must
1254 * currently be active, which means the BO is already in the list.
1255 */
1256 emit_end_query(cmd_buffer, va, avail_va, pool->type);
1257
1258 /*
1259 * For multiview we have to emit a query for each bit in the mask,
1260 * however the first query we emit will get the totals for all the
1261 * operations, so we don't want to get a real value in the other
1262 * queries. This emits a fake begin/end sequence so the waiting
1263 * code gets a completed query value and doesn't hang, but the
1264 * query returns 0.
1265 */
1266 if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
1267 uint64_t avail_va = va + pool->availability_offset + 4 * query;
1268
1269
1270 for (unsigned i = 1; i < util_bitcount(cmd_buffer->state.subpass->view_mask); i++) {
1271 va += pool->stride;
1272 avail_va += 4;
1273 emit_begin_query(cmd_buffer, va, pool->type, 0);
1274 emit_end_query(cmd_buffer, va, avail_va, pool->type);
1275 }
1276 }
1277 }
1278
1279 void radv_CmdWriteTimestamp(
1280 VkCommandBuffer commandBuffer,
1281 VkPipelineStageFlagBits pipelineStage,
1282 VkQueryPool queryPool,
1283 uint32_t query)
1284 {
1285 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1286 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
1287 bool mec = radv_cmd_buffer_uses_mec(cmd_buffer);
1288 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1289 uint64_t va = radv_buffer_get_va(pool->bo);
1290 uint64_t avail_va = va + pool->availability_offset + 4 * query;
1291 uint64_t query_va = va + pool->stride * query;
1292
1293 radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo);
1294
1295 int num_queries = 1;
1296 if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask)
1297 num_queries = util_bitcount(cmd_buffer->state.subpass->view_mask);
1298
1299 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 28 * num_queries);
1300
1301 for (unsigned i = 0; i < num_queries; i++) {
1302 switch(pipelineStage) {
1303 case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:
1304 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1305 radeon_emit(cs, COPY_DATA_COUNT_SEL | COPY_DATA_WR_CONFIRM |
1306 COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
1307 COPY_DATA_DST_SEL(V_370_MEM_ASYNC));
1308 radeon_emit(cs, 0);
1309 radeon_emit(cs, 0);
1310 radeon_emit(cs, query_va);
1311 radeon_emit(cs, query_va >> 32);
1312
1313 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1314 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1315 S_370_WR_CONFIRM(1) |
1316 S_370_ENGINE_SEL(V_370_ME));
1317 radeon_emit(cs, avail_va);
1318 radeon_emit(cs, avail_va >> 32);
1319 radeon_emit(cs, 1);
1320 break;
1321 default:
1322 si_cs_emit_write_event_eop(cs,
1323 cmd_buffer->device->physical_device->rad_info.chip_class,
1324 mec,
1325 V_028A90_BOTTOM_OF_PIPE_TS, 0,
1326 EOP_DATA_SEL_TIMESTAMP,
1327 query_va, 0, 0,
1328 cmd_buffer->gfx9_eop_bug_va);
1329 si_cs_emit_write_event_eop(cs,
1330 cmd_buffer->device->physical_device->rad_info.chip_class,
1331 mec,
1332 V_028A90_BOTTOM_OF_PIPE_TS, 0,
1333 EOP_DATA_SEL_VALUE_32BIT,
1334 avail_va, 0, 1,
1335 cmd_buffer->gfx9_eop_bug_va);
1336 break;
1337 }
1338 query_va += pool->stride;
1339 avail_va += 4;
1340 }
1341 assert(cmd_buffer->cs->cdw <= cdw_max);
1342 }