2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * Based on radeon_winsys.h which is:
6 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
7 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #ifndef RADV_RADEON_WINSYS_H
30 #define RADV_RADEON_WINSYS_H
36 #include "main/macros.h"
37 #include "amd_family.h"
43 #define FREE(x) free(x)
45 enum radeon_bo_domain
{ /* bitfield */
46 RADEON_DOMAIN_GTT
= 2,
47 RADEON_DOMAIN_VRAM
= 4,
48 RADEON_DOMAIN_VRAM_GTT
= RADEON_DOMAIN_VRAM
| RADEON_DOMAIN_GTT
,
49 RADEON_DOMAIN_GDS
= 8,
50 RADEON_DOMAIN_OA
= 16,
53 enum radeon_bo_flag
{ /* bitfield */
54 RADEON_FLAG_GTT_WC
= (1 << 0),
55 RADEON_FLAG_CPU_ACCESS
= (1 << 1),
56 RADEON_FLAG_NO_CPU_ACCESS
= (1 << 2),
57 RADEON_FLAG_VIRTUAL
= (1 << 3),
58 RADEON_FLAG_VA_UNCACHED
= (1 << 4),
59 RADEON_FLAG_IMPLICIT_SYNC
= (1 << 5),
60 RADEON_FLAG_NO_INTERPROCESS_SHARING
= (1 << 6),
61 RADEON_FLAG_READ_ONLY
= (1 << 7),
62 RADEON_FLAG_32BIT
= (1 << 8),
63 RADEON_FLAG_PREFER_LOCAL_BO
= (1 << 9),
66 enum radeon_bo_usage
{ /* bitfield */
67 RADEON_USAGE_READ
= 2,
68 RADEON_USAGE_WRITE
= 4,
69 RADEON_USAGE_READWRITE
= RADEON_USAGE_READ
| RADEON_USAGE_WRITE
72 enum radeon_ctx_priority
{
73 RADEON_CTX_PRIORITY_INVALID
= -1,
74 RADEON_CTX_PRIORITY_LOW
= 0,
75 RADEON_CTX_PRIORITY_MEDIUM
,
76 RADEON_CTX_PRIORITY_HIGH
,
77 RADEON_CTX_PRIORITY_REALTIME
,
80 enum radeon_value_id
{
81 RADEON_ALLOCATED_VRAM
,
82 RADEON_ALLOCATED_VRAM_VIS
,
85 RADEON_NUM_BYTES_MOVED
,
87 RADEON_NUM_VRAM_CPU_PAGE_FAULTS
,
89 RADEON_VRAM_VIS_USAGE
,
91 RADEON_GPU_TEMPERATURE
,
96 struct radeon_cmdbuf
{
97 unsigned cdw
; /* Number of used dwords. */
98 unsigned max_dw
; /* Maximum number of dwords. */
99 uint32_t *buf
; /* The base pointer of the chunk. */
102 #define RADEON_SURF_TYPE_MASK 0xFF
103 #define RADEON_SURF_TYPE_SHIFT 0
104 #define RADEON_SURF_TYPE_1D 0
105 #define RADEON_SURF_TYPE_2D 1
106 #define RADEON_SURF_TYPE_3D 2
107 #define RADEON_SURF_TYPE_CUBEMAP 3
108 #define RADEON_SURF_TYPE_1D_ARRAY 4
109 #define RADEON_SURF_TYPE_2D_ARRAY 5
110 #define RADEON_SURF_MODE_MASK 0xFF
111 #define RADEON_SURF_MODE_SHIFT 8
113 #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
114 #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
115 #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
117 enum radeon_bo_layout
{
118 RADEON_LAYOUT_LINEAR
= 0,
120 RADEON_LAYOUT_SQUARETILED
,
122 RADEON_LAYOUT_UNKNOWN
125 /* Tiling info for display code, DRI sharing, and other data. */
126 struct radeon_bo_metadata
{
127 /* Tiling flags describing the texture layout for display code
132 enum radeon_bo_layout microtile
;
133 enum radeon_bo_layout macrotile
;
134 unsigned pipe_config
;
146 unsigned swizzle_mode
:5;
150 /* Additional metadata associated with the buffer, in bytes.
151 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
152 * Supported by amdgpu only.
154 uint32_t size_metadata
;
155 uint32_t metadata
[64];
158 uint32_t syncobj_handle
;
159 struct radeon_winsys_fence
;
161 struct radeon_winsys_bo
{
164 bool vram_cpu_access
;
166 struct radv_winsys_sem_counts
{
167 uint32_t syncobj_count
;
170 struct radeon_winsys_sem
**sem
;
173 struct radv_winsys_sem_info
{
176 struct radv_winsys_sem_counts wait
;
177 struct radv_winsys_sem_counts signal
;
180 struct radv_winsys_bo_list
{
181 struct radeon_winsys_bo
**bos
;
185 /* Kernel effectively allows 0-31. This sets some priorities for fixed
186 * functionality buffers */
188 RADV_BO_PRIORITY_APPLICATION_MAX
= 28,
190 /* virtual buffers have 0 priority since the priority is not used. */
191 RADV_BO_PRIORITY_VIRTUAL
= 0,
193 /* This should be considerably lower than most of the stuff below,
194 * but how much lower is hard to say since we don't know application
195 * assignments. Put it pretty high since it is GTT anyway. */
196 RADV_BO_PRIORITY_QUERY_POOL
= 29,
198 RADV_BO_PRIORITY_DESCRIPTOR
= 30,
199 RADV_BO_PRIORITY_UPLOAD_BUFFER
= 30,
200 RADV_BO_PRIORITY_FENCE
= 30,
201 RADV_BO_PRIORITY_SHADER
= 31,
202 RADV_BO_PRIORITY_SCRATCH
= 31,
203 RADV_BO_PRIORITY_CS
= 31,
206 struct radeon_winsys
{
207 void (*destroy
)(struct radeon_winsys
*ws
);
209 void (*query_info
)(struct radeon_winsys
*ws
,
210 struct radeon_info
*info
);
212 uint64_t (*query_value
)(struct radeon_winsys
*ws
,
213 enum radeon_value_id value
);
215 bool (*read_registers
)(struct radeon_winsys
*ws
, unsigned reg_offset
,
216 unsigned num_registers
, uint32_t *out
);
218 const char *(*get_chip_name
)(struct radeon_winsys
*ws
);
220 struct radeon_winsys_bo
*(*buffer_create
)(struct radeon_winsys
*ws
,
223 enum radeon_bo_domain domain
,
224 enum radeon_bo_flag flags
,
227 void (*buffer_destroy
)(struct radeon_winsys_bo
*bo
);
228 void *(*buffer_map
)(struct radeon_winsys_bo
*bo
);
230 struct radeon_winsys_bo
*(*buffer_from_ptr
)(struct radeon_winsys
*ws
,
235 struct radeon_winsys_bo
*(*buffer_from_fd
)(struct radeon_winsys
*ws
,
238 uint64_t *alloc_size
);
240 bool (*buffer_get_fd
)(struct radeon_winsys
*ws
,
241 struct radeon_winsys_bo
*bo
,
244 void (*buffer_unmap
)(struct radeon_winsys_bo
*bo
);
246 void (*buffer_set_metadata
)(struct radeon_winsys_bo
*bo
,
247 struct radeon_bo_metadata
*md
);
248 void (*buffer_get_metadata
)(struct radeon_winsys_bo
*bo
,
249 struct radeon_bo_metadata
*md
);
251 void (*buffer_virtual_bind
)(struct radeon_winsys_bo
*parent
,
252 uint64_t offset
, uint64_t size
,
253 struct radeon_winsys_bo
*bo
, uint64_t bo_offset
);
254 struct radeon_winsys_ctx
*(*ctx_create
)(struct radeon_winsys
*ws
,
255 enum radeon_ctx_priority priority
);
256 void (*ctx_destroy
)(struct radeon_winsys_ctx
*ctx
);
258 bool (*ctx_wait_idle
)(struct radeon_winsys_ctx
*ctx
,
259 enum ring_type ring_type
, int ring_index
);
261 struct radeon_cmdbuf
*(*cs_create
)(struct radeon_winsys
*ws
,
262 enum ring_type ring_type
);
264 void (*cs_destroy
)(struct radeon_cmdbuf
*cs
);
266 void (*cs_reset
)(struct radeon_cmdbuf
*cs
);
268 bool (*cs_finalize
)(struct radeon_cmdbuf
*cs
);
270 void (*cs_grow
)(struct radeon_cmdbuf
* cs
, size_t min_size
);
272 int (*cs_submit
)(struct radeon_winsys_ctx
*ctx
,
274 struct radeon_cmdbuf
**cs_array
,
276 struct radeon_cmdbuf
*initial_preamble_cs
,
277 struct radeon_cmdbuf
*continue_preamble_cs
,
278 struct radv_winsys_sem_info
*sem_info
,
279 const struct radv_winsys_bo_list
*bo_list
, /* optional */
281 struct radeon_winsys_fence
*fence
);
283 void (*cs_add_buffer
)(struct radeon_cmdbuf
*cs
,
284 struct radeon_winsys_bo
*bo
);
286 void (*cs_execute_secondary
)(struct radeon_cmdbuf
*parent
,
287 struct radeon_cmdbuf
*child
);
289 void (*cs_dump
)(struct radeon_cmdbuf
*cs
, FILE* file
, const int *trace_ids
, int trace_id_count
);
291 int (*surface_init
)(struct radeon_winsys
*ws
,
292 const struct ac_surf_info
*surf_info
,
293 struct radeon_surf
*surf
);
295 struct radeon_winsys_fence
*(*create_fence
)();
296 void (*destroy_fence
)(struct radeon_winsys_fence
*fence
);
297 void (*reset_fence
)(struct radeon_winsys_fence
*fence
);
298 void (*signal_fence
)(struct radeon_winsys_fence
*fence
);
299 bool (*is_fence_waitable
)(struct radeon_winsys_fence
*fence
);
300 bool (*fence_wait
)(struct radeon_winsys
*ws
,
301 struct radeon_winsys_fence
*fence
,
304 bool (*fences_wait
)(struct radeon_winsys
*ws
,
305 struct radeon_winsys_fence
*const *fences
,
306 uint32_t fence_count
,
310 /* old semaphores - non shareable */
311 struct radeon_winsys_sem
*(*create_sem
)(struct radeon_winsys
*ws
);
312 void (*destroy_sem
)(struct radeon_winsys_sem
*sem
);
314 /* new shareable sync objects */
315 int (*create_syncobj
)(struct radeon_winsys
*ws
, uint32_t *handle
);
316 void (*destroy_syncobj
)(struct radeon_winsys
*ws
, uint32_t handle
);
318 void (*reset_syncobj
)(struct radeon_winsys
*ws
, uint32_t handle
);
319 void (*signal_syncobj
)(struct radeon_winsys
*ws
, uint32_t handle
);
320 bool (*wait_syncobj
)(struct radeon_winsys
*ws
, const uint32_t *handles
, uint32_t handle_count
,
321 bool wait_all
, uint64_t timeout
);
323 int (*export_syncobj
)(struct radeon_winsys
*ws
, uint32_t syncobj
, int *fd
);
324 int (*import_syncobj
)(struct radeon_winsys
*ws
, int fd
, uint32_t *syncobj
);
326 int (*export_syncobj_to_sync_file
)(struct radeon_winsys
*ws
, uint32_t syncobj
, int *fd
);
328 /* Note that this, unlike the normal import, uses an existing syncobj. */
329 int (*import_syncobj_from_sync_file
)(struct radeon_winsys
*ws
, uint32_t syncobj
, int fd
);
333 static inline void radeon_emit(struct radeon_cmdbuf
*cs
, uint32_t value
)
335 cs
->buf
[cs
->cdw
++] = value
;
338 static inline void radeon_emit_array(struct radeon_cmdbuf
*cs
,
339 const uint32_t *values
, unsigned count
)
341 memcpy(cs
->buf
+ cs
->cdw
, values
, count
* 4);
345 static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo
*bo
)
350 static inline void radv_cs_add_buffer(struct radeon_winsys
*ws
,
351 struct radeon_cmdbuf
*cs
,
352 struct radeon_winsys_bo
*bo
)
357 ws
->cs_add_buffer(cs
, bo
);
360 #endif /* RADV_RADEON_WINSYS_H */