2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * Based on radeon_winsys.h which is:
6 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
7 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #ifndef RADV_RADEON_WINSYS_H
30 #define RADV_RADEON_WINSYS_H
36 #include "main/macros.h"
37 #include "amd_family.h"
43 #define FREE(x) free(x)
45 enum radeon_bo_domain
{ /* bitfield */
46 RADEON_DOMAIN_GTT
= 2,
47 RADEON_DOMAIN_VRAM
= 4,
48 RADEON_DOMAIN_VRAM_GTT
= RADEON_DOMAIN_VRAM
| RADEON_DOMAIN_GTT
51 enum radeon_bo_flag
{ /* bitfield */
52 RADEON_FLAG_GTT_WC
= (1 << 0),
53 RADEON_FLAG_CPU_ACCESS
= (1 << 1),
54 RADEON_FLAG_NO_CPU_ACCESS
= (1 << 2),
55 RADEON_FLAG_VIRTUAL
= (1 << 3),
56 RADEON_FLAG_VA_UNCACHED
= (1 << 4),
57 RADEON_FLAG_IMPLICIT_SYNC
= (1 << 5),
58 RADEON_FLAG_NO_INTERPROCESS_SHARING
= (1 << 6),
59 RADEON_FLAG_READ_ONLY
= (1 << 7),
60 RADEON_FLAG_32BIT
= (1 << 8),
61 RADEON_FLAG_PREFER_LOCAL_BO
= (1 << 9),
64 enum radeon_bo_usage
{ /* bitfield */
65 RADEON_USAGE_READ
= 2,
66 RADEON_USAGE_WRITE
= 4,
67 RADEON_USAGE_READWRITE
= RADEON_USAGE_READ
| RADEON_USAGE_WRITE
79 enum radeon_ctx_priority
{
80 RADEON_CTX_PRIORITY_INVALID
= -1,
81 RADEON_CTX_PRIORITY_LOW
= 0,
82 RADEON_CTX_PRIORITY_MEDIUM
,
83 RADEON_CTX_PRIORITY_HIGH
,
84 RADEON_CTX_PRIORITY_REALTIME
,
87 enum radeon_value_id
{
88 RADEON_ALLOCATED_VRAM
,
89 RADEON_ALLOCATED_VRAM_VIS
,
92 RADEON_NUM_BYTES_MOVED
,
94 RADEON_NUM_VRAM_CPU_PAGE_FAULTS
,
96 RADEON_VRAM_VIS_USAGE
,
98 RADEON_GPU_TEMPERATURE
,
103 struct radeon_cmdbuf
{
104 unsigned cdw
; /* Number of used dwords. */
105 unsigned max_dw
; /* Maximum number of dwords. */
106 uint32_t *buf
; /* The base pointer of the chunk. */
109 #define RADEON_SURF_TYPE_MASK 0xFF
110 #define RADEON_SURF_TYPE_SHIFT 0
111 #define RADEON_SURF_TYPE_1D 0
112 #define RADEON_SURF_TYPE_2D 1
113 #define RADEON_SURF_TYPE_3D 2
114 #define RADEON_SURF_TYPE_CUBEMAP 3
115 #define RADEON_SURF_TYPE_1D_ARRAY 4
116 #define RADEON_SURF_TYPE_2D_ARRAY 5
117 #define RADEON_SURF_MODE_MASK 0xFF
118 #define RADEON_SURF_MODE_SHIFT 8
120 #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
121 #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
122 #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
124 enum radeon_bo_layout
{
125 RADEON_LAYOUT_LINEAR
= 0,
127 RADEON_LAYOUT_SQUARETILED
,
129 RADEON_LAYOUT_UNKNOWN
132 /* Tiling info for display code, DRI sharing, and other data. */
133 struct radeon_bo_metadata
{
134 /* Tiling flags describing the texture layout for display code
139 enum radeon_bo_layout microtile
;
140 enum radeon_bo_layout macrotile
;
141 unsigned pipe_config
;
153 unsigned swizzle_mode
:5;
157 /* Additional metadata associated with the buffer, in bytes.
158 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
159 * Supported by amdgpu only.
161 uint32_t size_metadata
;
162 uint32_t metadata
[64];
165 uint32_t syncobj_handle
;
166 struct radeon_winsys_fence
;
168 struct radeon_winsys_bo
{
171 bool vram_cpu_access
;
173 struct radv_winsys_sem_counts
{
174 uint32_t syncobj_count
;
177 struct radeon_winsys_sem
**sem
;
180 struct radv_winsys_sem_info
{
183 struct radv_winsys_sem_counts wait
;
184 struct radv_winsys_sem_counts signal
;
187 struct radv_winsys_bo_list
{
188 struct radeon_winsys_bo
**bos
;
192 /* Kernel effectively allows 0-31. This sets some priorities for fixed
193 * functionality buffers */
195 RADV_BO_PRIORITY_APPLICATION_MAX
= 28,
197 /* virtual buffers have 0 priority since the priority is not used. */
198 RADV_BO_PRIORITY_VIRTUAL
= 0,
200 /* This should be considerably lower than most of the stuff below,
201 * but how much lower is hard to say since we don't know application
202 * assignments. Put it pretty high since it is GTT anyway. */
203 RADV_BO_PRIORITY_QUERY_POOL
= 29,
205 RADV_BO_PRIORITY_DESCRIPTOR
= 30,
206 RADV_BO_PRIORITY_UPLOAD_BUFFER
= 30,
207 RADV_BO_PRIORITY_FENCE
= 30,
208 RADV_BO_PRIORITY_SHADER
= 31,
209 RADV_BO_PRIORITY_SCRATCH
= 31,
210 RADV_BO_PRIORITY_CS
= 31,
213 struct radeon_winsys
{
214 void (*destroy
)(struct radeon_winsys
*ws
);
216 void (*query_info
)(struct radeon_winsys
*ws
,
217 struct radeon_info
*info
);
219 uint64_t (*query_value
)(struct radeon_winsys
*ws
,
220 enum radeon_value_id value
);
222 bool (*read_registers
)(struct radeon_winsys
*ws
, unsigned reg_offset
,
223 unsigned num_registers
, uint32_t *out
);
225 const char *(*get_chip_name
)(struct radeon_winsys
*ws
);
227 struct radeon_winsys_bo
*(*buffer_create
)(struct radeon_winsys
*ws
,
230 enum radeon_bo_domain domain
,
231 enum radeon_bo_flag flags
,
234 void (*buffer_destroy
)(struct radeon_winsys_bo
*bo
);
235 void *(*buffer_map
)(struct radeon_winsys_bo
*bo
);
237 struct radeon_winsys_bo
*(*buffer_from_ptr
)(struct radeon_winsys
*ws
,
242 struct radeon_winsys_bo
*(*buffer_from_fd
)(struct radeon_winsys
*ws
,
245 unsigned *stride
, unsigned *offset
);
247 bool (*buffer_get_fd
)(struct radeon_winsys
*ws
,
248 struct radeon_winsys_bo
*bo
,
251 void (*buffer_unmap
)(struct radeon_winsys_bo
*bo
);
253 void (*buffer_set_metadata
)(struct radeon_winsys_bo
*bo
,
254 struct radeon_bo_metadata
*md
);
255 void (*buffer_get_metadata
)(struct radeon_winsys_bo
*bo
,
256 struct radeon_bo_metadata
*md
);
258 void (*buffer_virtual_bind
)(struct radeon_winsys_bo
*parent
,
259 uint64_t offset
, uint64_t size
,
260 struct radeon_winsys_bo
*bo
, uint64_t bo_offset
);
261 struct radeon_winsys_ctx
*(*ctx_create
)(struct radeon_winsys
*ws
,
262 enum radeon_ctx_priority priority
);
263 void (*ctx_destroy
)(struct radeon_winsys_ctx
*ctx
);
265 bool (*ctx_wait_idle
)(struct radeon_winsys_ctx
*ctx
,
266 enum ring_type ring_type
, int ring_index
);
268 struct radeon_cmdbuf
*(*cs_create
)(struct radeon_winsys
*ws
,
269 enum ring_type ring_type
);
271 void (*cs_destroy
)(struct radeon_cmdbuf
*cs
);
273 void (*cs_reset
)(struct radeon_cmdbuf
*cs
);
275 bool (*cs_finalize
)(struct radeon_cmdbuf
*cs
);
277 void (*cs_grow
)(struct radeon_cmdbuf
* cs
, size_t min_size
);
279 int (*cs_submit
)(struct radeon_winsys_ctx
*ctx
,
281 struct radeon_cmdbuf
**cs_array
,
283 struct radeon_cmdbuf
*initial_preamble_cs
,
284 struct radeon_cmdbuf
*continue_preamble_cs
,
285 struct radv_winsys_sem_info
*sem_info
,
286 const struct radv_winsys_bo_list
*bo_list
, /* optional */
288 struct radeon_winsys_fence
*fence
);
290 void (*cs_add_buffer
)(struct radeon_cmdbuf
*cs
,
291 struct radeon_winsys_bo
*bo
);
293 void (*cs_execute_secondary
)(struct radeon_cmdbuf
*parent
,
294 struct radeon_cmdbuf
*child
);
296 void (*cs_dump
)(struct radeon_cmdbuf
*cs
, FILE* file
, const int *trace_ids
, int trace_id_count
);
298 int (*surface_init
)(struct radeon_winsys
*ws
,
299 const struct ac_surf_info
*surf_info
,
300 struct radeon_surf
*surf
);
302 struct radeon_winsys_fence
*(*create_fence
)();
303 void (*destroy_fence
)(struct radeon_winsys_fence
*fence
);
304 void (*reset_fence
)(struct radeon_winsys_fence
*fence
);
305 void (*signal_fence
)(struct radeon_winsys_fence
*fence
);
306 bool (*is_fence_waitable
)(struct radeon_winsys_fence
*fence
);
307 bool (*fence_wait
)(struct radeon_winsys
*ws
,
308 struct radeon_winsys_fence
*fence
,
311 bool (*fences_wait
)(struct radeon_winsys
*ws
,
312 struct radeon_winsys_fence
*const *fences
,
313 uint32_t fence_count
,
317 /* old semaphores - non shareable */
318 struct radeon_winsys_sem
*(*create_sem
)(struct radeon_winsys
*ws
);
319 void (*destroy_sem
)(struct radeon_winsys_sem
*sem
);
321 /* new shareable sync objects */
322 int (*create_syncobj
)(struct radeon_winsys
*ws
, uint32_t *handle
);
323 void (*destroy_syncobj
)(struct radeon_winsys
*ws
, uint32_t handle
);
325 void (*reset_syncobj
)(struct radeon_winsys
*ws
, uint32_t handle
);
326 void (*signal_syncobj
)(struct radeon_winsys
*ws
, uint32_t handle
);
327 bool (*wait_syncobj
)(struct radeon_winsys
*ws
, const uint32_t *handles
, uint32_t handle_count
,
328 bool wait_all
, uint64_t timeout
);
330 int (*export_syncobj
)(struct radeon_winsys
*ws
, uint32_t syncobj
, int *fd
);
331 int (*import_syncobj
)(struct radeon_winsys
*ws
, int fd
, uint32_t *syncobj
);
333 int (*export_syncobj_to_sync_file
)(struct radeon_winsys
*ws
, uint32_t syncobj
, int *fd
);
335 /* Note that this, unlike the normal import, uses an existing syncobj. */
336 int (*import_syncobj_from_sync_file
)(struct radeon_winsys
*ws
, uint32_t syncobj
, int fd
);
340 static inline void radeon_emit(struct radeon_cmdbuf
*cs
, uint32_t value
)
342 cs
->buf
[cs
->cdw
++] = value
;
345 static inline void radeon_emit_array(struct radeon_cmdbuf
*cs
,
346 const uint32_t *values
, unsigned count
)
348 memcpy(cs
->buf
+ cs
->cdw
, values
, count
* 4);
352 static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo
*bo
)
357 static inline void radv_cs_add_buffer(struct radeon_winsys
*ws
,
358 struct radeon_cmdbuf
*cs
,
359 struct radeon_winsys_bo
*bo
)
364 ws
->cs_add_buffer(cs
, bo
);
367 #endif /* RADV_RADEON_WINSYS_H */