2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * Based on radeon_winsys.h which is:
6 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
7 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #ifndef RADV_RADEON_WINSYS_H
30 #define RADV_RADEON_WINSYS_H
35 #include "main/macros.h"
36 #include "amd_family.h"
42 #define FREE(x) free(x)
44 enum radeon_bo_domain
{ /* bitfield */
45 RADEON_DOMAIN_GTT
= 2,
46 RADEON_DOMAIN_VRAM
= 4,
47 RADEON_DOMAIN_VRAM_GTT
= RADEON_DOMAIN_VRAM
| RADEON_DOMAIN_GTT
50 enum radeon_bo_flag
{ /* bitfield */
51 RADEON_FLAG_GTT_WC
= (1 << 0),
52 RADEON_FLAG_CPU_ACCESS
= (1 << 1),
53 RADEON_FLAG_NO_CPU_ACCESS
= (1 << 2),
54 RADEON_FLAG_VIRTUAL
= (1 << 3),
55 RADEON_FLAG_VA_UNCACHED
= (1 << 4),
58 enum radeon_bo_usage
{ /* bitfield */
59 RADEON_USAGE_READ
= 2,
60 RADEON_USAGE_WRITE
= 4,
61 RADEON_USAGE_READWRITE
= RADEON_USAGE_READ
| RADEON_USAGE_WRITE
73 struct radeon_winsys_cs
{
74 unsigned cdw
; /* Number of used dwords. */
75 unsigned max_dw
; /* Maximum number of dwords. */
76 uint32_t *buf
; /* The base pointer of the chunk. */
79 #define RADEON_SURF_TYPE_MASK 0xFF
80 #define RADEON_SURF_TYPE_SHIFT 0
81 #define RADEON_SURF_TYPE_1D 0
82 #define RADEON_SURF_TYPE_2D 1
83 #define RADEON_SURF_TYPE_3D 2
84 #define RADEON_SURF_TYPE_CUBEMAP 3
85 #define RADEON_SURF_TYPE_1D_ARRAY 4
86 #define RADEON_SURF_TYPE_2D_ARRAY 5
87 #define RADEON_SURF_MODE_MASK 0xFF
88 #define RADEON_SURF_MODE_SHIFT 8
90 #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
91 #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
92 #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
94 enum radeon_bo_layout
{
95 RADEON_LAYOUT_LINEAR
= 0,
97 RADEON_LAYOUT_SQUARETILED
,
102 /* Tiling info for display code, DRI sharing, and other data. */
103 struct radeon_bo_metadata
{
104 /* Tiling flags describing the texture layout for display code
109 enum radeon_bo_layout microtile
;
110 enum radeon_bo_layout macrotile
;
111 unsigned pipe_config
;
123 unsigned swizzle_mode
:5;
127 /* Additional metadata associated with the buffer, in bytes.
128 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
129 * Supported by amdgpu only.
131 uint32_t size_metadata
;
132 uint32_t metadata
[64];
135 uint32_t syncobj_handle
;
136 struct radeon_winsys_fence
;
138 struct radeon_winsys_bo
{
141 struct radv_winsys_sem_counts
{
142 uint32_t syncobj_count
;
145 struct radeon_winsys_sem
**sem
;
148 struct radv_winsys_sem_info
{
151 struct radv_winsys_sem_counts wait
;
152 struct radv_winsys_sem_counts signal
;
155 struct radeon_winsys
{
156 void (*destroy
)(struct radeon_winsys
*ws
);
158 void (*query_info
)(struct radeon_winsys
*ws
,
159 struct radeon_info
*info
);
161 bool (*read_registers
)(struct radeon_winsys
*ws
, unsigned reg_offset
,
162 unsigned num_registers
, uint32_t *out
);
164 const char *(*get_chip_name
)(struct radeon_winsys
*ws
);
166 struct radeon_winsys_bo
*(*buffer_create
)(struct radeon_winsys
*ws
,
169 enum radeon_bo_domain domain
,
170 enum radeon_bo_flag flags
);
172 void (*buffer_destroy
)(struct radeon_winsys_bo
*bo
);
173 void *(*buffer_map
)(struct radeon_winsys_bo
*bo
);
175 struct radeon_winsys_bo
*(*buffer_from_fd
)(struct radeon_winsys
*ws
,
177 unsigned *stride
, unsigned *offset
);
179 bool (*buffer_get_fd
)(struct radeon_winsys
*ws
,
180 struct radeon_winsys_bo
*bo
,
183 void (*buffer_unmap
)(struct radeon_winsys_bo
*bo
);
185 void (*buffer_set_metadata
)(struct radeon_winsys_bo
*bo
,
186 struct radeon_bo_metadata
*md
);
188 void (*buffer_virtual_bind
)(struct radeon_winsys_bo
*parent
,
189 uint64_t offset
, uint64_t size
,
190 struct radeon_winsys_bo
*bo
, uint64_t bo_offset
);
191 struct radeon_winsys_ctx
*(*ctx_create
)(struct radeon_winsys
*ws
);
192 void (*ctx_destroy
)(struct radeon_winsys_ctx
*ctx
);
194 bool (*ctx_wait_idle
)(struct radeon_winsys_ctx
*ctx
,
195 enum ring_type ring_type
, int ring_index
);
197 struct radeon_winsys_cs
*(*cs_create
)(struct radeon_winsys
*ws
,
198 enum ring_type ring_type
);
200 void (*cs_destroy
)(struct radeon_winsys_cs
*cs
);
202 void (*cs_reset
)(struct radeon_winsys_cs
*cs
);
204 bool (*cs_finalize
)(struct radeon_winsys_cs
*cs
);
206 void (*cs_grow
)(struct radeon_winsys_cs
* cs
, size_t min_size
);
208 int (*cs_submit
)(struct radeon_winsys_ctx
*ctx
,
210 struct radeon_winsys_cs
**cs_array
,
212 struct radeon_winsys_cs
*initial_preamble_cs
,
213 struct radeon_winsys_cs
*continue_preamble_cs
,
214 struct radv_winsys_sem_info
*sem_info
,
216 struct radeon_winsys_fence
*fence
);
218 void (*cs_add_buffer
)(struct radeon_winsys_cs
*cs
,
219 struct radeon_winsys_bo
*bo
,
222 void (*cs_execute_secondary
)(struct radeon_winsys_cs
*parent
,
223 struct radeon_winsys_cs
*child
);
225 void (*cs_dump
)(struct radeon_winsys_cs
*cs
, FILE* file
, const int *trace_ids
, int trace_id_count
);
227 int (*surface_init
)(struct radeon_winsys
*ws
,
228 const struct ac_surf_info
*surf_info
,
229 struct radeon_surf
*surf
);
231 int (*surface_best
)(struct radeon_winsys
*ws
,
232 struct radeon_surf
*surf
);
234 struct radeon_winsys_fence
*(*create_fence
)();
235 void (*destroy_fence
)(struct radeon_winsys_fence
*fence
);
236 bool (*fence_wait
)(struct radeon_winsys
*ws
,
237 struct radeon_winsys_fence
*fence
,
241 /* old semaphores - non shareable */
242 struct radeon_winsys_sem
*(*create_sem
)(struct radeon_winsys
*ws
);
243 void (*destroy_sem
)(struct radeon_winsys_sem
*sem
);
245 /* new shareable sync objects */
246 int (*create_syncobj
)(struct radeon_winsys
*ws
, uint32_t *handle
);
247 void (*destroy_syncobj
)(struct radeon_winsys
*ws
, uint32_t handle
);
249 int (*export_syncobj
)(struct radeon_winsys
*ws
, uint32_t syncobj
, int *fd
);
250 int (*import_syncobj
)(struct radeon_winsys
*ws
, int fd
, uint32_t *syncobj
);
254 static inline void radeon_emit(struct radeon_winsys_cs
*cs
, uint32_t value
)
256 cs
->buf
[cs
->cdw
++] = value
;
259 static inline void radeon_emit_array(struct radeon_winsys_cs
*cs
,
260 const uint32_t *values
, unsigned count
)
262 memcpy(cs
->buf
+ cs
->cdw
, values
, count
* 4);
266 static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo
*bo
)
271 #endif /* RADV_RADEON_WINSYS_H */