2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * Based on radeon_winsys.h which is:
6 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
7 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #ifndef RADV_RADEON_WINSYS_H
30 #define RADV_RADEON_WINSYS_H
35 #include "main/macros.h"
36 #include "amd_family.h"
42 #define FREE(x) free(x)
44 enum radeon_bo_domain
{ /* bitfield */
45 RADEON_DOMAIN_GTT
= 2,
46 RADEON_DOMAIN_VRAM
= 4,
47 RADEON_DOMAIN_VRAM_GTT
= RADEON_DOMAIN_VRAM
| RADEON_DOMAIN_GTT
50 enum radeon_bo_flag
{ /* bitfield */
51 RADEON_FLAG_GTT_WC
= (1 << 0),
52 RADEON_FLAG_CPU_ACCESS
= (1 << 1),
53 RADEON_FLAG_NO_CPU_ACCESS
= (1 << 2),
54 RADEON_FLAG_VIRTUAL
= (1 << 3),
55 RADEON_FLAG_VA_UNCACHED
= (1 << 4),
56 RADEON_FLAG_IMPLICIT_SYNC
= (1 << 5),
57 RADEON_FLAG_NO_INTERPROCESS_SHARING
= (1 << 6),
60 enum radeon_bo_usage
{ /* bitfield */
61 RADEON_USAGE_READ
= 2,
62 RADEON_USAGE_WRITE
= 4,
63 RADEON_USAGE_READWRITE
= RADEON_USAGE_READ
| RADEON_USAGE_WRITE
75 enum radeon_ctx_priority
{
76 RADEON_CTX_PRIORITY_INVALID
= -1,
77 RADEON_CTX_PRIORITY_LOW
= 0,
78 RADEON_CTX_PRIORITY_MEDIUM
,
79 RADEON_CTX_PRIORITY_HIGH
,
80 RADEON_CTX_PRIORITY_REALTIME
,
83 struct radeon_winsys_cs
{
84 unsigned cdw
; /* Number of used dwords. */
85 unsigned max_dw
; /* Maximum number of dwords. */
86 uint32_t *buf
; /* The base pointer of the chunk. */
89 #define RADEON_SURF_TYPE_MASK 0xFF
90 #define RADEON_SURF_TYPE_SHIFT 0
91 #define RADEON_SURF_TYPE_1D 0
92 #define RADEON_SURF_TYPE_2D 1
93 #define RADEON_SURF_TYPE_3D 2
94 #define RADEON_SURF_TYPE_CUBEMAP 3
95 #define RADEON_SURF_TYPE_1D_ARRAY 4
96 #define RADEON_SURF_TYPE_2D_ARRAY 5
97 #define RADEON_SURF_MODE_MASK 0xFF
98 #define RADEON_SURF_MODE_SHIFT 8
100 #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
101 #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
102 #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
104 enum radeon_bo_layout
{
105 RADEON_LAYOUT_LINEAR
= 0,
107 RADEON_LAYOUT_SQUARETILED
,
109 RADEON_LAYOUT_UNKNOWN
112 /* Tiling info for display code, DRI sharing, and other data. */
113 struct radeon_bo_metadata
{
114 /* Tiling flags describing the texture layout for display code
119 enum radeon_bo_layout microtile
;
120 enum radeon_bo_layout macrotile
;
121 unsigned pipe_config
;
133 unsigned swizzle_mode
:5;
137 /* Additional metadata associated with the buffer, in bytes.
138 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
139 * Supported by amdgpu only.
141 uint32_t size_metadata
;
142 uint32_t metadata
[64];
145 uint32_t syncobj_handle
;
146 struct radeon_winsys_fence
;
148 struct radeon_winsys_bo
{
152 struct radv_winsys_sem_counts
{
153 uint32_t syncobj_count
;
156 struct radeon_winsys_sem
**sem
;
159 struct radv_winsys_sem_info
{
162 struct radv_winsys_sem_counts wait
;
163 struct radv_winsys_sem_counts signal
;
166 struct radeon_winsys
{
167 void (*destroy
)(struct radeon_winsys
*ws
);
169 void (*query_info
)(struct radeon_winsys
*ws
,
170 struct radeon_info
*info
);
172 bool (*read_registers
)(struct radeon_winsys
*ws
, unsigned reg_offset
,
173 unsigned num_registers
, uint32_t *out
);
175 const char *(*get_chip_name
)(struct radeon_winsys
*ws
);
177 struct radeon_winsys_bo
*(*buffer_create
)(struct radeon_winsys
*ws
,
180 enum radeon_bo_domain domain
,
181 enum radeon_bo_flag flags
);
183 void (*buffer_destroy
)(struct radeon_winsys_bo
*bo
);
184 void *(*buffer_map
)(struct radeon_winsys_bo
*bo
);
186 struct radeon_winsys_bo
*(*buffer_from_fd
)(struct radeon_winsys
*ws
,
188 unsigned *stride
, unsigned *offset
);
190 bool (*buffer_get_fd
)(struct radeon_winsys
*ws
,
191 struct radeon_winsys_bo
*bo
,
194 void (*buffer_unmap
)(struct radeon_winsys_bo
*bo
);
196 void (*buffer_set_metadata
)(struct radeon_winsys_bo
*bo
,
197 struct radeon_bo_metadata
*md
);
199 void (*buffer_virtual_bind
)(struct radeon_winsys_bo
*parent
,
200 uint64_t offset
, uint64_t size
,
201 struct radeon_winsys_bo
*bo
, uint64_t bo_offset
);
202 struct radeon_winsys_ctx
*(*ctx_create
)(struct radeon_winsys
*ws
,
203 enum radeon_ctx_priority priority
);
204 void (*ctx_destroy
)(struct radeon_winsys_ctx
*ctx
);
206 bool (*ctx_wait_idle
)(struct radeon_winsys_ctx
*ctx
,
207 enum ring_type ring_type
, int ring_index
);
209 struct radeon_winsys_cs
*(*cs_create
)(struct radeon_winsys
*ws
,
210 enum ring_type ring_type
);
212 void (*cs_destroy
)(struct radeon_winsys_cs
*cs
);
214 void (*cs_reset
)(struct radeon_winsys_cs
*cs
);
216 bool (*cs_finalize
)(struct radeon_winsys_cs
*cs
);
218 void (*cs_grow
)(struct radeon_winsys_cs
* cs
, size_t min_size
);
220 int (*cs_submit
)(struct radeon_winsys_ctx
*ctx
,
222 struct radeon_winsys_cs
**cs_array
,
224 struct radeon_winsys_cs
*initial_preamble_cs
,
225 struct radeon_winsys_cs
*continue_preamble_cs
,
226 struct radv_winsys_sem_info
*sem_info
,
228 struct radeon_winsys_fence
*fence
);
230 void (*cs_add_buffer
)(struct radeon_winsys_cs
*cs
,
231 struct radeon_winsys_bo
*bo
,
234 void (*cs_execute_secondary
)(struct radeon_winsys_cs
*parent
,
235 struct radeon_winsys_cs
*child
);
237 void (*cs_dump
)(struct radeon_winsys_cs
*cs
, FILE* file
, const int *trace_ids
, int trace_id_count
);
239 int (*surface_init
)(struct radeon_winsys
*ws
,
240 const struct ac_surf_info
*surf_info
,
241 struct radeon_surf
*surf
);
243 int (*surface_best
)(struct radeon_winsys
*ws
,
244 struct radeon_surf
*surf
);
246 struct radeon_winsys_fence
*(*create_fence
)();
247 void (*destroy_fence
)(struct radeon_winsys_fence
*fence
);
248 bool (*fence_wait
)(struct radeon_winsys
*ws
,
249 struct radeon_winsys_fence
*fence
,
253 /* old semaphores - non shareable */
254 struct radeon_winsys_sem
*(*create_sem
)(struct radeon_winsys
*ws
);
255 void (*destroy_sem
)(struct radeon_winsys_sem
*sem
);
257 /* new shareable sync objects */
258 int (*create_syncobj
)(struct radeon_winsys
*ws
, uint32_t *handle
);
259 void (*destroy_syncobj
)(struct radeon_winsys
*ws
, uint32_t handle
);
261 int (*export_syncobj
)(struct radeon_winsys
*ws
, uint32_t syncobj
, int *fd
);
262 int (*import_syncobj
)(struct radeon_winsys
*ws
, int fd
, uint32_t *syncobj
);
266 static inline void radeon_emit(struct radeon_winsys_cs
*cs
, uint32_t value
)
268 cs
->buf
[cs
->cdw
++] = value
;
271 static inline void radeon_emit_array(struct radeon_winsys_cs
*cs
,
272 const uint32_t *values
, unsigned count
)
274 memcpy(cs
->buf
+ cs
->cdw
, values
, count
* 4);
278 static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo
*bo
)
283 static inline void radv_cs_add_buffer(struct radeon_winsys
*ws
,
284 struct radeon_winsys_cs
*cs
,
285 struct radeon_winsys_bo
*bo
,
291 ws
->cs_add_buffer(cs
, bo
, priority
);
294 #endif /* RADV_RADEON_WINSYS_H */