2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * Based on radeon_winsys.h which is:
6 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
7 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #ifndef RADV_RADEON_WINSYS_H
30 #define RADV_RADEON_WINSYS_H
35 #include "main/macros.h"
36 #include "amd_family.h"
38 #define FREE(x) free(x)
40 enum radeon_bo_domain
{ /* bitfield */
41 RADEON_DOMAIN_GTT
= 2,
42 RADEON_DOMAIN_VRAM
= 4,
43 RADEON_DOMAIN_VRAM_GTT
= RADEON_DOMAIN_VRAM
| RADEON_DOMAIN_GTT
46 enum radeon_bo_flag
{ /* bitfield */
47 RADEON_FLAG_GTT_WC
= (1 << 0),
48 RADEON_FLAG_CPU_ACCESS
= (1 << 1),
49 RADEON_FLAG_NO_CPU_ACCESS
= (1 << 2),
52 enum radeon_bo_usage
{ /* bitfield */
53 RADEON_USAGE_READ
= 2,
54 RADEON_USAGE_WRITE
= 4,
55 RADEON_USAGE_READWRITE
= RADEON_USAGE_READ
| RADEON_USAGE_WRITE
67 struct radeon_winsys_cs
{
68 unsigned cdw
; /* Number of used dwords. */
69 unsigned max_dw
; /* Maximum number of dwords. */
70 uint32_t *buf
; /* The base pointer of the chunk. */
74 /* PCI info: domain:bus:dev:func */
82 enum radeon_family family
;
84 enum chip_class chip_class
;
85 uint32_t gart_page_size
;
88 uint64_t visible_vram_size
;
89 bool has_dedicated_vram
;
90 bool has_virtual_memory
;
91 bool gfx_ib_pad_with_type2
;
94 uint32_t vce_fw_version
;
95 uint32_t vce_harvest_config
;
96 uint32_t clock_crystal_freq
;
99 uint32_t drm_major
; /* version */
101 uint32_t drm_patchlevel
;
105 uint32_t r600_max_quad_pipes
; /* wave size / 16 */
106 uint32_t max_shader_clock
;
107 uint32_t num_good_compute_units
;
108 uint32_t max_se
; /* shader engines */
109 uint32_t max_sh_per_se
; /* shader arrays per shader engine */
111 /* Render backends (color + depth blocks). */
112 uint32_t r300_num_gb_pipes
;
113 uint32_t r300_num_z_pipes
;
114 uint32_t r600_gb_backend_map
; /* R600 harvest config */
115 bool r600_gb_backend_map_valid
;
116 uint32_t r600_num_banks
;
117 uint32_t num_render_backends
;
118 uint32_t num_tile_pipes
; /* pipe count from PIPE_CONFIG */
119 uint32_t pipe_interleave_bytes
;
120 uint32_t enabled_rb_mask
; /* GCN harvest config */
123 uint32_t si_tile_mode_array
[32];
124 uint32_t cik_macrotile_mode_array
[16];
127 #define RADEON_SURF_MAX_LEVEL 32
129 #define RADEON_SURF_TYPE_MASK 0xFF
130 #define RADEON_SURF_TYPE_SHIFT 0
131 #define RADEON_SURF_TYPE_1D 0
132 #define RADEON_SURF_TYPE_2D 1
133 #define RADEON_SURF_TYPE_3D 2
134 #define RADEON_SURF_TYPE_CUBEMAP 3
135 #define RADEON_SURF_TYPE_1D_ARRAY 4
136 #define RADEON_SURF_TYPE_2D_ARRAY 5
137 #define RADEON_SURF_MODE_MASK 0xFF
138 #define RADEON_SURF_MODE_SHIFT 8
139 #define RADEON_SURF_MODE_LINEAR_ALIGNED 1
140 #define RADEON_SURF_MODE_1D 2
141 #define RADEON_SURF_MODE_2D 3
142 #define RADEON_SURF_SCANOUT (1 << 16)
143 #define RADEON_SURF_ZBUFFER (1 << 17)
144 #define RADEON_SURF_SBUFFER (1 << 18)
145 #define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
146 #define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
147 #define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
148 #define RADEON_SURF_FMASK (1 << 21)
149 #define RADEON_SURF_DISABLE_DCC (1 << 22)
151 #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
152 #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
153 #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
155 struct radeon_surf_level
{
164 uint32_t pitch_bytes
;
167 uint64_t dcc_fast_clear_size
;
172 /* surface defintions from the winsys */
174 /* These are inputs to the calculator. */
187 /* These are return values. Some of them can be set by the caller, but
188 * they will be treated as hints (e.g. bankw, bankh) and might be
189 * changed by the calculator.
192 uint64_t bo_alignment
;
193 /* This applies to EG and later. */
198 uint32_t stencil_tile_split
;
199 uint64_t stencil_offset
;
200 struct radeon_surf_level level
[RADEON_SURF_MAX_LEVEL
];
201 struct radeon_surf_level stencil_level
[RADEON_SURF_MAX_LEVEL
];
202 uint32_t tiling_index
[RADEON_SURF_MAX_LEVEL
];
203 uint32_t stencil_tiling_index
[RADEON_SURF_MAX_LEVEL
];
204 uint32_t pipe_config
;
206 uint32_t macro_tile_index
;
207 uint32_t micro_tile_mode
; /* displayable, thin, depth, rotated */
209 /* Whether the depth miptree or stencil miptree as used by the DB are
210 * adjusted from their TC compatible form to ensure depth/stencil
211 * compatibility. If either is true, the corresponding plane cannot be
215 bool stencil_adjusted
;
218 uint64_t dcc_alignment
;
221 enum radeon_bo_layout
{
222 RADEON_LAYOUT_LINEAR
= 0,
224 RADEON_LAYOUT_SQUARETILED
,
226 RADEON_LAYOUT_UNKNOWN
229 /* Tiling info for display code, DRI sharing, and other data. */
230 struct radeon_bo_metadata
{
231 /* Tiling flags describing the texture layout for display code
234 enum radeon_bo_layout microtile
;
235 enum radeon_bo_layout macrotile
;
236 unsigned pipe_config
;
245 /* Additional metadata associated with the buffer, in bytes.
246 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
247 * Supported by amdgpu only.
249 uint32_t size_metadata
;
250 uint32_t metadata
[64];
253 struct radeon_winsys_bo
;
254 struct radeon_winsys_fence
;
256 struct radeon_winsys
{
257 void (*destroy
)(struct radeon_winsys
*ws
);
259 void (*query_info
)(struct radeon_winsys
*ws
,
260 struct radeon_info
*info
);
262 struct radeon_winsys_bo
*(*buffer_create
)(struct radeon_winsys
*ws
,
265 enum radeon_bo_domain domain
,
266 enum radeon_bo_flag flags
);
268 void (*buffer_destroy
)(struct radeon_winsys_bo
*bo
);
269 void *(*buffer_map
)(struct radeon_winsys_bo
*bo
);
271 struct radeon_winsys_bo
*(*buffer_from_fd
)(struct radeon_winsys
*ws
,
273 unsigned *stride
, unsigned *offset
);
275 bool (*buffer_get_fd
)(struct radeon_winsys
*ws
,
276 struct radeon_winsys_bo
*bo
,
279 void (*buffer_unmap
)(struct radeon_winsys_bo
*bo
);
281 uint64_t (*buffer_get_va
)(struct radeon_winsys_bo
*bo
);
283 void (*buffer_set_metadata
)(struct radeon_winsys_bo
*bo
,
284 struct radeon_bo_metadata
*md
);
285 struct radeon_winsys_ctx
*(*ctx_create
)(struct radeon_winsys
*ws
);
286 void (*ctx_destroy
)(struct radeon_winsys_ctx
*ctx
);
288 bool (*ctx_wait_idle
)(struct radeon_winsys_ctx
*ctx
);
290 struct radeon_winsys_cs
*(*cs_create
)(struct radeon_winsys
*ws
,
291 enum ring_type ring_type
);
293 void (*cs_destroy
)(struct radeon_winsys_cs
*cs
);
295 void (*cs_reset
)(struct radeon_winsys_cs
*cs
);
297 bool (*cs_finalize
)(struct radeon_winsys_cs
*cs
);
299 void (*cs_grow
)(struct radeon_winsys_cs
* cs
, size_t min_size
);
301 int (*cs_submit
)(struct radeon_winsys_ctx
*ctx
,
302 struct radeon_winsys_cs
**cs_array
,
305 struct radeon_winsys_fence
*fence
);
307 void (*cs_add_buffer
)(struct radeon_winsys_cs
*cs
,
308 struct radeon_winsys_bo
*bo
,
311 void (*cs_execute_secondary
)(struct radeon_winsys_cs
*parent
,
312 struct radeon_winsys_cs
*child
);
314 int (*surface_init
)(struct radeon_winsys
*ws
,
315 struct radeon_surf
*surf
);
317 int (*surface_best
)(struct radeon_winsys
*ws
,
318 struct radeon_surf
*surf
);
320 struct radeon_winsys_fence
*(*create_fence
)();
321 void (*destroy_fence
)(struct radeon_winsys_fence
*fence
);
322 bool (*fence_wait
)(struct radeon_winsys
*ws
,
323 struct radeon_winsys_fence
*fence
,
328 static inline void radeon_emit(struct radeon_winsys_cs
*cs
, uint32_t value
)
330 cs
->buf
[cs
->cdw
++] = value
;
333 static inline void radeon_emit_array(struct radeon_winsys_cs
*cs
,
334 const uint32_t *values
, unsigned count
)
336 memcpy(cs
->buf
+ cs
->cdw
, values
, count
* 4);
340 #endif /* RADV_RADEON_WINSYS_H */