2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * Based on radeon_winsys.h which is:
6 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
7 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #ifndef RADV_RADEON_WINSYS_H
30 #define RADV_RADEON_WINSYS_H
36 #include "main/macros.h"
37 #include "amd_family.h"
43 #define FREE(x) free(x)
45 enum radeon_bo_domain
{ /* bitfield */
46 RADEON_DOMAIN_GTT
= 2,
47 RADEON_DOMAIN_VRAM
= 4,
48 RADEON_DOMAIN_VRAM_GTT
= RADEON_DOMAIN_VRAM
| RADEON_DOMAIN_GTT
51 enum radeon_bo_flag
{ /* bitfield */
52 RADEON_FLAG_GTT_WC
= (1 << 0),
53 RADEON_FLAG_CPU_ACCESS
= (1 << 1),
54 RADEON_FLAG_NO_CPU_ACCESS
= (1 << 2),
55 RADEON_FLAG_VIRTUAL
= (1 << 3),
56 RADEON_FLAG_VA_UNCACHED
= (1 << 4),
57 RADEON_FLAG_IMPLICIT_SYNC
= (1 << 5),
58 RADEON_FLAG_NO_INTERPROCESS_SHARING
= (1 << 6),
59 RADEON_FLAG_READ_ONLY
= (1 << 7),
62 enum radeon_bo_usage
{ /* bitfield */
63 RADEON_USAGE_READ
= 2,
64 RADEON_USAGE_WRITE
= 4,
65 RADEON_USAGE_READWRITE
= RADEON_USAGE_READ
| RADEON_USAGE_WRITE
77 enum radeon_ctx_priority
{
78 RADEON_CTX_PRIORITY_INVALID
= -1,
79 RADEON_CTX_PRIORITY_LOW
= 0,
80 RADEON_CTX_PRIORITY_MEDIUM
,
81 RADEON_CTX_PRIORITY_HIGH
,
82 RADEON_CTX_PRIORITY_REALTIME
,
85 enum radeon_value_id
{
87 RADEON_NUM_BYTES_MOVED
,
89 RADEON_NUM_VRAM_CPU_PAGE_FAULTS
,
91 RADEON_VRAM_VIS_USAGE
,
93 RADEON_GPU_TEMPERATURE
,
98 struct radeon_winsys_cs
{
99 unsigned cdw
; /* Number of used dwords. */
100 unsigned max_dw
; /* Maximum number of dwords. */
101 uint32_t *buf
; /* The base pointer of the chunk. */
104 #define RADEON_SURF_TYPE_MASK 0xFF
105 #define RADEON_SURF_TYPE_SHIFT 0
106 #define RADEON_SURF_TYPE_1D 0
107 #define RADEON_SURF_TYPE_2D 1
108 #define RADEON_SURF_TYPE_3D 2
109 #define RADEON_SURF_TYPE_CUBEMAP 3
110 #define RADEON_SURF_TYPE_1D_ARRAY 4
111 #define RADEON_SURF_TYPE_2D_ARRAY 5
112 #define RADEON_SURF_MODE_MASK 0xFF
113 #define RADEON_SURF_MODE_SHIFT 8
115 #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
116 #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
117 #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
119 enum radeon_bo_layout
{
120 RADEON_LAYOUT_LINEAR
= 0,
122 RADEON_LAYOUT_SQUARETILED
,
124 RADEON_LAYOUT_UNKNOWN
127 /* Tiling info for display code, DRI sharing, and other data. */
128 struct radeon_bo_metadata
{
129 /* Tiling flags describing the texture layout for display code
134 enum radeon_bo_layout microtile
;
135 enum radeon_bo_layout macrotile
;
136 unsigned pipe_config
;
148 unsigned swizzle_mode
:5;
152 /* Additional metadata associated with the buffer, in bytes.
153 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
154 * Supported by amdgpu only.
156 uint32_t size_metadata
;
157 uint32_t metadata
[64];
160 uint32_t syncobj_handle
;
161 struct radeon_winsys_fence
;
163 struct radeon_winsys_bo
{
167 struct radv_winsys_sem_counts
{
168 uint32_t syncobj_count
;
171 struct radeon_winsys_sem
**sem
;
174 struct radv_winsys_sem_info
{
177 struct radv_winsys_sem_counts wait
;
178 struct radv_winsys_sem_counts signal
;
181 struct radv_winsys_bo_list
{
182 struct radeon_winsys_bo
**bos
;
186 struct radeon_winsys
{
187 void (*destroy
)(struct radeon_winsys
*ws
);
189 void (*query_info
)(struct radeon_winsys
*ws
,
190 struct radeon_info
*info
);
192 uint64_t (*query_value
)(struct radeon_winsys
*ws
,
193 enum radeon_value_id value
);
195 bool (*read_registers
)(struct radeon_winsys
*ws
, unsigned reg_offset
,
196 unsigned num_registers
, uint32_t *out
);
198 const char *(*get_chip_name
)(struct radeon_winsys
*ws
);
200 struct radeon_winsys_bo
*(*buffer_create
)(struct radeon_winsys
*ws
,
203 enum radeon_bo_domain domain
,
204 enum radeon_bo_flag flags
);
206 void (*buffer_destroy
)(struct radeon_winsys_bo
*bo
);
207 void *(*buffer_map
)(struct radeon_winsys_bo
*bo
);
209 struct radeon_winsys_bo
*(*buffer_from_ptr
)(struct radeon_winsys
*ws
,
213 struct radeon_winsys_bo
*(*buffer_from_fd
)(struct radeon_winsys
*ws
,
215 unsigned *stride
, unsigned *offset
);
217 bool (*buffer_get_fd
)(struct radeon_winsys
*ws
,
218 struct radeon_winsys_bo
*bo
,
221 void (*buffer_unmap
)(struct radeon_winsys_bo
*bo
);
223 void (*buffer_set_metadata
)(struct radeon_winsys_bo
*bo
,
224 struct radeon_bo_metadata
*md
);
226 void (*buffer_virtual_bind
)(struct radeon_winsys_bo
*parent
,
227 uint64_t offset
, uint64_t size
,
228 struct radeon_winsys_bo
*bo
, uint64_t bo_offset
);
229 struct radeon_winsys_ctx
*(*ctx_create
)(struct radeon_winsys
*ws
,
230 enum radeon_ctx_priority priority
);
231 void (*ctx_destroy
)(struct radeon_winsys_ctx
*ctx
);
233 bool (*ctx_wait_idle
)(struct radeon_winsys_ctx
*ctx
,
234 enum ring_type ring_type
, int ring_index
);
236 struct radeon_winsys_cs
*(*cs_create
)(struct radeon_winsys
*ws
,
237 enum ring_type ring_type
);
239 void (*cs_destroy
)(struct radeon_winsys_cs
*cs
);
241 void (*cs_reset
)(struct radeon_winsys_cs
*cs
);
243 bool (*cs_finalize
)(struct radeon_winsys_cs
*cs
);
245 void (*cs_grow
)(struct radeon_winsys_cs
* cs
, size_t min_size
);
247 int (*cs_submit
)(struct radeon_winsys_ctx
*ctx
,
249 struct radeon_winsys_cs
**cs_array
,
251 struct radeon_winsys_cs
*initial_preamble_cs
,
252 struct radeon_winsys_cs
*continue_preamble_cs
,
253 struct radv_winsys_sem_info
*sem_info
,
254 const struct radv_winsys_bo_list
*bo_list
, /* optional */
256 struct radeon_winsys_fence
*fence
);
258 void (*cs_add_buffer
)(struct radeon_winsys_cs
*cs
,
259 struct radeon_winsys_bo
*bo
,
262 void (*cs_execute_secondary
)(struct radeon_winsys_cs
*parent
,
263 struct radeon_winsys_cs
*child
);
265 void (*cs_dump
)(struct radeon_winsys_cs
*cs
, FILE* file
, const int *trace_ids
, int trace_id_count
);
267 int (*surface_init
)(struct radeon_winsys
*ws
,
268 const struct ac_surf_info
*surf_info
,
269 struct radeon_surf
*surf
);
271 int (*surface_best
)(struct radeon_winsys
*ws
,
272 struct radeon_surf
*surf
);
274 struct radeon_winsys_fence
*(*create_fence
)();
275 void (*destroy_fence
)(struct radeon_winsys_fence
*fence
);
276 bool (*fence_wait
)(struct radeon_winsys
*ws
,
277 struct radeon_winsys_fence
*fence
,
280 bool (*fences_wait
)(struct radeon_winsys
*ws
,
281 struct radeon_winsys_fence
*const *fences
,
282 uint32_t fence_count
,
286 /* old semaphores - non shareable */
287 struct radeon_winsys_sem
*(*create_sem
)(struct radeon_winsys
*ws
);
288 void (*destroy_sem
)(struct radeon_winsys_sem
*sem
);
290 /* new shareable sync objects */
291 int (*create_syncobj
)(struct radeon_winsys
*ws
, uint32_t *handle
);
292 void (*destroy_syncobj
)(struct radeon_winsys
*ws
, uint32_t handle
);
294 void (*reset_syncobj
)(struct radeon_winsys
*ws
, uint32_t handle
);
295 void (*signal_syncobj
)(struct radeon_winsys
*ws
, uint32_t handle
);
296 bool (*wait_syncobj
)(struct radeon_winsys
*ws
, const uint32_t *handles
, uint32_t handle_count
,
297 bool wait_all
, uint64_t timeout
);
299 int (*export_syncobj
)(struct radeon_winsys
*ws
, uint32_t syncobj
, int *fd
);
300 int (*import_syncobj
)(struct radeon_winsys
*ws
, int fd
, uint32_t *syncobj
);
302 int (*export_syncobj_to_sync_file
)(struct radeon_winsys
*ws
, uint32_t syncobj
, int *fd
);
304 /* Note that this, unlike the normal import, uses an existing syncobj. */
305 int (*import_syncobj_from_sync_file
)(struct radeon_winsys
*ws
, uint32_t syncobj
, int fd
);
309 static inline void radeon_emit(struct radeon_winsys_cs
*cs
, uint32_t value
)
311 cs
->buf
[cs
->cdw
++] = value
;
314 static inline void radeon_emit_array(struct radeon_winsys_cs
*cs
,
315 const uint32_t *values
, unsigned count
)
317 memcpy(cs
->buf
+ cs
->cdw
, values
, count
* 4);
321 static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo
*bo
)
326 static inline void radv_cs_add_buffer(struct radeon_winsys
*ws
,
327 struct radeon_winsys_cs
*cs
,
328 struct radeon_winsys_bo
*bo
,
334 ws
->cs_add_buffer(cs
, bo
, priority
);
337 #endif /* RADV_RADEON_WINSYS_H */