src/amd/vulkan/radv_radeon_winsys.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * Based on radeon_winsys.h which is:
   6  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   7  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  26  * IN THE SOFTWARE.
  27  */
  28
  29 #ifndef RADV_RADEON_WINSYS_H
  30 #define RADV_RADEON_WINSYS_H
  31
  32 #include <stdint.h>
  33 #include <stdbool.h>
  34 #include <stdlib.h>
  35 #include "main/macros.h"
  36 #include "amd_family.h"
  37
  38 struct ac_surf_info;
  39 struct radeon_surf;
  40
  41 #define FREE(x) free(x)
  42
  43 enum radeon_bo_domain { /* bitfield */
  44         RADEON_DOMAIN_GTT  = 2,
  45         RADEON_DOMAIN_VRAM = 4,
  46         RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  47 };
  48
  49 enum radeon_bo_flag { /* bitfield */
  50         RADEON_FLAG_GTT_WC =        (1 << 0),
  51         RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  52         RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  53         RADEON_FLAG_VIRTUAL =       (1 << 3)
  54 };
  55
  56 enum radeon_bo_usage { /* bitfield */
  57         RADEON_USAGE_READ = 2,
  58         RADEON_USAGE_WRITE = 4,
  59         RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  60 };
  61
  62 enum ring_type {
  63         RING_GFX = 0,
  64         RING_COMPUTE,
  65         RING_DMA,
  66         RING_UVD,
  67         RING_VCE,
  68         RING_LAST,
  69 };
  70
  71 struct radeon_winsys_cs {
  72         unsigned cdw;  /* Number of used dwords. */
  73         unsigned max_dw; /* Maximum number of dwords. */
  74         uint32_t *buf; /* The base pointer of the chunk. */
  75 };
  76
  77 struct radeon_info {
  78         /* PCI info: domain:bus:dev:func */
  79         uint32_t                    pci_domain;
  80         uint32_t                    pci_bus;
  81         uint32_t                    pci_dev;
  82         uint32_t                    pci_func;
  83
  84         /* Device info. */
  85         uint32_t                    pci_id;
  86         enum radeon_family          family;
  87         const char                  *name;
  88         enum chip_class             chip_class;
  89         uint32_t                    gart_page_size;
  90         uint64_t                    gart_size;
  91         uint64_t                    vram_size;
  92         uint64_t                    visible_vram_size;
  93         bool                        has_dedicated_vram;
  94         bool                     has_virtual_memory;
  95         bool                        gfx_ib_pad_with_type2;
  96         bool                     has_uvd;
  97         uint32_t                    sdma_rings;
  98         uint32_t                    compute_rings;
  99         uint32_t                    vce_fw_version;
 100         uint32_t                    vce_harvest_config;
 101         uint32_t                    clock_crystal_freq; /* in kHz */
 102
 103         /* Kernel info. */
 104         uint32_t                    drm_major; /* version */
 105         uint32_t                    drm_minor;
 106         uint32_t                    drm_patchlevel;
 107         bool                     has_userptr;
 108
 109         /* Shader cores. */
 110         uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 111         uint32_t                    max_shader_clock;
 112         uint32_t                    num_good_compute_units;
 113         uint32_t                    max_se; /* shader engines */
 114         uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 115
 116         /* Render backends (color + depth blocks). */
 117         uint32_t                    r300_num_gb_pipes;
 118         uint32_t                    r300_num_z_pipes;
 119         uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 120         bool                     r600_gb_backend_map_valid;
 121         uint32_t                    r600_num_banks;
 122         uint32_t                    num_render_backends;
 123         uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 124         uint32_t                    pipe_interleave_bytes;
 125         uint32_t                    enabled_rb_mask; /* GCN harvest config */
 126
 127         /* Tile modes. */
 128         uint32_t                    si_tile_mode_array[32];
 129         uint32_t                    cik_macrotile_mode_array[16];
 130 };
 131
 132 #define RADEON_SURF_TYPE_MASK                   0xFF
 133 #define RADEON_SURF_TYPE_SHIFT                  0
 134 #define     RADEON_SURF_TYPE_1D                     0
 135 #define     RADEON_SURF_TYPE_2D                     1
 136 #define     RADEON_SURF_TYPE_3D                     2
 137 #define     RADEON_SURF_TYPE_CUBEMAP                3
 138 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 139 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 140 #define RADEON_SURF_MODE_MASK                   0xFF
 141 #define RADEON_SURF_MODE_SHIFT                  8
 142
 143 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 144 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 145 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 146
 147 enum radeon_bo_layout {
 148         RADEON_LAYOUT_LINEAR = 0,
 149         RADEON_LAYOUT_TILED,
 150         RADEON_LAYOUT_SQUARETILED,
 151
 152         RADEON_LAYOUT_UNKNOWN
 153 };
 154
 155 /* Tiling info for display code, DRI sharing, and other data. */
 156 struct radeon_bo_metadata {
 157         /* Tiling flags describing the texture layout for display code
 158          * and DRI sharing.
 159          */
 160         enum radeon_bo_layout   microtile;
 161         enum radeon_bo_layout   macrotile;
 162         unsigned                pipe_config;
 163         unsigned                bankw;
 164         unsigned                bankh;
 165         unsigned                tile_split;
 166         unsigned                mtilea;
 167         unsigned                num_banks;
 168         unsigned                stride;
 169         bool                    scanout;
 170
 171         /* Additional metadata associated with the buffer, in bytes.
 172          * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 173          * Supported by amdgpu only.
 174          */
 175         uint32_t                size_metadata;
 176         uint32_t                metadata[64];
 177 };
 178
 179 struct radeon_winsys_bo;
 180 struct radeon_winsys_fence;
 181 struct radeon_winsys_sem;
 182
 183 struct radeon_winsys {
 184         void (*destroy)(struct radeon_winsys *ws);
 185
 186         void (*query_info)(struct radeon_winsys *ws,
 187                            struct radeon_info *info);
 188
 189         struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws,
 190                                                   uint64_t size,
 191                                                   unsigned alignment,
 192                                                   enum radeon_bo_domain domain,
 193                                                   enum radeon_bo_flag flags);
 194
 195         void (*buffer_destroy)(struct radeon_winsys_bo *bo);
 196         void *(*buffer_map)(struct radeon_winsys_bo *bo);
 197
 198         struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws,
 199                                                    int fd,
 200                                                    unsigned *stride, unsigned *offset);
 201
 202         bool (*buffer_get_fd)(struct radeon_winsys *ws,
 203                               struct radeon_winsys_bo *bo,
 204                               int *fd);
 205
 206         void (*buffer_unmap)(struct radeon_winsys_bo *bo);
 207
 208         uint64_t (*buffer_get_va)(struct radeon_winsys_bo *bo);
 209
 210         void (*buffer_set_metadata)(struct radeon_winsys_bo *bo,
 211                                     struct radeon_bo_metadata *md);
 212
 213         void (*buffer_virtual_bind)(struct radeon_winsys_bo *parent,
 214                                     uint64_t offset, uint64_t size,
 215                                     struct radeon_winsys_bo *bo, uint64_t bo_offset);
 216         struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 217         void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 218
 219         bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
 220                               enum ring_type ring_type, int ring_index);
 221
 222         struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws,
 223                                               enum ring_type ring_type);
 224
 225         void (*cs_destroy)(struct radeon_winsys_cs *cs);
 226
 227         void (*cs_reset)(struct radeon_winsys_cs *cs);
 228
 229         bool (*cs_finalize)(struct radeon_winsys_cs *cs);
 230
 231         void (*cs_grow)(struct radeon_winsys_cs * cs, size_t min_size);
 232
 233         int (*cs_submit)(struct radeon_winsys_ctx *ctx,
 234                          int queue_index,
 235                          struct radeon_winsys_cs **cs_array,
 236                          unsigned cs_count,
 237                          struct radeon_winsys_cs *initial_preamble_cs,
 238                          struct radeon_winsys_cs *continue_preamble_cs,
 239                          struct radeon_winsys_sem **wait_sem,
 240                          unsigned wait_sem_count,
 241                          struct radeon_winsys_sem **signal_sem,
 242                          unsigned signal_sem_count,
 243                          bool can_patch,
 244                          struct radeon_winsys_fence *fence);
 245
 246         void (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 247                               struct radeon_winsys_bo *bo,
 248                               uint8_t priority);
 249
 250         void (*cs_execute_secondary)(struct radeon_winsys_cs *parent,
 251                                     struct radeon_winsys_cs *child);
 252
 253         void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, uint32_t trace_id);
 254
 255         int (*surface_init)(struct radeon_winsys *ws,
 256                             const struct ac_surf_info *surf_info,
 257                             struct radeon_surf *surf);
 258
 259         int (*surface_best)(struct radeon_winsys *ws,
 260                             struct radeon_surf *surf);
 261
 262         struct radeon_winsys_fence *(*create_fence)();
 263         void (*destroy_fence)(struct radeon_winsys_fence *fence);
 264         bool (*fence_wait)(struct radeon_winsys *ws,
 265                            struct radeon_winsys_fence *fence,
 266                            bool absolute,
 267                            uint64_t timeout);
 268
 269         struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws);
 270         void (*destroy_sem)(struct radeon_winsys_sem *sem);
 271
 272 };
 273
 274 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 275 {
 276         cs->buf[cs->cdw++] = value;
 277 }
 278
 279 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 280                                      const uint32_t *values, unsigned count)
 281 {
 282         memcpy(cs->buf + cs->cdw, values, count * 4);
 283         cs->cdw += count;
 284 }
 285
 286 #endif /* RADV_RADEON_WINSYS_H */