src/amd/vulkan/radv_radeon_winsys.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * Based on radeon_winsys.h which is:
   6  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   7  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  26  * IN THE SOFTWARE.
  27  */
  28
  29 #ifndef RADV_RADEON_WINSYS_H
  30 #define RADV_RADEON_WINSYS_H
  31
  32 #include <stdio.h>
  33 #include <stdint.h>
  34 #include <stdbool.h>
  35 #include <stdlib.h>
  36 #include "main/macros.h"
  37 #include "amd_family.h"
  38
  39 struct radeon_info;
  40 struct ac_surf_info;
  41 struct radeon_surf;
  42
  43 #define FREE(x) free(x)
  44
  45 enum radeon_bo_domain { /* bitfield */
  46         RADEON_DOMAIN_GTT  = 2,
  47         RADEON_DOMAIN_VRAM = 4,
  48         RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT,
  49         RADEON_DOMAIN_GDS = 8,
  50         RADEON_DOMAIN_OA = 16,
  51 };
  52
  53 enum radeon_bo_flag { /* bitfield */
  54         RADEON_FLAG_GTT_WC =        (1 << 0),
  55         RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  56         RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  57         RADEON_FLAG_VIRTUAL =       (1 << 3),
  58         RADEON_FLAG_VA_UNCACHED =   (1 << 4),
  59         RADEON_FLAG_IMPLICIT_SYNC = (1 << 5),
  60         RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 6),
  61         RADEON_FLAG_READ_ONLY =     (1 << 7),
  62         RADEON_FLAG_32BIT =         (1 << 8),
  63         RADEON_FLAG_PREFER_LOCAL_BO = (1 << 9),
  64 };
  65
  66 enum radeon_bo_usage { /* bitfield */
  67         RADEON_USAGE_READ = 2,
  68         RADEON_USAGE_WRITE = 4,
  69         RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  70 };
  71
  72 enum ring_type {
  73         RING_GFX = 0,
  74         RING_COMPUTE,
  75         RING_DMA,
  76         RING_UVD,
  77         RING_VCE,
  78         RING_LAST,
  79 };
  80
  81 enum radeon_ctx_priority {
  82         RADEON_CTX_PRIORITY_INVALID = -1,
  83         RADEON_CTX_PRIORITY_LOW = 0,
  84         RADEON_CTX_PRIORITY_MEDIUM,
  85         RADEON_CTX_PRIORITY_HIGH,
  86         RADEON_CTX_PRIORITY_REALTIME,
  87 };
  88
  89 enum radeon_value_id {
  90         RADEON_ALLOCATED_VRAM,
  91         RADEON_ALLOCATED_VRAM_VIS,
  92         RADEON_ALLOCATED_GTT,
  93         RADEON_TIMESTAMP,
  94         RADEON_NUM_BYTES_MOVED,
  95         RADEON_NUM_EVICTIONS,
  96         RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
  97         RADEON_VRAM_USAGE,
  98         RADEON_VRAM_VIS_USAGE,
  99         RADEON_GTT_USAGE,
 100         RADEON_GPU_TEMPERATURE,
 101         RADEON_CURRENT_SCLK,
 102         RADEON_CURRENT_MCLK,
 103 };
 104
 105 struct radeon_cmdbuf {
 106         unsigned cdw;  /* Number of used dwords. */
 107         unsigned max_dw; /* Maximum number of dwords. */
 108         uint32_t *buf; /* The base pointer of the chunk. */
 109 };
 110
 111 #define RADEON_SURF_TYPE_MASK                   0xFF
 112 #define RADEON_SURF_TYPE_SHIFT                  0
 113 #define     RADEON_SURF_TYPE_1D                     0
 114 #define     RADEON_SURF_TYPE_2D                     1
 115 #define     RADEON_SURF_TYPE_3D                     2
 116 #define     RADEON_SURF_TYPE_CUBEMAP                3
 117 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 118 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 119 #define RADEON_SURF_MODE_MASK                   0xFF
 120 #define RADEON_SURF_MODE_SHIFT                  8
 121
 122 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 123 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 124 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 125
 126 enum radeon_bo_layout {
 127         RADEON_LAYOUT_LINEAR = 0,
 128         RADEON_LAYOUT_TILED,
 129         RADEON_LAYOUT_SQUARETILED,
 130
 131         RADEON_LAYOUT_UNKNOWN
 132 };
 133
 134 /* Tiling info for display code, DRI sharing, and other data. */
 135 struct radeon_bo_metadata {
 136         /* Tiling flags describing the texture layout for display code
 137          * and DRI sharing.
 138          */
 139         union {
 140                 struct {
 141                         enum radeon_bo_layout   microtile;
 142                         enum radeon_bo_layout   macrotile;
 143                         unsigned                pipe_config;
 144                         unsigned                bankw;
 145                         unsigned                bankh;
 146                         unsigned                tile_split;
 147                         unsigned                mtilea;
 148                         unsigned                num_banks;
 149                         unsigned                stride;
 150                         bool                    scanout;
 151                 } legacy;
 152
 153                 struct {
 154                         /* surface flags */
 155                         unsigned swizzle_mode:5;
 156                 } gfx9;
 157         } u;
 158
 159         /* Additional metadata associated with the buffer, in bytes.
 160          * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 161          * Supported by amdgpu only.
 162          */
 163         uint32_t                size_metadata;
 164         uint32_t                metadata[64];
 165 };
 166
 167 uint32_t syncobj_handle;
 168 struct radeon_winsys_fence;
 169
 170 struct radeon_winsys_bo {
 171         uint64_t va;
 172         bool is_local;
 173         bool vram_cpu_access;
 174 };
 175 struct radv_winsys_sem_counts {
 176         uint32_t syncobj_count;
 177         uint32_t sem_count;
 178         uint32_t *syncobj;
 179         struct radeon_winsys_sem **sem;
 180 };
 181
 182 struct radv_winsys_sem_info {
 183         bool cs_emit_signal;
 184         bool cs_emit_wait;
 185         struct radv_winsys_sem_counts wait;
 186         struct radv_winsys_sem_counts signal;
 187 };
 188
 189 struct radv_winsys_bo_list {
 190         struct radeon_winsys_bo **bos;
 191         unsigned count;
 192 };
 193
 194 /* Kernel effectively allows 0-31. This sets some priorities for fixed
 195  * functionality buffers */
 196 enum {
 197         RADV_BO_PRIORITY_APPLICATION_MAX = 28,
 198
 199         /* virtual buffers have 0 priority since the priority is not used. */
 200         RADV_BO_PRIORITY_VIRTUAL = 0,
 201
 202         /* This should be considerably lower than most of the stuff below,
 203          * but how much lower is hard to say since we don't know application
 204          * assignments. Put it pretty high since it is GTT anyway. */
 205         RADV_BO_PRIORITY_QUERY_POOL = 29,
 206
 207         RADV_BO_PRIORITY_DESCRIPTOR = 30,
 208         RADV_BO_PRIORITY_UPLOAD_BUFFER = 30,
 209         RADV_BO_PRIORITY_FENCE = 30,
 210         RADV_BO_PRIORITY_SHADER = 31,
 211         RADV_BO_PRIORITY_SCRATCH = 31,
 212         RADV_BO_PRIORITY_CS = 31,
 213 };
 214
 215 struct radeon_winsys {
 216         void (*destroy)(struct radeon_winsys *ws);
 217
 218         void (*query_info)(struct radeon_winsys *ws,
 219                            struct radeon_info *info);
 220
 221         uint64_t (*query_value)(struct radeon_winsys *ws,
 222                                 enum radeon_value_id value);
 223
 224         bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 225                                unsigned num_registers, uint32_t *out);
 226
 227         const char *(*get_chip_name)(struct radeon_winsys *ws);
 228
 229         struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws,
 230                                                   uint64_t size,
 231                                                   unsigned alignment,
 232                                                   enum radeon_bo_domain domain,
 233                                                   enum radeon_bo_flag flags,
 234                                                   unsigned priority);
 235
 236         void (*buffer_destroy)(struct radeon_winsys_bo *bo);
 237         void *(*buffer_map)(struct radeon_winsys_bo *bo);
 238
 239         struct radeon_winsys_bo *(*buffer_from_ptr)(struct radeon_winsys *ws,
 240                                                     void *pointer,
 241                                                     uint64_t size,
 242                                                     unsigned priority);
 243
 244         struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws,
 245                                                    int fd,
 246                                                    unsigned priority,
 247                                                    uint64_t *alloc_size);
 248
 249         bool (*buffer_get_fd)(struct radeon_winsys *ws,
 250                               struct radeon_winsys_bo *bo,
 251                               int *fd);
 252
 253         void (*buffer_unmap)(struct radeon_winsys_bo *bo);
 254
 255         void (*buffer_set_metadata)(struct radeon_winsys_bo *bo,
 256                                     struct radeon_bo_metadata *md);
 257         void (*buffer_get_metadata)(struct radeon_winsys_bo *bo,
 258                                     struct radeon_bo_metadata *md);
 259
 260         void (*buffer_virtual_bind)(struct radeon_winsys_bo *parent,
 261                                     uint64_t offset, uint64_t size,
 262                                     struct radeon_winsys_bo *bo, uint64_t bo_offset);
 263         struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws,
 264                                                 enum radeon_ctx_priority priority);
 265         void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 266
 267         bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
 268                               enum ring_type ring_type, int ring_index);
 269
 270         struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws,
 271                                               enum ring_type ring_type);
 272
 273         void (*cs_destroy)(struct radeon_cmdbuf *cs);
 274
 275         void (*cs_reset)(struct radeon_cmdbuf *cs);
 276
 277         bool (*cs_finalize)(struct radeon_cmdbuf *cs);
 278
 279         void (*cs_grow)(struct radeon_cmdbuf * cs, size_t min_size);
 280
 281         int (*cs_submit)(struct radeon_winsys_ctx *ctx,
 282                          int queue_index,
 283                          struct radeon_cmdbuf **cs_array,
 284                          unsigned cs_count,
 285                          struct radeon_cmdbuf *initial_preamble_cs,
 286                          struct radeon_cmdbuf *continue_preamble_cs,
 287                          struct radv_winsys_sem_info *sem_info,
 288                          const struct radv_winsys_bo_list *bo_list, /* optional */
 289                          bool can_patch,
 290                          struct radeon_winsys_fence *fence);
 291
 292         void (*cs_add_buffer)(struct radeon_cmdbuf *cs,
 293                               struct radeon_winsys_bo *bo);
 294
 295         void (*cs_execute_secondary)(struct radeon_cmdbuf *parent,
 296                                     struct radeon_cmdbuf *child);
 297
 298         void (*cs_dump)(struct radeon_cmdbuf *cs, FILE* file, const int *trace_ids, int trace_id_count);
 299
 300         int (*surface_init)(struct radeon_winsys *ws,
 301                             const struct ac_surf_info *surf_info,
 302                             struct radeon_surf *surf);
 303
 304         struct radeon_winsys_fence *(*create_fence)();
 305         void (*destroy_fence)(struct radeon_winsys_fence *fence);
 306         void (*reset_fence)(struct radeon_winsys_fence *fence);
 307         void (*signal_fence)(struct radeon_winsys_fence *fence);
 308         bool (*is_fence_waitable)(struct radeon_winsys_fence *fence);
 309         bool (*fence_wait)(struct radeon_winsys *ws,
 310                            struct radeon_winsys_fence *fence,
 311                            bool absolute,
 312                            uint64_t timeout);
 313         bool (*fences_wait)(struct radeon_winsys *ws,
 314                             struct radeon_winsys_fence *const *fences,
 315                             uint32_t fence_count,
 316                             bool wait_all,
 317                             uint64_t timeout);
 318
 319         /* old semaphores - non shareable */
 320         struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws);
 321         void (*destroy_sem)(struct radeon_winsys_sem *sem);
 322
 323         /* new shareable sync objects */
 324         int (*create_syncobj)(struct radeon_winsys *ws, uint32_t *handle);
 325         void (*destroy_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 326
 327         void (*reset_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 328         void (*signal_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 329         bool (*wait_syncobj)(struct radeon_winsys *ws, const uint32_t *handles, uint32_t handle_count,
 330                              bool wait_all, uint64_t timeout);
 331
 332         int (*export_syncobj)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
 333         int (*import_syncobj)(struct radeon_winsys *ws, int fd, uint32_t *syncobj);
 334
 335         int (*export_syncobj_to_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
 336
 337         /* Note that this, unlike the normal import, uses an existing syncobj. */
 338         int (*import_syncobj_from_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int fd);
 339
 340 };
 341
 342 static inline void radeon_emit(struct radeon_cmdbuf *cs, uint32_t value)
 343 {
 344         cs->buf[cs->cdw++] = value;
 345 }
 346
 347 static inline void radeon_emit_array(struct radeon_cmdbuf *cs,
 348                                      const uint32_t *values, unsigned count)
 349 {
 350         memcpy(cs->buf + cs->cdw, values, count * 4);
 351         cs->cdw += count;
 352 }
 353
 354 static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo *bo)
 355 {
 356         return bo->va;
 357 }
 358
 359 static inline void radv_cs_add_buffer(struct radeon_winsys *ws,
 360                                       struct radeon_cmdbuf *cs,
 361                                       struct radeon_winsys_bo *bo)
 362 {
 363         if (bo->is_local)
 364                 return;
 365
 366         ws->cs_add_buffer(cs, bo);
 367 }
 368
 369 #endif /* RADV_RADEON_WINSYS_H */