src/amd/vulkan/radv_radeon_winsys.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * Based on radeon_winsys.h which is:
   6  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   7  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  26  * IN THE SOFTWARE.
  27  */
  28
  29 #ifndef RADV_RADEON_WINSYS_H
  30 #define RADV_RADEON_WINSYS_H
  31
  32 #include <stdio.h>
  33 #include <stdint.h>
  34 #include <stdbool.h>
  35 #include <stdlib.h>
  36 #include "main/macros.h"
  37 #include "amd_family.h"
  38
  39 struct radeon_info;
  40 struct ac_surf_info;
  41 struct radeon_surf;
  42
  43 #define FREE(x) free(x)
  44
  45 enum radeon_bo_domain { /* bitfield */
  46         RADEON_DOMAIN_GTT  = 2,
  47         RADEON_DOMAIN_VRAM = 4,
  48         RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  49 };
  50
  51 enum radeon_bo_flag { /* bitfield */
  52         RADEON_FLAG_GTT_WC =        (1 << 0),
  53         RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  54         RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  55         RADEON_FLAG_VIRTUAL =       (1 << 3),
  56         RADEON_FLAG_VA_UNCACHED =   (1 << 4),
  57         RADEON_FLAG_IMPLICIT_SYNC = (1 << 5),
  58         RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 6),
  59         RADEON_FLAG_READ_ONLY =     (1 << 7),
  60         RADEON_FLAG_32BIT =         (1 << 8),
  61         RADEON_FLAG_PREFER_LOCAL_BO = (1 << 9),
  62 };
  63
  64 enum radeon_bo_usage { /* bitfield */
  65         RADEON_USAGE_READ = 2,
  66         RADEON_USAGE_WRITE = 4,
  67         RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  68 };
  69
  70 enum ring_type {
  71         RING_GFX = 0,
  72         RING_COMPUTE,
  73         RING_DMA,
  74         RING_UVD,
  75         RING_VCE,
  76         RING_LAST,
  77 };
  78
  79 enum radeon_ctx_priority {
  80         RADEON_CTX_PRIORITY_INVALID = -1,
  81         RADEON_CTX_PRIORITY_LOW = 0,
  82         RADEON_CTX_PRIORITY_MEDIUM,
  83         RADEON_CTX_PRIORITY_HIGH,
  84         RADEON_CTX_PRIORITY_REALTIME,
  85 };
  86
  87 enum radeon_value_id {
  88         RADEON_ALLOCATED_VRAM,
  89         RADEON_ALLOCATED_VRAM_VIS,
  90         RADEON_ALLOCATED_GTT,
  91         RADEON_TIMESTAMP,
  92         RADEON_NUM_BYTES_MOVED,
  93         RADEON_NUM_EVICTIONS,
  94         RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
  95         RADEON_VRAM_USAGE,
  96         RADEON_VRAM_VIS_USAGE,
  97         RADEON_GTT_USAGE,
  98         RADEON_GPU_TEMPERATURE,
  99         RADEON_CURRENT_SCLK,
 100         RADEON_CURRENT_MCLK,
 101 };
 102
 103 struct radeon_cmdbuf {
 104         unsigned cdw;  /* Number of used dwords. */
 105         unsigned max_dw; /* Maximum number of dwords. */
 106         uint32_t *buf; /* The base pointer of the chunk. */
 107 };
 108
 109 #define RADEON_SURF_TYPE_MASK                   0xFF
 110 #define RADEON_SURF_TYPE_SHIFT                  0
 111 #define     RADEON_SURF_TYPE_1D                     0
 112 #define     RADEON_SURF_TYPE_2D                     1
 113 #define     RADEON_SURF_TYPE_3D                     2
 114 #define     RADEON_SURF_TYPE_CUBEMAP                3
 115 #define     RADEON_SURF_TYPE_1D_ARRAY               4
 116 #define     RADEON_SURF_TYPE_2D_ARRAY               5
 117 #define RADEON_SURF_MODE_MASK                   0xFF
 118 #define RADEON_SURF_MODE_SHIFT                  8
 119
 120 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
 121 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 122 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 123
 124 enum radeon_bo_layout {
 125         RADEON_LAYOUT_LINEAR = 0,
 126         RADEON_LAYOUT_TILED,
 127         RADEON_LAYOUT_SQUARETILED,
 128
 129         RADEON_LAYOUT_UNKNOWN
 130 };
 131
 132 /* Tiling info for display code, DRI sharing, and other data. */
 133 struct radeon_bo_metadata {
 134         /* Tiling flags describing the texture layout for display code
 135          * and DRI sharing.
 136          */
 137         union {
 138                 struct {
 139                         enum radeon_bo_layout   microtile;
 140                         enum radeon_bo_layout   macrotile;
 141                         unsigned                pipe_config;
 142                         unsigned                bankw;
 143                         unsigned                bankh;
 144                         unsigned                tile_split;
 145                         unsigned                mtilea;
 146                         unsigned                num_banks;
 147                         unsigned                stride;
 148                         bool                    scanout;
 149                 } legacy;
 150
 151                 struct {
 152                         /* surface flags */
 153                         unsigned swizzle_mode:5;
 154                 } gfx9;
 155         } u;
 156
 157         /* Additional metadata associated with the buffer, in bytes.
 158          * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 159          * Supported by amdgpu only.
 160          */
 161         uint32_t                size_metadata;
 162         uint32_t                metadata[64];
 163 };
 164
 165 uint32_t syncobj_handle;
 166 struct radeon_winsys_fence;
 167
 168 struct radeon_winsys_bo {
 169         uint64_t va;
 170         bool is_local;
 171         bool vram_cpu_access;
 172 };
 173 struct radv_winsys_sem_counts {
 174         uint32_t syncobj_count;
 175         uint32_t sem_count;
 176         uint32_t *syncobj;
 177         struct radeon_winsys_sem **sem;
 178 };
 179
 180 struct radv_winsys_sem_info {
 181         bool cs_emit_signal;
 182         bool cs_emit_wait;
 183         struct radv_winsys_sem_counts wait;
 184         struct radv_winsys_sem_counts signal;
 185 };
 186
 187 struct radv_winsys_bo_list {
 188         struct radeon_winsys_bo **bos;
 189         unsigned count;
 190 };
 191
 192 /* Kernel effectively allows 0-31. This sets some priorities for fixed
 193  * functionality buffers */
 194 enum {
 195         RADV_BO_PRIORITY_APPLICATION_MAX = 28,
 196
 197         /* virtual buffers have 0 priority since the priority is not used. */
 198         RADV_BO_PRIORITY_VIRTUAL = 0,
 199
 200         /* This should be considerably lower than most of the stuff below,
 201          * but how much lower is hard to say since we don't know application
 202          * assignments. Put it pretty high since it is GTT anyway. */
 203         RADV_BO_PRIORITY_QUERY_POOL = 29,
 204
 205         RADV_BO_PRIORITY_DESCRIPTOR = 30,
 206         RADV_BO_PRIORITY_UPLOAD_BUFFER = 30,
 207         RADV_BO_PRIORITY_FENCE = 30,
 208         RADV_BO_PRIORITY_SHADER = 31,
 209         RADV_BO_PRIORITY_SCRATCH = 31,
 210         RADV_BO_PRIORITY_CS = 31,
 211 };
 212
 213 struct radeon_winsys {
 214         void (*destroy)(struct radeon_winsys *ws);
 215
 216         void (*query_info)(struct radeon_winsys *ws,
 217                            struct radeon_info *info);
 218
 219         uint64_t (*query_value)(struct radeon_winsys *ws,
 220                                 enum radeon_value_id value);
 221
 222         bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 223                                unsigned num_registers, uint32_t *out);
 224
 225         const char *(*get_chip_name)(struct radeon_winsys *ws);
 226
 227         struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws,
 228                                                   uint64_t size,
 229                                                   unsigned alignment,
 230                                                   enum radeon_bo_domain domain,
 231                                                   enum radeon_bo_flag flags,
 232                                                   unsigned priority);
 233
 234         void (*buffer_destroy)(struct radeon_winsys_bo *bo);
 235         void *(*buffer_map)(struct radeon_winsys_bo *bo);
 236
 237         struct radeon_winsys_bo *(*buffer_from_ptr)(struct radeon_winsys *ws,
 238                                                     void *pointer,
 239                                                     uint64_t size,
 240                                                     unsigned priority);
 241
 242         struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws,
 243                                                    int fd,
 244                                                    unsigned priority,
 245                                                    unsigned *stride, unsigned *offset);
 246
 247         bool (*buffer_get_fd)(struct radeon_winsys *ws,
 248                               struct radeon_winsys_bo *bo,
 249                               int *fd);
 250
 251         void (*buffer_unmap)(struct radeon_winsys_bo *bo);
 252
 253         void (*buffer_set_metadata)(struct radeon_winsys_bo *bo,
 254                                     struct radeon_bo_metadata *md);
 255         void (*buffer_get_metadata)(struct radeon_winsys_bo *bo,
 256                                     struct radeon_bo_metadata *md);
 257
 258         void (*buffer_virtual_bind)(struct radeon_winsys_bo *parent,
 259                                     uint64_t offset, uint64_t size,
 260                                     struct radeon_winsys_bo *bo, uint64_t bo_offset);
 261         struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws,
 262                                                 enum radeon_ctx_priority priority);
 263         void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 264
 265         bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
 266                               enum ring_type ring_type, int ring_index);
 267
 268         struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws,
 269                                               enum ring_type ring_type);
 270
 271         void (*cs_destroy)(struct radeon_cmdbuf *cs);
 272
 273         void (*cs_reset)(struct radeon_cmdbuf *cs);
 274
 275         bool (*cs_finalize)(struct radeon_cmdbuf *cs);
 276
 277         void (*cs_grow)(struct radeon_cmdbuf * cs, size_t min_size);
 278
 279         int (*cs_submit)(struct radeon_winsys_ctx *ctx,
 280                          int queue_index,
 281                          struct radeon_cmdbuf **cs_array,
 282                          unsigned cs_count,
 283                          struct radeon_cmdbuf *initial_preamble_cs,
 284                          struct radeon_cmdbuf *continue_preamble_cs,
 285                          struct radv_winsys_sem_info *sem_info,
 286                          const struct radv_winsys_bo_list *bo_list, /* optional */
 287                          bool can_patch,
 288                          struct radeon_winsys_fence *fence);
 289
 290         void (*cs_add_buffer)(struct radeon_cmdbuf *cs,
 291                               struct radeon_winsys_bo *bo);
 292
 293         void (*cs_execute_secondary)(struct radeon_cmdbuf *parent,
 294                                     struct radeon_cmdbuf *child);
 295
 296         void (*cs_dump)(struct radeon_cmdbuf *cs, FILE* file, const int *trace_ids, int trace_id_count);
 297
 298         int (*surface_init)(struct radeon_winsys *ws,
 299                             const struct ac_surf_info *surf_info,
 300                             struct radeon_surf *surf);
 301
 302         struct radeon_winsys_fence *(*create_fence)();
 303         void (*destroy_fence)(struct radeon_winsys_fence *fence);
 304         bool (*fence_wait)(struct radeon_winsys *ws,
 305                            struct radeon_winsys_fence *fence,
 306                            bool absolute,
 307                            uint64_t timeout);
 308         bool (*fences_wait)(struct radeon_winsys *ws,
 309                             struct radeon_winsys_fence *const *fences,
 310                             uint32_t fence_count,
 311                             bool wait_all,
 312                             uint64_t timeout);
 313
 314         /* old semaphores - non shareable */
 315         struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws);
 316         void (*destroy_sem)(struct radeon_winsys_sem *sem);
 317
 318         /* new shareable sync objects */
 319         int (*create_syncobj)(struct radeon_winsys *ws, uint32_t *handle);
 320         void (*destroy_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 321
 322         void (*reset_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 323         void (*signal_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 324         bool (*wait_syncobj)(struct radeon_winsys *ws, const uint32_t *handles, uint32_t handle_count,
 325                              bool wait_all, uint64_t timeout);
 326
 327         int (*export_syncobj)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
 328         int (*import_syncobj)(struct radeon_winsys *ws, int fd, uint32_t *syncobj);
 329
 330         int (*export_syncobj_to_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
 331
 332         /* Note that this, unlike the normal import, uses an existing syncobj. */
 333         int (*import_syncobj_from_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int fd);
 334
 335 };
 336
 337 static inline void radeon_emit(struct radeon_cmdbuf *cs, uint32_t value)
 338 {
 339         cs->buf[cs->cdw++] = value;
 340 }
 341
 342 static inline void radeon_emit_array(struct radeon_cmdbuf *cs,
 343                                      const uint32_t *values, unsigned count)
 344 {
 345         memcpy(cs->buf + cs->cdw, values, count * 4);
 346         cs->cdw += count;
 347 }
 348
 349 static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo *bo)
 350 {
 351         return bo->va;
 352 }
 353
 354 static inline void radv_cs_add_buffer(struct radeon_winsys *ws,
 355                                       struct radeon_cmdbuf *cs,
 356                                       struct radeon_winsys_bo *bo)
 357 {
 358         if (bo->is_local)
 359                 return;
 360
 361         ws->cs_add_buffer(cs, bo);
 362 }
 363
 364 #endif /* RADV_RADEON_WINSYS_H */