2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40 #include <llvm-c/Support.h>
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
51 #include "util/string_buffer.h"
53 static const struct nir_shader_compiler_options nir_options
= {
54 .vertex_id_zero_based
= true,
59 .lower_device_index_to_zero
= true,
63 .lower_pack_snorm_2x16
= true,
64 .lower_pack_snorm_4x8
= true,
65 .lower_pack_unorm_2x16
= true,
66 .lower_pack_unorm_4x8
= true,
67 .lower_unpack_snorm_2x16
= true,
68 .lower_unpack_snorm_4x8
= true,
69 .lower_unpack_unorm_2x16
= true,
70 .lower_unpack_unorm_4x8
= true,
71 .lower_extract_byte
= true,
72 .lower_extract_word
= true,
75 .lower_mul_2x32_64
= true,
76 .max_unroll_iterations
= 32
79 VkResult
radv_CreateShaderModule(
81 const VkShaderModuleCreateInfo
* pCreateInfo
,
82 const VkAllocationCallbacks
* pAllocator
,
83 VkShaderModule
* pShaderModule
)
85 RADV_FROM_HANDLE(radv_device
, device
, _device
);
86 struct radv_shader_module
*module
;
88 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
89 assert(pCreateInfo
->flags
== 0);
91 module
= vk_alloc2(&device
->alloc
, pAllocator
,
92 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
93 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
95 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
98 module
->size
= pCreateInfo
->codeSize
;
99 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
101 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
103 *pShaderModule
= radv_shader_module_to_handle(module
);
108 void radv_DestroyShaderModule(
110 VkShaderModule _module
,
111 const VkAllocationCallbacks
* pAllocator
)
113 RADV_FROM_HANDLE(radv_device
, device
, _device
);
114 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
119 vk_free2(&device
->alloc
, pAllocator
, module
);
123 radv_optimize_nir(struct nir_shader
*shader
, bool optimize_conservatively
,
127 unsigned lower_flrp
=
128 (shader
->options
->lower_flrp16
? 16 : 0) |
129 (shader
->options
->lower_flrp32
? 32 : 0) |
130 (shader
->options
->lower_flrp64
? 64 : 0);
135 NIR_PASS(progress
, shader
, nir_split_array_vars
, nir_var_function_temp
);
136 NIR_PASS(progress
, shader
, nir_shrink_vec_array_vars
, nir_var_function_temp
);
138 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
139 NIR_PASS_V(shader
, nir_lower_pack
);
142 /* Only run this pass in the first call to
143 * radv_optimize_nir. Later calls assume that we've
144 * lowered away any copy_deref instructions and we
145 * don't want to introduce any more.
147 NIR_PASS(progress
, shader
, nir_opt_find_array_copies
);
150 NIR_PASS(progress
, shader
, nir_opt_copy_prop_vars
);
151 NIR_PASS(progress
, shader
, nir_opt_dead_write_vars
);
153 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
, NULL
);
154 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
156 NIR_PASS(progress
, shader
, nir_copy_prop
);
157 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
158 NIR_PASS(progress
, shader
, nir_opt_dce
);
159 if (nir_opt_trivial_continues(shader
)) {
161 NIR_PASS(progress
, shader
, nir_copy_prop
);
162 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
163 NIR_PASS(progress
, shader
, nir_opt_dce
);
165 NIR_PASS(progress
, shader
, nir_opt_if
, true);
166 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
167 NIR_PASS(progress
, shader
, nir_opt_cse
);
168 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8, true, true);
169 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
170 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
172 if (lower_flrp
!= 0) {
173 bool lower_flrp_progress
= false;
174 NIR_PASS(lower_flrp_progress
,
178 false /* always_precise */,
179 shader
->options
->lower_ffma
);
180 if (lower_flrp_progress
) {
181 NIR_PASS(progress
, shader
,
182 nir_opt_constant_folding
);
186 /* Nothing should rematerialize any flrps, so we only
187 * need to do this lowering once.
192 NIR_PASS(progress
, shader
, nir_opt_undef
);
193 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
194 if (shader
->options
->max_unroll_iterations
) {
195 NIR_PASS(progress
, shader
, nir_opt_loop_unroll
, 0);
197 } while (progress
&& !optimize_conservatively
);
199 NIR_PASS(progress
, shader
, nir_opt_shrink_load
);
200 NIR_PASS(progress
, shader
, nir_opt_move_load_ubo
);
204 radv_shader_compile_to_nir(struct radv_device
*device
,
205 struct radv_shader_module
*module
,
206 const char *entrypoint_name
,
207 gl_shader_stage stage
,
208 const VkSpecializationInfo
*spec_info
,
209 const VkPipelineCreateFlags flags
,
210 const struct radv_pipeline_layout
*layout
)
214 /* Some things such as our meta clear/blit code will give us a NIR
215 * shader directly. In that case, we just ignore the SPIR-V entirely
216 * and just use the NIR shader */
218 nir
->options
= &nir_options
;
219 nir_validate_shader(nir
, "in internal shader");
221 assert(exec_list_length(&nir
->functions
) == 1);
223 uint32_t *spirv
= (uint32_t *) module
->data
;
224 assert(module
->size
% 4 == 0);
226 if (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SPIRV
)
227 radv_print_spirv(spirv
, module
->size
, stderr
);
229 uint32_t num_spec_entries
= 0;
230 struct nir_spirv_specialization
*spec_entries
= NULL
;
231 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
232 num_spec_entries
= spec_info
->mapEntryCount
;
233 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
234 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
235 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
236 const void *data
= spec_info
->pData
+ entry
.offset
;
237 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
239 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
240 if (spec_info
->dataSize
== 8)
241 spec_entries
[i
].data64
= *(const uint64_t *)data
;
243 spec_entries
[i
].data32
= *(const uint32_t *)data
;
246 const struct spirv_to_nir_options spirv_options
= {
247 .lower_ubo_ssbo_access_to_offsets
= true,
249 .derivative_group
= true,
250 .descriptor_array_dynamic_indexing
= true,
251 .descriptor_array_non_uniform_indexing
= true,
252 .descriptor_indexing
= true,
253 .device_group
= true,
254 .draw_parameters
= true,
258 .geometry_streams
= true,
259 .image_read_without_format
= true,
260 .image_write_without_format
= true,
264 .int64_atomics
= true,
266 .physical_storage_buffer_address
= true,
267 .runtime_descriptor_array
= true,
268 .shader_viewport_index_layer
= true,
269 .stencil_export
= true,
270 .storage_8bit
= true,
271 .storage_16bit
= true,
272 .storage_image_ms
= true,
273 .subgroup_arithmetic
= true,
274 .subgroup_ballot
= true,
275 .subgroup_basic
= true,
276 .subgroup_quad
= true,
277 .subgroup_shuffle
= true,
278 .subgroup_vote
= true,
279 .tessellation
= true,
280 .transform_feedback
= true,
281 .trinary_minmax
= true,
282 .variable_pointers
= true,
284 .ubo_addr_format
= nir_address_format_32bit_index_offset
,
285 .ssbo_addr_format
= nir_address_format_32bit_index_offset
,
286 .phys_ssbo_addr_format
= nir_address_format_64bit_global
,
287 .push_const_addr_format
= nir_address_format_logical
,
288 .shared_addr_format
= nir_address_format_32bit_offset
,
290 nir_function
*entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
291 spec_entries
, num_spec_entries
,
292 stage
, entrypoint_name
,
293 &spirv_options
, &nir_options
);
294 nir
= entry_point
->shader
;
295 assert(nir
->info
.stage
== stage
);
296 nir_validate_shader(nir
, "after spirv_to_nir");
300 /* We have to lower away local constant initializers right before we
301 * inline functions. That way they get properly initialized at the top
302 * of the function and not at the top of its caller.
304 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_function_temp
);
305 NIR_PASS_V(nir
, nir_lower_returns
);
306 NIR_PASS_V(nir
, nir_inline_functions
);
307 NIR_PASS_V(nir
, nir_opt_deref
);
309 /* Pick off the single entrypoint that we want */
310 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
311 if (func
->is_entrypoint
)
312 func
->name
= ralloc_strdup(func
, "main");
314 exec_node_remove(&func
->node
);
316 assert(exec_list_length(&nir
->functions
) == 1);
318 /* Make sure we lower constant initializers on output variables so that
319 * nir_remove_dead_variables below sees the corresponding stores
321 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_shader_out
);
323 /* Now that we've deleted all but the main function, we can go ahead and
324 * lower the rest of the constant initializers.
326 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
328 /* Split member structs. We do this before lower_io_to_temporaries so that
329 * it doesn't lower system values to temporaries by accident.
331 NIR_PASS_V(nir
, nir_split_var_copies
);
332 NIR_PASS_V(nir
, nir_split_per_member_structs
);
334 NIR_PASS_V(nir
, nir_remove_dead_variables
,
335 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
337 NIR_PASS_V(nir
, nir_lower_system_values
);
338 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
339 NIR_PASS_V(nir
, radv_nir_lower_ycbcr_textures
, layout
);
342 /* Vulkan uses the separate-shader linking model */
343 nir
->info
.separate_shader
= true;
345 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
347 static const nir_lower_tex_options tex_options
= {
349 .lower_tg4_offsets
= true,
352 nir_lower_tex(nir
, &tex_options
);
354 nir_lower_vars_to_ssa(nir
);
356 if (nir
->info
.stage
== MESA_SHADER_VERTEX
||
357 nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
358 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
359 nir_shader_get_entrypoint(nir
), true, true);
360 } else if (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
||
361 nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
362 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
363 nir_shader_get_entrypoint(nir
), true, false);
366 nir_split_var_copies(nir
);
368 nir_lower_global_vars_to_local(nir
);
369 nir_remove_dead_variables(nir
, nir_var_function_temp
);
370 nir_lower_subgroups(nir
, &(struct nir_lower_subgroups_options
) {
372 .ballot_bit_size
= 64,
373 .lower_to_scalar
= 1,
374 .lower_subgroup_masks
= 1,
376 .lower_shuffle_to_32bit
= 1,
377 .lower_vote_eq_to_ballot
= 1,
380 nir_lower_load_const_to_scalar(nir
);
382 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
383 radv_optimize_nir(nir
, false, true);
385 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
386 * to remove any copies introduced by nir_opt_find_array_copies().
388 nir_lower_var_copies(nir
);
390 /* Indirect lowering must be called after the radv_optimize_nir() loop
391 * has been called at least once. Otherwise indirect lowering can
392 * bloat the instruction count of the loop and cause it to be
393 * considered too large for unrolling.
395 ac_lower_indirect_derefs(nir
, device
->physical_device
->rad_info
.chip_class
);
396 radv_optimize_nir(nir
, flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
, false);
402 radv_alloc_shader_memory(struct radv_device
*device
,
403 struct radv_shader_variant
*shader
)
405 mtx_lock(&device
->shader_slab_mutex
);
406 list_for_each_entry(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
408 list_for_each_entry(struct radv_shader_variant
, s
, &slab
->shaders
, slab_list
) {
409 if (s
->bo_offset
- offset
>= shader
->code_size
) {
410 shader
->bo
= slab
->bo
;
411 shader
->bo_offset
= offset
;
412 list_addtail(&shader
->slab_list
, &s
->slab_list
);
413 mtx_unlock(&device
->shader_slab_mutex
);
414 return slab
->ptr
+ offset
;
416 offset
= align_u64(s
->bo_offset
+ s
->code_size
, 256);
418 if (slab
->size
- offset
>= shader
->code_size
) {
419 shader
->bo
= slab
->bo
;
420 shader
->bo_offset
= offset
;
421 list_addtail(&shader
->slab_list
, &slab
->shaders
);
422 mtx_unlock(&device
->shader_slab_mutex
);
423 return slab
->ptr
+ offset
;
427 mtx_unlock(&device
->shader_slab_mutex
);
428 struct radv_shader_slab
*slab
= calloc(1, sizeof(struct radv_shader_slab
));
430 slab
->size
= 256 * 1024;
431 slab
->bo
= device
->ws
->buffer_create(device
->ws
, slab
->size
, 256,
433 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
434 (device
->physical_device
->cpdma_prefetch_writes_memory
?
435 0 : RADEON_FLAG_READ_ONLY
),
436 RADV_BO_PRIORITY_SHADER
);
437 slab
->ptr
= (char*)device
->ws
->buffer_map(slab
->bo
);
438 list_inithead(&slab
->shaders
);
440 mtx_lock(&device
->shader_slab_mutex
);
441 list_add(&slab
->slabs
, &device
->shader_slabs
);
443 shader
->bo
= slab
->bo
;
444 shader
->bo_offset
= 0;
445 list_add(&shader
->slab_list
, &slab
->shaders
);
446 mtx_unlock(&device
->shader_slab_mutex
);
451 radv_destroy_shader_slabs(struct radv_device
*device
)
453 list_for_each_entry_safe(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
454 device
->ws
->buffer_destroy(slab
->bo
);
457 mtx_destroy(&device
->shader_slab_mutex
);
460 /* For the UMR disassembler. */
461 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
462 #define DEBUGGER_NUM_MARKERS 5
465 radv_get_shader_binary_size(struct ac_shader_binary
*binary
)
467 return binary
->code_size
+ DEBUGGER_NUM_MARKERS
* 4;
471 radv_fill_shader_variant(struct radv_device
*device
,
472 struct radv_shader_variant
*variant
,
473 struct ac_shader_binary
*binary
,
474 gl_shader_stage stage
)
476 bool scratch_enabled
= variant
->config
.scratch_bytes_per_wave
> 0;
477 struct radv_shader_info
*info
= &variant
->info
.info
;
478 unsigned vgpr_comp_cnt
= 0;
480 variant
->code_size
= radv_get_shader_binary_size(binary
);
481 variant
->rsrc2
= S_00B12C_USER_SGPR(variant
->info
.num_user_sgprs
) |
482 S_00B12C_USER_SGPR_MSB(variant
->info
.num_user_sgprs
>> 5) |
483 S_00B12C_SCRATCH_EN(scratch_enabled
) |
484 S_00B12C_SO_BASE0_EN(!!info
->so
.strides
[0]) |
485 S_00B12C_SO_BASE1_EN(!!info
->so
.strides
[1]) |
486 S_00B12C_SO_BASE2_EN(!!info
->so
.strides
[2]) |
487 S_00B12C_SO_BASE3_EN(!!info
->so
.strides
[3]) |
488 S_00B12C_SO_EN(!!info
->so
.num_outputs
);
490 variant
->rsrc1
= S_00B848_VGPRS((variant
->config
.num_vgprs
- 1) / 4) |
491 S_00B848_SGPRS((variant
->config
.num_sgprs
- 1) / 8) |
492 S_00B848_DX10_CLAMP(1) |
493 S_00B848_FLOAT_MODE(variant
->config
.float_mode
);
496 case MESA_SHADER_TESS_EVAL
:
498 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
500 case MESA_SHADER_TESS_CTRL
:
501 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
502 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
504 variant
->rsrc2
|= S_00B12C_OC_LDS_EN(1);
507 case MESA_SHADER_VERTEX
:
508 case MESA_SHADER_GEOMETRY
:
509 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
511 case MESA_SHADER_FRAGMENT
:
513 case MESA_SHADER_COMPUTE
:
515 S_00B84C_TGID_X_EN(info
->cs
.uses_block_id
[0]) |
516 S_00B84C_TGID_Y_EN(info
->cs
.uses_block_id
[1]) |
517 S_00B84C_TGID_Z_EN(info
->cs
.uses_block_id
[2]) |
518 S_00B84C_TIDIG_COMP_CNT(info
->cs
.uses_thread_id
[2] ? 2 :
519 info
->cs
.uses_thread_id
[1] ? 1 : 0) |
520 S_00B84C_TG_SIZE_EN(info
->cs
.uses_local_invocation_idx
) |
521 S_00B84C_LDS_SIZE(variant
->config
.lds_size
);
524 unreachable("unsupported shader type");
528 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
529 stage
== MESA_SHADER_GEOMETRY
) {
530 unsigned es_type
= variant
->info
.gs
.es_type
;
531 unsigned gs_vgpr_comp_cnt
, es_vgpr_comp_cnt
;
533 if (es_type
== MESA_SHADER_VERTEX
) {
534 es_vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
535 } else if (es_type
== MESA_SHADER_TESS_EVAL
) {
536 es_vgpr_comp_cnt
= 3;
538 unreachable("invalid shader ES type");
541 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
542 * VGPR[0:4] are always loaded.
544 if (info
->uses_invocation_id
) {
545 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
546 } else if (info
->uses_prim_id
) {
547 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
548 } else if (variant
->info
.gs
.vertices_in
>= 3) {
549 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
551 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
554 variant
->rsrc1
|= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
555 variant
->rsrc2
|= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
556 S_00B22C_OC_LDS_EN(es_type
== MESA_SHADER_TESS_EVAL
);
557 } else if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
558 stage
== MESA_SHADER_TESS_CTRL
) {
559 variant
->rsrc1
|= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt
);
561 variant
->rsrc1
|= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
);
564 void *ptr
= radv_alloc_shader_memory(device
, variant
);
565 memcpy(ptr
, binary
->code
, binary
->code_size
);
567 /* Add end-of-code markers for the UMR disassembler. */
568 uint32_t *ptr32
= (uint32_t *)ptr
+ binary
->code_size
/ 4;
569 for (unsigned i
= 0; i
< DEBUGGER_NUM_MARKERS
; i
++)
570 ptr32
[i
] = DEBUGGER_END_OF_CODE_MARKER
;
574 static void radv_init_llvm_target()
576 LLVMInitializeAMDGPUTargetInfo();
577 LLVMInitializeAMDGPUTarget();
578 LLVMInitializeAMDGPUTargetMC();
579 LLVMInitializeAMDGPUAsmPrinter();
581 /* For inline assembly. */
582 LLVMInitializeAMDGPUAsmParser();
584 /* Workaround for bug in llvm 4.0 that causes image intrinsics
586 * https://reviews.llvm.org/D26348
588 * Workaround for bug in llvm that causes the GPU to hang in presence
589 * of nested loops because there is an exec mask issue. The proper
590 * solution is to fix LLVM but this might require a bunch of work.
591 * https://bugs.llvm.org/show_bug.cgi?id=37744
593 * "mesa" is the prefix for error messages.
595 if (HAVE_LLVM
>= 0x0800) {
596 const char *argv
[2] = { "mesa", "-simplifycfg-sink-common=false" };
597 LLVMParseCommandLineOptions(2, argv
, NULL
);
600 const char *argv
[3] = { "mesa", "-simplifycfg-sink-common=false",
601 "-amdgpu-skip-threshold=1" };
602 LLVMParseCommandLineOptions(3, argv
, NULL
);
606 static once_flag radv_init_llvm_target_once_flag
= ONCE_FLAG_INIT
;
608 static void radv_init_llvm_once(void)
610 call_once(&radv_init_llvm_target_once_flag
, radv_init_llvm_target
);
613 static struct radv_shader_variant
*
614 shader_variant_create(struct radv_device
*device
,
615 struct radv_shader_module
*module
,
616 struct nir_shader
* const *shaders
,
618 gl_shader_stage stage
,
619 struct radv_nir_compiler_options
*options
,
622 unsigned *code_size_out
)
624 enum radeon_family chip_family
= device
->physical_device
->rad_info
.family
;
625 enum ac_target_machine_options tm_options
= 0;
626 struct radv_shader_variant
*variant
;
627 struct ac_shader_binary binary
;
628 struct ac_llvm_compiler ac_llvm
;
629 bool thread_compiler
;
630 variant
= calloc(1, sizeof(struct radv_shader_variant
));
634 options
->family
= chip_family
;
635 options
->chip_class
= device
->physical_device
->rad_info
.chip_class
;
636 options
->dump_shader
= radv_can_dump_shader(device
, module
, gs_copy_shader
);
637 options
->dump_preoptir
= options
->dump_shader
&&
638 device
->instance
->debug_flags
& RADV_DEBUG_PREOPTIR
;
639 options
->record_llvm_ir
= device
->keep_shader_info
;
640 options
->check_ir
= device
->instance
->debug_flags
& RADV_DEBUG_CHECKIR
;
641 options
->tess_offchip_block_dw_size
= device
->tess_offchip_block_dw_size
;
642 options
->address32_hi
= device
->physical_device
->rad_info
.address32_hi
;
644 if (options
->supports_spill
)
645 tm_options
|= AC_TM_SUPPORTS_SPILL
;
646 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
647 tm_options
|= AC_TM_SISCHED
;
648 if (options
->check_ir
)
649 tm_options
|= AC_TM_CHECK_IR
;
650 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_LOAD_STORE_OPT
)
651 tm_options
|= AC_TM_NO_LOAD_STORE_OPT
;
653 thread_compiler
= !(device
->instance
->debug_flags
& RADV_DEBUG_NOTHREADLLVM
);
654 radv_init_llvm_once();
655 radv_init_llvm_compiler(&ac_llvm
,
657 chip_family
, tm_options
);
658 if (gs_copy_shader
) {
659 assert(shader_count
== 1);
660 radv_compile_gs_copy_shader(&ac_llvm
, *shaders
, &binary
,
661 &variant
->config
, &variant
->info
,
664 radv_compile_nir_shader(&ac_llvm
, &binary
, &variant
->config
,
665 &variant
->info
, shaders
, shader_count
,
669 radv_destroy_llvm_compiler(&ac_llvm
, thread_compiler
);
671 radv_fill_shader_variant(device
, variant
, &binary
, stage
);
674 *code_out
= binary
.code
;
675 *code_size_out
= binary
.code_size
;
680 free(binary
.global_symbol_offsets
);
682 variant
->ref_count
= 1;
684 if (device
->keep_shader_info
) {
685 variant
->disasm_string
= binary
.disasm_string
;
686 variant
->llvm_ir_string
= binary
.llvm_ir_string
;
687 if (!gs_copy_shader
&& !module
->nir
) {
688 variant
->nir
= *shaders
;
689 variant
->spirv
= (uint32_t *)module
->data
;
690 variant
->spirv_size
= module
->size
;
693 free(binary
.disasm_string
);
699 struct radv_shader_variant
*
700 radv_shader_variant_create(struct radv_device
*device
,
701 struct radv_shader_module
*module
,
702 struct nir_shader
*const *shaders
,
704 struct radv_pipeline_layout
*layout
,
705 const struct radv_shader_variant_key
*key
,
707 unsigned *code_size_out
)
709 struct radv_nir_compiler_options options
= {0};
711 options
.layout
= layout
;
715 options
.unsafe_math
= !!(device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
);
716 options
.supports_spill
= true;
718 return shader_variant_create(device
, module
, shaders
, shader_count
, shaders
[shader_count
- 1]->info
.stage
,
719 &options
, false, code_out
, code_size_out
);
722 struct radv_shader_variant
*
723 radv_create_gs_copy_shader(struct radv_device
*device
,
724 struct nir_shader
*shader
,
726 unsigned *code_size_out
,
729 struct radv_nir_compiler_options options
= {0};
731 options
.key
.has_multiview_view_index
= multiview
;
733 return shader_variant_create(device
, NULL
, &shader
, 1, MESA_SHADER_VERTEX
,
734 &options
, true, code_out
, code_size_out
);
738 radv_shader_variant_destroy(struct radv_device
*device
,
739 struct radv_shader_variant
*variant
)
741 if (!p_atomic_dec_zero(&variant
->ref_count
))
744 mtx_lock(&device
->shader_slab_mutex
);
745 list_del(&variant
->slab_list
);
746 mtx_unlock(&device
->shader_slab_mutex
);
748 ralloc_free(variant
->nir
);
749 free(variant
->disasm_string
);
750 free(variant
->llvm_ir_string
);
755 radv_get_shader_name(struct radv_shader_variant
*var
, gl_shader_stage stage
)
758 case MESA_SHADER_VERTEX
: return var
->info
.vs
.as_ls
? "Vertex Shader as LS" : var
->info
.vs
.as_es
? "Vertex Shader as ES" : "Vertex Shader as VS";
759 case MESA_SHADER_GEOMETRY
: return "Geometry Shader";
760 case MESA_SHADER_FRAGMENT
: return "Pixel Shader";
761 case MESA_SHADER_COMPUTE
: return "Compute Shader";
762 case MESA_SHADER_TESS_CTRL
: return "Tessellation Control Shader";
763 case MESA_SHADER_TESS_EVAL
: return var
->info
.tes
.as_es
? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
765 return "Unknown shader";
770 generate_shader_stats(struct radv_device
*device
,
771 struct radv_shader_variant
*variant
,
772 gl_shader_stage stage
,
773 struct _mesa_string_buffer
*buf
)
775 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
776 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
777 struct ac_shader_config
*conf
;
778 unsigned max_simd_waves
;
779 unsigned lds_per_wave
= 0;
781 max_simd_waves
= ac_get_max_simd_waves(device
->physical_device
->rad_info
.family
);
783 conf
= &variant
->config
;
785 if (stage
== MESA_SHADER_FRAGMENT
) {
786 lds_per_wave
= conf
->lds_size
* lds_increment
+
787 align(variant
->info
.fs
.num_interp
* 48,
789 } else if (stage
== MESA_SHADER_COMPUTE
) {
790 unsigned max_workgroup_size
=
791 radv_nir_get_max_workgroup_size(chip_class
, variant
->nir
);
792 lds_per_wave
= (conf
->lds_size
* lds_increment
) /
793 DIV_ROUND_UP(max_workgroup_size
, 64);
799 ac_get_num_physical_sgprs(chip_class
) / conf
->num_sgprs
);
804 RADV_NUM_PHYSICAL_VGPRS
/ conf
->num_vgprs
);
806 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
810 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
812 if (stage
== MESA_SHADER_FRAGMENT
) {
813 _mesa_string_buffer_printf(buf
, "*** SHADER CONFIG ***\n"
814 "SPI_PS_INPUT_ADDR = 0x%04x\n"
815 "SPI_PS_INPUT_ENA = 0x%04x\n",
816 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
819 _mesa_string_buffer_printf(buf
, "*** SHADER STATS ***\n"
822 "Spilled SGPRs: %d\n"
823 "Spilled VGPRs: %d\n"
824 "PrivMem VGPRS: %d\n"
825 "Code Size: %d bytes\n"
827 "Scratch: %d bytes per wave\n"
829 "********************\n\n\n",
830 conf
->num_sgprs
, conf
->num_vgprs
,
831 conf
->spilled_sgprs
, conf
->spilled_vgprs
,
832 variant
->info
.private_mem_vgprs
, variant
->code_size
,
833 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
838 radv_shader_dump_stats(struct radv_device
*device
,
839 struct radv_shader_variant
*variant
,
840 gl_shader_stage stage
,
843 struct _mesa_string_buffer
*buf
= _mesa_string_buffer_create(NULL
, 256);
845 generate_shader_stats(device
, variant
, stage
, buf
);
847 fprintf(file
, "\n%s:\n", radv_get_shader_name(variant
, stage
));
848 fprintf(file
, "%s", buf
->buf
);
850 _mesa_string_buffer_destroy(buf
);
854 radv_GetShaderInfoAMD(VkDevice _device
,
855 VkPipeline _pipeline
,
856 VkShaderStageFlagBits shaderStage
,
857 VkShaderInfoTypeAMD infoType
,
861 RADV_FROM_HANDLE(radv_device
, device
, _device
);
862 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
863 gl_shader_stage stage
= vk_to_mesa_shader_stage(shaderStage
);
864 struct radv_shader_variant
*variant
= pipeline
->shaders
[stage
];
865 struct _mesa_string_buffer
*buf
;
866 VkResult result
= VK_SUCCESS
;
868 /* Spec doesn't indicate what to do if the stage is invalid, so just
869 * return no info for this. */
871 return vk_error(device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
874 case VK_SHADER_INFO_TYPE_STATISTICS_AMD
:
876 *pInfoSize
= sizeof(VkShaderStatisticsInfoAMD
);
878 unsigned lds_multiplier
= device
->physical_device
->rad_info
.chip_class
>= GFX7
? 512 : 256;
879 struct ac_shader_config
*conf
= &variant
->config
;
881 VkShaderStatisticsInfoAMD statistics
= {};
882 statistics
.shaderStageMask
= shaderStage
;
883 statistics
.numPhysicalVgprs
= RADV_NUM_PHYSICAL_VGPRS
;
884 statistics
.numPhysicalSgprs
= ac_get_num_physical_sgprs(device
->physical_device
->rad_info
.chip_class
);
885 statistics
.numAvailableSgprs
= statistics
.numPhysicalSgprs
;
887 if (stage
== MESA_SHADER_COMPUTE
) {
888 unsigned *local_size
= variant
->nir
->info
.cs
.local_size
;
889 unsigned workgroup_size
= local_size
[0] * local_size
[1] * local_size
[2];
891 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
/
892 ceil((double)workgroup_size
/ statistics
.numPhysicalVgprs
);
894 statistics
.computeWorkGroupSize
[0] = local_size
[0];
895 statistics
.computeWorkGroupSize
[1] = local_size
[1];
896 statistics
.computeWorkGroupSize
[2] = local_size
[2];
898 statistics
.numAvailableVgprs
= statistics
.numPhysicalVgprs
;
901 statistics
.resourceUsage
.numUsedVgprs
= conf
->num_vgprs
;
902 statistics
.resourceUsage
.numUsedSgprs
= conf
->num_sgprs
;
903 statistics
.resourceUsage
.ldsSizePerLocalWorkGroup
= 32768;
904 statistics
.resourceUsage
.ldsUsageSizeInBytes
= conf
->lds_size
* lds_multiplier
;
905 statistics
.resourceUsage
.scratchMemUsageInBytes
= conf
->scratch_bytes_per_wave
;
907 size_t size
= *pInfoSize
;
908 *pInfoSize
= sizeof(statistics
);
910 memcpy(pInfo
, &statistics
, MIN2(size
, *pInfoSize
));
912 if (size
< *pInfoSize
)
913 result
= VK_INCOMPLETE
;
917 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD
:
918 buf
= _mesa_string_buffer_create(NULL
, 1024);
920 _mesa_string_buffer_printf(buf
, "%s:\n", radv_get_shader_name(variant
, stage
));
921 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->llvm_ir_string
);
922 _mesa_string_buffer_printf(buf
, "%s\n\n", variant
->disasm_string
);
923 generate_shader_stats(device
, variant
, stage
, buf
);
925 /* Need to include the null terminator. */
926 size_t length
= buf
->length
+ 1;
931 size_t size
= *pInfoSize
;
934 memcpy(pInfo
, buf
->buf
, MIN2(size
, length
));
937 result
= VK_INCOMPLETE
;
940 _mesa_string_buffer_destroy(buf
);
943 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
944 result
= VK_ERROR_FEATURE_NOT_PRESENT
;