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2fc7060d6c2e811ff645bee324871366b10cefa4
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "nir/nir.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
36
37 #include <llvm-c/Core.h>
38 #include <llvm-c/TargetMachine.h>
39
40 #include "sid.h"
41 #include "gfx9d.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48
49 #include "util/string_buffer.h"
50
51 static const struct nir_shader_compiler_options nir_options = {
52 .vertex_id_zero_based = true,
53 .lower_scmp = true,
54 .lower_flrp32 = true,
55 .lower_flrp64 = true,
56 .lower_device_index_to_zero = true,
57 .lower_fsat = true,
58 .lower_fdiv = true,
59 .lower_sub = true,
60 .lower_pack_snorm_2x16 = true,
61 .lower_pack_snorm_4x8 = true,
62 .lower_pack_unorm_2x16 = true,
63 .lower_pack_unorm_4x8 = true,
64 .lower_unpack_snorm_2x16 = true,
65 .lower_unpack_snorm_4x8 = true,
66 .lower_unpack_unorm_2x16 = true,
67 .lower_unpack_unorm_4x8 = true,
68 .lower_extract_byte = true,
69 .lower_extract_word = true,
70 .lower_ffma = true,
71 .lower_fpow = true,
72 .vs_inputs_dual_locations = true,
73 .max_unroll_iterations = 32
74 };
75
76 VkResult radv_CreateShaderModule(
77 VkDevice _device,
78 const VkShaderModuleCreateInfo* pCreateInfo,
79 const VkAllocationCallbacks* pAllocator,
80 VkShaderModule* pShaderModule)
81 {
82 RADV_FROM_HANDLE(radv_device, device, _device);
83 struct radv_shader_module *module;
84
85 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
86 assert(pCreateInfo->flags == 0);
87
88 module = vk_alloc2(&device->alloc, pAllocator,
89 sizeof(*module) + pCreateInfo->codeSize, 8,
90 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
91 if (module == NULL)
92 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
93
94 module->nir = NULL;
95 module->size = pCreateInfo->codeSize;
96 memcpy(module->data, pCreateInfo->pCode, module->size);
97
98 _mesa_sha1_compute(module->data, module->size, module->sha1);
99
100 *pShaderModule = radv_shader_module_to_handle(module);
101
102 return VK_SUCCESS;
103 }
104
105 void radv_DestroyShaderModule(
106 VkDevice _device,
107 VkShaderModule _module,
108 const VkAllocationCallbacks* pAllocator)
109 {
110 RADV_FROM_HANDLE(radv_device, device, _device);
111 RADV_FROM_HANDLE(radv_shader_module, module, _module);
112
113 if (!module)
114 return;
115
116 vk_free2(&device->alloc, pAllocator, module);
117 }
118
119 void
120 radv_optimize_nir(struct nir_shader *shader)
121 {
122 bool progress;
123
124 do {
125 progress = false;
126
127 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
128 NIR_PASS_V(shader, nir_lower_64bit_pack);
129 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
130 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
131
132 NIR_PASS(progress, shader, nir_copy_prop);
133 NIR_PASS(progress, shader, nir_opt_remove_phis);
134 NIR_PASS(progress, shader, nir_opt_dce);
135 if (nir_opt_trivial_continues(shader)) {
136 progress = true;
137 NIR_PASS(progress, shader, nir_copy_prop);
138 NIR_PASS(progress, shader, nir_opt_remove_phis);
139 NIR_PASS(progress, shader, nir_opt_dce);
140 }
141 NIR_PASS(progress, shader, nir_opt_if);
142 NIR_PASS(progress, shader, nir_opt_dead_cf);
143 NIR_PASS(progress, shader, nir_opt_cse);
144 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
145 NIR_PASS(progress, shader, nir_opt_algebraic);
146 NIR_PASS(progress, shader, nir_opt_constant_folding);
147 NIR_PASS(progress, shader, nir_opt_undef);
148 NIR_PASS(progress, shader, nir_opt_conditional_discard);
149 if (shader->options->max_unroll_iterations) {
150 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
151 }
152 } while (progress);
153
154 NIR_PASS(progress, shader, nir_opt_shrink_load);
155 }
156
157 nir_shader *
158 radv_shader_compile_to_nir(struct radv_device *device,
159 struct radv_shader_module *module,
160 const char *entrypoint_name,
161 gl_shader_stage stage,
162 const VkSpecializationInfo *spec_info)
163 {
164 if (strcmp(entrypoint_name, "main") != 0) {
165 radv_finishme("Multiple shaders per module not really supported");
166 }
167
168 nir_shader *nir;
169 nir_function *entry_point;
170 if (module->nir) {
171 /* Some things such as our meta clear/blit code will give us a NIR
172 * shader directly. In that case, we just ignore the SPIR-V entirely
173 * and just use the NIR shader */
174 nir = module->nir;
175 nir->options = &nir_options;
176 nir_validate_shader(nir);
177
178 assert(exec_list_length(&nir->functions) == 1);
179 struct exec_node *node = exec_list_get_head(&nir->functions);
180 entry_point = exec_node_data(nir_function, node, node);
181 } else {
182 uint32_t *spirv = (uint32_t *) module->data;
183 assert(module->size % 4 == 0);
184
185 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
186 radv_print_spirv(spirv, module->size, stderr);
187
188 uint32_t num_spec_entries = 0;
189 struct nir_spirv_specialization *spec_entries = NULL;
190 if (spec_info && spec_info->mapEntryCount > 0) {
191 num_spec_entries = spec_info->mapEntryCount;
192 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
193 for (uint32_t i = 0; i < num_spec_entries; i++) {
194 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
195 const void *data = spec_info->pData + entry.offset;
196 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
197
198 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
199 if (spec_info->dataSize == 8)
200 spec_entries[i].data64 = *(const uint64_t *)data;
201 else
202 spec_entries[i].data32 = *(const uint32_t *)data;
203 }
204 }
205 const struct spirv_to_nir_options spirv_options = {
206 .caps = {
207 .device_group = true,
208 .draw_parameters = true,
209 .float64 = true,
210 .image_read_without_format = true,
211 .image_write_without_format = true,
212 .tessellation = true,
213 .int64 = true,
214 .multiview = true,
215 .subgroup_basic = true,
216 .variable_pointers = true,
217 .gcn_shader = true,
218 },
219 };
220 entry_point = spirv_to_nir(spirv, module->size / 4,
221 spec_entries, num_spec_entries,
222 stage, entrypoint_name,
223 &spirv_options, &nir_options);
224 nir = entry_point->shader;
225 assert(nir->info.stage == stage);
226 nir_validate_shader(nir);
227
228 free(spec_entries);
229
230 /* We have to lower away local constant initializers right before we
231 * inline functions. That way they get properly initialized at the top
232 * of the function and not at the top of its caller.
233 */
234 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
235 NIR_PASS_V(nir, nir_lower_returns);
236 NIR_PASS_V(nir, nir_inline_functions);
237
238 /* Pick off the single entrypoint that we want */
239 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
240 if (func != entry_point)
241 exec_node_remove(&func->node);
242 }
243 assert(exec_list_length(&nir->functions) == 1);
244 entry_point->name = ralloc_strdup(entry_point, "main");
245
246 NIR_PASS_V(nir, nir_remove_dead_variables,
247 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
248
249 /* Now that we've deleted all but the main function, we can go ahead and
250 * lower the rest of the constant initializers.
251 */
252 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
253 NIR_PASS_V(nir, nir_lower_system_values);
254 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
255 }
256
257 /* Vulkan uses the separate-shader linking model */
258 nir->info.separate_shader = true;
259
260 nir_shader_gather_info(nir, entry_point->impl);
261
262 static const nir_lower_tex_options tex_options = {
263 .lower_txp = ~0,
264 };
265
266 nir_lower_tex(nir, &tex_options);
267
268 nir_lower_vars_to_ssa(nir);
269 nir_lower_var_copies(nir);
270 nir_lower_global_vars_to_local(nir);
271 nir_remove_dead_variables(nir, nir_var_local);
272 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
273 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
274 .subgroup_size = 64,
275 .ballot_bit_size = 64,
276 .lower_to_scalar = 1,
277 .lower_subgroup_masks = 1,
278 .lower_shuffle = 1,
279 .lower_quad = 1,
280 });
281
282 radv_optimize_nir(nir);
283
284 return nir;
285 }
286
287 void *
288 radv_alloc_shader_memory(struct radv_device *device,
289 struct radv_shader_variant *shader)
290 {
291 mtx_lock(&device->shader_slab_mutex);
292 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
293 uint64_t offset = 0;
294 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
295 if (s->bo_offset - offset >= shader->code_size) {
296 shader->bo = slab->bo;
297 shader->bo_offset = offset;
298 list_addtail(&shader->slab_list, &s->slab_list);
299 mtx_unlock(&device->shader_slab_mutex);
300 return slab->ptr + offset;
301 }
302 offset = align_u64(s->bo_offset + s->code_size, 256);
303 }
304 if (slab->size - offset >= shader->code_size) {
305 shader->bo = slab->bo;
306 shader->bo_offset = offset;
307 list_addtail(&shader->slab_list, &slab->shaders);
308 mtx_unlock(&device->shader_slab_mutex);
309 return slab->ptr + offset;
310 }
311 }
312
313 mtx_unlock(&device->shader_slab_mutex);
314 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
315
316 slab->size = 256 * 1024;
317 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
318 RADEON_DOMAIN_VRAM,
319 RADEON_FLAG_NO_INTERPROCESS_SHARING |
320 device->physical_device->cpdma_prefetch_writes_memory ?
321 0 : RADEON_FLAG_READ_ONLY);
322 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
323 list_inithead(&slab->shaders);
324
325 mtx_lock(&device->shader_slab_mutex);
326 list_add(&slab->slabs, &device->shader_slabs);
327
328 shader->bo = slab->bo;
329 shader->bo_offset = 0;
330 list_add(&shader->slab_list, &slab->shaders);
331 mtx_unlock(&device->shader_slab_mutex);
332 return slab->ptr;
333 }
334
335 void
336 radv_destroy_shader_slabs(struct radv_device *device)
337 {
338 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
339 device->ws->buffer_destroy(slab->bo);
340 free(slab);
341 }
342 mtx_destroy(&device->shader_slab_mutex);
343 }
344
345 static void
346 radv_fill_shader_variant(struct radv_device *device,
347 struct radv_shader_variant *variant,
348 struct ac_shader_binary *binary,
349 gl_shader_stage stage)
350 {
351 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
352 unsigned vgpr_comp_cnt = 0;
353
354 if (scratch_enabled && !device->llvm_supports_spill)
355 radv_finishme("shader scratch support only available with LLVM 4.0");
356
357 variant->code_size = binary->code_size;
358 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
359 S_00B12C_SCRATCH_EN(scratch_enabled);
360
361 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
362 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
363 S_00B848_DX10_CLAMP(1) |
364 S_00B848_FLOAT_MODE(variant->config.float_mode);
365
366 switch (stage) {
367 case MESA_SHADER_TESS_EVAL:
368 vgpr_comp_cnt = 3;
369 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
370 break;
371 case MESA_SHADER_TESS_CTRL:
372 if (device->physical_device->rad_info.chip_class >= GFX9)
373 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
374 else
375 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
376 break;
377 case MESA_SHADER_VERTEX:
378 case MESA_SHADER_GEOMETRY:
379 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
380 break;
381 case MESA_SHADER_FRAGMENT:
382 break;
383 case MESA_SHADER_COMPUTE: {
384 struct radv_shader_info *info = &variant->info.info;
385 variant->rsrc2 |=
386 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
387 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
388 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
389 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
390 info->cs.uses_thread_id[1] ? 1 : 0) |
391 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
392 S_00B84C_LDS_SIZE(variant->config.lds_size);
393 break;
394 }
395 default:
396 unreachable("unsupported shader type");
397 break;
398 }
399
400 if (device->physical_device->rad_info.chip_class >= GFX9 &&
401 stage == MESA_SHADER_GEOMETRY) {
402 struct radv_shader_info *info = &variant->info.info;
403 unsigned es_type = variant->info.gs.es_type;
404 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
405
406 if (es_type == MESA_SHADER_VERTEX) {
407 es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
408 } else if (es_type == MESA_SHADER_TESS_EVAL) {
409 es_vgpr_comp_cnt = 3;
410 } else {
411 unreachable("invalid shader ES type");
412 }
413
414 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
415 * VGPR[0:4] are always loaded.
416 */
417 if (info->uses_invocation_id)
418 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
419 else if (info->uses_prim_id)
420 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
421 else if (variant->info.gs.vertices_in >= 3)
422 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
423 else
424 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
425
426 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
427 variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
428 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
429 } else if (device->physical_device->rad_info.chip_class >= GFX9 &&
430 stage == MESA_SHADER_TESS_CTRL)
431 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
432 else
433 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
434
435 void *ptr = radv_alloc_shader_memory(device, variant);
436 memcpy(ptr, binary->code, binary->code_size);
437 }
438
439 static struct radv_shader_variant *
440 shader_variant_create(struct radv_device *device,
441 struct radv_shader_module *module,
442 struct nir_shader * const *shaders,
443 int shader_count,
444 gl_shader_stage stage,
445 struct radv_nir_compiler_options *options,
446 bool gs_copy_shader,
447 void **code_out,
448 unsigned *code_size_out)
449 {
450 enum radeon_family chip_family = device->physical_device->rad_info.family;
451 bool dump_shaders = radv_can_dump_shader(device, module);
452 enum ac_target_machine_options tm_options = 0;
453 struct radv_shader_variant *variant;
454 struct ac_shader_binary binary;
455 LLVMTargetMachineRef tm;
456
457 variant = calloc(1, sizeof(struct radv_shader_variant));
458 if (!variant)
459 return NULL;
460
461 options->family = chip_family;
462 options->chip_class = device->physical_device->rad_info.chip_class;
463 options->dump_preoptir = radv_can_dump_shader(device, module) &&
464 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
465
466 if (options->supports_spill)
467 tm_options |= AC_TM_SUPPORTS_SPILL;
468 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
469 tm_options |= AC_TM_SISCHED;
470 tm = ac_create_target_machine(chip_family, tm_options);
471
472 if (gs_copy_shader) {
473 assert(shader_count == 1);
474 radv_compile_gs_copy_shader(tm, *shaders, &binary,
475 &variant->config, &variant->info,
476 options, dump_shaders);
477 } else {
478 radv_compile_nir_shader(tm, &binary, &variant->config,
479 &variant->info, shaders, shader_count,
480 options, dump_shaders);
481 }
482
483 LLVMDisposeTargetMachine(tm);
484
485 radv_fill_shader_variant(device, variant, &binary, stage);
486
487 if (code_out) {
488 *code_out = binary.code;
489 *code_size_out = binary.code_size;
490 } else
491 free(binary.code);
492 free(binary.config);
493 free(binary.rodata);
494 free(binary.global_symbol_offsets);
495 free(binary.relocs);
496 variant->ref_count = 1;
497
498 if (device->keep_shader_info) {
499 variant->disasm_string = binary.disasm_string;
500 if (!gs_copy_shader && !module->nir) {
501 variant->nir = *shaders;
502 variant->spirv = (uint32_t *)module->data;
503 variant->spirv_size = module->size;
504 }
505 } else {
506 free(binary.disasm_string);
507 }
508
509 return variant;
510 }
511
512 struct radv_shader_variant *
513 radv_shader_variant_create(struct radv_device *device,
514 struct radv_shader_module *module,
515 struct nir_shader *const *shaders,
516 int shader_count,
517 struct radv_pipeline_layout *layout,
518 const struct radv_shader_variant_key *key,
519 void **code_out,
520 unsigned *code_size_out)
521 {
522 struct radv_nir_compiler_options options = {0};
523
524 options.layout = layout;
525 if (key)
526 options.key = *key;
527
528 options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
529 options.supports_spill = device->llvm_supports_spill;
530
531 return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
532 &options, false, code_out, code_size_out);
533 }
534
535 struct radv_shader_variant *
536 radv_create_gs_copy_shader(struct radv_device *device,
537 struct nir_shader *shader,
538 void **code_out,
539 unsigned *code_size_out,
540 bool multiview)
541 {
542 struct radv_nir_compiler_options options = {0};
543
544 options.key.has_multiview_view_index = multiview;
545
546 return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
547 &options, true, code_out, code_size_out);
548 }
549
550 void
551 radv_shader_variant_destroy(struct radv_device *device,
552 struct radv_shader_variant *variant)
553 {
554 if (!p_atomic_dec_zero(&variant->ref_count))
555 return;
556
557 mtx_lock(&device->shader_slab_mutex);
558 list_del(&variant->slab_list);
559 mtx_unlock(&device->shader_slab_mutex);
560
561 ralloc_free(variant->nir);
562 free(variant->disasm_string);
563 free(variant);
564 }
565
566 const char *
567 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
568 {
569 switch (stage) {
570 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
571 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
572 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
573 case MESA_SHADER_COMPUTE: return "Compute Shader";
574 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
575 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
576 default:
577 return "Unknown shader";
578 };
579 }
580
581 static uint32_t
582 get_total_sgprs(struct radv_device *device)
583 {
584 if (device->physical_device->rad_info.chip_class >= VI)
585 return 800;
586 else
587 return 512;
588 }
589
590 static void
591 generate_shader_stats(struct radv_device *device,
592 struct radv_shader_variant *variant,
593 gl_shader_stage stage,
594 struct _mesa_string_buffer *buf)
595 {
596 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
597 struct ac_shader_config *conf;
598 unsigned max_simd_waves;
599 unsigned lds_per_wave = 0;
600
601 switch (device->physical_device->rad_info.family) {
602 /* These always have 8 waves: */
603 case CHIP_POLARIS10:
604 case CHIP_POLARIS11:
605 case CHIP_POLARIS12:
606 max_simd_waves = 8;
607 break;
608 default:
609 max_simd_waves = 10;
610 }
611
612 conf = &variant->config;
613
614 if (stage == MESA_SHADER_FRAGMENT) {
615 lds_per_wave = conf->lds_size * lds_increment +
616 align(variant->info.fs.num_interp * 48,
617 lds_increment);
618 }
619
620 if (conf->num_sgprs)
621 max_simd_waves = MIN2(max_simd_waves, get_total_sgprs(device) / conf->num_sgprs);
622
623 if (conf->num_vgprs)
624 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
625
626 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
627 * that PS can use.
628 */
629 if (lds_per_wave)
630 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
631
632 if (stage == MESA_SHADER_FRAGMENT) {
633 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
634 "SPI_PS_INPUT_ADDR = 0x%04x\n"
635 "SPI_PS_INPUT_ENA = 0x%04x\n",
636 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
637 }
638
639 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
640 "SGPRS: %d\n"
641 "VGPRS: %d\n"
642 "Spilled SGPRs: %d\n"
643 "Spilled VGPRs: %d\n"
644 "PrivMem VGPRS: %d\n"
645 "Code Size: %d bytes\n"
646 "LDS: %d blocks\n"
647 "Scratch: %d bytes per wave\n"
648 "Max Waves: %d\n"
649 "********************\n\n\n",
650 conf->num_sgprs, conf->num_vgprs,
651 conf->spilled_sgprs, conf->spilled_vgprs,
652 variant->info.private_mem_vgprs, variant->code_size,
653 conf->lds_size, conf->scratch_bytes_per_wave,
654 max_simd_waves);
655 }
656
657 void
658 radv_shader_dump_stats(struct radv_device *device,
659 struct radv_shader_variant *variant,
660 gl_shader_stage stage,
661 FILE *file)
662 {
663 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
664
665 generate_shader_stats(device, variant, stage, buf);
666
667 fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
668 fprintf(file, "%s", buf->buf);
669
670 _mesa_string_buffer_destroy(buf);
671 }
672
673 VkResult
674 radv_GetShaderInfoAMD(VkDevice _device,
675 VkPipeline _pipeline,
676 VkShaderStageFlagBits shaderStage,
677 VkShaderInfoTypeAMD infoType,
678 size_t* pInfoSize,
679 void* pInfo)
680 {
681 RADV_FROM_HANDLE(radv_device, device, _device);
682 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
683 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
684 struct radv_shader_variant *variant = pipeline->shaders[stage];
685 struct _mesa_string_buffer *buf;
686 VkResult result = VK_SUCCESS;
687
688 /* Spec doesn't indicate what to do if the stage is invalid, so just
689 * return no info for this. */
690 if (!variant)
691 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
692
693 switch (infoType) {
694 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
695 if (!pInfo) {
696 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
697 } else {
698 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
699 struct ac_shader_config *conf = &variant->config;
700
701 VkShaderStatisticsInfoAMD statistics = {};
702 statistics.shaderStageMask = shaderStage;
703 statistics.numPhysicalVgprs = 256;
704 statistics.numPhysicalSgprs = get_total_sgprs(device);
705 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
706
707 if (stage == MESA_SHADER_COMPUTE) {
708 unsigned *local_size = variant->nir->info.cs.local_size;
709 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
710
711 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
712 ceil(workgroup_size / statistics.numPhysicalVgprs);
713
714 statistics.computeWorkGroupSize[0] = local_size[0];
715 statistics.computeWorkGroupSize[1] = local_size[1];
716 statistics.computeWorkGroupSize[2] = local_size[2];
717 } else {
718 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
719 }
720
721 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
722 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
723 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
724 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
725 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
726
727 size_t size = *pInfoSize;
728 *pInfoSize = sizeof(statistics);
729
730 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
731
732 if (size < *pInfoSize)
733 result = VK_INCOMPLETE;
734 }
735
736 break;
737 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
738 buf = _mesa_string_buffer_create(NULL, 1024);
739
740 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage));
741 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
742 generate_shader_stats(device, variant, stage, buf);
743
744 /* Need to include the null terminator. */
745 size_t length = buf->length + 1;
746
747 if (!pInfo) {
748 *pInfoSize = length;
749 } else {
750 size_t size = *pInfoSize;
751 *pInfoSize = length;
752
753 memcpy(pInfo, buf->buf, MIN2(size, length));
754
755 if (size < length)
756 result = VK_INCOMPLETE;
757 }
758
759 _mesa_string_buffer_destroy(buf);
760 break;
761 default:
762 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
763 result = VK_ERROR_FEATURE_NOT_PRESENT;
764 break;
765 }
766
767 return result;
768 }