2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
37 #include <llvm-c/Core.h>
38 #include <llvm-c/TargetMachine.h>
42 #include "r600d_common.h"
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "vk_format.h"
47 #include "util/debug.h"
48 #include "ac_exp_param.h"
50 static const struct nir_shader_compiler_options nir_options
= {
51 .vertex_id_zero_based
= true,
57 .lower_pack_snorm_2x16
= true,
58 .lower_pack_snorm_4x8
= true,
59 .lower_pack_unorm_2x16
= true,
60 .lower_pack_unorm_4x8
= true,
61 .lower_unpack_snorm_2x16
= true,
62 .lower_unpack_snorm_4x8
= true,
63 .lower_unpack_unorm_2x16
= true,
64 .lower_unpack_unorm_4x8
= true,
65 .lower_extract_byte
= true,
66 .lower_extract_word
= true,
67 .max_unroll_iterations
= 32
70 VkResult
radv_CreateShaderModule(
72 const VkShaderModuleCreateInfo
* pCreateInfo
,
73 const VkAllocationCallbacks
* pAllocator
,
74 VkShaderModule
* pShaderModule
)
76 RADV_FROM_HANDLE(radv_device
, device
, _device
);
77 struct radv_shader_module
*module
;
79 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO
);
80 assert(pCreateInfo
->flags
== 0);
82 module
= vk_alloc2(&device
->alloc
, pAllocator
,
83 sizeof(*module
) + pCreateInfo
->codeSize
, 8,
84 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
86 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
89 module
->size
= pCreateInfo
->codeSize
;
90 memcpy(module
->data
, pCreateInfo
->pCode
, module
->size
);
92 _mesa_sha1_compute(module
->data
, module
->size
, module
->sha1
);
94 *pShaderModule
= radv_shader_module_to_handle(module
);
99 void radv_DestroyShaderModule(
101 VkShaderModule _module
,
102 const VkAllocationCallbacks
* pAllocator
)
104 RADV_FROM_HANDLE(radv_device
, device
, _device
);
105 RADV_FROM_HANDLE(radv_shader_module
, module
, _module
);
110 vk_free2(&device
->alloc
, pAllocator
, module
);
114 radv_optimize_nir(struct nir_shader
*shader
)
121 NIR_PASS_V(shader
, nir_lower_vars_to_ssa
);
122 NIR_PASS_V(shader
, nir_lower_64bit_pack
);
123 NIR_PASS_V(shader
, nir_lower_alu_to_scalar
);
124 NIR_PASS_V(shader
, nir_lower_phis_to_scalar
);
126 NIR_PASS(progress
, shader
, nir_copy_prop
);
127 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
128 NIR_PASS(progress
, shader
, nir_opt_dce
);
129 if (nir_opt_trivial_continues(shader
)) {
131 NIR_PASS(progress
, shader
, nir_copy_prop
);
132 NIR_PASS(progress
, shader
, nir_opt_remove_phis
);
133 NIR_PASS(progress
, shader
, nir_opt_dce
);
135 NIR_PASS(progress
, shader
, nir_opt_if
);
136 NIR_PASS(progress
, shader
, nir_opt_dead_cf
);
137 NIR_PASS(progress
, shader
, nir_opt_cse
);
138 NIR_PASS(progress
, shader
, nir_opt_peephole_select
, 8);
139 NIR_PASS(progress
, shader
, nir_opt_algebraic
);
140 NIR_PASS(progress
, shader
, nir_opt_constant_folding
);
141 NIR_PASS(progress
, shader
, nir_opt_undef
);
142 NIR_PASS(progress
, shader
, nir_opt_conditional_discard
);
143 if (shader
->options
->max_unroll_iterations
) {
144 NIR_PASS(progress
, shader
, nir_opt_loop_unroll
, 0);
150 radv_shader_compile_to_nir(struct radv_device
*device
,
151 struct radv_shader_module
*module
,
152 const char *entrypoint_name
,
153 gl_shader_stage stage
,
154 const VkSpecializationInfo
*spec_info
)
156 if (strcmp(entrypoint_name
, "main") != 0) {
157 radv_finishme("Multiple shaders per module not really supported");
161 nir_function
*entry_point
;
163 /* Some things such as our meta clear/blit code will give us a NIR
164 * shader directly. In that case, we just ignore the SPIR-V entirely
165 * and just use the NIR shader */
167 nir
->options
= &nir_options
;
168 nir_validate_shader(nir
);
170 assert(exec_list_length(&nir
->functions
) == 1);
171 struct exec_node
*node
= exec_list_get_head(&nir
->functions
);
172 entry_point
= exec_node_data(nir_function
, node
, node
);
174 uint32_t *spirv
= (uint32_t *) module
->data
;
175 assert(module
->size
% 4 == 0);
177 if (device
->debug_flags
& RADV_DEBUG_DUMP_SPIRV
)
178 radv_print_spirv(module
, stderr
);
180 uint32_t num_spec_entries
= 0;
181 struct nir_spirv_specialization
*spec_entries
= NULL
;
182 if (spec_info
&& spec_info
->mapEntryCount
> 0) {
183 num_spec_entries
= spec_info
->mapEntryCount
;
184 spec_entries
= malloc(num_spec_entries
* sizeof(*spec_entries
));
185 for (uint32_t i
= 0; i
< num_spec_entries
; i
++) {
186 VkSpecializationMapEntry entry
= spec_info
->pMapEntries
[i
];
187 const void *data
= spec_info
->pData
+ entry
.offset
;
188 assert(data
+ entry
.size
<= spec_info
->pData
+ spec_info
->dataSize
);
190 spec_entries
[i
].id
= spec_info
->pMapEntries
[i
].constantID
;
191 if (spec_info
->dataSize
== 8)
192 spec_entries
[i
].data64
= *(const uint64_t *)data
;
194 spec_entries
[i
].data32
= *(const uint32_t *)data
;
197 const struct nir_spirv_supported_extensions supported_ext
= {
198 .draw_parameters
= true,
200 .image_read_without_format
= true,
201 .image_write_without_format
= true,
202 .tessellation
= true,
205 .variable_pointers
= true,
207 entry_point
= spirv_to_nir(spirv
, module
->size
/ 4,
208 spec_entries
, num_spec_entries
,
209 stage
, entrypoint_name
, &supported_ext
, &nir_options
);
210 nir
= entry_point
->shader
;
211 assert(nir
->stage
== stage
);
212 nir_validate_shader(nir
);
216 /* We have to lower away local constant initializers right before we
217 * inline functions. That way they get properly initialized at the top
218 * of the function and not at the top of its caller.
220 NIR_PASS_V(nir
, nir_lower_constant_initializers
, nir_var_local
);
221 NIR_PASS_V(nir
, nir_lower_returns
);
222 NIR_PASS_V(nir
, nir_inline_functions
);
224 /* Pick off the single entrypoint that we want */
225 foreach_list_typed_safe(nir_function
, func
, node
, &nir
->functions
) {
226 if (func
!= entry_point
)
227 exec_node_remove(&func
->node
);
229 assert(exec_list_length(&nir
->functions
) == 1);
230 entry_point
->name
= ralloc_strdup(entry_point
, "main");
232 NIR_PASS_V(nir
, nir_remove_dead_variables
,
233 nir_var_shader_in
| nir_var_shader_out
| nir_var_system_value
);
235 /* Now that we've deleted all but the main function, we can go ahead and
236 * lower the rest of the constant initializers.
238 NIR_PASS_V(nir
, nir_lower_constant_initializers
, ~0);
239 NIR_PASS_V(nir
, nir_lower_system_values
);
240 NIR_PASS_V(nir
, nir_lower_clip_cull_distance_arrays
);
243 /* Vulkan uses the separate-shader linking model */
244 nir
->info
.separate_shader
= true;
246 nir_shader_gather_info(nir
, entry_point
->impl
);
248 nir_variable_mode indirect_mask
= 0;
249 indirect_mask
|= nir_var_shader_in
;
250 indirect_mask
|= nir_var_local
;
252 nir_lower_indirect_derefs(nir
, indirect_mask
);
254 static const nir_lower_tex_options tex_options
= {
258 nir_lower_tex(nir
, &tex_options
);
260 nir_lower_vars_to_ssa(nir
);
261 nir_lower_var_copies(nir
);
262 nir_lower_global_vars_to_local(nir
);
263 nir_remove_dead_variables(nir
, nir_var_local
);
264 radv_optimize_nir(nir
);
266 if (device
->debug_flags
& RADV_DEBUG_DUMP_SHADERS
)
267 nir_print_shader(nir
, stderr
);
273 radv_alloc_shader_memory(struct radv_device
*device
,
274 struct radv_shader_variant
*shader
)
276 mtx_lock(&device
->shader_slab_mutex
);
277 list_for_each_entry(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
279 list_for_each_entry(struct radv_shader_variant
, s
, &slab
->shaders
, slab_list
) {
280 if (s
->bo_offset
- offset
>= shader
->code_size
) {
281 shader
->bo
= slab
->bo
;
282 shader
->bo_offset
= offset
;
283 list_addtail(&shader
->slab_list
, &s
->slab_list
);
284 mtx_unlock(&device
->shader_slab_mutex
);
285 return slab
->ptr
+ offset
;
287 offset
= align_u64(s
->bo_offset
+ s
->code_size
, 256);
289 if (slab
->size
- offset
>= shader
->code_size
) {
290 shader
->bo
= slab
->bo
;
291 shader
->bo_offset
= offset
;
292 list_addtail(&shader
->slab_list
, &slab
->shaders
);
293 mtx_unlock(&device
->shader_slab_mutex
);
294 return slab
->ptr
+ offset
;
298 mtx_unlock(&device
->shader_slab_mutex
);
299 struct radv_shader_slab
*slab
= calloc(1, sizeof(struct radv_shader_slab
));
301 slab
->size
= 256 * 1024;
302 slab
->bo
= device
->ws
->buffer_create(device
->ws
, slab
->size
, 256,
303 RADEON_DOMAIN_VRAM
, 0);
304 slab
->ptr
= (char*)device
->ws
->buffer_map(slab
->bo
);
305 list_inithead(&slab
->shaders
);
307 mtx_lock(&device
->shader_slab_mutex
);
308 list_add(&slab
->slabs
, &device
->shader_slabs
);
310 shader
->bo
= slab
->bo
;
311 shader
->bo_offset
= 0;
312 list_add(&shader
->slab_list
, &slab
->shaders
);
313 mtx_unlock(&device
->shader_slab_mutex
);
318 radv_destroy_shader_slabs(struct radv_device
*device
)
320 list_for_each_entry_safe(struct radv_shader_slab
, slab
, &device
->shader_slabs
, slabs
) {
321 device
->ws
->buffer_destroy(slab
->bo
);
324 mtx_destroy(&device
->shader_slab_mutex
);
328 radv_fill_shader_variant(struct radv_device
*device
,
329 struct radv_shader_variant
*variant
,
330 struct ac_shader_binary
*binary
,
331 gl_shader_stage stage
)
333 bool scratch_enabled
= variant
->config
.scratch_bytes_per_wave
> 0;
334 unsigned vgpr_comp_cnt
= 0;
336 if (scratch_enabled
&& !device
->llvm_supports_spill
)
337 radv_finishme("shader scratch support only available with LLVM 4.0");
339 variant
->code_size
= binary
->code_size
;
340 variant
->rsrc2
= S_00B12C_USER_SGPR(variant
->info
.num_user_sgprs
) |
341 S_00B12C_SCRATCH_EN(scratch_enabled
);
344 case MESA_SHADER_TESS_EVAL
:
347 case MESA_SHADER_TESS_CTRL
:
348 variant
->rsrc2
|= S_00B42C_OC_LDS_EN(1);
350 case MESA_SHADER_VERTEX
:
351 case MESA_SHADER_GEOMETRY
:
352 vgpr_comp_cnt
= variant
->info
.vs
.vgpr_comp_cnt
;
354 case MESA_SHADER_FRAGMENT
:
356 case MESA_SHADER_COMPUTE
:
358 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
359 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
360 S_00B84C_TG_SIZE_EN(1) |
361 S_00B84C_LDS_SIZE(variant
->config
.lds_size
);
364 unreachable("unsupported shader type");
368 variant
->rsrc1
= S_00B848_VGPRS((variant
->config
.num_vgprs
- 1) / 4) |
369 S_00B848_SGPRS((variant
->config
.num_sgprs
- 1) / 8) |
370 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
371 S_00B848_DX10_CLAMP(1) |
372 S_00B848_FLOAT_MODE(variant
->config
.float_mode
);
374 void *ptr
= radv_alloc_shader_memory(device
, variant
);
375 memcpy(ptr
, binary
->code
, binary
->code_size
);
378 static struct radv_shader_variant
*
379 shader_variant_create(struct radv_device
*device
,
380 struct radv_shader_module
*module
,
381 struct nir_shader
*shader
,
382 gl_shader_stage stage
,
383 struct ac_nir_compiler_options
*options
,
386 unsigned *code_size_out
)
388 enum radeon_family chip_family
= device
->physical_device
->rad_info
.family
;
389 bool dump_shaders
= device
->debug_flags
& RADV_DEBUG_DUMP_SHADERS
;
390 enum ac_target_machine_options tm_options
= 0;
391 struct radv_shader_variant
*variant
;
392 struct ac_shader_binary binary
;
393 LLVMTargetMachineRef tm
;
395 variant
= calloc(1, sizeof(struct radv_shader_variant
));
399 options
->family
= chip_family
;
400 options
->chip_class
= device
->physical_device
->rad_info
.chip_class
;
402 if (options
->supports_spill
)
403 tm_options
|= AC_TM_SUPPORTS_SPILL
;
404 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
405 tm_options
|= AC_TM_SISCHED
;
406 tm
= ac_create_target_machine(chip_family
, tm_options
);
408 if (gs_copy_shader
) {
409 ac_create_gs_copy_shader(tm
, shader
, &binary
, &variant
->config
,
410 &variant
->info
, options
, dump_shaders
);
412 ac_compile_nir_shader(tm
, &binary
, &variant
->config
,
413 &variant
->info
, shader
, options
,
417 LLVMDisposeTargetMachine(tm
);
419 radv_fill_shader_variant(device
, variant
, &binary
, stage
);
422 *code_out
= binary
.code
;
423 *code_size_out
= binary
.code_size
;
428 free(binary
.global_symbol_offsets
);
430 variant
->ref_count
= 1;
432 if (device
->trace_bo
) {
433 variant
->disasm_string
= binary
.disasm_string
;
434 if (!gs_copy_shader
&& !module
->nir
) {
435 variant
->nir
= shader
;
438 free(binary
.disasm_string
);
444 struct radv_shader_variant
*
445 radv_shader_variant_create(struct radv_device
*device
,
446 struct radv_shader_module
*module
,
447 struct nir_shader
*shader
,
448 struct radv_pipeline_layout
*layout
,
449 const struct ac_shader_variant_key
*key
,
451 unsigned *code_size_out
)
453 struct ac_nir_compiler_options options
= {0};
455 options
.layout
= layout
;
459 options
.unsafe_math
= !!(device
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
);
460 options
.supports_spill
= device
->llvm_supports_spill
;
462 return shader_variant_create(device
, module
, shader
, shader
->stage
,
463 &options
, false, code_out
, code_size_out
);
466 struct radv_shader_variant
*
467 radv_create_gs_copy_shader(struct radv_device
*device
,
468 struct nir_shader
*shader
,
470 unsigned *code_size_out
,
473 struct ac_nir_compiler_options options
= {0};
475 options
.key
.has_multiview_view_index
= multiview
;
477 return shader_variant_create(device
, NULL
, shader
, MESA_SHADER_VERTEX
,
478 &options
, true, code_out
, code_size_out
);
482 radv_shader_variant_destroy(struct radv_device
*device
,
483 struct radv_shader_variant
*variant
)
485 if (!p_atomic_dec_zero(&variant
->ref_count
))
488 mtx_lock(&device
->shader_slab_mutex
);
489 list_del(&variant
->slab_list
);
490 mtx_unlock(&device
->shader_slab_mutex
);
492 ralloc_free(variant
->nir
);
493 free(variant
->disasm_string
);
498 radv_shader_stage_to_user_data_0(gl_shader_stage stage
, bool has_gs
,
502 case MESA_SHADER_FRAGMENT
:
503 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
504 case MESA_SHADER_VERTEX
:
506 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
508 return has_gs
? R_00B330_SPI_SHADER_USER_DATA_ES_0
: R_00B130_SPI_SHADER_USER_DATA_VS_0
;
509 case MESA_SHADER_GEOMETRY
:
510 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
511 case MESA_SHADER_COMPUTE
:
512 return R_00B900_COMPUTE_USER_DATA_0
;
513 case MESA_SHADER_TESS_CTRL
:
514 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
515 case MESA_SHADER_TESS_EVAL
:
517 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
519 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
521 unreachable("unknown shader");
526 radv_get_shader_name(struct radv_shader_variant
*var
, gl_shader_stage stage
)
529 case MESA_SHADER_VERTEX
: return var
->info
.vs
.as_ls
? "Vertex Shader as LS" : var
->info
.vs
.as_es
? "Vertex Shader as ES" : "Vertex Shader as VS";
530 case MESA_SHADER_GEOMETRY
: return "Geometry Shader";
531 case MESA_SHADER_FRAGMENT
: return "Pixel Shader";
532 case MESA_SHADER_COMPUTE
: return "Compute Shader";
533 case MESA_SHADER_TESS_CTRL
: return "Tessellation Control Shader";
534 case MESA_SHADER_TESS_EVAL
: return var
->info
.tes
.as_es
? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
536 return "Unknown shader";
541 radv_shader_dump_stats(struct radv_device
*device
,
542 struct radv_shader_variant
*variant
,
543 gl_shader_stage stage
,
546 unsigned lds_increment
= device
->physical_device
->rad_info
.chip_class
>= CIK
? 512 : 256;
547 struct ac_shader_config
*conf
;
548 unsigned max_simd_waves
;
549 unsigned lds_per_wave
= 0;
551 switch (device
->physical_device
->rad_info
.family
) {
552 /* These always have 8 waves: */
562 conf
= &variant
->config
;
564 if (stage
== MESA_SHADER_FRAGMENT
) {
565 lds_per_wave
= conf
->lds_size
* lds_increment
+
566 align(variant
->info
.fs
.num_interp
* 48,
570 if (conf
->num_sgprs
) {
571 if (device
->physical_device
->rad_info
.chip_class
>= VI
)
572 max_simd_waves
= MIN2(max_simd_waves
, 800 / conf
->num_sgprs
);
574 max_simd_waves
= MIN2(max_simd_waves
, 512 / conf
->num_sgprs
);
578 max_simd_waves
= MIN2(max_simd_waves
, 256 / conf
->num_vgprs
);
580 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
584 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
586 fprintf(file
, "\n%s:\n", radv_get_shader_name(variant
, stage
));
588 if (stage
== MESA_SHADER_FRAGMENT
) {
589 fprintf(file
, "*** SHADER CONFIG ***\n"
590 "SPI_PS_INPUT_ADDR = 0x%04x\n"
591 "SPI_PS_INPUT_ENA = 0x%04x\n",
592 conf
->spi_ps_input_addr
, conf
->spi_ps_input_ena
);
595 fprintf(file
, "*** SHADER STATS ***\n"
598 "Spilled SGPRs: %d\n"
599 "Spilled VGPRs: %d\n"
600 "Code Size: %d bytes\n"
602 "Scratch: %d bytes per wave\n"
604 "********************\n\n\n",
605 conf
->num_sgprs
, conf
->num_vgprs
,
606 conf
->spilled_sgprs
, conf
->spilled_vgprs
, variant
->code_size
,
607 conf
->lds_size
, conf
->scratch_bytes_per_wave
,