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34bfa44793082ba8f7b13ef8f8a701d8c53dd2a6
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40 #include <llvm-c/Support.h>
41
42 #include "sid.h"
43 #include "gfx9d.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50
51 #include "util/string_buffer.h"
52
53 static const struct nir_shader_compiler_options nir_options = {
54 .vertex_id_zero_based = true,
55 .lower_scmp = true,
56 .lower_flrp32 = true,
57 .lower_flrp64 = true,
58 .lower_device_index_to_zero = true,
59 .lower_fsat = true,
60 .lower_fdiv = true,
61 .lower_sub = true,
62 .lower_pack_snorm_2x16 = true,
63 .lower_pack_snorm_4x8 = true,
64 .lower_pack_unorm_2x16 = true,
65 .lower_pack_unorm_4x8 = true,
66 .lower_unpack_snorm_2x16 = true,
67 .lower_unpack_snorm_4x8 = true,
68 .lower_unpack_unorm_2x16 = true,
69 .lower_unpack_unorm_4x8 = true,
70 .lower_extract_byte = true,
71 .lower_extract_word = true,
72 .lower_ffma = true,
73 .lower_fpow = true,
74 .max_unroll_iterations = 32
75 };
76
77 VkResult radv_CreateShaderModule(
78 VkDevice _device,
79 const VkShaderModuleCreateInfo* pCreateInfo,
80 const VkAllocationCallbacks* pAllocator,
81 VkShaderModule* pShaderModule)
82 {
83 RADV_FROM_HANDLE(radv_device, device, _device);
84 struct radv_shader_module *module;
85
86 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
87 assert(pCreateInfo->flags == 0);
88
89 module = vk_alloc2(&device->alloc, pAllocator,
90 sizeof(*module) + pCreateInfo->codeSize, 8,
91 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
92 if (module == NULL)
93 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
94
95 module->nir = NULL;
96 module->size = pCreateInfo->codeSize;
97 memcpy(module->data, pCreateInfo->pCode, module->size);
98
99 _mesa_sha1_compute(module->data, module->size, module->sha1);
100
101 *pShaderModule = radv_shader_module_to_handle(module);
102
103 return VK_SUCCESS;
104 }
105
106 void radv_DestroyShaderModule(
107 VkDevice _device,
108 VkShaderModule _module,
109 const VkAllocationCallbacks* pAllocator)
110 {
111 RADV_FROM_HANDLE(radv_device, device, _device);
112 RADV_FROM_HANDLE(radv_shader_module, module, _module);
113
114 if (!module)
115 return;
116
117 vk_free2(&device->alloc, pAllocator, module);
118 }
119
120 void
121 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
122 bool allow_copies)
123 {
124 bool progress;
125
126 do {
127 progress = false;
128
129 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_local);
130 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_local);
131
132 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
133 NIR_PASS_V(shader, nir_lower_pack);
134
135 if (allow_copies) {
136 /* Only run this pass in the first call to
137 * radv_optimize_nir. Later calls assume that we've
138 * lowered away any copy_deref instructions and we
139 * don't want to introduce any more.
140 */
141 NIR_PASS(progress, shader, nir_opt_find_array_copies);
142 }
143
144 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
145 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
146
147 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
148 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
149
150 NIR_PASS(progress, shader, nir_copy_prop);
151 NIR_PASS(progress, shader, nir_opt_remove_phis);
152 NIR_PASS(progress, shader, nir_opt_dce);
153 if (nir_opt_trivial_continues(shader)) {
154 progress = true;
155 NIR_PASS(progress, shader, nir_copy_prop);
156 NIR_PASS(progress, shader, nir_opt_remove_phis);
157 NIR_PASS(progress, shader, nir_opt_dce);
158 }
159 NIR_PASS(progress, shader, nir_opt_if);
160 NIR_PASS(progress, shader, nir_opt_dead_cf);
161 NIR_PASS(progress, shader, nir_opt_cse);
162 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
163 NIR_PASS(progress, shader, nir_opt_algebraic);
164 NIR_PASS(progress, shader, nir_opt_constant_folding);
165 NIR_PASS(progress, shader, nir_opt_undef);
166 NIR_PASS(progress, shader, nir_opt_conditional_discard);
167 if (shader->options->max_unroll_iterations) {
168 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
169 }
170 } while (progress && !optimize_conservatively);
171
172 NIR_PASS(progress, shader, nir_opt_shrink_load);
173 NIR_PASS(progress, shader, nir_opt_move_load_ubo);
174 }
175
176 nir_shader *
177 radv_shader_compile_to_nir(struct radv_device *device,
178 struct radv_shader_module *module,
179 const char *entrypoint_name,
180 gl_shader_stage stage,
181 const VkSpecializationInfo *spec_info,
182 const VkPipelineCreateFlags flags)
183 {
184 nir_shader *nir;
185 nir_function *entry_point;
186 if (module->nir) {
187 /* Some things such as our meta clear/blit code will give us a NIR
188 * shader directly. In that case, we just ignore the SPIR-V entirely
189 * and just use the NIR shader */
190 nir = module->nir;
191 nir->options = &nir_options;
192 nir_validate_shader(nir, "in internal shader");
193
194 assert(exec_list_length(&nir->functions) == 1);
195 struct exec_node *node = exec_list_get_head(&nir->functions);
196 entry_point = exec_node_data(nir_function, node, node);
197 } else {
198 uint32_t *spirv = (uint32_t *) module->data;
199 assert(module->size % 4 == 0);
200
201 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
202 radv_print_spirv(spirv, module->size, stderr);
203
204 uint32_t num_spec_entries = 0;
205 struct nir_spirv_specialization *spec_entries = NULL;
206 if (spec_info && spec_info->mapEntryCount > 0) {
207 num_spec_entries = spec_info->mapEntryCount;
208 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
209 for (uint32_t i = 0; i < num_spec_entries; i++) {
210 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
211 const void *data = spec_info->pData + entry.offset;
212 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
213
214 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
215 if (spec_info->dataSize == 8)
216 spec_entries[i].data64 = *(const uint64_t *)data;
217 else
218 spec_entries[i].data32 = *(const uint32_t *)data;
219 }
220 }
221 const struct spirv_to_nir_options spirv_options = {
222 .caps = {
223 .device_group = true,
224 .draw_parameters = true,
225 .float64 = true,
226 .image_read_without_format = true,
227 .image_write_without_format = true,
228 .tessellation = true,
229 .int64 = true,
230 .int16 = true,
231 .multiview = true,
232 .subgroup_arithmetic = true,
233 .subgroup_ballot = true,
234 .subgroup_basic = true,
235 .subgroup_quad = true,
236 .subgroup_shuffle = true,
237 .subgroup_vote = true,
238 .variable_pointers = true,
239 .gcn_shader = true,
240 .trinary_minmax = true,
241 .shader_viewport_index_layer = true,
242 .descriptor_array_dynamic_indexing = true,
243 .runtime_descriptor_array = true,
244 .stencil_export = true,
245 .storage_16bit = true,
246 .geometry_streams = true,
247 .transform_feedback = true,
248 .storage_image_ms = true,
249 },
250 };
251 entry_point = spirv_to_nir(spirv, module->size / 4,
252 spec_entries, num_spec_entries,
253 stage, entrypoint_name,
254 &spirv_options, &nir_options);
255 nir = entry_point->shader;
256 assert(nir->info.stage == stage);
257 nir_validate_shader(nir, "after spirv_to_nir");
258
259 free(spec_entries);
260
261 /* We have to lower away local constant initializers right before we
262 * inline functions. That way they get properly initialized at the top
263 * of the function and not at the top of its caller.
264 */
265 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
266 NIR_PASS_V(nir, nir_lower_returns);
267 NIR_PASS_V(nir, nir_inline_functions);
268 NIR_PASS_V(nir, nir_opt_deref);
269
270 /* Pick off the single entrypoint that we want */
271 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
272 if (func != entry_point)
273 exec_node_remove(&func->node);
274 }
275 assert(exec_list_length(&nir->functions) == 1);
276 entry_point->name = ralloc_strdup(entry_point, "main");
277
278 /* Make sure we lower constant initializers on output variables so that
279 * nir_remove_dead_variables below sees the corresponding stores
280 */
281 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
282
283 /* Now that we've deleted all but the main function, we can go ahead and
284 * lower the rest of the constant initializers.
285 */
286 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
287
288 /* Split member structs. We do this before lower_io_to_temporaries so that
289 * it doesn't lower system values to temporaries by accident.
290 */
291 NIR_PASS_V(nir, nir_split_var_copies);
292 NIR_PASS_V(nir, nir_split_per_member_structs);
293
294 NIR_PASS_V(nir, nir_remove_dead_variables,
295 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
296
297 NIR_PASS_V(nir, nir_lower_system_values);
298 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
299 }
300
301 /* Vulkan uses the separate-shader linking model */
302 nir->info.separate_shader = true;
303
304 nir_shader_gather_info(nir, entry_point->impl);
305
306 static const nir_lower_tex_options tex_options = {
307 .lower_txp = ~0,
308 };
309
310 nir_lower_tex(nir, &tex_options);
311
312 nir_lower_vars_to_ssa(nir);
313
314 if (nir->info.stage == MESA_SHADER_VERTEX ||
315 nir->info.stage == MESA_SHADER_GEOMETRY) {
316 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
317 nir_shader_get_entrypoint(nir), true, true);
318 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL||
319 nir->info.stage == MESA_SHADER_FRAGMENT) {
320 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
321 nir_shader_get_entrypoint(nir), true, false);
322 }
323
324 nir_split_var_copies(nir);
325
326 nir_lower_global_vars_to_local(nir);
327 nir_remove_dead_variables(nir, nir_var_local);
328 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
329 .subgroup_size = 64,
330 .ballot_bit_size = 64,
331 .lower_to_scalar = 1,
332 .lower_subgroup_masks = 1,
333 .lower_shuffle = 1,
334 .lower_shuffle_to_32bit = 1,
335 .lower_vote_eq_to_ballot = 1,
336 });
337
338 nir_lower_load_const_to_scalar(nir);
339
340 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
341 radv_optimize_nir(nir, false, true);
342
343 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
344 * to remove any copies introduced by nir_opt_find_array_copies().
345 */
346 nir_lower_var_copies(nir);
347
348 /* Indirect lowering must be called after the radv_optimize_nir() loop
349 * has been called at least once. Otherwise indirect lowering can
350 * bloat the instruction count of the loop and cause it to be
351 * considered too large for unrolling.
352 */
353 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
354 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
355
356 return nir;
357 }
358
359 void *
360 radv_alloc_shader_memory(struct radv_device *device,
361 struct radv_shader_variant *shader)
362 {
363 mtx_lock(&device->shader_slab_mutex);
364 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
365 uint64_t offset = 0;
366 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
367 if (s->bo_offset - offset >= shader->code_size) {
368 shader->bo = slab->bo;
369 shader->bo_offset = offset;
370 list_addtail(&shader->slab_list, &s->slab_list);
371 mtx_unlock(&device->shader_slab_mutex);
372 return slab->ptr + offset;
373 }
374 offset = align_u64(s->bo_offset + s->code_size, 256);
375 }
376 if (slab->size - offset >= shader->code_size) {
377 shader->bo = slab->bo;
378 shader->bo_offset = offset;
379 list_addtail(&shader->slab_list, &slab->shaders);
380 mtx_unlock(&device->shader_slab_mutex);
381 return slab->ptr + offset;
382 }
383 }
384
385 mtx_unlock(&device->shader_slab_mutex);
386 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
387
388 slab->size = 256 * 1024;
389 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
390 RADEON_DOMAIN_VRAM,
391 RADEON_FLAG_NO_INTERPROCESS_SHARING |
392 (device->physical_device->cpdma_prefetch_writes_memory ?
393 0 : RADEON_FLAG_READ_ONLY));
394 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
395 list_inithead(&slab->shaders);
396
397 mtx_lock(&device->shader_slab_mutex);
398 list_add(&slab->slabs, &device->shader_slabs);
399
400 shader->bo = slab->bo;
401 shader->bo_offset = 0;
402 list_add(&shader->slab_list, &slab->shaders);
403 mtx_unlock(&device->shader_slab_mutex);
404 return slab->ptr;
405 }
406
407 void
408 radv_destroy_shader_slabs(struct radv_device *device)
409 {
410 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
411 device->ws->buffer_destroy(slab->bo);
412 free(slab);
413 }
414 mtx_destroy(&device->shader_slab_mutex);
415 }
416
417 /* For the UMR disassembler. */
418 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
419 #define DEBUGGER_NUM_MARKERS 5
420
421 static unsigned
422 radv_get_shader_binary_size(struct ac_shader_binary *binary)
423 {
424 return binary->code_size + DEBUGGER_NUM_MARKERS * 4;
425 }
426
427 static void
428 radv_fill_shader_variant(struct radv_device *device,
429 struct radv_shader_variant *variant,
430 struct ac_shader_binary *binary,
431 gl_shader_stage stage)
432 {
433 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
434 struct radv_shader_info *info = &variant->info.info;
435 unsigned vgpr_comp_cnt = 0;
436
437 variant->code_size = radv_get_shader_binary_size(binary);
438 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
439 S_00B12C_USER_SGPR_MSB(variant->info.num_user_sgprs >> 5) |
440 S_00B12C_SCRATCH_EN(scratch_enabled) |
441 S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
442 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
443 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
444 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
445 S_00B12C_SO_EN(!!info->so.num_outputs);
446
447 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
448 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
449 S_00B848_DX10_CLAMP(1) |
450 S_00B848_FLOAT_MODE(variant->config.float_mode);
451
452 switch (stage) {
453 case MESA_SHADER_TESS_EVAL:
454 vgpr_comp_cnt = 3;
455 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
456 break;
457 case MESA_SHADER_TESS_CTRL:
458 if (device->physical_device->rad_info.chip_class >= GFX9) {
459 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
460 } else {
461 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
462 }
463 break;
464 case MESA_SHADER_VERTEX:
465 case MESA_SHADER_GEOMETRY:
466 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
467 break;
468 case MESA_SHADER_FRAGMENT:
469 break;
470 case MESA_SHADER_COMPUTE:
471 variant->rsrc2 |=
472 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
473 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
474 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
475 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
476 info->cs.uses_thread_id[1] ? 1 : 0) |
477 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
478 S_00B84C_LDS_SIZE(variant->config.lds_size);
479 break;
480 default:
481 unreachable("unsupported shader type");
482 break;
483 }
484
485 if (device->physical_device->rad_info.chip_class >= GFX9 &&
486 stage == MESA_SHADER_GEOMETRY) {
487 unsigned es_type = variant->info.gs.es_type;
488 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
489
490 if (es_type == MESA_SHADER_VERTEX) {
491 es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
492 } else if (es_type == MESA_SHADER_TESS_EVAL) {
493 es_vgpr_comp_cnt = 3;
494 } else {
495 unreachable("invalid shader ES type");
496 }
497
498 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
499 * VGPR[0:4] are always loaded.
500 */
501 if (info->uses_invocation_id) {
502 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
503 } else if (info->uses_prim_id) {
504 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
505 } else if (variant->info.gs.vertices_in >= 3) {
506 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
507 } else {
508 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
509 }
510
511 variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
512 variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
513 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
514 } else if (device->physical_device->rad_info.chip_class >= GFX9 &&
515 stage == MESA_SHADER_TESS_CTRL) {
516 variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
517 } else {
518 variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
519 }
520
521 void *ptr = radv_alloc_shader_memory(device, variant);
522 memcpy(ptr, binary->code, binary->code_size);
523
524 /* Add end-of-code markers for the UMR disassembler. */
525 uint32_t *ptr32 = (uint32_t *)ptr + binary->code_size / 4;
526 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
527 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
528
529 }
530
531 static void radv_init_llvm_target()
532 {
533 LLVMInitializeAMDGPUTargetInfo();
534 LLVMInitializeAMDGPUTarget();
535 LLVMInitializeAMDGPUTargetMC();
536 LLVMInitializeAMDGPUAsmPrinter();
537
538 /* For inline assembly. */
539 LLVMInitializeAMDGPUAsmParser();
540
541 /* Workaround for bug in llvm 4.0 that causes image intrinsics
542 * to disappear.
543 * https://reviews.llvm.org/D26348
544 *
545 * Workaround for bug in llvm that causes the GPU to hang in presence
546 * of nested loops because there is an exec mask issue. The proper
547 * solution is to fix LLVM but this might require a bunch of work.
548 * https://bugs.llvm.org/show_bug.cgi?id=37744
549 *
550 * "mesa" is the prefix for error messages.
551 */
552 if (HAVE_LLVM >= 0x0800) {
553 const char *argv[2] = { "mesa", "-simplifycfg-sink-common=false" };
554 LLVMParseCommandLineOptions(2, argv, NULL);
555
556 } else {
557 const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false",
558 "-amdgpu-skip-threshold=1" };
559 LLVMParseCommandLineOptions(3, argv, NULL);
560 }
561 }
562
563 static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT;
564
565 static void radv_init_llvm_once(void)
566 {
567 call_once(&radv_init_llvm_target_once_flag, radv_init_llvm_target);
568 }
569
570 static struct radv_shader_variant *
571 shader_variant_create(struct radv_device *device,
572 struct radv_shader_module *module,
573 struct nir_shader * const *shaders,
574 int shader_count,
575 gl_shader_stage stage,
576 struct radv_nir_compiler_options *options,
577 bool gs_copy_shader,
578 void **code_out,
579 unsigned *code_size_out)
580 {
581 enum radeon_family chip_family = device->physical_device->rad_info.family;
582 enum ac_target_machine_options tm_options = 0;
583 struct radv_shader_variant *variant;
584 struct ac_shader_binary binary;
585 struct ac_llvm_compiler ac_llvm;
586 bool thread_compiler;
587 variant = calloc(1, sizeof(struct radv_shader_variant));
588 if (!variant)
589 return NULL;
590
591 options->family = chip_family;
592 options->chip_class = device->physical_device->rad_info.chip_class;
593 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
594 options->dump_preoptir = options->dump_shader &&
595 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
596 options->record_llvm_ir = device->keep_shader_info;
597 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
598 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
599 options->address32_hi = device->physical_device->rad_info.address32_hi;
600
601 if (options->supports_spill)
602 tm_options |= AC_TM_SUPPORTS_SPILL;
603 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
604 tm_options |= AC_TM_SISCHED;
605 if (options->check_ir)
606 tm_options |= AC_TM_CHECK_IR;
607
608 thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
609 radv_init_llvm_once();
610 radv_init_llvm_compiler(&ac_llvm,
611 thread_compiler,
612 chip_family, tm_options);
613 if (gs_copy_shader) {
614 assert(shader_count == 1);
615 radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
616 &variant->config, &variant->info,
617 options);
618 } else {
619 radv_compile_nir_shader(&ac_llvm, &binary, &variant->config,
620 &variant->info, shaders, shader_count,
621 options);
622 }
623
624 radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
625
626 radv_fill_shader_variant(device, variant, &binary, stage);
627
628 if (code_out) {
629 *code_out = binary.code;
630 *code_size_out = binary.code_size;
631 } else
632 free(binary.code);
633 free(binary.config);
634 free(binary.rodata);
635 free(binary.global_symbol_offsets);
636 free(binary.relocs);
637 variant->ref_count = 1;
638
639 if (device->keep_shader_info) {
640 variant->disasm_string = binary.disasm_string;
641 variant->llvm_ir_string = binary.llvm_ir_string;
642 if (!gs_copy_shader && !module->nir) {
643 variant->nir = *shaders;
644 variant->spirv = (uint32_t *)module->data;
645 variant->spirv_size = module->size;
646 }
647 } else {
648 free(binary.disasm_string);
649 }
650
651 return variant;
652 }
653
654 struct radv_shader_variant *
655 radv_shader_variant_create(struct radv_device *device,
656 struct radv_shader_module *module,
657 struct nir_shader *const *shaders,
658 int shader_count,
659 struct radv_pipeline_layout *layout,
660 const struct radv_shader_variant_key *key,
661 void **code_out,
662 unsigned *code_size_out)
663 {
664 struct radv_nir_compiler_options options = {0};
665
666 options.layout = layout;
667 if (key)
668 options.key = *key;
669
670 options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
671 options.supports_spill = true;
672
673 return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
674 &options, false, code_out, code_size_out);
675 }
676
677 struct radv_shader_variant *
678 radv_create_gs_copy_shader(struct radv_device *device,
679 struct nir_shader *shader,
680 void **code_out,
681 unsigned *code_size_out,
682 bool multiview)
683 {
684 struct radv_nir_compiler_options options = {0};
685
686 options.key.has_multiview_view_index = multiview;
687
688 return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
689 &options, true, code_out, code_size_out);
690 }
691
692 void
693 radv_shader_variant_destroy(struct radv_device *device,
694 struct radv_shader_variant *variant)
695 {
696 if (!p_atomic_dec_zero(&variant->ref_count))
697 return;
698
699 mtx_lock(&device->shader_slab_mutex);
700 list_del(&variant->slab_list);
701 mtx_unlock(&device->shader_slab_mutex);
702
703 ralloc_free(variant->nir);
704 free(variant->disasm_string);
705 free(variant->llvm_ir_string);
706 free(variant);
707 }
708
709 const char *
710 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
711 {
712 switch (stage) {
713 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
714 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
715 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
716 case MESA_SHADER_COMPUTE: return "Compute Shader";
717 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
718 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
719 default:
720 return "Unknown shader";
721 };
722 }
723
724 static void
725 generate_shader_stats(struct radv_device *device,
726 struct radv_shader_variant *variant,
727 gl_shader_stage stage,
728 struct _mesa_string_buffer *buf)
729 {
730 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
731 struct ac_shader_config *conf;
732 unsigned max_simd_waves;
733 unsigned lds_per_wave = 0;
734
735 max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family);
736
737 conf = &variant->config;
738
739 if (stage == MESA_SHADER_FRAGMENT) {
740 lds_per_wave = conf->lds_size * lds_increment +
741 align(variant->info.fs.num_interp * 48,
742 lds_increment);
743 }
744
745 if (conf->num_sgprs)
746 max_simd_waves =
747 MIN2(max_simd_waves,
748 radv_get_num_physical_sgprs(device->physical_device) / conf->num_sgprs);
749
750 if (conf->num_vgprs)
751 max_simd_waves =
752 MIN2(max_simd_waves,
753 RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs);
754
755 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
756 * that PS can use.
757 */
758 if (lds_per_wave)
759 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
760
761 if (stage == MESA_SHADER_FRAGMENT) {
762 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
763 "SPI_PS_INPUT_ADDR = 0x%04x\n"
764 "SPI_PS_INPUT_ENA = 0x%04x\n",
765 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
766 }
767
768 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
769 "SGPRS: %d\n"
770 "VGPRS: %d\n"
771 "Spilled SGPRs: %d\n"
772 "Spilled VGPRs: %d\n"
773 "PrivMem VGPRS: %d\n"
774 "Code Size: %d bytes\n"
775 "LDS: %d blocks\n"
776 "Scratch: %d bytes per wave\n"
777 "Max Waves: %d\n"
778 "********************\n\n\n",
779 conf->num_sgprs, conf->num_vgprs,
780 conf->spilled_sgprs, conf->spilled_vgprs,
781 variant->info.private_mem_vgprs, variant->code_size,
782 conf->lds_size, conf->scratch_bytes_per_wave,
783 max_simd_waves);
784 }
785
786 void
787 radv_shader_dump_stats(struct radv_device *device,
788 struct radv_shader_variant *variant,
789 gl_shader_stage stage,
790 FILE *file)
791 {
792 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
793
794 generate_shader_stats(device, variant, stage, buf);
795
796 fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
797 fprintf(file, "%s", buf->buf);
798
799 _mesa_string_buffer_destroy(buf);
800 }
801
802 VkResult
803 radv_GetShaderInfoAMD(VkDevice _device,
804 VkPipeline _pipeline,
805 VkShaderStageFlagBits shaderStage,
806 VkShaderInfoTypeAMD infoType,
807 size_t* pInfoSize,
808 void* pInfo)
809 {
810 RADV_FROM_HANDLE(radv_device, device, _device);
811 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
812 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
813 struct radv_shader_variant *variant = pipeline->shaders[stage];
814 struct _mesa_string_buffer *buf;
815 VkResult result = VK_SUCCESS;
816
817 /* Spec doesn't indicate what to do if the stage is invalid, so just
818 * return no info for this. */
819 if (!variant)
820 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
821
822 switch (infoType) {
823 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
824 if (!pInfo) {
825 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
826 } else {
827 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
828 struct ac_shader_config *conf = &variant->config;
829
830 VkShaderStatisticsInfoAMD statistics = {};
831 statistics.shaderStageMask = shaderStage;
832 statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
833 statistics.numPhysicalSgprs = radv_get_num_physical_sgprs(device->physical_device);
834 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
835
836 if (stage == MESA_SHADER_COMPUTE) {
837 unsigned *local_size = variant->nir->info.cs.local_size;
838 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
839
840 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
841 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
842
843 statistics.computeWorkGroupSize[0] = local_size[0];
844 statistics.computeWorkGroupSize[1] = local_size[1];
845 statistics.computeWorkGroupSize[2] = local_size[2];
846 } else {
847 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
848 }
849
850 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
851 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
852 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
853 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
854 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
855
856 size_t size = *pInfoSize;
857 *pInfoSize = sizeof(statistics);
858
859 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
860
861 if (size < *pInfoSize)
862 result = VK_INCOMPLETE;
863 }
864
865 break;
866 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
867 buf = _mesa_string_buffer_create(NULL, 1024);
868
869 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage));
870 _mesa_string_buffer_printf(buf, "%s\n\n", variant->llvm_ir_string);
871 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
872 generate_shader_stats(device, variant, stage, buf);
873
874 /* Need to include the null terminator. */
875 size_t length = buf->length + 1;
876
877 if (!pInfo) {
878 *pInfoSize = length;
879 } else {
880 size_t size = *pInfoSize;
881 *pInfoSize = length;
882
883 memcpy(pInfo, buf->buf, MIN2(size, length));
884
885 if (size < length)
886 result = VK_INCOMPLETE;
887 }
888
889 _mesa_string_buffer_destroy(buf);
890 break;
891 default:
892 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
893 result = VK_ERROR_FEATURE_NOT_PRESENT;
894 break;
895 }
896
897 return result;
898 }